A dead time control circuit and method
By combining feedback circuits and floating ground circuits, the dead time is automatically adjusted, solving the problem of interconnection between upper and lower transistors in analog circuits and ensuring the reliability and performance of power devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INST OF RADIO MEASUREMENT
- Filing Date
- 2022-12-27
- Publication Date
- 2026-05-29
AI Technical Summary
In analog circuits, the dead time control of power devices is difficult to effectively prevent the upper and lower transistors from conducting to each other, resulting in excessive peak discharge current, which may damage the chip.
By employing a feedback circuit, a floating ground circuit, and an upper transistor gate potential detection circuit, and by automatically adjusting the discharge delay time, the upper and lower transistors are ensured to follow the principle of turning off before turning on, thus avoiding mutual conduction.
It enables automatic adjustment of discharge delay time without manual intervention, preventing damage to power transistors and chips, and improving chip reliability and performance.
Smart Images
Figure CN116015042B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to electronic circuit technology. More specifically, it relates to a dead-time control circuit and method. Background Technology
[0002] In analog circuits, especially in power devices, a discharge circuit is designed to make the falling edge as steep as possible. Typically, a discharge transistor (N-transistor) is connected below the power transistor (P-transistor) to discharge the charge on the subsequent load. At the instant the P-transistor turns off and the N-transistor turns on, or vice versa, a current may flow between the two transistors; this current flow time is called the dead time. Because the peak discharge current is very large, if this current flow occurs between the P-transistor and the N-transistor, it can easily cause the P-transistor and the chip to burn out. Therefore, for chip reliability, the conduction time of the P-transistor and the discharge transistor needs to be controlled by dead time. Summary of the Invention
[0003] The purpose of this invention is to provide a dead time control circuit and method to solve at least one of the problems existing in the prior art.
[0004] To achieve the above objectives, the present invention adopts the following technical solution:
[0005] The first aspect of the present invention provides a dead time control circuit, the circuit comprising:
[0006] The feedback circuit is used to generate a first enable signal and a second enable signal when the modulation signal is high; wherein, the first enable signal is low and is used to control the lower transistor to turn off.
[0007] A floating ground circuit is used to output the gate control signal of the upper transistor when the second enable signal is high.
[0008] The upper transistor gate potential detection circuit is used to turn on the upper transistor when the upper transistor gate control signal is low.
[0009] Optionally, the upper gate potential detection circuit includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; wherein
[0010] The gate of the first MOS transistor is connected to the gate of the second MOS transistor;
[0011] The source of the first MOSFET is connected to the drain of the second MOSFET;
[0012] The drain of the first MOSFET is connected to the first power supply;
[0013] The source of the second MOS transistor is connected to the first output terminal of the floating ground circuit;
[0014] The gate of the third MOS transistor is connected to the source of the first MOS transistor and the drain of the second MOS transistor.
[0015] The drain of the third MOS transistor is connected to the drain of the first MOS transistor and the first power supply.
[0016] The source of the third MOS transistor is connected to the drain of the fourth MOS transistor;
[0017] The gate of the fourth MOS transistor is connected to the bias voltage;
[0018] The source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor;
[0019] The source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor;
[0020] The gate of the sixth MOS transistor receives the modulation signal;
[0021] The source of the sixth MOS transistor is grounded.
[0022] Optionally, the feedback circuit includes a NAND gate, a NOR gate, a first inverter, and a second inverter; wherein
[0023] The input terminal of the first inverter receives the modulation signal;
[0024] The output of the first inverter is connected to the first input of the NOR gate;
[0025] The first input terminal of the NAND gate is connected to the output terminal of the first inverter;
[0026] The second input terminal of the NAND gate is connected to the source of the fifth MOS transistor;
[0027] The output of the NAND gate is connected to the input of the second inverter.
[0028] The output terminal of the second inverter is connected to the second input terminal of the NOR gate and the gate of the fifth MOS transistor;
[0029] The output of the NOR gate is connected to the first input of the floating ground circuit.
[0030] Optionally, the second input terminal of the floating ground circuit is connected to the first power supply and the drain of the third MOSFET; the second output terminal of the floating ground circuit is connected to the gate of the first MOSFET and the gate of the second MOSFET.
[0031] Optionally, the circuit further includes an upper transistor and a lower transistor; wherein
[0032] The drain of the upper tube is connected to the second power supply;
[0033] The source of the upper tube is connected to the drain of the lower tube;
[0034] The gate of the upper transistor is connected to the gate of the first MOS transistor and the gate of the second MOS transistor;
[0035] The gate of the lower transistor is connected to the output terminal of the second inverter and the second input terminal of the NOR gate;
[0036] The source of the lower tube is grounded.
[0037] Optionally, the feedback circuit receives the modulation signal and the source signal of the fifth MOS transistor, and outputs the first enable signal to the gate of the lower transistor and the second enable signal to the first input terminal of the floating ground circuit.
[0038] Optionally, the floating ground circuit receives the first power supply and the second enable signal; outputs a first floating ground potential to the source of the second MOS transistor and a second floating ground potential to the gate of the first MOS transistor and the gate of the second MOS transistor.
[0039] Optionally, the upper transistor gate potential detection circuit receives the upper transistor source signal, the second floating ground potential, the bias voltage, the first enable signal, and the modulation signal; and outputs the source signal of the fifth MOS transistor to the second input terminal of the NAND gate and the upper transistor gate control signal to the upper transistor gate.
[0040] Optionally, the voltage range of the first power supply is 18V to 28V; the floating ground potential range of the first output terminal of the floating ground circuit is 18V to 23V.
[0041] A second aspect of the present invention provides a method for controlling dead time, the method comprising:
[0042] Using a feedback circuit, a first enable signal and a second enable signal are generated based on the high level of the modulation signal. The first enable signal is low level and is used to control the lower transistor to turn off.
[0043] Using a floating ground circuit, the upper transistor gate control signal is output when the second enable signal is high.
[0044] The upper transistor is turned on when the upper transistor gate control signal is low, using the upper transistor gate potential detection circuit.
[0045] The beneficial effects of this invention are as follows:
[0046] The dead time control circuit disclosed in this invention automatically adjusts the discharge delay time without any manual intervention to ensure that the upper and lower transistors are not connected and that the discharge delay is as small as possible. This prevents large peak currents from burning out the power transistors and the chip, ensuring chip performance while improving chip reliability. Attached Figure Description
[0047] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
[0048] Figure 1 The diagram shows a structural schematic of a dead-time control circuit provided in an embodiment of the present invention. Detailed Implementation
[0049] To more clearly illustrate the present invention, the following description, in conjunction with embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.
[0050] After the power transistor is turned off, if there is no discharge circuit to discharge the charge on the subsequent load, the falling edge will be extremely slow and exhibit a trailing effect. Because the peak discharge current is very large, if the upper and lower transistors are turned on in opposite directions, it can easily cause the external VDMOS and the chip to burn out. Therefore, for the reliability of the chip, the conduction time of the VDMOS power transistor and the discharge transistor needs to be controlled by dead time.
[0051] In view of this, one embodiment of the present invention provides a dead time control circuit, the circuit including a feedback circuit for generating a first enable signal and a second enable signal when the modulation signal is high; wherein the first enable signal is low and is used to control the lower transistor to turn off; a floating ground circuit for outputting an upper transistor gate control signal when the second enable signal is high; and an upper transistor gate potential detection circuit for turning on the upper transistor when the upper transistor gate control signal is low.
[0052] In one possible implementation, the upper-side gate potential detection circuit includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; wherein the gate of the first MOSFET is connected to the gate of the second MOSFET; the source of the first MOSFET is connected to the drain of the second MOSFET; the drain of the first MOSFET is connected to a first power supply; the source of the second MOSFET is connected to the first output terminal of the floating ground circuit; the gate of the third MOSFET is connected to the source of the first MOSFET and the drain of the second MOSFET; the drain of the third MOSFET is connected to the drain of the first MOSFET and the first power supply; the source of the third MOSFET is connected to the drain of the fourth MOSFET; the gate of the fourth MOSFET is connected to a bias voltage; the source of the fourth MOSFET is connected to the drain of the fifth MOSFET; the source of the fifth MOSFET is connected to the drain of the sixth MOSFET; the gate of the sixth MOSFET receives a modulation signal; and the source of the sixth MOSFET is grounded.
[0053] In one possible implementation, the feedback circuit includes a NAND gate, a NOR gate, a first inverter, and a second inverter; wherein the input of the first inverter receives the modulation signal; the output of the first inverter is connected to the first input of the NOR gate; the first input of the NAND gate is connected to the output of the first inverter; the second input of the NAND gate is connected to the source of the fifth MOS transistor; the output of the NAND gate is connected to the input of the second inverter; the output of the second inverter is connected to the second input of the NOR gate and the gate of the fifth MOS transistor; and the output of the NOR gate is connected to the first input of the floating ground circuit.
[0054] In one possible implementation, the second input terminal of the floating ground circuit is connected to the first power supply and the drain of the third MOSFET; the second output terminal of the floating ground circuit is connected to the gate of the first MOSFET and the gate of the second MOSFET.
[0055] In one possible implementation, the circuit further includes an upper transistor and a lower transistor; wherein the drain of the upper transistor is connected to a second power supply; the source of the upper transistor is connected to the drain of the lower transistor; the gate of the upper transistor is connected to the gate of the first MOS transistor and the gate of the second MOS transistor; the gate of the lower transistor is connected to the output of the second inverter and the second input of the NOR gate; and the source of the lower transistor is grounded.
[0056] Specifically, the dead time control circuit provided in this embodiment comprises an upper transistor gate potential detection circuit, a feedback circuit, and a floating ground circuit. For example... Figure 1 The diagram shows a structural schematic of a dead-time control circuit provided in an embodiment of the present invention.
[0057] Figure 1 The upper transistor gate potential detection circuit on the left side consists of an inverter (Q1 and Q2), two high-voltage P transistors Q3 and Q5, and two high-voltage N transistors Q4 and Q6. Among them, the N transistor Q5, controlled by the enable signal A, is a thick-gate transistor that can withstand a high voltage of 40V. Its function is to monitor the gate potential of the upper transistor.
[0058] Figure 1 VIN is the input control signal, and OUT is the gate control signal for the upper transistor. When OUT is low, the external upper transistor P-channel MOSFET is turned on. OUT is connected to P-channel MOSFET Q3 via an inverter (composed of Q1 and Q2). When OUT is low, Q3 is turned off. VIN is out of phase with OUT, so transistor Q6 is turned on.
[0059] The feedback circuit for the NAND and NOR gates consists of one NAND gate, one NOR gate, and two inverters. When transistor Q6 is turned on, one input of the NAND gate is pulled low. VIN outputs signal C through an inverter. C enters one input of the NAND gate and one input of the NOR gate, while the other input of the NOR gate comes from the enable signal B.
[0060] The enable signal B, output from the NOR gate, enters the floating ground circuit module. This module controls the output OUT and the floating ground level. The floating ground level and VDD28 maintain a 5V voltage difference through the floating ground circuit, achieving a high-voltage to low-voltage conversion. The signal thus follows the principle of "off before on," meaning that turning off the upper (or lower) transistor requires no waiting and is immediately controlled by the signal; turning on the upper (or lower) transistor requires waiting for the lower transistor to be turned off before enabling it.
[0061] When the upper transistor is to be turned on, VIN is at a high potential. Figure 1 When transistor Q6 is turned on, input terminal 2 of the NAND gate is at a low potential, resulting in a high output. After passing through an inverter, enable signal A goes low. Enable signal A controls the N transistor to turn off, thus turning off the external bleeder (lower transistor). Simultaneously, VIN, after passing through an inverter, outputs signal C as a low level. This signal then enters the NOR gate, causing enable signal B to go high. Enable signal B enters the floating ground circuit module, which inverts the output of OUT, causing OUT to go low and turning on the upper transistor. This achieves automatic control by turning off the lower transistor first and then turning on the upper transistor.
[0062] In one possible implementation, the feedback circuit receives the modulation signal and the source signal of the fifth MOS transistor, outputs the first enable signal to the gate of the lower transistor and the second enable signal to the first input terminal of the floating ground circuit.
[0063] In one possible implementation, the floating ground circuit receives the first power supply and the second enable signal; outputs a first floating ground potential to the source of the second MOS transistor and a second floating ground potential to the gate of the first MOS transistor and the gate of the second MOS transistor.
[0064] In one possible implementation, the upper transistor gate potential detection circuit receives the upper transistor source signal, the second floating ground potential, the bias voltage, the first enable signal, and the modulation signal; and outputs the source signal of the fifth MOS transistor to the second input terminal of the NAND gate and the upper transistor gate control signal to the upper transistor gate.
[0065] In one possible implementation, the voltage range of the first power supply is 18V to 28V; the floating ground potential range of the first output terminal of the floating ground circuit is 18V to 23V.
[0066] The purpose of this embodiment is to control the dead time so that the alternating operation of the upper and lower transistors always follows the principle of "turn off first, then turn on." Here, the upper and lower transistors are P-type and N-type transistors, respectively. That is, when the upper (or lower) transistor is turned off, there is no waiting time; it can be turned off immediately by the control signal. When the upper (or lower) transistor is turned on, it needs to wait until the lower (or upper) transistor is turned off before enabling it, ensuring that no through-current occurs. This prevents large peak currents from burning out the power transistors and the chip, improving the chip's reliability.
[0067] A second embodiment of the present invention provides a dead time control method, which includes using a feedback circuit to generate a first enable signal and a second enable signal when the modulation signal is high, wherein the first enable signal is low and is used to control the lower transistor to turn off; using a floating ground circuit to output an upper transistor gate control signal when the second enable signal is high; and using an upper transistor gate potential detection circuit to turn on the upper transistor when the upper transistor gate control signal is low.
[0068] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.
[0069] It should also be noted that in the description of this invention, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0070] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.
Claims
1. A dead-time control circuit, characterized in that, The circuit includes The feedback circuit is used to generate a first enable signal and a second enable signal when the modulation signal is high; wherein, the first enable signal is low and is used to control the lower transistor to turn off. A floating ground circuit is used to output the gate control signal of the upper transistor when the second enable signal is high. The upper transistor gate potential detection circuit is used to turn on the upper transistor when the upper transistor gate control signal is low. The upper-side gate potential detection circuit includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; wherein... The gate of the first MOS transistor is connected to the gate of the second MOS transistor; The source of the first MOSFET is connected to the drain of the second MOSFET; The drain of the first MOSFET is connected to the first power supply; The source of the second MOS transistor is connected to the first output terminal of the floating ground circuit; The gate of the third MOS transistor is connected to the source of the first MOS transistor and the drain of the second MOS transistor. The drain of the third MOS transistor is connected to the drain of the first MOS transistor and the first power supply. The source of the third MOS transistor is connected to the drain of the fourth MOS transistor; The gate of the fourth MOS transistor is connected to the bias voltage; The source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor; The source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor; The gate of the sixth MOS transistor receives the modulation signal; The source of the sixth MOS transistor is grounded; The feedback circuit includes a NAND gate, a NOR gate, a first inverter, and a second inverter; wherein The input terminal of the first inverter receives the modulation signal; The output of the first inverter is connected to the first input of the NOR gate; The first input terminal of the NAND gate is connected to the output terminal of the first inverter; The second input terminal of the NAND gate is connected to the source of the fifth MOS transistor; The output of the NAND gate is connected to the input of the second inverter. The output terminal of the second inverter is connected to the second input terminal of the NOR gate and the gate of the fifth MOS transistor; The output of the NOR gate is connected to the first input of the floating ground circuit. The second input terminal of the floating ground circuit is connected to the first power supply and the drain of the third MOSFET; the second output terminal of the floating ground circuit is connected to the gate of the first MOSFET and the gate of the second MOSFET. The circuit further includes an upper transistor and a lower transistor; wherein The drain of the upper tube is connected to the second power supply; The source of the upper tube is connected to the drain of the lower tube; The gate of the upper transistor is connected to the gate of the first MOS transistor and the gate of the second MOS transistor; The gate of the lower transistor is connected to the output terminal of the second inverter and the second input terminal of the NOR gate; The source of the lower tube is grounded.
2. The dead time control circuit according to claim 1, characterized in that, The feedback circuit receives the modulation signal and the source signal of the fifth MOS transistor, and outputs the first enable signal to the gate of the lower transistor and the second enable signal to the first input terminal of the floating ground circuit.
3. The dead time control circuit according to claim 2, characterized in that, The floating ground circuit receives the first power supply and the second enable signal; it outputs a first floating ground potential to the source of the second MOS transistor and a second floating ground potential to the gate of the first MOS transistor and the gate of the second MOS transistor.
4. The dead time control circuit according to claim 3, characterized in that, The upper transistor gate potential detection circuit receives the upper transistor source signal, the second floating ground potential, the bias voltage, the first enable signal, and the modulation signal; The source signal of the fifth MOS transistor is output to the second input terminal of the NAND gate, and the gate control signal of the upper transistor is output to the gate of the upper transistor.
5. The dead time control circuit according to claim 1, characterized in that, The voltage range of the first power supply is 18V to 28V; the floating ground potential range of the first output terminal of the floating ground circuit is 18V to 23V.
6. A control method applied to a dead-time control circuit as described in any one of claims 1 to 5, characterized in that, The method includes Using a feedback circuit, a first enable signal and a second enable signal are generated based on the high level of the modulation signal. The first enable signal is low level and is used to control the lower transistor to turn off. Using a floating ground circuit, the upper transistor gate control signal is output when the second enable signal is high. The upper transistor is turned on when the upper transistor gate control signal is low, using the upper transistor gate potential detection circuit.