Comparator with built-in offset cancellation
By designing a comparator with built-in offset cancellation, combined with open-loop offset cancellation technology and cascade comparators, the problem that the differential comparator cannot detect current with high precision is solved, and high-precision current detection is achieved. It is suitable for high-precision current measurement chips and equipment.
Patent Information
- Application Number
- CN202211723033.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-30
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2042-12-30
AI Technical Summary
Existing differential comparators cannot effectively eliminate noise and process offsets, resulting in the inability to achieve high-precision current detection.
A comparator with built-in offset cancellation is used, including a differential amplifier, a differential sampling capacitor, a cascade amplifier, a switching circuit, a latch and a trigger. Through open-loop offset cancellation technology and the design of a cascade comparator, the offset voltage is eliminated and the gain is increased to reduce the equivalent offset caused by the latch.
It achieves high-precision detection of the current flowing through the resistor, which is suitable for high-precision current measurement chips and equipment, especially in battery pack power measurement and chip protection.
Smart Images
Figure CN116015256B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a comparator with built-in offset elimination. Background Art
[0002] With the increasing popularity of integrated circuits and the improvement of people's living standards, the demand for integrated circuit precision is increasing. For example, the measurement of high-value precious metals is increasingly demanding high-speed, high-precision ADCs (Analog to Digital Converters). In 5G communications, broadband demodulation requires the participation of high-precision comparators. Overcurrent and overvoltage protection in high-power power supplies is also an application for high-precision comparators. Current and voltage detection in various power supply links in data center equipment also requires the use of high-precision comparators.
[0003] The existing differential comparator ensures the comparator output accuracy by stabilizing the common mode voltage output by the differential comparator (such as Figure 1 However, this technology only ensures that the output will not deviate due to input differential signal jitter and does not improve noise or process offsets. Furthermore, the offset voltage of commonly used differential comparators is in the millivolt range, making them incapable of determining the microvolt-level voltage across a current sense resistor, thus preventing high-precision current detection. Summary of the Invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a comparator with built-in offset cancellation, so as to solve the problem that the existing comparator cannot accurately realize high-precision detection of current.
[0005] To achieve the above-mentioned and other related objectives, the present invention provides a comparator with built-in offset cancellation, the comparator comprising:
[0006] A differential amplifier, a differential sampling capacitor, at least one cascade amplifier, at least two cascade sampling capacitors, at least one switch circuit, a latch, and a trigger.
[0007] The input end of the first switch circuit is connected to the common mode voltage, and the output end thereof is respectively connected to the input end of the cascade amplifier. In the sampling phase, the switch circuit is closed to short-circuit the input end of the cascade amplifier, and in the comparison phase, the switch circuit is opened;
[0008] The differential amplifier is used to receive a voltage signal to be measured and a reference voltage signal, and its output end is connected to the differential sampling capacitor. In a sampling phase, the offset voltage of the differential amplifier is sampled and the sampled offset voltage is stored in the differential sampling capacitor. In a comparison phase, the voltage signal to be measured is compared with the reference voltage signal.
[0009] The input end of the cascade amplifier is connected to the differential amplifier via the differential sampling capacitor, and the output end thereof is connected to the cascade sampling capacitor. In a sampling phase, the offset voltage of the cascade amplifier is sampled and the sampled offset voltage is stored in the cascade sampling capacitor. In a comparison phase, the comparison result of the differential amplifier is amplified.
[0010] The input end of the latch is connected to the output end of the cascade amplifier through the cascade sampling capacitor and receives a first clock signal. One output end of the latch is connected to the input end of the trigger, and the other output end of the latch is left floating. In the comparison stage, the latch is opened after the comparison result output by the cascade amplifier is stable.
[0011] The trigger is used to output the final comparison result output by the latch.
[0012] Optionally, when there are multiple cascade amplifiers, the comparator with built-in offset cancellation has the same number of switching circuits, the multiple cascade amplifiers are cascaded through the cascade sampling capacitor, and the input end of each cascade amplifier is connected to the common mode voltage through the switching circuit.
[0013] Optionally, the differential amplifier includes first, second, third, and fourth PMOS transistors, a voltage source, a first current source, a second current source, a first load module, and a second load module.
[0014] The source of the first PMOS transistor is connected to the voltage source via the first current source, the gate thereof serves as the first differential input terminal of the differential amplifier, and the drain thereof serves as the first differential output terminal of the differential amplifier, connected to the input terminal of the first load module and to the first differential sampling capacitor;
[0015] The source of the second PMOS transistor is connected to the voltage source through the first current source, the gate thereof serves as the second differential input terminal of the differential amplifier, and the drain thereof is connected to the input terminal of the second load module;
[0016] The output end of the first load module and the output end of the second load module are both connected to the ground;
[0017] The source of the third PMOS transistor is connected to the voltage source through the second current source, the gate thereof serves as the third differential input terminal of the differential amplifier, and the drain of the third PMOS transistor is connected to the input terminal of the first load module;
[0018] The source of the fourth PMOS transistor is connected to the voltage source through the second current source I2, the gate of the fourth PMOS transistor serves as the fourth differential input terminal of the differential amplifier, and the drain of the fourth PMOS transistor serves as the second differential output terminal of the differential amplifier, which is connected to the input terminal of the second load module and the second differential sampling capacitor.
[0019] Optionally, the first load module includes a first resistor; and the second load module includes a second resistor.
[0020] Optionally, the first load module includes first and second NMOS transistors, and the second load module includes third and fourth NMOS transistors, wherein the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor and serves as the input end of the first load module, the drain of the first NMOS transistor and its gate are interconnected, and its source is grounded, the gate of the second NMOS transistor is connected to the input end of the second load module, and its source is grounded; the gate of the third NMOS transistor is connected to the input end of the first load module, and its drain is connected to the drain of the fourth NMOS transistor, and serves as the input end of the second load module, and its source is grounded; the gate of the fourth NMOS transistor is connected to the drain, and its source is grounded.
[0021] Optionally, the differential amplifier includes fifth, sixth, seventh, and eighth NMOS transistors, the voltage source, the third current source, the fourth current source, the third load module, and the fourth load module.
[0022] The input end of the third load module is connected to the voltage source, and the output end thereof is connected to the drain of the fifth NMOS transistor and to the first differential sampling capacitor;
[0023] The gate of the fifth NMOS transistor serves as the second differential input terminal of the differential amplifier, the drain of the fifth NMOS transistor serves as the second differential output terminal of the differential amplifier, and the source of the fifth NMOS transistor is grounded through the third current source I3;
[0024] The drain of the sixth NMOS transistor is connected to the output end of the fourth load module, the gate thereof serves as the first differential input end of the differential amplifier, and the source thereof is grounded through the third current source;
[0025] The input end of the fourth load module is connected to the voltage source, and the output end thereof is connected to the drain of the seventh NMOS transistor and to the second differential sampling capacitor;
[0026] The gate of the seventh NMOS transistor serves as the third differential input terminal of the differential amplifier, the drain of the seventh NMOS transistor serves as the second differential output terminal of the differential amplifier, and the source of the seventh NMOS transistor is grounded through the fourth current source I4;
[0027] The drain of the eighth NMOS transistor is connected to the output end of the first load module, the gate thereof serves as the fourth differential input end of the differential amplifier, and the source thereof is grounded through the fourth current source.
[0028] Optionally, the third load module includes a third resistor; and the fourth load module includes a fourth resistor.
[0029] Optionally, the third load module includes a fifth and a sixth PMOS transistor, and the fourth load module includes a seventh and an eighth PMOS transistor, wherein the source of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor and is connected to the voltage source as the input end of the third load module, the gate of the fifth PMOS transistor is interconnected with its drain, and its drain is connected to the drain of the sixth PMOS transistor and serves as the output end of the fourth load module, and the gate of the sixth PMOS transistor is connected to the output end of the fourth load module; the source of the seventh PMOS transistor is connected to the source of the eighth PMMOS transistor and is connected to the voltage source as the input end of the fourth load module, the gate of the seventh PMOS transistor is connected to the output end of the third load module, and its drain is connected to the drain of the eighth PMOS transistor and serves as the output end of the fourth load module, and the gate and drain of the eighth PMOS transistor are interconnected.
[0030] Optionally, the switching circuit includes a first switch and a second switch, one end of the first switch is connected to the common-mode voltage as the first input end of the switching circuit, and the other end is connected to an input end of the cascade amplifier as the first output end of the switching circuit; one end of the second switch is connected to the common-mode voltage as the second input end of the switching circuit, and the other end is connected to the other input end of the cascade amplifier as the second output end of the switching circuit.
[0031] As described above, the comparator with built-in offset cancellation of the present invention uses a four-input fully differential amplifier to compare the voltage across the resistor to be detected with a reference voltage. Combined with open-loop offset cancellation technology, the offset of the four-input fully differential comparator and the cascaded comparator is almost completely eliminated. Simultaneously, the input equivalent offset introduced by the latch can be reduced to the microvolt level by increasing the gain of the cascaded comparator, thereby achieving high-precision detection of the current flowing through the resistor. Therefore, the present invention can be applied to high-precision current measurement chips or devices (such as battery capacity measurement and chip protection in battery packs) and can also be used as a current wake-up comparator. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 The diagram shows an existing comparator circuit.
[0033] Figure 2 Shown is a circuit diagram of a comparator with built-in offset cancellation according to the present invention.
[0034] Figure 3 Shown is a circuit diagram of a cascade amplifier of the present invention.
[0035] Figure 4 Shown is a circuit diagram of another cascade amplifier of the present invention.
[0036] Figure 5 Shown is a differential amplifier circuit diagram in embodiment 1 of the present invention.
[0037] Figure 6 Shown is another differential amplifier circuit diagram in embodiment 1 of the present invention.
[0038] Figure 7 Shown is a differential amplifier circuit diagram in the second embodiment of the present invention.
[0039] Figure 8 Shown is another differential amplifier circuit diagram in the second embodiment of the present invention.
[0040] Figure 9 A diagram of the logic signals used in the present invention.
[0041] Explanation of Figure Numbers
[0042] 10: differential amplifier; 11: first load module; 12: second load module; 13: third load module; 14: fourth load module; 20: cascade amplifier; 21: fifth load module; 22: sixth load module; 30: switch circuit; 31: first switch; 32: second switch; 40: latch; 50: trigger DETAILED DESCRIPTION
[0043] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0044] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may also be more complex.
[0045] like Figure 2 As shown, this embodiment provides a comparator with built-in offset cancellation, the comparator comprising: a differential amplifier 10, a differential sampling capacitor C1, at least one cascade amplifier 20, at least two cascade sampling capacitors C2, at least one switch circuit 30, a latch 40 and a trigger 50.
[0046] The input end of the first switch circuit 30 is connected to the common mode voltage VCM, and the output end thereof is respectively connected to the input end of the cascade amplifier 20. In the sampling phase, the switch circuit 30 is closed to short-circuit the input end of the cascade amplifier 20, and in the comparison phase, the switch circuit 30 is opened;
[0047] The differential amplifier 10 is used to receive a voltage signal to be measured and a reference voltage signal, and its output end is connected to the differential sampling capacitor C1. In the sampling phase, the offset voltage of the differential amplifier 10 is sampled and the sampled offset voltage is stored in the differential sampling capacitor C1. In the comparison phase, the voltage signal to be measured is compared with the reference voltage signal.
[0048] The input end of the cascade amplifier 20 is connected to the differential amplifier 10 via the differential sampling capacitor C1, and the output end thereof is connected to the cascade sampling capacitor C2. During the sampling phase, the offset voltage of the cascade amplifier 20 is sampled and the sampled offset voltage is stored in the cascade sampling capacitor C2. During the comparison phase, the comparison result of the differential amplifier 10 is amplified.
[0049] The input end of the latch 40 is connected to the output end of the cascade amplifier 20 through the cascade sampling capacitor C2 and receives the first clock signal. One output end of the latch 40 is connected to the input end of the trigger 50, and the other output end of the latch 40 is left floating. In the comparison stage, the latch 40 is opened after the comparison result output by the cascade amplifier 20 stabilizes.
[0050] The trigger 50 is used to output the final comparison result output by the latch 40 .
[0051] In this embodiment, when the number of the cascade amplifier is one, the number of the cascade sampling capacitors C2 is two, namely C21 and C22. When the number of the cascade amplifier is multiple, the number of the cascade sampling capacitors C2 is twice the number of the cascade amplifiers.
[0052] In this embodiment, the trigger is a D trigger, and the final comparison result is output through the Q terminal of the D trigger. At this time, the Q' terminal of the D trigger is suspended.
[0053] Specifically, the switching circuit 30 includes a first switch 31 and a second switch 32. One end of the first switch 31 is connected to the common-mode voltage VCM as the first input end of the switching circuit 30, and the other end is connected to an input end of the cascade amplifier 20 as the first output end of the switching circuit 30. One end of the second switch 32 is connected to the common-mode voltage VCM as the second input end of the switching circuit 30, and the other end is connected to the other input end of the cascade amplifier 20 as the second output end of the switching circuit 30.
[0054] Specifically, when there are multiple cascade amplifiers 20, the comparator with built-in offset cancellation has the same number of switching circuits 30, the multiple cascade amplifiers 20 are cascaded through the cascade sampling capacitor C2, and the input end of each cascade amplifier 20 is connected to the common mode voltage VCM through the switching circuit 30.
[0055] In this embodiment, the cascade amplifier 20 can be any type of fully differential amplifier using current cancellation technology, and the cascade amplifier 20 is further configured to increase gain to reduce the equivalent input offset voltage generated by the latch 40. Furthermore, the gain of a single cascade amplifier 20 can be adjusted by adjusting the W / L ratio of each MOS transistor in the cascade amplifier 20, thereby increasing the gain value A. The gain value A can also be adjusted by increasing the number of cascade amplifiers 20, thereby reducing the error in the equivalent offset voltage generated by the latch 40 to the microvolt level.
[0056] In this embodiment, the cascade amplifier 20 includes a ninth PMOS transistor P9, a tenth PMOS transistor P10, a fifth load module 21, a sixth load module 22, a fifth current source I5, and the voltage source VCC. The source of the ninth PMOS transistor P9 is connected to the voltage source VCC through the fifth current source I5, the gate of the ninth PMOS transistor P9 serves as the first input terminal VIP, and the drain of the ninth PMOS transistor P9 serves as the first output terminal VON and is connected to the input terminal of the fifth load module 21. The output terminal of the fifth load module 21 is grounded. The source of the tenth PMOS transistor P10 is connected to the voltage source VCC through the fifth current source I5, the gate of the ninth PMOS transistor P9 serves as the second input terminal VOP, and the drain of the ninth PMOS transistor P10 is connected to the input terminal of the sixth load module 22. The output terminal of the sixth load module 22 is grounded.
[0057] Furthermore, if Figure 3As shown, the fifth load module 21 includes a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, and a twelfth NMOS transistor N12. The drain of the ninth NMOS transistor N9 is connected to the drain of the tenth NMOS transistor N10 and serves as the input terminal of the fifth load module 21. The gate of the ninth NMOS transistor N9 and its drain are interconnected, and its source is grounded. The gate of the tenth NMOS transistor N10 is connected to the input terminal of the sixth load module 22, and its source is grounded. The gate of the eleventh NMOS transistor N11 is connected to the input terminal of the fifth load module 22, and its drain is connected to the drain of the twelfth NMOS transistor N12 and serves as the input terminal of the sixth load module 22, and its source is grounded. The gate of the twelfth NMOS transistor N11 is connected to the input terminal of the fifth load module 22, and its drain is connected to the drain of the twelfth NMOS transistor N12 and serves as the input terminal of the sixth load module 22, and its source is grounded. The gate of the twelfth NMOS transistor N12 and its drain are interconnected, and its source is grounded.
[0058] like Figure 4 As shown, the fifth load module 21 includes a fifth resistor R5, and the sixth load module 22 includes a sixth resistor R6.
[0059] Example 1
[0060] Specifically, the differential amplifier 10 includes first, second, third, and fourth PMOS transistors, a voltage source VCC, a first current source I1, a second current source I2, a first load module 11, and a second load module 12.
[0061] The source of the first PMOS transistor P1 is connected to the voltage source VCC via the first current source I1, the gate thereof serves as the first differential input terminal Vinp of the differential amplifier 10, and the drain thereof serves as the first differential output terminal Voutn_1 of the differential amplifier 10, connected to the input terminal of the first load module 11, and connected to the first differential sampling capacitor C11;
[0062] The source of the second PMOS transistor P2 is connected to the voltage source VCC via the first current source I1, the gate thereof serves as the second differential input terminal Vinn of the differential amplifier 10, and the drain thereof is connected to the input terminal of the second load module 12;
[0063] The output end of the first load module 11 and the output end of the second load module 12 are both connected to the ground;
[0064] The source of the third PMOS transistor P3 is connected to the voltage source VCC via the second current source I2, and the gate thereof serves as the third differential input terminal Vinn_vref of the differential amplifier 10. The drain of the third PMOS transistor P3 is connected to the input terminal of the first load module 11;
[0065] The source of the fourth PMOS transistor P4 is connected to the voltage source VCC through the second current source I2. The gate of the fourth PMOS transistor P4 serves as the fourth differential input terminal Vinp_vref of the differential amplifier 10. The drain of the fourth PMOS transistor P4 serves as the second differential output terminal Voutp_1 of the differential amplifier 10, which is connected to the input terminal of the second load module 12 and the second differential sampling capacitor C12.
[0066] The differential amplifier 10 provided in this embodiment eliminates the offset by adopting an open-loop offset cancellation technique, and can perform relatively accurate sampling when sampling the offset voltage, as demonstrated by the formula derivation as follows:
[0067] The first differential input terminal Vinp, the second differential input terminal Vinn, the third differential input terminal Vinn_vref, and the fourth differential input terminal Vinp_vref of the differential amplifier 10 are assumed to have two equivalent offset voltage sources Vos1 and Vos2 (such as Figure 5 For ease of analysis, the following derivation is performed: Vref = Vinp_vref - Vinn_vref > 0; Vin = Vinp - Vinn; Vos1, Vos2 > 0; Ios1, Ios2 are the current deviations due to the equivalent offset voltage sources Vos1, Vos2, respectively; Ivin, Ivin_vref1, and Ivin_vref2 are the current deviations due to the voltages Vin and Vref, respectively. Ios1, Ios2, Ivin, Ivin_vref1, and Ivin_vref2 are > 0. When sampling the offset voltage of the differential amplifier 10, Vinp, Vinn, and Vinp_vref, Vinn_vref, are connected to reference voltages, respectively, to sample the offset voltage, and the sampled offset voltage is stored in the differential sampling capacitor C1.
[0068] Ivin_vref1 represents the difference in current generated by the reference voltage at the first differential input terminal Vinp and the second differential input terminal Viinn on the first PMOS transistor P1 and the second PMOS transistor P2, and Ivin_vref2 represents the difference in current generated by the reference voltage at the third differential input terminal Vinn_vref and the fourth differential input terminal Vinp_vref on the third PMOS transistor P3 and the fourth PMOS transistor P4. At this time, the current I flowing through the first PMOS transistor P1 is P1 , the current I flowing through the second PMOS tube P2 P2 , the current I flowing through the third PMOS tube P3 P3 , the current I flowing through the fourth PMOS tube P4 P4 ,but
[0069]
[0070]
[0071]
[0072]
[0073] The first differential output voltage Voutn_1 of the differential amplifier 10 is:
[0074]
[0075] The second differential output voltage Voutp_1 is:
[0076]
[0077] During comparison, the first differential input terminal Vinp and the second differential input terminal Vinn are connected to the measured voltage (the voltage across the resistor to be measured), and the third differential input terminal Vinn_vref and the fourth differential input terminal Vinp_vref are connected to the two ends of the reference voltage. At this time, the voltage Voutn_1 of the first differential output terminal of the differential amplifier 10 is:
[0078]
[0079] The second differential output voltage Voutp_1 is:
[0080]
[0081] The voltage Voutn output after sampling by the first differential sampling capacitor C11 is:
[0082] Voutn=(I P1 +I P3 )×R1=(I vin_vref1 -I vin )×R1
[0083] The output voltage Voutp after sampling by the second differential sampling capacitor C12 is:
[0084] Voutp=(l p2 +l P4 )×R2=(-I vin_vref1 +I vin )×R2
[0085] In the above formula, the resistance values of the first resistor R1 and the second resistor R2 may be the same.
[0086] Since the gate voltages of the third PMOS transistor P3 and the fourth PMOS transistor P4 do not change, it can be considered that Ios2 is completely eliminated. However, for the first PMOS transistor P1 and the second PMOS transistor P2, Ios1 cannot be completely eliminated due to the nonlinear relationship between the voltage and current of the MOS transistors. However, although Ios1 cannot be completely eliminated, as the voltage Vin and the voltage Vref gradually approach each other, Ios1 is almost completely eliminated near the flip point. Therefore, it can be seen that the output voltage through the first differential sampling capacitor C11 and the second differential sampling capacitor C12 is only determined by the voltage to be measured (the voltage across the resistor to be measured) and the reference voltage.
[0087] like Figure 5 As shown, as an example, the first load module 11 includes a first resistor R1; the second load module 12 includes a second resistor R2.
[0088] like Figure 6 As shown, as an example, the first load module 11 includes first and second NMOS transistors N2, and the second load module 12 includes third and fourth NMOS transistors N4, wherein the drain of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2 and serves as the input end of the first load module 11, the drain of the first NMOS transistor N1 is interconnected with its gate, and its source is grounded, the gate of the second NMOS transistor N2 is connected to the input end of the second load module 12, and its source is grounded; the gate of the third NMOS transistor N3 is connected to the input end of the first load module 11, and its drain is connected to the drain of the fourth NMOS transistor N4 and serves as the input end of the second load module 12, and its source is grounded; the gate of the fourth NMOS transistor N4 is connected to the drain, and its source is grounded.
[0089] In this embodiment, the chip area can be reduced by using an NMOS transistor as a load.
[0090] Example 2
[0091] The difference between this embodiment and the first embodiment is that an NMOS transistor is used as the input transistor.
[0092] Specifically, the differential amplifier 10 includes a fifth, a sixth, a seventh, and an eighth NMOS transistor, the voltage source VCC, a third current source I3, a fourth current source I4, a third load module 13, and a fourth load module 14.
[0093] The input end of the third load module 13 is connected to the voltage source VCC, and the output end thereof is connected to the drain of the fifth NMOS transistor N5 and to the first differential sampling capacitor C11;
[0094] The gate of the fifth NMOS transistor N5 serves as the second differential input terminal Vinn of the differential amplifier 10, the drain of the fifth NMOS transistor N5 serves as the first differential output terminal Voutn_1 of the differential amplifier 10, and the source of the fifth NMOS transistor N5 is grounded through the third current source I3;
[0095] The drain of the sixth NMOS transistor N6 is connected to the output terminal of the fourth load module 14, the gate thereof serves as the first differential input terminal Vinp of the differential amplifier 10, and the source thereof is grounded through the third current source I3;
[0096] The input end of the fourth load module 14 is connected to the voltage source VCC, and the output end thereof is connected to the drain of the seventh NMOS transistor N7 and to the second differential sampling capacitor C12;
[0097] The gate of the seventh NMOS transistor N7 serves as the third differential input terminal Vinn_vref of the differential amplifier 10, the drain of the seventh NMOS transistor N7 serves as the second differential output terminal Voutp_1 of the differential amplifier 10, and the source of the seventh NMOS transistor N7 is grounded through the fourth current source I4;
[0098] The drain of the eighth NMOS transistor N8 is connected to the output terminal of the third load module 11 , the gate thereof serves as the fourth differential input terminal Vinp_vref of the differential amplifier 10 , and the source thereof is grounded through the fourth current source I4 .
[0099] In this embodiment, the principle of the differential amplifier 10 eliminating the offset voltage is the same as that in the first embodiment, and will not be described again here.
[0100] like Figure 7 As shown, as an example, the third load module 13 includes a third resistor R3; the fourth load module 14 includes a fourth resistor R4.
[0101] like Figure 8As shown, as an example, the third load module 13 includes a fifth and a sixth PMOS transistor, and the fourth load module 14 includes a seventh and an eighth PMOS transistor P8, wherein the source of the fifth PMOS transistor P5 is connected to the source of the sixth PMOS transistor P6 and is connected to the voltage source VCC as the input end of the third load module 13, the gate of the fifth PMOS transistor P5 is interconnected with its drain, and its drain is connected to the drain of the sixth PMOS transistor P6 and serves as the output end of the fourth load module 14, and the gate of the sixth PMOS transistor P6 is connected to the output end of the fourth load module 14; the source of the seventh PMOS transistor P7 is connected to the source of the eighth PMOS transistor and is connected to the voltage source VCC as the input end of the fourth load module 14, the gate of the seventh PMOS transistor P7 is connected to the output end of the third load module 13, and its drain is connected to the drain of the eighth PMOS transistor P8 and serves as the output end of the fourth load module 14, and the gate and drain of the eighth PMOS transistor P8 are interconnected.
[0102] The working process of the comparator with built-in offset cancellation is as follows: first, the offset voltage of the amplifier (differential amplifier and cascade amplifier) is sampled, and the sampled offset voltage is stored, and then the voltage signal to be measured is compared with the reference voltage signal. Specifically: Figure 9 As shown, the clock signal CLK is generated by an external circuit and is used to control the first clock signal CLK_Latch, the switch signal CLK_sample and the clock signal Outputsample of the trigger. C0~C1 is a comparison cycle. During the comparison cycle, when the switch signal CLK_sample is high (that is, all switches in the switch circuit are in a closed state), the input terminals of the differential amplifier (the first, second, third, and fourth differential input terminals) are connected to the reference voltage to receive the reference voltage signal. The input terminals of the cascade amplifier are short-circuited with the common-mode voltage VCM to sample the offset voltage respectively. The sampled offset voltage is stored on the differential sampling capacitor C1 or the cascade sampling capacitor C2. When the switch CLK_sample is low (that is, all switches in the switching circuit are in the off state), the cascade amplifier is disconnected from the common-mode voltage VCM, the first differential input terminal and the second differential input terminal of the differential amplifier are connected to the two ends of the voltage signal to be measured, the third differential input terminal and the fourth differential input terminal of the differential amplifier are connected to the two ends of the reference voltage, and the output terminal of the differential amplifier is connected to the input terminal of the cascade amplifier, and the comparison between the voltage to be measured (the voltage across the resistor to be detected) and the reference voltage is started.
[0103] After the comparison result of the cascade amplifier connected to the latch stabilizes, the first clock signal CLK_Latch becomes high, and the latch opens to further process the amplified result of the cascade amplifier and amplify it to ground or a voltage source. After the result output by the latch stabilizes, the final comparison result is output at its output terminal on the rising edge of the flip-flop's clock signal Output sample.
[0104] In summary, the comparator with built-in offset cancellation of the present invention uses a four-input fully differential amplifier to compare the voltage across the resistor to be detected with the reference voltage, and combines the open-loop offset cancellation technology to almost completely eliminate the offset of the four-input fully differential comparator and the cascade comparator. At the same time, the input equivalent offset caused by the latch can also be reduced to the microvolt level by increasing the gain of the cascade comparator, thereby achieving high-precision detection of the current flowing through the resistor. Therefore, the present invention can be applied to high-precision current measurement chips or devices (electricity measurement and chip protection in battery packs), and can also be used as a current wake-up comparator. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.
[0105] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A comparator with built-in offset cancellation, characterized in that: The comparator includes: a differential amplifier, a differential sampling capacitor, at least one cascade amplifier, at least two cascade sampling capacitors, at least one switch circuit, a latch and a trigger; The input end of the switch circuit is connected to the common mode voltage, and the output end thereof is respectively connected to the input end of the cascade amplifier. In the sampling phase, the switch circuit is closed to short-circuit the input end of the cascade amplifier, and in the comparison phase, the switch circuit is opened; The differential amplifier is used to receive a voltage signal to be measured and a reference voltage signal, and its output end is connected to the differential sampling capacitor. In a sampling phase, the offset voltage of the differential amplifier is sampled and the sampled offset voltage is stored in the differential sampling capacitor. In a comparison phase, the voltage signal to be measured is compared with the reference voltage signal. The input end of the cascade amplifier is connected to the differential amplifier via the differential sampling capacitor, and the output end thereof is connected to the cascade sampling capacitor. In a sampling phase, the offset voltage of the cascade amplifier is sampled and the sampled offset voltage is stored in the cascade sampling capacitor. In a comparison phase, the comparison result of the differential amplifier is amplified. The input end of the latch is connected to the output end of the cascade amplifier via the cascade sampling capacitor and receives a first clock signal. One output end thereof is connected to the input end of the trigger, and the other output end thereof is left floating. In the comparison phase, the latch is opened after the comparison result output by the cascade amplifier is stable. The trigger is used to output the final comparison result output by the latch.
2. The comparator with built-in offset cancellation according to claim 1, wherein: When there are multiple cascade amplifiers, the comparator with built-in offset cancellation has the same number of switch circuits, the multiple cascade amplifiers are cascaded through the cascade sampling capacitor, and the input end of each cascade amplifier is connected to the common mode voltage through the switch circuit.
3. The comparator with built-in offset cancellation according to claim 1 or 2, characterized in that: The differential amplifier includes first, second, third, and fourth PMOS tubes, a voltage source, a first current source, a second current source, a first load module, and a second load module; The source of the first PMOS transistor is connected to the voltage source via the first current source, the gate thereof serves as the first differential input terminal of the differential amplifier, and the drain thereof serves as the first differential output terminal of the differential amplifier, connected to the input terminal of the first load module and to the first differential sampling capacitor; The source of the second PMOS transistor is connected to the voltage source through the first current source, the gate thereof serves as the second differential input terminal of the differential amplifier, and the drain thereof is connected to the input terminal of the second load module; The output end of the first load module and the output end of the second load module are both connected to the ground; The source of the third PMOS transistor is connected to the voltage source through the second current source, the gate thereof serves as the third differential input terminal of the differential amplifier, and the drain of the third PMOS transistor is connected to the input terminal of the first load module; The source of the fourth PMOS transistor is connected to the voltage source through the second current source, the gate of the fourth PMOS transistor serves as the fourth differential input terminal of the differential amplifier, and the drain of the fourth PMOS transistor serves as the second differential output terminal of the differential amplifier, which is connected to the input terminal of the second load module and the second differential sampling capacitor.
4. The comparator with built-in offset cancellation according to claim 3, wherein: The first load module includes a first resistor; the second load module includes a second resistor.
5. The comparator with built-in offset cancellation according to claim 3, wherein: The first load module includes first and second NMOS transistors, and the second load module includes third and fourth NMOS transistors; The drain of the first NMOS transistor is connected to the drain of the second NMOS transistor and serves as the input end of the first load module. The drain of the first NMOS transistor and its gate are interconnected, and its source is grounded. The gate of the second NMOS transistor is connected to the input end of the second load module, and its source is grounded. The gate of the third NMOS transistor is connected to the input end of the first load module, and its drain is connected to the drain of the fourth NMOS transistor and serves as the input end of the second load module, and its source is grounded. The gate of the fourth NMOS transistor and its drain are interconnected, and its source is grounded.
6. The comparator with built-in offset cancellation according to claim 1 or 2, characterized in that: The differential amplifier includes fifth, sixth, seventh, and eighth NMOS transistors, a voltage source, a third current source, a fourth current source, a third load module, and a fourth load module; The input end of the third load module is connected to the voltage source, and the output end thereof is connected to the drain of the fifth NMOS transistor and to the first differential sampling capacitor; The gate of the fifth NMOS transistor serves as the second differential input terminal of the differential amplifier, the drain of the fifth NMOS transistor serves as the second differential output terminal of the differential amplifier, and the source of the fifth NMOS transistor is grounded through the third current source; The drain of the sixth NMOS transistor is connected to the output end of the fourth load module, the gate thereof serves as the first differential input end of the differential amplifier, and the source thereof is grounded through the third current source; The input end of the fourth load module is connected to the voltage source, and the output end thereof is connected to the drain of the seventh NMOS transistor and to the second differential sampling capacitor; The gate of the seventh NMOS transistor serves as the third differential input terminal of the differential amplifier, the drain of the seventh NMOS transistor serves as the second differential output terminal of the differential amplifier, and the source of the seventh NMOS transistor is grounded through the fourth current source; The drain of the eighth NMOS transistor is connected to the output end of the first load module, the gate thereof serves as the fourth differential input end of the differential amplifier, and the source thereof is grounded through the fourth current source.
7. The comparator with built-in offset cancellation according to claim 6, wherein: The third load module includes a third resistor; the fourth load module includes a fourth resistor.
8. The comparator with built-in offset cancellation according to claim 6, wherein: The third load module includes fifth and sixth PMOS transistors, and the fourth load module includes seventh and eighth PMOS transistors; The source of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor and is connected to the voltage source as the input of the third load module. The gate of the fifth PMOS transistor is interconnected with its drain, and its drain is connected to the drain of the sixth PMOS transistor and serves as the output of the fourth load module. The gate of the sixth PMOS transistor is connected to the output of the fourth load module. The source of the seventh PMOS transistor is connected to the source of the eighth PMMOS transistor and is connected to the voltage source as the input of the fourth load module. The gate of the seventh PMOS transistor is connected to the output of the third load module, and its drain is connected to the drain of the eighth PMOS transistor and serves as the output of the fourth load module. The gate and drain of the eighth PMOS transistor are interconnected.
9. The comparator with built-in offset cancellation according to claim 1 or 2, characterized in that: The switching circuit includes a first switch and a second switch, one end of the first switch is connected to the common-mode voltage as the first input end of the switching circuit, and the other end is connected to an input end of the cascade amplifier as the first output end of the switching circuit; one end of the second switch is connected to the common-mode voltage as the second input end of the switching circuit, and the other end is connected to the other input end of the cascade amplifier as the second output end of the switching circuit.
Citation Information
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