A method and device for calibrating switched capacitors in pipeline ADCs

Abstract

The present application provides a method and device for calibrating switched capacitors in a pipeline ADC. The method includes: selecting a subconverter; connecting a reference voltage switch in the i-th branch of a DAC module in the subconverter to a positive reference voltage source, and sending a calibration analog signal to the subconverter to obtain a first residual signal output by the subconverter; connecting the reference voltage switch in the i-th branch to a negative reference voltage source, and sending an analog signal to the subconverter to obtain a second residual signal output by the subconverter; calculating the actual capacitance value of the switched capacitor in the i-th branch based on the first residual signal, the second residual signal, the voltage value of the positive reference voltage source, and the capacitance value of the feedback capacitor in the subconverter; and calibrating the switched capacitor in the i-th branch based on the actual capacitance value. The present application can calibrate the switched capacitor in a pipeline ADC without introducing a special test circuit and a high-precision auxiliary ADC.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a method and device for calibrating a switched capacitor in a pipeline ADC. Background Art

[0002] Analog to Digital Converter (ADC) is widely used in modern communication systems, among which pipeline ADC is the most popular structure.

[0003] For pipeline ADCs, the ratio of the switch capacitor to the feedback capacitor is a key factor in determining the accuracy of the pipeline ADC. However, since the actual capacitance value of the switch capacitor deviates from its ideal design value, the deviation needs to be calibrated.

[0004] Existing calibration methods include trimming the switched capacitor voltage during production, or introducing a slower but more accurate auxiliary ADC to calibrate conversion errors in real time. However, the former requires additional test circuitry and expensive test equipment, while the latter comes at the expense of area and power consumption. Summary of the Invention

[0005] In view of this, the purpose of the present application is to provide a method and device for calibrating the switched capacitors in a pipeline ADC, which can calibrate the switched capacitors in the pipeline ADC without introducing special test circuits and high-precision auxiliary ADCs.

[0006] In a first aspect, an embodiment of the present application provides a method for calibrating a switched capacitor in a pipeline ADC, the method comprising:

[0007] S101, selecting a target sub-converter from a plurality of cascaded sub-converters included in the pipeline ADC;

[0008] S102, configuring the latest target sub-converter to a sampling mode to charge each switch capacitor in the latest target sub-converter;

[0009] S103. After each switched capacitor in the latest target sub-converter is completely charged, the latest target sub-converter is configured to a conversion mode, the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter is connected to the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and a calibration analog signal is sent to the latest target sub-converter to obtain a first residual signal output by the latest target sub-converter, where an initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target sub-converter.

[0010] S104: Connecting the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter to the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and sending the calibration analog signal to the latest target sub-converter to obtain a second residual signal output by the latest target sub-converter, wherein, for each reference branch except the i-th branch in the DAC module in the latest target sub-converter, when the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter is respectively connected to the positive reference voltage source and the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, the reference voltage switches in the reference branch are all connected to the positive reference voltage source in the reference branch, or are all connected to the negative reference voltage source in the reference branch;

[0011] S105: Calculate the latest actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the target sub-converter based on the latest first residual signal, the latest second residual signal, the latest voltage value of the positive reference voltage source in the i-th branch of the DAC module in the target sub-converter, and the latest capacitance value of the feedback capacitor in the target sub-converter;

[0012] S106 , calibrating the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter.

[0013] In one possible implementation, an initial value of i is 1; after calibrating the switched capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switched capacitor in the i-th branch of the DAC module in the latest target sub-converter, the method further includes:

[0014] Determine whether the current i is less than n-1;

[0015] If the current i is less than n-1, then i+1 is added and the process returns to step S102;

[0016] If the current i is not less than n-1, it is determined whether the switch capacitor in the DAC module in the latest target sub-converter has been calibrated n times;

[0017] If calibration of the switched capacitor in the DAC module in the latest target sub-converter has not been performed n times, the circuit connection relationship between the switched capacitor in the n-1th branch in the DAC module in the latest target sub-converter and the switched capacitor in the nth branch in the DAC module in the latest target sub-converter in the latest target sub-converter are replaced with each other, and the process returns to step S102.

[0018] In one possible implementation, if the current value i is not less than n-1, after determining whether calibration of the switch capacitor in the DAC module in the latest target sub-converter has been performed n times, the method further includes:

[0019] If the switched capacitor in the DAC module of the latest target sub-converter has been calibrated n times, determining whether the latest target sub-converter is a sub-converter in the first stage of the pipeline ADC;

[0020] If the latest target sub-converter is not the sub-converter at the first stage in the pipeline ADC, then the sub-converter at the previous stage of the latest target sub-converter in the pipeline ADC is used as the latest target sub-converter, i is set to the initial value, and the process returns to step S102;

[0021] If the latest target sub-converter is the sub-converter in the first stage of the pipeline ADC, the process ends.

[0022] In one possible implementation, calculating the latest actual capacitance value of the switch capacitor in the i-th branch in the DAC module of the target sub-converter based on the latest first residual signal, the latest second residual signal, the latest voltage value of the positive reference voltage source in the i-th branch in the DAC module of the target sub-converter, and the latest capacitance value of the feedback capacitor in the target sub-converter includes:

[0023] The actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter is calculated using the following formula;

[0024]

[0025] Among them, C i is the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter, V ref is the voltage value of the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, C F is the capacitance value of the feedback capacitor in the latest target sub-converter, V out (T i =1) is the latest first residual signal, V out (T i =-1) is the latest second residual signal.

[0026] In a second aspect, an embodiment of the present application provides a device for calibrating a switched capacitor in a pipeline ADC, the device comprising:

[0027] a selection module, configured to select a target sub-converter from a plurality of cascaded sub-converters included in the pipeline ADC;

[0028] a first processing module, configured to configure the latest target sub-converter to a sampling mode to charge each switching capacitor in the latest target sub-converter;

[0029] a second processing module, configured to, after each switched capacitor in the latest target sub-converter is completely charged, configure the latest target sub-converter to a conversion mode, connect the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter to the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and send a calibration analog signal to the latest target sub-converter to obtain a first residual signal output by the latest target sub-converter, wherein an initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target sub-converter;

[0030] a third processing module, configured to connect the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter to the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and send the calibration analog signal to the latest target sub-converter to obtain a second residual signal output by the latest target sub-converter, wherein, for each reference branch except the i-th branch in the DAC module in the latest target sub-converter, when the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter is respectively connected to the positive reference voltage source and the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, the reference voltage switches in the reference branch are all connected to the positive reference voltage source in the reference branch, or are all connected to the negative reference voltage source in the reference branch;

[0031] a calculation module, configured to calculate a latest actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the target sub-converter based on the latest first residual signal, the latest second residual signal, the latest voltage value of the positive reference voltage source in the i-th branch of the DAC module in the target sub-converter, and the latest capacitance value of the feedback capacitor in the target sub-converter;

[0032] The calibration module is configured to calibrate the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter.

[0033] In a possible implementation, the initial value of i is 1; and the apparatus further includes:

[0034] a first determination module, configured to determine whether a current value i is less than n-1 after the calibration module calibrates the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter;

[0035] a fourth processing module, configured to, if the current value i is less than n-1, increase the value i+1 and send the value to the first processing module for processing again;

[0036] A second judgment module is configured to judge whether the switch capacitor in the DAC module in the latest target sub-converter has been calibrated n times if the current i is not less than n-1;

[0037] a fifth processing module, configured to replace the circuit connection relationship between the switched capacitor in the n-1th branch of the DAC module in the latest target sub-converter and the switched capacitor in the nth branch of the DAC module in the latest target sub-converter, if calibration of the switched capacitor in the DAC module in the latest target sub-converter has not been performed n times, and to submit the circuit connection relationship between the switched capacitor in the n-1th branch of the DAC module in the latest target sub-converter to the first processing module for reprocessing.

[0038] In a possible implementation, the device further includes:

[0039] a third determination module, configured to, if the current value i is not less than n-1 in the second determination module, determine whether calibration of the switched capacitor in the DAC module of the latest target sub-converter has been performed n times, and if calibration of the switched capacitor in the DAC module of the latest target sub-converter has been performed n times, determine whether the latest target sub-converter is a sub-converter in the first stage of the pipeline ADC;

[0040] a sixth processing module, configured to, if the latest target sub-converter is not the sub-converter in the first stage of the pipeline ADC, use the sub-converter in the previous stage of the latest target sub-converter in the pipeline ADC as the latest target sub-converter, set i to the initial value, and return the result to the first processing module for processing again;

[0041] The seventh processing module is configured to terminate the process if the latest target sub-converter is the sub-converter in the first stage of the pipeline ADC.

[0042] In a possible implementation, the calculation module is specifically configured to:

[0043] The actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter is calculated using the following formula;

[0044]

[0045] Among them, C i is the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter, V ref is the voltage value of the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, C F is the capacitance value of the feedback capacitor in the latest target sub-converter, V out (T i =1) is the latest first residual signal, V out (T i =-1) is the latest second residual signal.

[0046] In a third aspect, an embodiment of the present application further provides an electronic device comprising: a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to perform the steps of the method for calibrating the switched capacitor in the pipeline ADC described in any one of the first aspects.

[0047] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for calibrating the switched capacitor in the pipeline ADC as described in any one of the first aspects are executed.

[0048] The embodiments of the present application provide a method and apparatus for calibrating switched capacitors in a pipeline ADC, which can calibrate switched capacitors in a pipeline ADC without introducing a special test circuit and a high-precision auxiliary ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 A flow chart of a method for calibrating a switched capacitor in a pipeline ADC provided by an embodiment of the present application is shown;

[0051] Figure 2 A schematic structural diagram of a pipeline ADC provided in an embodiment of the present application is shown;

[0052] Figure 3 A schematic structural diagram of a pipeline ADC neutron converter provided in an embodiment of the present application is shown;

[0053] Figure 4 A flow chart of another method for calibrating a switched capacitor in a pipeline ADC provided by an embodiment of the present application is shown;

[0054] Figure 5 A schematic structural diagram of another pipeline ADC neutron converter provided in an embodiment of the present application is shown;

[0055] Figure 6 A flow chart of another method for calibrating a switched capacitor in a pipeline ADC provided by an embodiment of the present application is shown;

[0056] Figure 7 A schematic structural diagram of a device for calibrating switched capacitors in a pipeline ADC according to an embodiment of the present application is shown;

[0057] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0059] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0060] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0061] To facilitate understanding of this embodiment, a method and system for calibrating a switched capacitor in a pipeline ADC provided in an embodiment of the present application are introduced in detail.

[0062] Reference Figure 1 FIG. 1 is a flow chart of a method for calibrating a switched capacitor in a pipeline ADC according to an embodiment of the present application, the method comprising:

[0063] Illustratively, the pipeline ADC includes a plurality of cascaded subconverters. Each subconverter is configured to convert a received analog signal into a digital signal of a corresponding preset bit position. Each non-last subconverter is configured to generate a residual signal based on the received analog signal and the converted digital signal, and output the residual signal to a subconverter in a subsequent stage in the pipeline ADC. The non-last subconverters include subconverters in the first to second-to-last stages of the pipeline ADC. The residual signal is an analog signal.

[0064] If the preset bit number corresponding to a sub-converter is m, then the DAC module in the sub-converter has 2 m branches (i.e., there are 2 m Switched capacitors, 2 m -1 reference voltage switch, the last branch includes 2 grounding switches but does not include the reference voltage switch).

[0065] The above are explanations of the existing pipeline ADC and there are no changes.

[0066] S101, selecting a target sub-converter from a plurality of cascaded sub-converters included in the pipeline ADC;

[0067] Since the performance of a pipeline ADC often depends primarily on the capacitance values of the switch capacitors in the ADC modules of the sub-converters in the first few stages of the pipeline, a sub-converter in an intermediate stage (i.e., a stage between the first and last stages) in the pipeline ADC can be determined as the target sub-converter.

[0068] Reference Figure 2 FIG. 1 is a schematic diagram of the structure of a pipeline ADC provided in an embodiment of the present application. Figure 2 The digital signal outputs of each stage of sub-converters are combined by the digital combination block to obtain a combined digital signal output.

[0069] S102 : Configure the latest target sub-converter to a sampling mode to charge each switch capacitor in the latest target sub-converter.

[0070] Reference Figure 3 As shown, it is a structural diagram of a pipeline ADC neutron converter provided by an embodiment of the present application, wherein φ1 is a charging switch, φ2 in the first branch to the n-1th branch is a reference voltage switch, φ2 in the nth branch is a ground switch, +Vref is a positive reference voltage source, -Vref is a negative reference voltage source, and when in sampling mode, Figure 3 φ1 is closed and φ2 is open.

[0071] S103. After each switched capacitor in the latest target sub-converter is completely charged, the latest target sub-converter is configured to a conversion mode, the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter is connected to the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and a calibration analog signal is sent to the latest target sub-converter to obtain a first residual signal output by the latest target sub-converter, where an initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target sub-converter.

[0072] DAC module, that is, Digital to Analog Converter (DAC) module.

[0073] When the subconverter is in conversion mode, Figure 3 φ2 in the circuit is closed and φ1 in the circuit is open.

[0074] The calibration analog signal may be generated by a hardware state machine.

[0075] S104: Connecting the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter to the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and sending the calibration analog signal to the latest target sub-converter to obtain a second residual signal output by the latest target sub-converter, wherein, for each reference branch except the i-th branch in the DAC module in the latest target sub-converter, when the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter is respectively connected to the positive reference voltage source and the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, the reference voltage switches in the reference branch are all connected to the positive reference voltage source in the reference branch, or are all connected to the negative reference voltage source in the reference branch;

[0076] The latest target sub-transformer keeps the conversion mode unchanged in this step.

[0077] For example, assuming that there are four branches in the DAC module of the latest target sub-converter (i.e., the preset bit corresponding to the latest target sub-converter is 2), when i is 1, that is, (in the second stage) when the reference voltage switches in the DAC module of the latest target sub-converter are connected to the positive reference voltage source and the negative reference voltage source in the first branch respectively, the reference voltage switches in the second to fourth branches remain stationary.

[0078] S105: Calculate the latest actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the target sub-converter based on the latest first residual signal, the latest second residual signal, the latest voltage value of the positive reference voltage source in the i-th branch of the DAC module in the target sub-converter, and the latest capacitance value of the feedback capacitor in the target sub-converter;

[0079] S106 , calibrating the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter.

[0080] The calibration results can be stored (burned) into digital registers.

[0081] Reference Figure 4 FIG. 1 is a flow chart of another method for calibrating switched capacitors in a pipeline ADC according to an embodiment of the present application. In one possible implementation, the initial value of i is 1. After calibrating the switched capacitors in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switched capacitors in the i-th branch of the DAC module in the latest target sub-converter, the method further includes:

[0082] S401, determine whether the current i is less than n-1;

[0083] If the current i is less than n-1, execute step S402;

[0084] S402, add i+1 and return to step S102;

[0085] If the current i is not less than n-1, execute step S403;

[0086] S403, determining whether calibration of the switch capacitor in the DAC module in the latest target sub-converter has been performed n times;

[0087] If the switched capacitor in the DAC module in the latest target sub-converter has not been calibrated n times, step S404 is executed;

[0088] S404. Replace the circuit connection relationship between the switch capacitor in the n-1th branch of the DAC module in the latest target sub-converter and the switch capacitor in the nth branch of the DAC module in the latest target sub-converter, and return to step S102.

[0089] That is, the switched capacitors in the first branch to the n-1th branch of the DAC module in the latest target sub-converter are calibrated in sequence. After completing the calibration of the switched capacitors in the first n-1 branches, since there is no reference voltage switch in the nth branch, it is necessary to replace the circuit connection relationship of the switched capacitor in the n-1th branch with the switched capacitor in the nth branch, and return to step S102 to complete the calibration of the switched capacitor in the original nth branch of the DAC module in the latest target sub-converter.

[0090] Reference Figure 5 FIG. 1 is a structural diagram of another pipeline ADC neutron converter provided in an embodiment of the present application. Figure 5 and Figure 3 Correspondingly, it is shown Figure 3 Figure 1 shows the situation where the switched capacitors in the n-1th branch of the DAC module in the sub-converter are interchanged with the switched capacitors in the nth branch of the DAC module in the sub-converter, where φ1 is a charging switch, φ2 in the first branch to the n-1th branch is a reference voltage switch, φ2 in the nth branch is a ground switch, +Vref is a positive reference voltage source, and -Vref is a negative reference voltage source.

[0091] Reference Figure 6 FIG. 1 is a flow chart of another method for calibrating switched capacitors in a pipeline ADC according to an embodiment of the present application. In one possible implementation, if the current value i is not less than n-1, then after determining whether n calibrations have been performed on the switched capacitors in the DAC module in the latest target sub-converter, the method further includes:

[0092] S601: If the switched capacitor in the DAC module of the latest target sub-converter has been calibrated n times, determine whether the latest target sub-converter is the sub-converter in the first stage of the pipeline ADC;

[0093] That is, if the calibration of each switch capacitor in the DAC module in the latest target sub-converter has been completed, it is determined whether the latest target sub-converter is the sub-converter in the first stage of the pipeline ADC.

[0094] If the latest target sub-converter is not the sub-converter in the first stage of the pipeline ADC, step S602 is executed;

[0095] S602, taking the subconverter in the pipeline ADC that is one stage before the latest target subconverter as the latest target subconverter, setting i to the initial value, and returning to step S102;

[0096] If the latest target sub-converter is the sub-converter at the first stage of the pipeline ADC, step S603 is executed.

[0097] S603: End the process.

[0098] That is, starting from the most initial target sub-converter in the pipeline ADC, the switch capacitance of the most initial target sub-converter and each stage of sub-converters before the most initial target sub-converter are calibrated in sequence.

[0099] For example, a pipeline ADC includes four cascaded sub-converters, and the initial target sub-converter is the sub-converter at the third stage of the pipeline ADC (the DAC module in the third-stage sub-converter includes eight switched capacitors, the DAC module in the second-stage sub-converter includes 16 switched capacitors, and the DAC module in the first-stage sub-converter includes four switched capacitors).

[0100] Then, after completing the calibration of all eight switch capacitors included in the DAC module of the sub-converter at the third stage in the pipeline ADC, calibrate the 16 switch capacitors included in the DAC module of the sub-converter at the second stage in the pipeline ADC;

[0101] After completing calibration of all 16 switch capacitors included in the DAC module of the sub-converter in the second stage of the pipeline ADC, calibrate the four switch capacitors included in the DAC module of the sub-converter in the first stage of the pipeline ADC;

[0102] After completing the calibration of all four switch capacitors included in the DAC module in the sub-converter at the first stage in the pipeline ADC, the process ends.

[0103] In one possible implementation, calculating the latest actual capacitance value of the switch capacitor in the i-th branch in the DAC module of the target sub-converter based on the latest first residual signal, the latest second residual signal, the latest voltage value of the positive reference voltage source in the i-th branch in the DAC module of the target sub-converter, and the latest capacitance value of the feedback capacitor in the target sub-converter includes:

[0104] The actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter is calculated using the following formula;

[0105]

[0106] Among them, C i is the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter, V ref is the voltage value of the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, C F is the capacitance value of the feedback capacitor in the latest target sub-converter, V out (T i =1) is the latest first residual signal, V out (T i =-1) is the latest second residual signal.

[0107] An embodiment of the present application provides a method for calibrating a switched capacitor in a pipeline ADC, which can calibrate the switched capacitor in the pipeline ADC without introducing a special test circuit and a high-precision auxiliary ADC.

[0108] Based on the same inventive concept, the embodiments of the present application also provide a calibration device for the switched capacitor in the pipeline ADC corresponding to the calibration method for the switched capacitor in the pipeline ADC in the embodiments. Since the principle of solving the problem by the device in the embodiments of the present application is similar to the calibration method for the switched capacitor in the pipeline ADC in the embodiments of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0109] Reference Figure 7 FIG. 1 is a schematic diagram of a device for calibrating a switched capacitor in a pipeline ADC according to an embodiment of the present application, wherein the device comprises:

[0110] A selection module 701 is configured to select a target sub-converter from a plurality of cascaded sub-converters included in the pipeline ADC;

[0111] A first processing module 702 is configured to configure the latest target sub-converter to a sampling mode to charge each switch capacitor in the latest target sub-converter;

[0112] a second processing module 703 configured to, after each switched capacitor in the latest target sub-converter is completely charged, configure the latest target sub-converter to a conversion mode, connect the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter to the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and send a calibration analog signal to the latest target sub-converter to obtain a first residual signal output by the latest target sub-converter, where an initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target sub-converter;

[0113] a third processing module 704, configured to connect the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter to the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and send the calibration analog signal to the latest target sub-converter to obtain a second residual signal output by the latest target sub-converter, wherein, for each reference branch except the i-th branch in the DAC module in the latest target sub-converter, when the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter is respectively connected to the positive reference voltage source and the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, the reference voltage switches in the reference branch are all connected to the positive reference voltage source in the reference branch, or are all connected to the negative reference voltage source in the reference branch;

[0114] a calculation module 705 configured to calculate a latest actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the target sub-converter based on the latest first residual signal, the latest second residual signal, the latest voltage value of the positive reference voltage source in the i-th branch of the DAC module in the target sub-converter, and the latest capacitance value of the feedback capacitor in the target sub-converter;

[0115] The calibration module 706 is configured to calibrate the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter.

[0116] In a possible implementation, the initial value of i is 1; and the apparatus further includes:

[0117] a first determination module, configured to determine whether a current value i is less than n-1 after the calibration module calibrates the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter;

[0118] A fourth processing module, configured to increase i+1 if the current value i is less than n-1, and send the value back to the first processing module 702 for processing;

[0119] A second judgment module is configured to judge whether the switch capacitor in the DAC module in the latest target sub-converter has been calibrated n times if the current i is not less than n-1;

[0120] A fifth processing module is configured to replace the circuit connection relationship between the switched capacitor in the n-1th branch of the DAC module in the latest target sub-converter and the switched capacitor in the nth branch of the DAC module in the latest target sub-converter, if calibration of the switched capacitor in the DAC module in the latest target sub-converter has not been performed n times, and to submit the circuit connection relationship between the switched capacitor in the n-1th branch of the DAC module in the latest target sub-converter to the first processing module 702 for reprocessing.

[0121] In a possible implementation, the device further includes:

[0122] a third determination module, configured to, if the current value i is not less than n-1 in the second determination module, determine whether calibration of the switched capacitor in the DAC module of the latest target sub-converter has been performed n times, and if calibration of the switched capacitor in the DAC module of the latest target sub-converter has been performed n times, determine whether the latest target sub-converter is a sub-converter in the first stage of the pipeline ADC;

[0123] a sixth processing module configured to, if the latest target sub-converter is not the sub-converter in the first stage of the pipeline ADC, use the sub-converter in the previous stage of the latest target sub-converter in the pipeline ADC as the latest target sub-converter, set i to the initial value, and submit the processing to the first processing module 702 again;

[0124] The seventh processing module is configured to terminate the process if the latest target sub-converter is the sub-converter in the first stage of the pipeline ADC.

[0125] In a possible implementation, the calculation module 704 is specifically configured to:

[0126] The actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter is calculated using the following formula;

[0127]

[0128] Among them, C i is the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter, V ref is the voltage value of the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, C F is the capacitance value of the feedback capacitor in the latest target sub-converter, V out (T i =1) is the latest first residual signal, V out (T i =-1) is the latest second residual signal.

[0129] An embodiment of the present application provides a calibration device for a switched capacitor in a pipeline ADC, which can calibrate the switched capacitor in the pipeline ADC without introducing a special test circuit and a high-precision auxiliary ADC.

[0130] Reference Figure 8 As shown, an electronic device 800 provided in an embodiment of the present application includes: a processor 801, a memory 802 and a bus, wherein the memory 802 stores machine-readable instructions executable by the processor 801. When the electronic device is running, the processor 801 communicates with the memory 802 through the bus, and the processor 801 executes the machine-readable instructions to perform the steps of the method for calibrating the switched capacitor in the pipeline ADC as described above.

[0131] Specifically, the memory 802 and the processor 801 can be general-purpose memories and processors, which are not specifically limited here. When the processor 801 runs the computer program stored in the memory 802, the method for calibrating the switched capacitor in the pipeline ADC can be executed.

[0132] Corresponding to the above-mentioned method for calibrating the switched capacitor in the pipeline ADC, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method for calibrating the switched capacitor in the pipeline ADC are executed.

[0133] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, system and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0134] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0135] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0136] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0137] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for calibrating switched capacitors in a pipeline ADC, characterized in that: The method comprises: S101, selecting a target sub-converter from a plurality of cascaded sub-converters included in the pipeline ADC; S102, configuring the latest target sub-converter to a sampling mode to charge each switch capacitor in the latest target sub-converter; S103. After each switched capacitor in the latest target sub-converter is completely charged, the latest target sub-converter is configured to a conversion mode, the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter is connected to the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and a calibration analog signal is sent to the latest target sub-converter to obtain a first residual signal output by the latest target sub-converter, where an initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target sub-converter. S104: Connecting the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter to the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and sending the calibration analog signal to the latest target sub-converter to obtain a second residual signal output by the latest target sub-converter, wherein, for each reference branch except the i-th branch in the DAC module in the latest target sub-converter, when the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter is respectively connected to the positive reference voltage source and the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, the reference voltage switches in the reference branch are all connected to the positive reference voltage source in the reference branch, or are all connected to the negative reference voltage source in the reference branch; S105: Calculate the latest actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the target sub-converter based on the latest first residual signal, the latest second residual signal, the latest voltage value of the positive reference voltage source in the i-th branch of the DAC module in the target sub-converter, and the latest capacitance value of the feedback capacitor in the target sub-converter; S106 , calibrating the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter.

2. The method for calibrating switched capacitors in a pipeline ADC according to claim 1, wherein: The initial value of i is 1; after calibrating the switched capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switched capacitor in the i-th branch of the DAC module in the latest target sub-converter, the method further includes: Determine whether the current i is less than n-1; If the current i is less than n-1, then i+1 is added and the process returns to step S102; If the current i is not less than n-1, it is determined whether the switch capacitor in the DAC module in the latest target sub-converter has been calibrated n times; If calibration of the switched capacitor in the DAC module in the latest target sub-converter has not been performed n times, the circuit connection relationship between the switched capacitor in the n-1th branch in the DAC module in the latest target sub-converter and the switched capacitor in the nth branch in the DAC module in the latest target sub-converter in the latest target sub-converter are replaced with each other, and the process returns to step S102.

3. The method for calibrating switched capacitors in a pipeline ADC according to claim 2, wherein: If the current value i is not less than n-1, then after determining whether calibration of the switch capacitor in the DAC module in the latest target sub-converter has been performed n times, the method further includes: If the switched capacitor in the DAC module of the latest target sub-converter has been calibrated n times, determining whether the latest target sub-converter is a sub-converter in the first stage of the pipeline ADC; If the latest target sub-converter is not the sub-converter at the first stage in the pipeline ADC, then the sub-converter at the previous stage of the latest target sub-converter in the pipeline ADC is used as the latest target sub-converter, i is set to the initial value, and the process returns to step S102; If the latest target sub-converter is the sub-converter in the first stage of the pipeline ADC, the process ends.

4. The method for calibrating switched capacitors in a pipeline ADC according to claim 1, wherein: Calculating the latest actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the target sub-converter based on the latest first residual signal, the latest second residual signal, the latest voltage value of the positive reference voltage source in the i-th branch of the DAC module in the target sub-converter, and the latest capacitance value of the feedback capacitor in the target sub-converter includes: The actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter is calculated using the following formula; Among them, C i is the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter, V ref is the voltage value of the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, C F is the capacitance value of the feedback capacitor in the latest target sub-converter, V out (T i =1) is the latest first residual signal, V out (T i =-1) is the latest second residual signal.

5. A calibration device for switched capacitors in a pipeline ADC, characterized in that: The device comprises: a selection module for selecting a target sub-converter from a plurality of cascaded sub-converters included in the pipeline ADC; a first processing module, configured to configure the latest target sub-converter to a sampling mode to charge each switching capacitor in the latest target sub-converter; a second processing module, configured to, after each switched capacitor in the latest target sub-converter is completely charged, configure the latest target sub-converter to a conversion mode, connect the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter to the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and send a calibration analog signal to the latest target sub-converter to obtain a first residual signal output by the latest target sub-converter, wherein an initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target sub-converter; a third processing module, configured to connect the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter to the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, and send the calibration analog signal to the latest target sub-converter to obtain a second residual signal output by the latest target sub-converter, wherein, for each reference branch except the i-th branch in the DAC module in the latest target sub-converter, when the reference voltage switch in the i-th branch of the DAC module in the latest target sub-converter is respectively connected to the positive reference voltage source and the negative reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, the reference voltage switches in the reference branch are all connected to the positive reference voltage source in the reference branch, or are all connected to the negative reference voltage source in the reference branch; a calculation module, configured to calculate a latest actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the target sub-converter based on the latest first residual signal, the latest second residual signal, the latest voltage value of the positive reference voltage source in the i-th branch of the DAC module in the target sub-converter, and the latest capacitance value of the feedback capacitor in the target sub-converter; The calibration module is configured to calibrate the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter.

6. The calibration device for switched capacitors in a pipeline ADC according to claim 5, wherein: The initial value of i is 1; the device further includes: a first determination module, configured to determine whether a current value i is less than n-1 after the calibration module calibrates the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter based on the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter; a fourth processing module, configured to, if the current value i is less than n-1, increase the value i+1 and send the value to the first processing module for processing again; A second judgment module is configured to judge whether the switch capacitor in the DAC module in the latest target sub-converter has been calibrated n times if the current i is not less than n-1; a fifth processing module, configured to replace the circuit connection relationship between the switched capacitor in the n-1th branch of the DAC module in the latest target sub-converter and the switched capacitor in the nth branch of the DAC module in the latest target sub-converter, if calibration of the switched capacitor in the DAC module in the latest target sub-converter has not been performed n times, and to submit the circuit connection relationship between the switched capacitor in the n-1th branch of the DAC module in the latest target sub-converter to the first processing module for reprocessing.

7. The calibration device for switched capacitors in a pipeline ADC according to claim 6, wherein: The device further comprises: a third determination module, configured to, if the current value i is not less than n-1 in the second determination module, determine whether calibration of the switched capacitor in the DAC module of the latest target sub-converter has been performed n times, and if calibration of the switched capacitor in the DAC module of the latest target sub-converter has been performed n times, determine whether the latest target sub-converter is a sub-converter in the first stage of the pipeline ADC; a sixth processing module, configured to, if the latest target sub-converter is not the sub-converter in the first stage of the pipeline ADC, use the sub-converter in the previous stage of the latest target sub-converter in the pipeline ADC as the latest target sub-converter, set i to the initial value, and return the result to the first processing module for processing again; The seventh processing module is configured to terminate the process if the latest target sub-converter is the sub-converter in the first stage of the pipeline ADC.

8. The calibration device for switched capacitors in a pipeline ADC according to claim 5, wherein: The computing module is specifically configured to: The actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter is calculated using the following formula; Among them, C i is the actual capacitance value of the switch capacitor in the i-th branch of the DAC module in the latest target sub-converter, V ref is the voltage value of the positive reference voltage source in the i-th branch of the DAC module in the latest target sub-converter, C F is the capacitance value of the feedback capacitor in the latest target sub-converter, V out (T i =1) is the latest first residual signal, V out (T i =-1) is the latest second residual signal.

9. An electronic device, characterized in that: include: A processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the storage medium communicate via the bus, and the processor executes the machine-readable instructions to perform the steps of the method for calibrating a switched capacitor in a pipeline ADC according to any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program executes the steps of the method for calibrating a switched capacitor in a pipeline ADC according to any one of claims 1 to 4.

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