Memory system security and authentication using asymmetric keys

Abstract

This application relates to memory system security and authentication using asymmetric keys. In some instances, a host system and a memory system can be configured to implement techniques for generating and distributing asymmetric keys that can support evaluating the authenticity of interfacing systems (e.g., system identity) in conjunction with exchanged signaling such as access commands, requests, data, or other signaling. Such techniques can include implementing asymmetric encryption security directly in the memory system. For example, a memory system can be configured to identify by encryption with a public asymmetric key, and can authenticate the authenticity of the memory system by signing a challenge using the memory system's asymmetric private key. Further, a host system can identify by signing signaling with its asymmetric private key, and the signature can be verified by the memory system using the host system's asymmetric public key.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 663,123, filed May 12, 2022, entitled "Memory System Security and Authentication Using Asymmetric Keys," and U.S. Provisional Patent Application No. 63 / 270,798, filed October 22, 2021, entitled "Memory System Security and Authentication Using Asymmetric Keys," each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to the security and authentication of memory systems using asymmetric keys. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even without an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a controller configured to couple to a memory system. The controller may be configured such that the apparatus: transmits a public key associated with the apparatus to the memory system, wherein the public key associated with the apparatus is at least partially based on a private key associated with the apparatus; and transmits signaling to the memory system, wherein at least a portion of the signaling is signed by the apparatus at least partially based on the private key associated with the apparatus.

[0007] Describe an apparatus. The apparatus may include a memory device and a controller coupled to the memory device. The controller may be configured such that the apparatus: receives a public key associated with a host system, wherein the public key associated with the host system is at least partially based on a private key associated with the host system; receives signaling from the host system; and determines a response to the signaling based at least partially on at least a portion of the attempted authentication signaling, wherein the at least partial portion of the attempted authentication signaling is at least partially based on the public key associated with the host system.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: transmit a public key associated with a host system via a host system, wherein the public key is at least partially based on a private key associated with the host system; and transmit signaling via the host system to a memory system, wherein at least a portion of the signaling is signed by the host system at least partially based on the private key associated with the host system.

[0009] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive, at a memory system, a public key associated with a host system, wherein the public key associated with the host system is at least partially based on a private key associated with the host system; receive, at the memory system, signaling from the host system; and determine a response to the signaling based at least partially on at least a portion of the attempted authentication signaling, wherein the at least partial portion of the attempted authentication signaling is at least partially based on the public key associated with the host system. Attached Figure Description

[0010] Figure 1 This document describes examples of systems that support the security and authentication of memory systems using asymmetric keys, based on the examples disclosed herein.

[0011] Figure 2 This document describes examples of systems that support the security and authentication of memory systems using asymmetric keys, based on the examples disclosed herein.

[0012] Figure 3 This document describes an example of a process flow that supports the security and authentication of a memory system using asymmetric keys, based on the examples disclosed herein.

[0013] Figure 4 A block diagram illustrating a host system that supports the security and authentication of a memory system using asymmetric keys, based on the examples disclosed herein.

[0014] Figure 5 A block diagram illustrating a memory system that supports security and authentication using asymmetric keys, based on the examples disclosed herein.

[0015] Figure 6 and 7 The flowchart illustrates a method for supporting the security and authentication of memory systems using asymmetric keys, based on the examples disclosed herein. Detailed Implementation

[0016] Some computing platforms may involve one or more host systems for communicating with one or more memory systems (e.g., directly or indirectly). In some instances, maintaining the security or integrity of such computing platforms may rely on the authentication of interconnected systems (e.g., authentication of system identity) to verify that such systems are exchanging signaling, such as access commands, requests, data, and other signaling with authenticity (e.g., between known and authenticated transmitting and receiving systems). However, some techniques used to maintain the authenticity of system identity (including some cryptographic protection techniques) may be vulnerable to stolen, cloned, or otherwise insecurely implemented identification or authentication information, or may not have been implemented in the context of signaling between the host system and the memory system itself to establish the authenticity of a particular device (e.g., based on unique hardware or device identity).

[0017] Based on the examples disclosed herein, host systems and memory systems can be configured to implement various techniques for generating and distributing asymmetric public keys, which can support the assessment of the authenticity of the interfacing system (e.g., system identity, hardware identity) before responding to exchange signaling (e.g., access commands, requests, data, or other signaling, such as assessing whether to trust received signaling, assessing whether to perform a responsive action, such as access or configuration of the memory system, executing an authenticated read command, or an authenticated write command)). In some instances, such techniques may include implementing asymmetric cryptographic security functionality directly in the memory system. For example, the memory system can be configured to perform cryptographic identification (e.g., through the host system) using a public asymmetric key associated with a unique hardware identity of the memory system, and the authenticity of the memory system can be verified by signing a challenge using a private asymmetric key. In some instances, the host system can identify a command by signing it with a private asymmetric key associated with a unique hardware identity of the host system, and the signature can be verified by the memory system using the host system's public asymmetric key. Once established, encrypted signaling (e.g., commands, requests, data) and responses can be facilitated using either asymmetric or symmetric keys, as determined by the system's configuration (e.g., based on command configuration bits at the host system, memory system, or both). By implementing such techniques at the device or system level for generating and distributing asymmetric device identification information, such as asymmetric public keys, interfacing hardware devices can support higher security (e.g., stronger authenticity verification) than other techniques that do not perform the distribution of encrypted hardware identification information, or whose distribution may be more easily cloned or stolen, such as techniques that distribute symmetric keys in a potentially insecure manner.

[0018] First, refer to Figure 1 and 2The features of this disclosure are described within the context of the system being described. (Referencing...) Figure 3 The features of this disclosure are described in the context of the process flow. (See references) Figures 4 to 7 These and other features of this disclosure are further illustrated and described in the context of device diagrams and flowcharts relating to the security and authentication of memory systems using asymmetric keys.

[0019] Figure 1 This document describes an example of system 100 that supports memory system security and authentication using asymmetric keys, based on the examples disclosed herein. System 100 includes a host system 105 coupled to memory system 110.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0021] The computing system 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transportation), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked commercial device), or any other computing device that includes memory and processing devices.

[0022] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices or entities (e.g., hardware entities, firmware entities, software entities) or various combinations thereof, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 can use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 The diagram shows a single host system 105 and a single memory system 110, but the host system 105 can be coupled to any number of memory systems 110, and the memory systems 110 can be coupled to any number of host systems 105.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface, which may support various signaling between host system 105 and memory system 110. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise transmit control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled and communicate with the memory device 130 to perform operations at the memory device 130 that are generally referred to as access operations, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory used by the memory system controller 115 for, for example, internal storage or operations related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and said data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0029] although Figure 1 The memory system 110 described herein has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, each located within the memory device 130, to perform the functions attributed herein to the memory system controller 115. Generally, one or more functions attributed herein to the memory system controller 115 may, in some cases, be alternatively performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130, at least partially managed by the memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device. In some instances, components of the memory system 110 may be implemented in a single semiconductor die, such as in a system-on-a-chip (SoC) implementation.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If configured to each store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to each store three bits of information, it may be referred to as a three-level cell (TLC); if configured to each store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Compared to SLC memory cells, multi-level memory cells can provide greater storage density, but in some cases may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0034] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, concurrent operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are located in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which concurrent operations can be performed. For example, concurrent operations can be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may also be called a bit line) (e.g., coupled thereto).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first-level granularity (e.g., at the page level), but can be erased at a second-level granularity (e.g., at the block level). That is, page 175 can be the smallest unit (e.g., a set of memory cells) of memory that can be independently programmed or read (e.g., programmed or read concurrently as a single programming or reading operation), and block 170 can be the smallest unit (e.g., a set of memory cells) of memory that can be independently erased (e.g., erased concurrently as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0037] System 100 may include any number of non-transitory computer-readable media that support memory system security and authentication using asymmetric keys. For example, host system 105, memory system controller 115, or memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0038] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] According to the examples disclosed herein, host system 105 and memory system 110 can be configured to implement various techniques for generating and distributing asymmetric public keys, which can support the assessment of the authenticity of host system 105 and memory system 110 (e.g., system identity, hardware identity) before responding to exchange signaling (e.g., access commands, requests, data, or other signaling, such as assessing whether to trust received signaling, assessing whether to perform a responsive action, such as access or configuration of memory system 110, executing an authenticated read command, or an authenticated write command)). In some instances, such techniques may include implementing asymmetric cryptographic security functionality directly in memory system 110. For example, memory system 110 can be configured to perform cryptographic identification using a public asymmetric key, and the authenticity of memory system 110 can be verified by signing a challenge using the memory system's asymmetric private key. In some instances, host system 105 can identify a command by signing it with host system 105's asymmetric private key, and the signature can be verified by memory system 110 using host system 105's asymmetric public key. Once established, encrypted signaling (e.g., commands, requests, data) and responses can be facilitated using either asymmetric or symmetric keys, as determined by the system configuration (e.g., based on command configuration bits at host system 105, memory system 110, or both). By implementing such techniques at the device or system level for generating and distributing asymmetric device identification information, such as asymmetric public keys, host system 105 and memory system 110 can support higher security (e.g., stronger authenticity verification) than other techniques that do not perform the distribution of encrypted hardware identification information, or whose distribution may be more easily cloned or stolen, such as techniques that distribute symmetric keys in a potentially insecure manner.

[0040] Figure 2 This document describes an example of a system 200 (e.g., a computing platform) that supports memory system security and authentication using asymmetric keys, based on the examples disclosed herein. System 200 may include a host system 105-a and a memory system 110-a, which may be used as a reference. Figure 1Examples of the corresponding systems described. Host system 105-a and memory system 110-a may implement various techniques for exchanging public keys to support signaling communication between the corresponding systems with identity authenticity (e.g., signature) and integrity (e.g., encryption), as well as other characteristics that can be based on the unique and private encrypted identity of host system 105-a and memory system 110-a. Host system 105-a may include host system controller 106-a and memory system 110-a may include memory system controller 115-a, and in some instances, host system controller 106-a and memory system controller 115-a may be configured to perform one or more of the described operations at host system 105-a and memory system 110-a, respectively. Although the single host system 105-a and single memory system 110-a of the reference system 200 describe the technology, the described technology can be extended to support the implementation of host systems 105 coupled to any number of memory systems 110, or the implementation of memory systems 110 coupled to any number of host systems 105, or the implementation of a network of multiple host systems 105 coupled to multiple memory systems 110.

[0041] Host system 105-a may be an example of a system that uses at least a portion of memory system 110-a (e.g., storage device 240) for information storage, and may include various operations supporting host system 105-a writing information to memory system 110-a or host system 105-a reading information from memory system 110-a, or both. In some instances, host system 105-a may be characterized as “local,” which may refer to a relatively direct or near-end physical, electrical, or otherwise communicatively coupled system. In some other instances, host system 105-a may be characterized as “remote,” which may refer to a relatively remote (e.g., not located in the same place) communication coupled system that may involve one or more wired, wireless, optical, or otherwise relatively distant communication coupled systems, such as cloud applications or otherwise distributed computing systems.

[0042] In some instances, host system 105-a may include one or more host entities 210, which may be coupled to or otherwise associated with the one or more host entities. Host entity 210 may be implemented as a hardware entity, firmware entity, or software entity, and may include various serial, parallel, or hierarchical couplings or logical organizations with or via host system 105-a. In some instances, host entity 210 may request or otherwise execute signaling with memory system 110-a via a common controller or interface (e.g., via host system controller 106-a). In various instances, host entity 210 may be associated with different functions, different feature sets, different permissions, different storage attributes (e.g., data protection attributes), and other different characteristics.

[0043] In some instances, each of the host entities 210 may be associated with a unique identifier (e.g., a confidential identifier, a unique device confidentiality, a unique entity confidentiality), which may contain or support the generation of a corresponding private key for the host entity 210. In some instances, the identifier of the host entity 210 itself may not be private, but a private key for the host entity 210 may be generated (e.g., generated by the host system 105-a) based on the identifier of the host entity 210 (e.g., public or private) and the private identifier of the host system 105-a (e.g., a private master identifier). Such techniques can support the unique identification and authentication (e.g., separation from other host entities 210) of each of the host entities 210 according to the examples disclosed herein.

[0044] Instances of host system 105-a may be associated with original equipment manufacturer (OEM) host entity 210-a, operating system (OS) vendor host entity 210-b, and independent software vendor (ISV) host entity 210-c. In some other instances, host system 105 may include any number of one or more host entities 210 or otherwise associate with said number of one or more host entities, including, but not limited to, one or more OEM host entities 210, OS vendor host entities 210, ISV host entities 210, or other types of host entities. In some instances, host entities 210 may be omitted or otherwise not considered separately. In this case, a master private key may be implemented by host system 105-a (and any applicable host entities 210), which may be based on a single or shared unique identifier of host system 105-a (e.g., a confidential identifier, a unique device secret, or a unique host secret associated with host system 105-a).

[0045] In some instances, host system 105-a may be associated with a location (e.g., key storage device 215) for storing authentication or encryption information (e.g., generated or received keys, certificates). For example, host system 105-a may use key storage device 215 to store one or more private keys or certificates associated with host system 105-a. In some instances, key storage device 215 may be part of host system 105-a, such as an implementation of a dedicated storage component of host system 105-a. Alternatively, one or more components of key storage device 215 may be located outside of host system 105-a, but may be otherwise accessible (e.g., securely) by host system 105-a. In various instances, key storage device 215 may include non-volatile storage locations (e.g., for static keys or keys maintained for a relatively long time), or volatile storage locations (e.g., for ephemeral keys or keys generated relatively frequently in other ways), or both. Although the key storage device 215 is shown as separate from the host system controller 106-a, in some instances, the key storage device 215 may be part of the host system controller 106-a or otherwise associated with the host system controller, for example, also containing the storage location of the firmware of the host system 105-a or the host system controller 106-a.

[0046] In some instances, host system 105-a may contain content 220, which may refer to various types of information stored at host system 105-a. In some instances, according to the examples disclosed herein, content 220 may be accessed or otherwise used to support various key generation (e.g., content-based key generation) or other cryptographic techniques. For example, content 220 may contain firmware of host system 105-a, such as boot code (e.g., Level 2 boot code, "L1" boot code), or firmware security descriptor (FSD), which can be used to establish the operational or cryptographic state of host system 105-a (e.g., firmware state). In some instances, information associated with content 220 may be transferred to memory system 110-a to support various authentication or cryptographic techniques (e.g., for memory system 110-a to generate keys or certificates for operation with memory system 110-a). Although content 220 is shown as separate from host system controller 106-a, in some instances, content 220 may be part of host system controller 106-a or otherwise associated with the host system controller, such as containing the storage location of firmware for host system 105-a or host system controller 106-a.

[0047] Memory system 110-a may include storage devices 240, which may refer to one or more instances of local memory 120 or a collection of storage capacity of one or more memory devices 130, or various combinations thereof included in or otherwise associated with memory system 110-a. In some instances, storage devices 240 may be partitioned or otherwise organized in partitions 245 (e.g., memory ranges, address ranges), which may refer to various subsets or ranges of logical or physical addresses of the associated local memory 120 or memory devices 130. In some instances, partition 245 may be assigned an initial address range and may be updated by assigning different address ranges, including adding additional new addresses, assigning to a subset of the initial address range (e.g., fine-tuning the range), or assigning to entirely new address ranges.

[0048] In some instances, partition 245, or portions thereof, may be assigned or allocated to different functions or attributes. For example, one or more partitions 245 may be associated with one or more corresponding host entities 210 or their corresponding public or private keys. In an instance implementation, partition 245-a may be associated with OEM host entity 210-c, partition 245-b may be associated with OS vendor host entity 210-b, and partition 245-c may be associated with ISV host entity 210-c. In some instances, partition 245-d may be unassigned (e.g., not dedicated to a particular purpose or entity, available space), or may be shared among multiple host entities 210, as well as other instances used to allocate partition 245. In some instances, partition 245 may be used to implement various hierarchical keying or authentication technologies. For example, each partition 245 or a portion of partition 245 may be assigned protection attributes or updated with protection attributes (e.g., enabling or disabling write protection attributes, enabling or disabling read protection attributes), which may be associated with various keys, authentication, or encryption specific to a given host entity 210, or generally, in other instances, with various keys, authentication, or encryption common to host system 105-a.

[0049] In some instances, memory system 110-a may be associated with a location (e.g., key storage device 250) for storing authentication or encryption information (e.g., generated or received keys, certificates). For example, memory system 110-a may use key storage device 250 to store one or more private keys associated with memory system 110-a, or one or more public keys or certificates generated by memory system 110-a, or one or more public keys or certificates received from host system 105-a (or other host system 105, not shown). In some instances, key storage device 250 may be part of memory system 110-a, such as an implementation of a dedicated storage component of memory system 110-a. Alternatively or additionally, key storage device 250 may be located outside of memory system 110-a, but may be otherwise accessible by memory system 110-a (e.g., securely). In various instances, key storage device 250 may include non-volatile storage locations (e.g., for static keys or keys maintained for a relatively long time), or volatile storage locations (e.g., for ephemeral keys or keys generated relatively frequently in other ways), or both. While key storage device 250 is shown separate from storage device 240, in some instances, key storage device 250 may be included within a portion of storage device 240 (e.g., included in a separate or dedicated partition 245). Furthermore, while key storage device 250 is shown separate from memory system controller 115-a, in some instances, key storage device 250 may be part of or otherwise associated with memory system controller 115-a, for example, also including storage locations for firmware for memory system 110-a or memory system controller 115-a (e.g., local memory 120).

[0050] In some instances, memory system 110-a may include a Physically Unclonable Function (PUF) 255 that supports the assignment or generation of a unique identifier for memory system 110-a (e.g., for generating a confidential identifier or unique device secret for memory system 110-a). PUF 255 may include various components or circuit elements having inherent physical characteristics that make PUF 255 unique, which can be used to establish the inherent uniqueness of memory system 110-a. For example, PUF may include a set of one or more transistors, resistors, capacitors, memory cells (e.g., SRAM cells, which in some cases may be included in a reference...) Figure 1The PUF 255 may be located in the local memory 120 described herein, or other circuit elements or combinations thereof, which, when accessed, support the generation of a unique digital signature for memory system 110-a. In some instances, the controller of memory system 110-a (e.g., memory system controller 115-a) may access or otherwise interact with the PUF 255 to generate one or more private keys for memory system 110-a, which may then be used to generate public keys for establishing authenticity or encryption between memory system 110-a and host system 105-a (e.g., or, where applicable, host entity 210). Although the PUF 255 is shown as separate from the key storage device 250, in some instances, the PUF 255 may be included in the key storage device 250 or otherwise interpreted as a portion of the key storage device (e.g., a portion of memory system controller 115-a, a portion of local memory 120 of memory system 110-a).

[0051] In various implementations, the PUF 255 itself, or the signaling generated by the PUF 255, or both, is inaccessible from outside the memory system 110-a. Within portions of the memory system 110-a, such inaccessibility may be supported by various implementations including the PUF 255 and other components involved in the described cryptographic techniques, wherein an attempt to access such components would be destructive to the components, or wherein such components or associated signaling are otherwise shielded from destructive or non-destructive probing or eavesdropping techniques. For example, if not all components of the memory system 110-a, then at least the PUF 255 and other components involved in the described cryptographic techniques (e.g., components involved in processing private keys or unique device secrets, which may include at least a portion or at least a part of the memory system controller 115-a) may be implemented within a continuous semiconductor chip, such as a SoC implementation.

[0052] In some instances, memory system 110-a may include a public key table 260 (e.g., an elliptic curve cryptography public key table), which may be configured to store, organize, or distribute public keys, such as public keys received from host system 105-a or public keys generated at memory system 110-a, or both. In some instances (e.g., in embodiments where host entity 210 is associated with a corresponding public key transmitted by host system 105-a), public key table 260 may maintain a corresponding public key or its mapping for each of OEM host entity 210-a, OS vendor host entity 210-b, and ISV host entity 210-c (e.g., associated with partitions 245-a, 245-b, and 245-c, respectively). Although the public key table 260 is shown as separate from the key storage device 250, in some instances, the public key table 260 may be contained in the key storage device 250 or otherwise interpreted as a portion of the key storage device (e.g., a portion of the memory system controller 115-a, a portion of the local memory 120 of the memory system 110-a).

[0053] In some implementations, public key table 260 may be associated with mappings between public keys and device identifiers, or partitions 245, or protection attributes (e.g., write protection configurations, read protection configurations), or various combinations thereof, as well as other mappings between keys and associated configurations. For example, public key table 260 may provide specific public keys or symmetric keys to mappings of one or more host systems 105 (e.g., host system 105-a) or their host entities 210. Such mappings may also include mappings between such keys and one or more partitions 245, or mappings between such keys or partitions 245 and one or more protection attributes, such as whether partition 245 is configured with read protection, write protection, or both. In some instances, the mapping of public key table 260 may include mappings of keys, host systems 105, or host entities 210 to multiple partitions 245, which may use a common key but have unique protection attributes to support each partition 245. In some instances, the public key table may support a key hierarchy structure that allows the master host system 105 or its associated key to assign partition 245 to another host system 105 or to host entity 210 or its corresponding key.

[0054] In some instances, memory system 110-a may include a platform configuration register (PCR) 270, which may store or measure software state (e.g., version, update status), such as the state of software running on memory system 110-a, and configuration data used by such software (e.g., platform software state for representing memory system 110-a). In some instances, PCR 270 may contain information that can be evaluated to determine whether memory system 110-a has been compromised or may otherwise be untrustworthy. Although PCR 270 is shown as separate from memory system controller 115-a, in some instances, PCR 270 may be part of or otherwise associated with memory system controller 115-a, such as a location associated with firmware for memory system 110-a or memory system controller 115-a (e.g., local memory 120). Such techniques may enable PCR 270 to store or measure the state of such firmware, which can be used to assess whether such firmware has been adversely updated (e.g., to assess whether memory system 110-a is authenticable).

[0055] In some instances, memory system 110-a may include a replay-protected memory block (RPMB) 265, which can be provided as a means of storing data in an authenticated and replay-protected manner, the data being read and written only via successfully authenticated read and write access. In some instances, RPMB 265 may contain information that can be evaluated to determine whether signaling exchanged with memory system 110-a has been intercepted and replayed, indicating whether one or more devices or connections of system 200 are untrusted. Although RPMB 265 is shown as separate from memory system controller 115-a, in some instances, RPMB 265 may be part of or otherwise associated with memory system controller 115-a, for example, containing a storage location (e.g., local memory 120) for firmware for memory system 110-a or memory system controller 115-a. In some instances, RPMB 265 may be associated with a fixed size, a fixed set of addresses, or both.

[0056] In some instances, memory system 110-a may contain content 280, which may refer to various types of information stored at memory system 110-a. In some instances, according to the examples disclosed herein, content 280 may be accessed or otherwise used to support various key generation (e.g., content-based key generation) or other cryptographic techniques. For example, content 280 may contain firmware of memory system 110-a, such as boot code (e.g., first-level boot code, "L0" boot code, second-level boot code, "L1" boot code, boot code that can be called or read by host system 105-a), or FSD, which can establish the operational or cryptographic state of memory system 110-a. In some instances, information associated with content 280 may be available to memory system 110-a to support various authentication or cryptographic techniques (e.g., for generating certificates that operate with host system 105-a). Although content 280 is shown as separate from memory system controller 115-a, in some instances, content 280 may be a portion of memory system controller 115-a or otherwise associated with said memory system controller, for example, containing storage locations for firmware for memory system 110-a or memory system controller 115-a. Furthermore, although content 280 is shown as separate from storage device 240, in some instances, content 280 may refer to information contained in a portion of storage device 240 (e.g., contained in a separate or dedicated partition 245). In some implementations, content 280 may receive information from or refer to one or more aspects of PCR 270.

[0057] One or more components of system 200 may be configured to implement asymmetric key distribution to establish authenticated signaling, encrypted signaling, or both (e.g., based on authenticated system identity) between host system 105-a and memory system 110-a. This may include implementing cryptographic security functionality directly within memory system 110-a (e.g., leveraging the capabilities of memory system controller 115-a to support various techniques for asymmetric cryptography). In some instances, such techniques may involve transmitting substantially public device identification information between host system 105-a and memory system 110-a, supporting private authentication for the respective system (e.g., device-specific or hardware-specific authentication, without attempting to maintain confidentiality or avoid exposure of the private or confidential key material exchanged corresponding to the respective device). In some instances, such asymmetric cryptography can be used to derive equivalents or other symmetric keys on each side of the signaling exchange (e.g., at each of host system 105-a and memory system 110-a) using a common secret that is not transmitted between host system 105-a and memory system 110-a. This can take full advantage of the efficiency of symmetric key techniques used for authenticated or encrypted signaling relative to asymmetric key techniques. In some instances, such techniques can be implemented to establish a virtual authentication channel 205 between host system 105-a and memory system 110-a, which can be used to transmit signaling (e.g., encrypted signaling, unencrypted signaling) and associated signatures (e.g., asymmetric signatures, such as Elliptic Curve Digital Signature Algorithm (ECDSA) signatures; symmetric signatures, such as Hash Message Authentication Code (HMAC) signatures) between host system 105-a and memory system 110-a.

[0058] In some instances, system 200 may be configured to support the signing and verification (e.g., authentication) of signaling between host system 105-a and memory system 110-a (e.g., based on signed command signaling, signed request signaling, signed data signaling, or signed response signaling). This can be implemented to authenticate the transport system carrying such signaling, or to ensure that the signaling has not been altered before being received by the receiving system, or both. According to such techniques, the receiving system may be able to evaluate the received signaling to determine whether the transmitted signaling was transmitted by an unverified or unauthorized transport system, or whether the transmitted signaling has been altered or otherwise compromised. In some instances, such techniques may support a one-to-many security arrangement because multiple receiving systems may be able to implement the same public key of the transport system (e.g., the same public key of an asymmetric key pair) associated with a single private key of the transport system (e.g., a single private key of an asymmetric key pair).

[0059] In some instances used for signing and verifying signaling between host system 105-a and memory system 110-a, the signature for a given instance of signaling (e.g., message, command, request, packet, response) can be derived from an instance of signaling that is hashed by a function (e.g., hash function, cryptographic hash algorithm) or otherwise processed, which receives the instance of signaling and a private key associated with the transport system as input. The output of such a function (e.g., signature, hash digest) can be recreated using the same function with the same signaling instance and the same private key associated with the transport system or an associated public key associated with the transport system (e.g., the public key of an asymmetric key pair). In one instance, for a signaling instance associated with 1 megabyte of program operation, a hash function based on 1 megabyte of data and a private key could be a 256-bit signature or hash digest.

[0060] To support the verification of the authenticity of the transmission system, the transmission system may transmit a signaling instance and a corresponding signature that can be received by the receiving system. The receiving system may have received or otherwise generated the associated public key of the transmission system, and therefore can generate a trial signature based on the received signaling instance and the associated public key of the transmission system. If the trial signature matches the received signature, the receiving system can determine that the transmission system is reliable (e.g., the signaling instance is a transmission from a trusted system) and can continue processing or otherwise perform responsive actions on the received signaling instance. In some implementations, signature generation can be configured such that the generated signatures will be different even when the signaling instances are the same. In such implementations, the signature generation and verification operations may further be based on random numbers, temporary values, or monotonic counters understood to be used by both the transmission and receiving systems.

[0061] In some instances, system 200 may be configured to support encryption and decryption processing of signaling between host system 105-a and memory system 110-a (e.g., based on encrypted signatures, encrypted command signaling, encrypted request signaling, encrypted data signaling, or encrypted responses), which may be implemented to ensure that the content of such signaling is not intercepted and decrypted or otherwise processed (e.g., to maintain the integrity of the signaling itself). According to such techniques, the transport system may encrypt the signaling instance for transmission using a key known to the transport system (e.g., the key of a symmetric key pair), and the receiving system may decrypt the received such signaling instance using a key known to the receiving system (e.g., the key of the same symmetric key pair), which may be the same as the symmetric key known to the transport system, or may otherwise be equivalent to or usable for such decryption. In some instances, such techniques may support a one-to-one security arrangement because the symmetric key pair can be understood as only a single transport system and a single receiving system (e.g., when the symmetric key pair is a unique identifier based on each of the transport and receiving systems). However, some encryption techniques can support arrangements other than one-to-one security arrangements, such as when the symmetric key is based on a unique identifier from more than two systems.

[0062] Some implementations of the described techniques may utilize asymmetric cryptography, where the public key associated with host system 105-a can be uploaded to one or more storage systems 110 (e.g., storage system 110-a) without exposing the private key of host system 105-a. This prevents malicious actors from stealing the key and impersonating the true key holder (e.g., impersonating host system 105-a). Such techniques may also allow for the replacement of the public key, which may differ from other techniques, such as those associated with RPMB or replay protected monotonic counters (RPMC). In some instances, such asymmetric cryptographic techniques may facilitate the use of public key infrastructure (PKI) technologies, where keys can be verified via a standardized chain of digital certificates.

[0063] In some implementations, public key exchange can support the generation of symmetric keys at each of the host system 105-a and memory system 110-a using techniques such as Diffie-Hellman key exchange or elliptic curve techniques, enabling the sharing of symmetric secrets between the device and the host without exposing the private keys of the respective systems. In some implementations, asymmetric Diffie-Hellman key exchange can be performed between the host system 105-a and memory system 110-a to generate symmetric keys, which are then used to achieve better performance at either the host system 105-a or memory system 110-a for authentication, encryption, or both. Furthermore, the same algorithm shared by the host system 105-a and memory system 110-a can be used to derive ephemeral symmetric keys, making it more difficult for adverse actors to extract or copy such keys; this is based on various techniques for generating ephemeral keys used for duration initiation or event initiation.

[0064] In some instances, the exchange of public keys may be associated with the creation of digital certificates, which may contain various signaling or other interactions with one or more certificate authorities or registration authorities, or may involve self-signed certificates or various combinations thereof. For example, host system 105-a, a cloud authority, or other centralized certification authority communicating with host system 105-a may generate a certificate signing request (CSR), which may be an instance of a self-signed certificate proving that storage system 110-a has a private key associated with the public key in the CSR. In some instances, such CSRs may be transmitted from storage system 110-a to a centralized certification authority as part of a manufacturing operation (e.g., for manufacturing storage system 110-a). In some implementations, in response to the identity of storage system 110-a being verified (e.g., by a cloud authority, vendor certification verification), a manufacturer-approved certificate may be provided to host system 105-a, storage system 110-a, or both. In some instances, such techniques may support requests for the system to download manufacturer-approved certificates (e.g., certificates approved by a certificate authority) or download CSRs.

[0065] Figure 3 This document describes an example of a process flow 300 that supports security and authentication of a memory system using asymmetric keys, based on the examples disclosed herein. The operation of process flow 300 can be performed by host system 105-b and memory system 110-b, and may be used as a reference. Figure 1 and 2Examples of the corresponding systems described. Aspects of process flow 300 may be implemented by one or more controllers (e.g., one or more corresponding controllers at each of host system 105-b and memory system 110-b) and other components. Alternatively or additionally, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., stored in the memory of host system 105-b and memory system 110-b or in corresponding firmware coupled to said host system and said memory system). For example, the instructions, when executed by a controller, may cause the controller to perform one or more operations of process flow 300.

[0066] In some instances, process flow 300 may include the generation of a public key that can be transferred between host system 105-b and memory system 110-b, which may be referred to as an asymmetric key or asymmetric public key (e.g., a public key for an asymmetric key pair, and public keys for corresponding private keys of the asymmetric key pair). The generation of such a public key may be based on a private key maintained at the respective system, wherein such private key is not shared outside the respective system. This technique enables host system 105-b and memory system 110-b to sign various transmitted signaling (e.g., for authenticating the transmission system) or encrypt various transmitted signaling (e.g., for information integrity), or both, without exchanging private identification information unique to each system. Therefore, this technique improves the ability to communicate with authenticity and integrity compared to other techniques that do not perform encryption hardware identification information distribution, or whose distribution may be more easily cloned or stolen (e.g., techniques that distribute symmetric keys in a potentially insecure manner).

[0067] For example, at 305, host system 105-b may generate a host system public key, which may be at least partially based on the host system private key (e.g., calculated using the host system private key). In various instances, the host system private key may be stored at host system 105-b, or otherwise generated at the host system using a private identifier such as a fuse configuration, an identity stored in non-volatile memory, the PUF of host system 105-b, or some other unique identifier of host system 105-b, which prevents cloning or extraction. In some instances, the host system private key may be generated based on a combination of a unique identifier (e.g., a unique device secret of host system 105-b) and content stored at host system 105-a (e.g., in content 220). In some instances, the host system public key generated at 305 may be associated with a specific address range (e.g., partition 245 or a portion thereof) or memory protection attributes (e.g., read protection, write protection) or a combination thereof at a particular host entity 210 or memory system 110-b. In some instances, such public key attributes may not be associated with the host system public key generated at 305, but may later be associated with one or more symmetric keys generated at least in part based on the host system public key, or may later be assigned by memory system 110-a.

[0068] In some instances (e.g., when host system 105-b and memory system 110-b are configured to support symmetric keys, encryption, or both), at 310, memory system 110-b may generate a memory system public key that is at least partially based on the memory system private key (e.g., calculated using the memory system private key). In various instances, a private identifier such as a fuse configuration, an identity stored in non-volatile memory, PUF 255, or some other unique identifier of memory system 110-b may be used to generate the memory system private key at memory system 110-b, which prevents cloning or extraction. In some instances, the memory system private key may be generated based on a combination of a unique identifier (e.g., the unique device secret of memory system 110-b) and content stored at memory system 110-b (e.g., in content 280). In some instances, the memory system public key generated at 310 may be associated with a specific address range (e.g., partition 245 or a portion thereof) or memory protection attributes (e.g., read protection, write protection) or a combination thereof at memory system 110-b. In some instances, the public key associated with memory system 110-b may be paired with or otherwise linked to the corresponding host system 105 or host system public key (e.g., the host system public key generated at 305) via public key table 260. In some instances, such keying attributes may not be associated with the memory system public key generated at 310, but may later be associated with one or more symmetric keys generated at least in part based on the host system public key.

[0069] In some instances, process flow 300 may include the exchange of generated public keys between host system 105-b and memory system 110-b. For example, at 315, host system 105-b may transmit a host system public key generated at 305, which may be received by memory system 110-b. In some instances (e.g., when host system 105-b and memory system 110-b are configured to support symmetric keys, encryption, or both), at 320, memory system 110-b may transmit a memory system public key generated at 310, which may be received by host system 105-b. In some instances, the transmitted public key may be stored at the corresponding receiving system (e.g., in key storage device 215, in key storage device 250), for example, stored in the non-volatile storage device of the corresponding receiving system or otherwise communicated with the corresponding receiving system. In some other instances, such transmitted or received public keys may not be stored, but keys generated based on such transmitted or received public keys may be stored after further processing. In some instances, such asymmetric public keys may be updatable, wherein such updates (e.g., according to one or more operations of 305 or 310) may be initiated based on a timer or event, and the subsequently generated updated or replaced asymmetric public keys may thus be transmitted from the generating system to the receiving system.

[0070] In some instances, process flow 300 may include the generation of a symmetric key by host system 105-b and memory system 110-b, which may be computed at least in part based on the correspondingly received public key. Such a symmetric key may be generated to be equal to or otherwise equivalent between the two systems (e.g., as a shared secret), or may be otherwise operable to enable one system to authenticate information signed using the other system or to decode information encoded using the other system, or both, although the transmission of private information is avoided. For example, at 325, host system 105-b may generate a symmetric key that may be at least in part based on the memory system public key transmitted at 320 and the host system 105-b's private key (e.g., computed using the memory system public key and the private key). Furthermore, at 330, memory system 110-b can also generate a symmetric key, which can be at least partially based on the host system public key transmitted at 315 and the private key of memory system 110-b (e.g., calculated using the host system public key and the private key). In some instances, such symmetric keys can be generated using Diffie-Hellman techniques or other exponential key exchange or generation protocols (including elliptic curve techniques). In some instances, the generated symmetric key can be stored at the generation system (e.g., in key storage device 215, in key storage device 250), for example, stored in the non-volatile storage device of the corresponding generation system or otherwise communicated with the corresponding generation system.

[0071] While in some instances the symmetric key (e.g., the "first" symmetric key) generated from the maintained private key and the received public key can be implemented directly in the techniques disclosed herein, in other instances such a symmetric key can be used as input for further key generation, such as the generation of ephemeral keys (e.g., the "second" symmetric key, an ephemeral symmetric key). For example, at each of 325 and 330, or in some other sequential operation, each of the host system 105-b and the memory system 110-b can generate a corresponding ephemeral key, which can be relatively temporary in nature. In some instances, the generation of such ephemeral keys can be duration-initiated, for example, generation initiated at a timer value that satisfies a threshold (e.g., at the host system 105-b, at the memory system 110-b, or both). In some instances, the generation of such ephemeral keys can be event-driven, such as upon powering on the memory system 110-b or host system 105-b (e.g., generating an ephemeral key per power cycle), upon resetting the memory system 110-b or host system 105-b, or upon encountering an error state in the memory system 110-b or host system 105-b. In some instances, either or both of the host system 105-b or memory system 110-b can be configured to transmit signaling as a command or request to cause another system to initiate the generation or replacement of ephemeral keys. This signaling can be associated with, or triggered or scheduled by, a signaling system that has already performed ephemeral key generation or regeneration, as well as other triggering events. In some instances, the generated ephemeral keys may be stored in volatile storage devices (e.g., in key storage device 250, in key storage device 215) or otherwise communicated with the corresponding generation system, which may be implemented to avoid fatigue or durability problems associated with the periodic updates of ephemeral keys in some non-volatile storage architectures. However, in some implementations (e.g., where fatigue of non-volatile memory cells is not considered), the ephemeral keys may be stored in non-volatile storage devices.

[0072] In some instances, process flow 300 may include determining (e.g., by host system 105-b) to transmit signaling to memory system 110-b, which may be associated with commands to access memory system 110-b (e.g., read commands, write commands), or commands or requests to reconfigure memory system 110-b (e.g., requests to modify operating parameters, requests to enter operating mode, requests to implement data protection attributes, polling of the status or configuration of memory system 110-b), and other requirements, commands, or other control signaling that may or may not be accompanied by other data (e.g., write data). Such signaling may be signed or encrypted, or both, depending on the described techniques used by host system 105-b and memory system 110-b with asymmetric keys.

[0073] In some instances, to support authentication of such signaling, or authentication of the transmitter of such signaling (e.g., for authentication of host system 105-b), at 335, host system 105-b may sign the signaling or at least a portion thereof based at least in part on a private key associated with host system 105-b (e.g., calculated using said private key). In some instances, such signing or the configuration of such signing may be based on the type or characteristics of the signaling. For example, in some implementations, signing is performed only on specific types of signaling, such as only on specific access commands (e.g., signing read commands, signing write commands, signing commands that change protection attributes).

[0074] In some instances, the signature at 335 may be at least partially based on a symmetric key generated at 325, which may be more secure or efficient than a signature based on a private key associated with host system 105-b. The determination of signing signaling with such a symmetric key may be based on the configuration (e.g., operating mode, mode register settings) or indication capabilities of host system 105-b, or the configuration or indication capabilities of memory system 110-b, or both. In some instances, the indication of whether signaling has been signed using a private key associated with host system 105-b or using a symmetric key generated at 325 may be indicated as part of the transmitted signaling, or may have been indicated by host system 105-b to memory system 110-b in an earlier transmission (e.g., an earlier instance of control signaling), or may have been requested by memory system 110-b. In other words, host system 105-b or memory system 110-b, or both, may be configured to dynamically sign signaling based on a private key associated with the transmitting device or a generated symmetric key. In some instances, such signatures may be attached to data contained in or otherwise accompanying signaling, which may or may not be encrypted.

[0075] In some instances, to support the integrity of such signaling (e.g., information integrity), at 340, host system 105-b may encrypt the signaling or at least a portion thereof based at least in part on a symmetric key generated at 325 (e.g., calculated using said symmetric key). In some instances, such encryption or the configuration of such encryption may be based on the type or characteristics of the signaling, or associated information. For example, in some implementations, only specific types of signaling are encrypted, such as only specific access commands (e.g., read commands are encrypted, write commands are encrypted, data associated with write commands is encrypted, commands that change protection attributes are encrypted).

[0076] At 345, host system 105-b can transmit signaling, at least a portion of which may be signed, encrypted, or both signed and encrypted, and which may be received by memory system 110-b. In some instances, the signaling at 340 may contain or be accompanied by a mark or other indication that the signaling has been signed, encrypted, or both signed and encrypted, such as vendor-specific bits that accompany or are otherwise associated with the signaling. Thus, memory system 110-b can process such indications to evaluate whether the received signaling at 345 can or should be authenticated, decrypted, or both (e.g., for determining whether to perform operation 350, operation 355, or both operations 350 and 355).

[0077] For example, at 350, memory system 110-b may attempt to authenticate the signaling at 345 (e.g., for verifying or authenticating the host system 105-b as the transmitter of the signaling, or the host entity 210 associated with host system 105-b). In various instances, the authentication evaluation at 350 may be based on a configuration or operating mode associated with authentication using an asymmetric key or using a symmetric key or both, which may be based on the indication of the signaling at 345, or previous signaling from host system 105-b. For example, to support authentication of the signaling or its transmitter, memory system 110-b may at least partially authenticate the signaling or at least a portion thereof based on (e.g., using) the host system public key received at 315 or at least partially based on the symmetric key generated at 330.

[0078] In some instances, at 355, memory system 110-b may attempt to decrypt the signaling at 345. In various instances, decryption at 355 may be based on the configuration or operating mode of host system 105-b, memory system 110-b, or both, or may be based on an indication of the signaling itself. For example, to support signaling decryption, memory system 110-b may at least partially decrypt the signaling or at least a portion thereof based on (e.g., using) the symmetric key generated at 330. In some instances, decryption at 355 may be performed only if the signaling is authenticated at 350.

[0079] At 360, memory system 110-b may evaluate whether to perform an operation in response to signaling at 345. For example, if authentication at 350 supports the determination of signaling at 345 transmitted by a trusted system (e.g., by host system 105-b), then memory system 110-b may determine to perform a responsive action, such as performing access to memory system 110-b commanded by signaling at 345, or updating operating parameters of memory system 110-b commanded or requested by signaling at 345. In some instances, such an operation may include performing an access command based on information decrypted at 355 (e.g., write information). Alternatively, if authentication at 350 does not support the determination of signaling at 345 transmitted by a trusted system (e.g., by host system 105-b), then memory system 110-b may determine not to perform a responsive operation based on signaling at 345, wherein such determination may or may not be signaled back to host system 105-b.

[0080] In some instances, host system 105-b, memory system 110-b, or both, may be configured to exchange response signaling based on (e.g., in response to) transmitted signaling (e.g., in response to signaling at 345). For example, in response to signaling associated with an access command from host system 105-b, memory system 110-b may transmit an acknowledgment of receipt of the command, an indication of whether the command access was executed, an identification of whether the command access was successful, or an identification of whether the access command or its transport system was authenticated, and other responsive signaling. In some instances, such a response may include information from the original command to confirm the action, such as returning or reflecting data from a write operation (e.g., unencrypted, encrypted, or hashed) to confirm the accuracy of the write. In some instances (e.g., in response to a read command), such a response may include information from memory system 110-b (e.g., from storage device 240), such as the requested read data (e.g., unencrypted or encrypted). In various implementations, such responses may be signed, encrypted, or both signed and encrypted, and may incorporate techniques similar to those used in 335 and 340, or different operations (e.g., based on configuration or operating mode, based on the type of signaling associated with such responses).

[0081] In some instances, to support authentication of such responses or the transmitter of such responses (e.g., for authentication of memory system 110-b), at 365, memory system 110-b may sign the response or at least a portion thereof based at least in part on a private key associated with memory system 110-b (e.g., calculated using said private key). In some instances, such signing or the configuration of such signing may be based on the type or characteristics of the response. For example, in some implementations, only responses to specific types of signaling are signed, such as only responses to specific access commands (e.g., responses to read commands are signed, responses to write commands are signed, responses to commands that change protection attributes are signed). In some instances, the signature at 365 may be based at least in part on a symmetric key generated at 330, which may be more secure or efficient than a signature based on the private key associated with memory system 110-b.

[0082] In some instances, to support the integrity of such responses (e.g., response integrity, information integrity), at 365, the memory system 110-b may encrypt the response or at least a portion thereof based at least in part on a symmetric key generated at 330 (e.g., calculated using said symmetric key). In some instances, such encryption or the configuration of such encryption may be based on the type or characteristics of the response or associated information. For example, in some implementations, only responses to specific types of response signaling are encrypted, such as only responses to specific access commands (e.g., responses to write commands are encrypted, responses to read commands are encrypted, data associated with read commands is encrypted, responses to commands that change protection attributes are encrypted).

[0083] At 360, memory system 110-b can transmit a response, at least a portion of which may be signed, encrypted, or both signed and encrypted, and which may be received by host system 105-b. In some instances, signaling at 370 may include or be accompanied by a tag indicating that the signaling is signed, encrypted, or both signed and encrypted, or other indications, such as vendor-specific bits accompanying or otherwise associated with the response signaling. Therefore, host system 105-b can process such indications to evaluate whether the received response at 370 can or should be authenticated, decrypted, or both (e.g., to determine whether the response is trustworthy).

[0084] For example, at 375, host system 105-b may attempt to authenticate the response signaling at 370 (e.g., for verifying or authenticating the transmitter in response, memory system 110-b). In various instances, the authentication evaluation at 375 may be based on a configuration or operating mode associated with authentication using an asymmetric key or using a symmetric key or both, which may be based on the response signaling at signaling 345 or 370, or on indications from previous signaling from host system 105-b or memory system 110-b. For example, to support authentication of the response signaling or its transmitter, host system 105-b may at least partially authenticate the signaling or at least a portion thereof based on (e.g., using) the memory system public key received at 320 or at least partially based on the symmetric key generated at 325.

[0085] In some instances, at 375, host system 105-b may attempt to decrypt the signaling at 370. In various instances, decryption at 375 may be based on the configuration or operating mode of host system 105-b, memory system 110-b, or both, or may be based on an indication of signaling at 345 or response signaling at 370. For example, to support decryption of response signaling, host system 105-b may at least partially decrypt the signaling or at least a portion thereof based on (e.g., using) the symmetric key generated at 325. In some instances, decryption at 375 may be performed only if authentication at 375 is successful.

[0086] Figure 4 A block diagram 400 illustrates a host system 420 that supports memory system security and authentication using asymmetric keys, based on the examples disclosed herein. Host system 420 may be used as a reference. Figures 1 to 3 Examples of various aspects of the described host system. Host system 420 or its various components may be examples of constructs for performing various aspects of memory system security and authentication using asymmetric keys as described herein. For example, host system 420 may include key transmission component 425, key receiving component 430, signaling transmission component 435, key management component 440, response receiving component 445, key storage component 450, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0087] Key transmission component 425 may be configured or otherwise supported for transmitting a public key (e.g., an asymmetric key) associated with host system 420, wherein the public key is at least partially based on a private key associated with host system 420. Signaling transmission component 435 may be configured or otherwise supported for transmitting signaling (e.g., to a memory system), wherein at least a portion of the signaling is signed based at least partially on the private key associated with host system 420. In some instances, the signaling may contain commands to access the memory system or commands to modify operating parameters of the memory system.

[0088] In some instances, the key receiving component 430 may be configured or otherwise supported for receiving a public key associated with a memory system, wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system 420. In some instances, the signaling transmission component may be configured to encrypt at least a portion of the signaling based at least partially on the private key associated with the host system 420, the public key associated with the memory system, or both.

[0089] In some instances, the key management component 440 may be configured or otherwise supported to generate a symmetric key based at least in part on a private key associated with the host system 420 and a received public key associated with the memory system, and to encrypt at least a portion of signaling based at least in part on the symmetric key. In some instances, the key storage component 450 may be configured or otherwise supported to store the symmetric key in a non-volatile storage location (e.g., at or in communication with the host system 420).

[0090] In some instances, the key management component 440 may be configured or otherwise supported to support means for generating a second symmetric key (e.g., a short key) that is at least partially based on the symmetric key, and to encrypt at least a portion of the signaling based at least partially on the second symmetric key. In some instances, the key storage component 450 may be configured or otherwise supported to support means for storing the second symmetric key in a volatile storage location (e.g., at or in communication with the host system 420). In some instances, the generation of the second symmetric key may be at least partially based on the memory system being powered on or reset. In some instances, the generation of the second symmetric key may be at least partially based on a threshold being met since the previous key generation. In some instances, the key management component 440 may be configured or otherwise supported to support means for receiving signaling for the generation of the start key (e.g., from the memory system), and to perform the generation of the second symmetric key in response to the signaling for the generation of the start key.

[0091] In some instances, the private key associated with the host system may be associated with a host entity of host system 420, and the key management component 440 may be configured or otherwise supported for generating a public key associated with host system 420 based at least in part on the private key associated with the host entity of host system 420. In some instances, the public key associated with the host system may be associated with an address range of a memory system. In some instances, the address range may be associated with memory protection attributes.

[0092] In some instances, the key management component 440 may be configured or otherwise supported to generate a public key associated with the host system 420 based at least in part on the master host private key and the private key associated with the entity of the host system 420.

[0093] In some instances, the key receiving component 430 may be configured or otherwise supported to include means for receiving a public key associated with a memory system, wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system 420. In some instances, the response receiving component 445 may be configured or otherwise supported to include means for receiving responses to signaling. In some instances, the response receiving component 445 may be configured or otherwise supported to include means for attempting to authenticate at least a portion of the response, at least partially based on the public key associated with the memory system.

[0094] Figure 5 A block diagram 500 illustrates a memory system 520 that supports memory system security and authentication using asymmetric keys, based on the examples disclosed herein. The memory system 520 may be used as a reference. Figures 1 to 3 Examples of various aspects of the described memory system. Memory system 520 or its various components may be examples of constructs for implementing the various aspects of memory system security and authentication using asymmetric keys as described herein. For example, memory system 520 may include a key transmission component 525, a key receiving component 530, a signaling receiving component 535, a key management component 540, a response transmission component 545, a key storage component 550, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0095] Key receiving component 530 may be configured or otherwise supported to receive a public key associated with a host system, wherein the public key associated with the host system is at least partially based on a private key associated with the host system. Signaling receiving component 535 may be configured or otherwise supported to receive signaling from the host system. In some instances, signaling receiving component 535 may be configured or otherwise supported to determine a response to signaling (e.g., what responsive action to take or whether to take a responsive action, such as accessing memory system 520) based at least partially on an attempt to authenticate at least a portion of the signaling, wherein the attempt to authenticate at least a portion of the signaling is at least partially based on the public key associated with the host system. In some instances, the signaling may contain a command to access memory system 520 or a command to modify operating parameters of memory system 520.

[0096] Key transmission component 525 may be configured or otherwise supported for transmitting a public key (e.g., an asymmetric key) associated with memory system 520, wherein the public key associated with memory system 520 is at least partially based on a private key associated with memory system 520 and is different from the public key associated with host system. In some instances, signaling receiving component 535 may be configured or otherwise supported for attempting to decrypt at least a portion of signaling based at least partially on the private key associated with memory system 520, the public key associated with host system, or both.

[0097] In some instances, the key management component 540 may be configured or otherwise supported to generate a symmetric key based at least in part on a private key associated with the memory system 520 and a public key associated with the host system, and to attempt to decrypt at least a portion of the signaling based at least in part on the symmetric key. In some instances, the key storage component 550 may be configured or otherwise supported to store the symmetric key in a non-volatile storage location (e.g., at or in communication with the memory system 520).

[0098] In some instances, the key management component 540 may be configured or otherwise supported to support means for generating a second symmetric key (e.g., a short key) that is at least partially based on the symmetric key, and to attempt to decrypt at least a portion of the signaling may be at least partially based on the second symmetric key. In some instances, the key storage component 550 may be configured or otherwise supported to support means for storing the second symmetric key in a volatile storage location (e.g., at or in communication with the memory system 520). In some instances, the generation of the second symmetric key may be at least partially based on the memory system 520 being powered on or reset. In some instances, the generation of the second symmetric key may be at least partially based on a threshold being met since the previous key generation. In some instances, the key management component 540 may be configured or otherwise supported to support means for receiving signaling for the generation of the start key (e.g., from a host system), and may perform the generation of the second symmetric key in response to the signaling for the generation of the start key.

[0099] In some instances, the public key associated with the memory system may be associated with an address range of the memory system 520. In some instances, the address range may be associated with memory protection attributes.

[0100] In some instances, key transmission component 525 may be configured or otherwise supported for transmitting a public key associated with memory system 520 (e.g., to a host system), wherein the public key associated with memory system 520 is at least partially based on a private key associated with memory system 520 and is different from the public key associated with the host system. In some instances, response transmission component 545 may be configured or otherwise supported for transmitting a response to signaling (e.g., to a host system), and may sign at least a portion of the response based at least partially on the private key associated with memory system 520.

[0101] In some instances, the key management component 540 may be configured or otherwise support components for generating private keys associated with the memory system 520, based at least in part on the physical non-cloning capabilities at the memory system 520.

[0102] Figure 6 The flowchart illustrates a method 600 for supporting security and authentication of memory systems using asymmetric keys, based on examples disclosed herein. The operation of method 600 can be implemented by a host system or its components as described herein. For example, the operation of method 600 can be implemented by a reference... Figures 1 to 4The described host system executes the method. Aspects of method 600 may be implemented by a controller and other components. Alternatively, aspects of method 600 may be implemented as instructions stored in memory (e.g., firmware coupled to the host system and stored in its memory). For example, if the instructions are executed by a controller, the controller may perform the operation of method 600. In some instances, the host system may execute a set of instructions to control functional elements of the device to perform the described function. Alternatively, the host system may use dedicated hardware to perform aspects of the described function.

[0103] At 605, the method may include transferring a public key associated with a host system to a memory system, wherein the public key associated with the host system is at least partially based on a private key associated with the host system. The operation at 605 may be performed according to examples disclosed herein. In some instances, it may be provided by reference... Figure 4 The described key transfer component 425 performs the operation of 605.

[0104] At 610, the method may include transmitting signaling to a memory system, wherein at least a portion of the signaling is signed based at least in part on a private key associated with the host system. The operation of 610 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 610 may be derived from references... Figure 4 The signaling transmission component 435 described is executed.

[0105] In some instances, the apparatus as described herein may perform one or more methods, such as method 600. The apparatus may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0106] Aspect 1: A method or apparatus comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing the following operations: transmitting a public key associated with a host system to a memory system, wherein the public key associated with the host system is at least partially based on a private key associated with the host system; and transmitting signaling to the memory system, wherein at least a portion of the signaling is signed by the host system at least partially based on the private key associated with the host system.

[0107] Aspect 2: According to the method of aspect 1, the signaling includes a command to access the memory system or a command to modify the operating parameters of the memory system.

[0108] Aspect 3: The method or apparatus according to any one of aspects 1 to 2 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for performing the following operations: receiving a public key associated with the memory system, wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system; and encrypting at least a portion of the signaling based at least partially on the private key associated with the host system, the public key associated with the memory system, or both.

[0109] Aspect 4: The method or apparatus according to aspect 3 further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing the following: generating a symmetric key based at least in part on the private key associated with the host system and the public key associated with the memory system, wherein at least a portion of the signaling is encrypted based at least in part on the symmetric key.

[0110] Aspect 5: The method or apparatus according to aspect 4 further includes operations, features, circuitry, logic, components, or instructions or any combination thereof for performing the following: storing the resulting symmetric key in a non-volatile storage location.

[0111] Aspect 6: The method or apparatus according to any one of aspects 4 to 5 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for performing the following: generating a second symmetric key at least partially based on the symmetric key, wherein the at least portion of the signaling is encrypted at least partially based on the second symmetric key.

[0112] Aspect 7: The method or apparatus according to aspect 6 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for performing the following: storing the resulting second symmetric key in a volatile storage location.

[0113] Aspect 8: The method or apparatus according to any one of aspects 6 to 7 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for performing the following: generating the second symmetric key at least in part based on the power-on or reset of the memory system.

[0114] Aspect 9: The method or apparatus according to any one of aspects 6 to 8 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for performing the following: generating the second symmetric key based at least in part on a threshold being satisfied since the previous key was generated.

[0115] Aspect 10: The method or apparatus according to any one of aspects 6 to 9 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for performing the following: (e.g., from a memory system) receiving signaling generated by a start key, and generating a second symmetric key in response to the signaling generated by the start key.

[0116] Aspect 11: The method or apparatus according to any one of Aspects 4 to 10, wherein the private key is associated with a host entity of the apparatus, the method or apparatus further comprising operations, features, circuitry, logic, components or instructions or any combination thereof for generating the public key associated with the host system, at least in part, based on the private key associated with the host entity of the host system.

[0117] Aspect 12: The method or apparatus according to any one of aspects 4 to 11, wherein the public key or the symmetric key associated with the host system is associated with an address range of the memory system.

[0118] Aspect 13: The method or apparatus according to aspect 12, wherein the address range is associated with memory protection attributes.

[0119] Aspect 14: The method or apparatus according to any one of aspects 1 to 13 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for performing the following: generating the public key associated with the host system based at least in part on the host private key and the private key associated with the entity of the host system.

[0120] Aspect 15: The method or apparatus according to any one of aspects 1 to 14 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for performing the following operations: receiving a public key associated with the memory system, wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system; receiving a response to the signaling; and attempting to authenticate at least a portion of the response, at least partially based on the public key associated with the memory system.

[0121] Figure 7 The flowchart illustrates a method 700 for supporting security and authentication of memory systems using asymmetric keys, based on examples disclosed herein. The operation of method 700 can be implemented by a memory system or its components as described herein. For example, the operation of method 700 can be implemented by reference to... Figures 1 to 3The memory system described in section 5 executes the method. Aspects of method 700 may be implemented by a controller and other components. Alternatively, aspects of method 700 may be implemented as instructions stored in memory (e.g., firmware coupled to the memory system and stored in the memory of the memory system). For example, if the instructions are executed by a controller, the controller may perform the operation of method 700. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0122] At 705, the method may include (e.g., at a memory system) receiving a public key associated with a host system, wherein the public key associated with the host system is at least partially based on a private key associated with the host system. The operation of 705 may be performed according to examples disclosed herein. In some instances, it may be provided by reference... Figure 5 The described key receiving component 530 performs the operation of 705.

[0123] At 710, the method may include (e.g., at a memory system) receiving signaling from a host system. The operation of 710 may be performed according to examples disclosed herein. In some instances, it may be provided by reference... Figure 5 The signaling receiving component 535 described performs the operation of 710.

[0124] At 715, the method may include determining a response to signaling based at least in part on an attempt to authenticate at least a portion of the signaling, wherein the attempt to authenticate at least a portion of the signaling is based at least in part on a public key associated with the host system. The operation of 715 may be performed according to examples disclosed herein. In some instances, it may be provided by reference... Figure 5 The signaling receiving component 535 described performs the operation of 715.

[0125] In some instances, the apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0126] Aspect 16: A method or apparatus comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing: receiving a public key associated with a host system at a memory system, wherein the received public key associated with the host system is at least partially based on a private key associated with the host system; receiving signaling from the host system at the memory system; and determining a response to the signaling at the memory system based at least partially on an attempt to authenticate at least a portion of the signaling, wherein the attempt to authenticate at least a portion of the signaling is at least partially based on the public key associated with the host system.

[0127] Aspect 17: The method according to aspect 16, wherein the signaling includes a command to access the memory system or a command to modify the operating parameters of the memory system.

[0128] Aspect 18: The method or apparatus according to any one of aspects 16 to 17 further comprises operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: transmitting a public key associated with the memory system, wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system; and attempting to decrypt at least a portion of the signaling based at least partially on the private key associated with the memory system and the public key associated with the host system, or both.

[0129] Aspect 19: The method or apparatus according to aspect 18 further comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing the following: generating a symmetric key at least in part based on the private key associated with the memory system and the public key associated with the host system, wherein the attempt to decrypt the at least portion of the signaling is at least in part based on the symmetric key.

[0130] Aspect 20: The method or apparatus according to aspect 19 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for performing the following: generating a second symmetric key at least partially based on the symmetric key, wherein an attempt to decrypt the at least portion of the signaling is at least partially based on the second symmetric key.

[0131] Aspect 21: The method or apparatus according to aspect 20 further includes operations, features, circuitry, logic, components, or instructions or any combination thereof for generating the second symmetric key at least in part based on the power-on of the memory system or a reset of the memory system.

[0132] Aspect 22: The method or apparatus according to any one of aspects 20 to 21 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for performing the following: generating the second symmetric key based at least in part on a threshold being satisfied since the previous key was generated.

[0133] Aspect 23: The method or apparatus according to any one of aspects 20 to 22 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for performing the following operations: receiving signaling generated from a start key from a host system, and generating a second symmetric key in response to the signaling generated from the start key.

[0134] Aspect 24: The method or apparatus according to any one of aspects 19 to 23, wherein the public key or the symmetric key associated with the memory system is associated with an address range of the memory system.

[0135] Aspect 25: The method or apparatus according to aspect 24, wherein the address range is associated with memory protection attributes.

[0136] Aspect 26: The method or apparatus according to any one of aspects 16 to 15 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for performing the following operations: transmitting a public key associated with the memory system (e.g., to the host system), wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system; and transmitting a response to the signaling, wherein at least a portion of the response is signed at least partially based on the private key associated with the memory system.

[0137] Aspect 27: The method or apparatus according to any one of aspects 16 to 26 further comprises operations, features, circuit systems, logic, components or instructions or any combination thereof for performing the following: generating the private key associated with the memory system based at least in part on a physical non-clonable function at the memory system.

[0138] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0139] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0140] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if any conductive path exists between them that can enable the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0141] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to be transmitted between the components via a conductive path, and in which a signal is allowed to be transmitted between the components via the conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted to allow signal flow.

[0142] The term "isolation" refers to the relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, if a switch is open, the components separated by the switch positioned between them are isolated from each other. If a controller isolates two components, then the controller achieves the following change: it prevents signals from flowing between the components using previously permitted conductive paths.

[0143] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0144] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0145] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action that occurs as a direct result of a preceding condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a preceding condition or action that is independent of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a preceding condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" some other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other conditions or actions.

[0146] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0147] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor can be "turned on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "turned off" or "deactivated."

[0148] The description herein, illustrated with reference to the accompanying drawings, describes example configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0149] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second reference numeral.

[0150] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations.

[0151] For example, the various illustrative blocks and components described herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0152] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0153] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. The combinations described above also fall within the scope of computer-readable media.

[0154] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will become apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A host system comprising: A controller configured to couple with a memory system, wherein the controller is configured such that the host system: The public key associated with the host system is transmitted to the memory system, wherein the public key associated with the host system is at least partially based on the private key associated with the host system, which is generated at least partially based on an identifier of one of a plurality of host entities of the host system; Transmit one or more commands to modify the protection attributes of the memory system corresponding to one of a plurality of partitions of the memory system, the one or more commands being encrypted and signed by the host system at least in part based on the private key associated with the host system, wherein each of the plurality of host entities is associated with a corresponding partition of the plurality of partitions, and each of the plurality of partitions corresponds to a corresponding address range of the memory system and is associated with a corresponding protection attribute; and Based at least in part on the encryption and signing of the one or more commands, receive at least one response to the one or more commands, the at least one response being associated with the execution of one or more operations to modify the protection attribute.

2. The host system of claim 1, wherein the controller is configured such that the host system: Receive a public key associated with the memory system, wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system; The symmetric key is generated at least in part based on the private key associated with the host system and the public key associated with the memory system; and At least in part, a portion of the one or more commands is encrypted and signed based on the symmetric key.

3. The host system of claim 2, wherein the controller is configured such that the host system: The symmetric key is stored in a non-volatile storage location.

4. The host system of claim 2, wherein the controller is configured such that the host system: A second symmetric key is generated, at least in part based on a threshold being met since the previous key was generated, and at least in part based on the symmetric key itself. The second symmetric key is different from the first symmetric key and is associated with an expiration period. The portion of the one or more commands is encrypted based at least in part on the second symmetric key.

5. The host system of claim 4, wherein the controller is configured such that the host system: The second symmetric key is stored in a volatile storage location.

6. The host system of claim 4, wherein the controller is configured such that the host system: The second symmetric key is generated at least in part based on the power-on or reset of the memory system.

7. The host system of claim 4, wherein the controller is configured such that the host system: Receive one or more commands generated from the start key from the memory system; and The second symmetric key is generated in response to one or more commands generated from the initial key.

8. The host system of claim 2, wherein the public key or the symmetric key associated with the host system is associated with a first address range of the memory system, the first address range corresponding to the partition.

9. The host system of claim 1, wherein the controller is configured such that the host system: The public key associated with the host system is generated, at least in part, based on the master host private key of the host system and the private key associated with the host entity of the host system.

10. The host system of claim 1, wherein the controller is configured such that the host system: Receive a public key associated with the memory system, wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system; and An attempt is made to authenticate at least a portion of the at least one response, at least in part, based on the public key associated with the memory system.

11. The host system of claim 1, wherein performing one or more operations to modify the protection attributes includes enabling or disabling write protection attributes of the partition, enabling or disabling read protection attributes of the partition, or a combination thereof.

12. A memory system comprising: One or more memory devices; and One or more controllers are coupled to and configured to make the memory system: Receive a public key associated with a host system, wherein the public key associated with the host system is at least partially based on a private key associated with the host system, the private key being generated at least partially based on an identifier of one of a plurality of host entities of the host system; Receive one or more commands from the host system to modify the protection attributes of the memory system corresponding to one of a plurality of partitions of the memory system, the one or more commands being encrypted and signed at least in part based on the private key associated with the host system, wherein each of the plurality of host entities is associated with a corresponding partition of the plurality of partitions, and each of the plurality of partitions corresponds to a corresponding address range of the memory system and is associated with a corresponding protection attribute; and The response to the one or more commands is determined at least in part based on an attempt to authenticate the one or more commands, the response being associated with the execution of one or more operations to modify the protection attribute, wherein the attempt to authenticate the one or more commands is at least in part based on the public key associated with the host system.

13. The memory system of claim 12, wherein the one or more controllers are configured such that the memory system: Transmit a public key associated with the memory system, wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system; A symmetric key is generated at least in part based on the private key associated with the memory system and the public key associated with the host system; and An attempt is made to decrypt a portion of the one or more commands, at least in part, based on the symmetric key.

14. The memory system of claim 13, wherein the one or more controllers are configured such that the memory system: A second symmetric key is generated, which is different from the first symmetric key and associated with an expiration period, based at least in part on a threshold that has elapsed since the previous key was generated and at least in part on the symmetric key, wherein an attempt to decrypt the portion of the one or more commands is based at least in part on the second symmetric key.

15. The memory system of claim 14, wherein the one or more controllers are configured such that the memory system: The second symmetric key is generated at least in part based on the power-on or reset of the memory system.

16. The memory system of claim 14, wherein the one or more controllers are configured such that the memory system: Receive one or more commands generated from the start key from the host system; and The second symmetric key is generated in response to one or more commands received in response to the initial key.

17. The memory system of claim 13, wherein the public key or the symmetric key associated with the memory system is associated with a first address range of the one or more memory devices, the first address range corresponding to the partition.

18. The memory system of claim 12, wherein the one or more controllers are configured such that the memory system: Transmit a public key associated with the memory system, wherein the public key associated with the memory system is at least partially based on a private key associated with the memory system and is different from the public key associated with the host system; and Transmitting a response to the one or more commands, wherein at least a portion of the response is signed by the memory system at least in part based on the private key associated with the memory system.

19. The memory system of claim 12, wherein the one or more controllers are configured such that the memory system: The private key associated with the memory system is generated, at least in part, based on the physical non-cloning capability at the memory system.

20. The memory system of claim 12, wherein performing the one or more operations to modify the protection attributes includes enabling or disabling write protection attributes of the partition, enabling or disabling read protection attributes of the partition, or a combination thereof.

21. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: The public key associated with the host system is transmitted through the host system, wherein the public key is based at least in part on the private key associated with the host system, and the private key is generated at least in part on an identifier of one of a plurality of host entities of the host system; One or more commands are transmitted through the host system to modify the protection attributes of the memory system corresponding to one of a plurality of partitions of the memory system, wherein at least a portion of the one or more commands is encrypted and signed by the host system at least partially based on the private key associated with the host system; wherein each of the plurality of host entities is associated with a corresponding partition among the plurality of partitions, and each of the plurality of partitions corresponds to a corresponding address range of the memory system and is associated with a corresponding protection attribute; and At least in part based on the encryption and signing of the one or more commands, at least one response to the one or more commands is received, wherein the response to at least one of the one or more commands is associated with the execution of one or more operations to modify the protection attribute.

22. The non-transitory computer-readable medium of claim 21, wherein performing one or more operations to modify the protection attributes includes enabling or disabling write protection attributes of the partition, enabling or disabling read protection attributes of the partition, or a combination thereof.

23. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: Receive a public key associated with a host system at the memory system, wherein the public key associated with the host system is at least partially based on a private key associated with the host system, the private key being generated at least partially based on an identifier of one of a plurality of host entities of the host system; The memory system receives one or more commands from the host system to modify the protection attributes of the memory system corresponding to one of a plurality of partitions of the memory system, the commands being encrypted and signed at least in part based on the private key associated with the host system, wherein each of the plurality of host entities is associated with a corresponding partition of the plurality of partitions, and each of the plurality of partitions corresponds to a corresponding address range of the memory system and is associated with a corresponding protection attribute; and The response to one or more commands is determined at least in part based on an attempt to authenticate at least a portion of the one or more commands, the response being associated with the execution of one or more operations to modify the protection attributes of the memory system, wherein the attempt to authenticate the one or more commands is at least in part based on the public key associated with the host system.

24. The non-transitory computer-readable medium of claim 23, wherein performing one or more operations to modify the protection attributes includes enabling or disabling write protection attributes of the partition, enabling or disabling read protection attributes of the partition, or a combination thereof.

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