Image sensor pixel output nonlinear correction and accelerated readout circuit

Abstract

The invention discloses an image sensor pixel output nonlinear correction and accelerated readout circuit, comprising a source follower M1 in a photosensitive pixel in a pixel array, a row selection switch S1, a source follower M2 in a dummy pixel, a row selection switch S2; switches S3, S4, S5, an operational amplifier AMP, a current sensing resistor Rs, a sampling capacitor Cs and a pixel array line COL in a column-level correction acceleration circuit. The invention solves the problem of output nonlinearity caused by an NMOS source follower in a traditional large-array pixel structure and slow signal establishment caused by super-long column line parasitics. In addition, the circuit proposed by the invention places a column-level circuit on the periphery of the pixel array, does not affect the overall layout, and only introduces extra power consumption of the operational amplifier. The source follower in the dummy pixel outside the photosensitive pixel array is used to form a feedback loop, and the device matching is good. The current passes through the time-division multiplexing column line current, and there is no current mismatch problem.

Description

Technical Field

[0001] The invention belongs to the technical field of image acquisition and information processing, and relates to an image sensor pixel output nonlinear correction and accelerated readout circuit. Background Art

[0002] With the advancement of CMOS process technology, CMOS image sensors (CIS) have now occupied the mainstream market with their advantages such as low power consumption, low cost, and easy processing.

[0003] Linearity is an important indicator of image sensors, which directly determines their imaging quality. However, due to the extremely stringent requirements on pixel area and fill factor of traditional ultra-large array image sensors, it is difficult to implement relatively complex structures in pixels, which makes linearity a major pain point for ultra-large array image sensors. At the same time, due to the parasitic capacitance and resistance caused by the ultra-long column lines of the large array, the column-level voltage signal of the large array image sensor is slowly established, which also leads to the problem of low frame rate of ultra-large array image sensors.

[0004] Traditional large-array CIS usually uses NMOS to construct active pixel (APS) circuits for small pixel area and high fill factor. However, NMOS source follower will cause nonlinear output response due to substrate bias effect, which affects the imaging quality of the image sensor.

[0005] Therefore, there is a need for a circuit that can solve column readout acceleration and pixel output nonlinear correction outside the pixel array to improve the linearity and frame rate of ultra-large array image sensors. Summary of the invention

[0006] The purpose of the present invention is to provide an image sensor pixel output nonlinear correction and accelerated readout circuit, which solves the problem of output nonlinearity caused by NMOS source follower in traditional large-area array pixel structure and slow signal establishment caused by super-long column line parasitic capacitance.

[0007] The technical solution adopted by the present invention is that the image sensor pixel output nonlinear correction and accelerated readout circuit includes a source follower M1 in a photosensitive pixel in a pixel array, the gate of the source follower M1 is connected to a charge storage node FD in the pixel, the drain of the source follower M1 is connected to a power supply voltage VDD, the source of the source follower M1 is connected to the source of a row selection switch S1, and the drain of the row selection switch S1 is connected to an array line COL;

[0008] It also includes a source follower M2 in the Dummy pixel, the gate of the source follower M2 is disconnected from the internal charge storage node FD and connected to the output OUT of the AMP, the drain of the source follower M2 is connected to the power supply voltage VDD, the source of the source follower M2 is connected to the drain of the row selection switch S2, and the source of the row selection switch S2 is connected to the array line COL;

[0009] It also includes switches S3, S4 and S6 in the column-level nonlinear correction and accelerated readout circuit. The sources of switches S3, S4 and S6 are connected to the pixel surface array line COL, the drain of switch S3 is connected to the output terminal OUT of the operational amplifier AMP, the drain of switch S4 and one end of the resistor Rs are connected to the positive input terminal VP of the operational amplifier AMP, the other end of the resistor Rs is connected to the source of switch S5 and the upper plate of the sampling capacitor Cs, the lower plate of the sampling capacitor Cs is connected to the ground voltage GND, and the drain of switch S5 is connected to the drain of switch S6 and the negative input terminal VN of the operational amplifier AMP.

[0010] The present invention is also characterized in that:

[0011] The row selection switch S1, the row selection switch S2, the switch S3, the switch S4, the switch S5, the switch S6, the source follower M1 and the source follower M2 are all N-channel enhancement type insulated gate field effect transistors, namely NMOS, and are arranged in a form in which the source and the drain are interchangeable.

[0012] The working sequence of the image sensor pixel output nonlinear correction and accelerated readout circuit includes the following steps:

[0013] Step 1, read out the acceleration mode:

[0014] Step 2: Pixel output nonlinear correction mode.

[0015] The specific process of step 1 is as follows: the voltage of the pixel FD node is read out to the column line through the source follower M1. At this time, the row selection switches S1, S3, S4, and S5 are turned on, and the row selection switches S2 and S6 are turned off. At this time, since the area array line COL will charge the sampling capacitor Cs, current will flow through the current detection resistor Rs, and the VP voltage of the operational amplifier AMP is greater than VN. The OUT end of the operational amplifier AMP will output current to accelerate the charging of the parasitic capacitance on the column line. When the voltage on the sampling capacitor Cs is equal to the output voltage of the source follower, the VP voltage is equal to the VN voltage. At this time, the acceleration ends and the voltage signal has been read into the sampling capacitor Cs.

[0016] The specific process of step 2 is as follows: the row selection switches S2 and S6 are turned on, the row selection switches S1, S3, S4, and S5 are turned off, and the voltage on the sampling capacitor Cs is raised by the V of the source follower M2 through the closed-loop negative feedback of the operational amplifier AMP. gs , so that the output voltage L_OUT is equal to the voltage in the voltage storage node FD in the photosensitive pixel.

[0017] The beneficial effect of the present invention is that the nonlinear correction and column-level acceleration circuit proposed by the present invention is located outside the pixel array, the circuit only introduces the extra power consumption of the operational amplifier, and uses the source follower in the Dummy pixel outside the photosensitive pixel array to form a feedback loop. The device matching is good, and the current also uses the column line current, so there is no current mismatch problem. One circuit solves the two major problems of pixel output nonlinearity and slow column line signal readout of the ultra-large array image sensor, which can improve the imaging quality and frame rate of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural schematic diagram of the image sensor pixel output nonlinear correction and accelerated readout circuit of the present invention;

[0019] Figure 2 It is a schematic diagram of the layout of the image sensor pixel output nonlinear correction and accelerated readout circuit of the present invention;

[0020] Figure 3 This is a working timing diagram of the image sensor pixel output nonlinear correction and accelerated readout circuit of the present invention. DETAILED DESCRIPTION

[0021] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The image sensor pixel output nonlinear correction and accelerated readout circuit of the present invention is as follows: Figure 1 As shown, it includes a source follower M1 and a row selection switch S1 in the photosensitive pixel in the pixel array, a source follower M2 and a row selection switch S2 in the Dummy pixel; switches S3, S4, S5, S6 in the column-level correction acceleration circuit, an operational amplifier AMP, a current sensing resistor Rs, a sampling capacitor Cs and a pixel array line COL.

[0023] The switches S1 to S6 and the source followers M1 and M2 are all N-channel enhancement type insulated gate field effect transistors, namely NMOS, and are arranged in a form in which the source and the drain are interchangeable.

[0024] The gates of S1 to S5 are all connected to the corresponding control signals; Cs is a sampling capacitor (of any type) used to store the voltage signal output by the pixel from the column line; Rs is a current sensing resistor (of any type) used to detect whether the column line signal is in the establishment process.

[0025] The gate of the source follower M1 in the photosensitive pixel is connected to the charge storage node FD in the pixel, the drain of M1 is connected to the power supply voltage VDD, the source of M1 is connected to the source of the row selection switch S1, and the drain of the row selection switch S1 is connected to the array line COL.

[0026] The gate of the source follower M2 in the dummy pixel is disconnected from the internal charge storage node FD and connected to the output OUT of the AMP, which is also the output L_OUT of the nonlinear correction and readout acceleration circuit proposed by the present invention. The drain of the source follower M2 is connected to the power supply voltage VDD, the source of the source follower M2 is connected to the drain of the row selection switch S2, and the source of the row selection switch S2 is connected to the array line COL.

[0027] The sources of switches S3, S4, and S6 in the column-level nonlinear correction and accelerated readout circuit are connected to the pixel surface array line COL, the drain of switch S3 is connected to the AMP output terminal OUT, the drain of switch S4 and one end of the current sensing resistor Rs are connected to the positive input terminal VP of the AMP, the other end of the current sensing resistor Rs is connected to the source of S5 and the upper plate of the sampling capacitor Cs, the lower plate of the sampling capacitor Cs is connected to the ground voltage GND, and the drain of switch S5 is connected to the drain of switch S6 and the negative input terminal VN of the AMP.

[0028] Figure 2 This is the layout of the pixel output nonlinear correction and accelerated readout circuit of the present invention. The circuit is placed below the pixel array and does not affect the overall layout.

[0029] The working sequence of the image sensor pixel output nonlinear correction and accelerated readout circuit of the present invention is as follows: Figure 3 As shown, a working method of a pixel output nonlinear correction and accelerated readout circuit is provided, and the steps are as follows: Step 1, readout acceleration mode: the pixel FD node voltage will be read out to the column line through the source follower M1, at this time, switches S1, S3, S4, S5 are turned on, and S2, S6 are turned off. At this time, since the column line will charge the sampling capacitor Cs, current will flow through Rs, and the VP voltage of the AMP is greater than VN. The OUT end of the AMP will output current to accelerate the charging of the parasitic capacitance on the column line. When the voltage on Cs is equal to the output voltage of the source follower, the VP voltage is equal to the VN voltage. At this time, the acceleration ends, and the voltage signal has been read into the capacitor Cs;

[0030] Step 2, pixel output nonlinear correction mode: At this time, S2 and S6 are turned on, S1, S3, S4, and S5 are turned off, and the voltage on Cs is raised by the V of the source follower M2 through the AMP closed-loop negative feedback. gs , so that the output voltage L_OUT is equal to the voltage in the voltage storage node FD in the photosensitive pixel.

[0031] The working principle of the image sensor pixel output nonlinear correction and accelerated readout circuit of the present invention is: first, the readout acceleration mode is used, at which the voltage of the photosensitive pixel FD node will be read out to the column line through the source follower M1, but due to the parasitic capacitance to the ground on the ultra-long column line, the signal is established very slowly. At this time, the column line will also charge the sampling capacitor Cs. At this time, due to the voltage difference generated by the column line charging current flowing through the resistor Rs, the voltage of the positive terminal VP of the AMP is greater than the negative terminal VN, so the operational amplifier will output a large current to the column line to achieve the effect of accelerated reading. When the voltage on the sampling capacitor CS is equal to the column line output voltage, the current will no longer flow through the resistor Rs. At this time, the VP voltage is equal to VN, and the acceleration ends; then it is a nonlinear correction mode. Since the photosensitive pixel and the Dummy pixel circuit parameters are the same, the voltage on the sampling capacitor Cs is also equal to the S1 source voltage in the photosensitive pixel. Due to the virtual short characteristics of VP and VN brought by the high gain of the operational amplifier, the S2 source voltage in the Dummy pixel is also the voltage on Cs at this time. In this way, the substrate bias effect of the source follower M1 and the source follower M2 is the same, and the final source follower M2 gate voltage is equal to the source follower M1 gate voltage. Therefore, the voltage output by the final output L_OUT of the correction circuit is also the photosensitive pixel FD node voltage. In this way, the pixel output nonlinear correction and accelerated readout circuit of the present invention completes the two functions of output nonlinear correction and accelerated readout through two working modes.

Claims

1. Image sensor pixel output nonlinear correction and accelerated readout circuit, characterized in that: It includes a source follower M1 in a photosensitive pixel in a pixel array, the gate of the source follower M1 is connected to a charge storage node FD in the photosensitive pixel, the drain of the source follower M1 is connected to a power supply voltage VDD, the source of the source follower M1 is connected to a source of a row selection switch S1, and the drain of the row selection switch S1 is connected to an array line COL; It also includes a source follower M2 in the Dummy pixel, the gate of the source follower M2 is disconnected from the charge storage node FD in the Dummy pixel and connected to the output OUT of the AMP, the drain of the source follower M2 is connected to the power supply voltage VDD, the source of the source follower M2 is connected to the drain of the row selection switch S2, and the source of the row selection switch S2 is connected to the array line COL; It also includes a switch S3, a switch S4, and a switch S6, wherein the sources of the switches S3, S4, S5, and S6 are connected to the pixel surface array line COL, the drain of the switch S3 is connected to the output terminal OUT of the operational amplifier AMP, the drain of the switch S4 and one end of the resistor Rs are both connected to the positive input terminal VP of the operational amplifier AMP, the other end of the resistor Rs is connected to the source of the switch S5 and the upper plate of the sampling capacitor Cs, the lower plate of the sampling capacitor Cs is connected to the ground voltage GND, and the drain of the switch S5 is connected to the drain of the switch S6 and the negative input terminal VN of the operational amplifier AMP; The row selection switch S1, row selection switch S2, switch S3, switch S4, switch S5, switch S6, source follower M1, source follower M2 are all N-channel enhancement type insulated gate field effect transistors NMOS, and are arranged in a form in which the source and drain are interchangeable; The working sequence of the image sensor pixel output nonlinear correction and accelerated readout circuit includes the following steps: Step 1, accelerated readout mode; The specific process of step 1 is as follows: the voltage of the charge storage node FD in the photosensitive pixel is read out to the surface array line COL through the source follower M1, the row selection switch S1, the switch S3, the switch S4, and the switch S5 are turned on, and the row selection switch S2 and the switch S6 are turned off, the surface array line COL charges the sampling capacitor Cs, and the current flows through the current detection resistor Rs. The voltage of the positive terminal VP of the operational amplifier AMP is greater than the voltage of the negative terminal VN. The OUT terminal of the operational amplifier AMP outputs a current to accelerate the charging of the surface array line COL. When the voltage on the sampling capacitor Cs is equal to the output voltage of the source follower M1, the voltage of the positive terminal VP of the operational amplifier AMP is equal to the voltage of the negative terminal VN, and the acceleration ends. The voltage signal has been read into the sampling capacitor Cs; Step 2, pixel output nonlinear correction mode; The specific process of step 2 is as follows: the row selection switches S2 and S6 are turned on, the row selection switches S1, S3, S4 and S5 are turned off, and the voltage on the sampling capacitor Cs is negatively fed back by the closed loop of the operational amplifier AMP to the voltage V of the source follower M2. gs Lifted to the sampling capacitor C S The voltage on the charge storage node FD in the photosensitive pixel is increased so that the circuit output voltage L_OUT is equal to the voltage of the charge storage node FD in the photosensitive pixel.

Images