Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a preparation method. The preparation method comprises: forming a peripheral circuit in a first region defined on an initial substrate, and covering the first region with a first filling layer; forming a groove on a part of the initial substrate other than the first region, and forming a first stack structure in the groove; forming a second stack structure on the first stack structure and the peripheral circuit; and forming a channel structure penetrating through the first stack structure and the second stack structure. Through the preparation method provided by the application, the peripheral circuit and the three-dimensional memory array are formed on different levels of the same substrate, which can effectively reduce the size of the peripheral circuit wafer, reduce the aspect ratio of the contact hole of the subsequently formed peripheral circuit, and thus facilitate the reduction of the connection process difficulty of the three-dimensional memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a three-dimensional memory (3D NAND) and its fabrication method. Background Technology

[0002] In a conventional three-dimensional memory, the peripheral circuits used to control signals entering and exiting the memory array may include high-voltage circuits, low-voltage circuits, and ultra-low-voltage circuits.

[0003] In some traditional 3D memory fabrication processes, peripheral circuits are usually integrated on a separate wafer. However, as the structure of 3D memory continues to develop towards higher layers and higher densities, the area of ​​the peripheral circuit wafer is becoming a key factor in determining the overall size of the 3D memory.

[0004] Therefore, how to effectively reduce the overall size of 3D memory without affecting the structural performance and product yield is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a three-dimensional memory and its fabrication method that can at least partially solve the above-mentioned problems existing in related technologies.

[0006] This application provides a method for fabricating a three-dimensional memory, the method comprising: forming a peripheral circuit in a first region defined on an initial substrate, and covering the first region with a first filling layer; forming a groove in a portion of the initial substrate other than the first region, and forming a first stacked structure in the groove; forming a second stacked structure on the first stacked structure and the peripheral circuit; and forming a channel structure penetrating the first stacked structure and the second stacked structure.

[0007] In one embodiment of this application, the first filling layer includes a first initial filling layer and a second initial filling layer. Forming a peripheral circuit in the first region and covering the first region with the first filling layer includes: forming a peripheral circuit in the first region; covering the first region with the first initial filling layer; forming a first contact, a second contact, and a third contact that are electrically connected to the source region, drain region, and gate structure of the peripheral circuit, respectively; and covering the first initial filling layer with the second initial filling layer.

[0008] In one embodiment of this application, the memory includes a channel structure, a gate gap structure, and a step structure, and the conductive impurities located in the source region and the drain region are annealed by the heat generated during the formation of the channel structure, the gate gap structure, and the step structure.

[0009] In one embodiment of this application, the first stacked structure and the second stacked structure together constitute the stacked structure of the memory, the stacked structure including a memory array region and a step region, the memory array region being used to form the channel structure, the step region being located at the periphery of the memory array region; and the step region including a first step region and a second step region, at least a portion of the first step region being located above the peripheral circuit.

[0010] In one embodiment of this application, after forming the channel structure, the method further includes forming a virtual channel structure and forming conductive contacts of the peripheral circuit. The method of forming the virtual channel structure and the conductive contacts includes: forming a first virtual channel structure above the peripheral circuit, which is directly opposite to any one of the first contact, the second contact, and the third contact; and forming a first portion of the conductive contact that penetrates through the first virtual channel structure, the first portion being electrically connected to any one of the first contact, the second contact, and the third contact.

[0011] In one embodiment of this application, the first virtual channel structure includes a first virtual channel hole; the first filling layer further includes a barrier layer located between the first initial filling layer and the second initial filling layer, and covering the top surface of the first contact, the top surface of the second contact and the top surface of the third contact; and the process of forming the first virtual channel hole stops at the barrier layer.

[0012] In one embodiment of this application, forming a first stacked structure within the groove includes:

[0013] The inner wall of the groove and the surface of the first filling layer are conformally covered by a dielectric stack; and the first stack structure is formed in the remaining portion within the groove.

[0014] In one embodiment of this application, the dielectric stack includes a first barrier dielectric layer, a first semiconductor layer, a second barrier dielectric layer, and a second semiconductor layer formed sequentially, and the channel structure extends through the stack structure and into the dielectric stack. The channel structure includes a channel hole and a functional layer and a channel layer sequentially disposed on the inner wall of the channel hole. After forming the channel structure, the method further includes: removing a portion of the initial substrate and a portion of the dielectric stack to expose a portion of the functional layer extending into the dielectric stack, and retaining at least a portion of the first semiconductor layer located on the surface of the first filling layer and the second semiconductor layer; removing the exposed functional layer to expose the corresponding channel layer; and forming a conductive layer connected to the exposed channel layer on the surface of the second semiconductor layer and the remaining surface of the first semiconductor layer.

[0015] In one embodiment of this application, forming a second stacked structure on the first stacked structure and the peripheral circuit includes: planarizing the top surface of the first stacked structure so that the top surface of the first stacked structure is flush with the top surface of the portion of the dielectric stack located on the first filler layer, thereby forming a coplanar structure.

[0016] In one embodiment of this application, after forming the channel structure, the method further includes: connecting a peripheral circuit chip to the side of the stacked structure away from the initial substrate, wherein the peripheral circuit chip includes any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits.

[0017] In one embodiment of this application, the peripheral circuit includes any one or a combination of peripheral high-voltage circuit, peripheral low-voltage circuit, and peripheral ultra-low-voltage circuit.

[0018] This application also provides a three-dimensional memory, the memory comprising: a substrate; peripheral circuitry formed on the substrate and covered by a first filling layer; a dielectric stack covering the surface of the first filling layer; a stacked structure including a first stacked structure and a second stacked structure, wherein the first stacked structure is formed on the surface of the substrate and the side surface of the dielectric stack, the top surface of the first stacked structure is flush with and coplanar with the top surface of the dielectric stack, and the second stacked structure is disposed on the coplanar surface; and a channel structure penetrating the stacked structure.

[0019] In one embodiment of this application, the stacked structure includes a memory array region and a step region, the memory array region being used to form the channel structure, and the step region being located at the periphery of the memory array region, wherein the step region includes a first step region and a second step region, and at least a portion of the first step region is located above the peripheral circuit.

[0020] In one embodiment of this application, the peripheral circuit includes a gate structure formed on the substrate and a source region and a drain region formed on the substrate and located on both sides of the gate structure. The memory further includes a virtual channel structure formed in the step region. The virtual channel structure includes a first virtual channel structure located above the peripheral circuit and facing any one of a first contact, a second contact, and a third contact. The first contact, the second contact, and the third contact are respectively facing the source region, the drain region, and the gate structure and forming an electrical connection.

[0021] In one embodiment of this application, the peripheral circuit further includes a conductive contact, the conductive contact including a first portion that penetrates the first virtual channel structure and is electrically connected to any one of the first contact, the second contact, and the third contact.

[0022] In one embodiment of this application, the dielectric stack includes: a first barrier dielectric layer, a first semiconductor layer, a second barrier dielectric layer, and a second semiconductor layer sequentially formed on the first filler layer.

[0023] In one embodiment of this application, the substrate includes a first portion and a second portion made of different materials. The peripheral circuit is formed in the first portion, and the second portion includes a conductive layer that is in contact with the dielectric stack and electrically connected to the channel structure.

[0024] In one embodiment of this application, the peripheral circuit includes any one or a combination of peripheral high-voltage circuit, peripheral low-voltage circuit, and peripheral ultra-low-voltage circuit.

[0025] In one embodiment of this application, the memory further includes: a peripheral circuit chip located on the side of the stacked structure away from the substrate, wherein the peripheral circuit chip includes any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits.

[0026] According to one embodiment of this application, a three-dimensional memory and its fabrication method are provided. By forming the peripheral circuit and the three-dimensional memory array on different horizontal planes of the same substrate, the size of the peripheral circuit wafer can be effectively reduced, while the aspect ratio of the contact holes of the peripheral circuit can be reduced, thereby helping to reduce the interconnection process difficulty of the three-dimensional memory. Furthermore, by forming the peripheral circuit and the three-dimensional memory array on the same substrate, and placing the peripheral low-voltage circuit and the peripheral ultra-low-voltage circuit on another chip, the overall size of the peripheral chip can be relatively reduced, thereby improving the storage density and integrability of the three-dimensional memory.

[0027] Furthermore, according to at least one embodiment of this application, the three-dimensional memory and its fabrication method provided in this application can improve the heat utilization rate of heat treatment and thermal processing during the fabrication of memory devices by annealing the conductive impurities in the source region, drain region and bias region of the peripheral circuit located on the same substrate with the heat generated during the formation of the channel structure, gate gap structure and step structure of the three-dimensional memory array.

[0028] In addition, according to at least one embodiment of this application, in the three-dimensional memory and its fabrication method provided in this application, the step region of the three-dimensional memory includes two parts, a first step region and a second step region, wherein at least a portion of the first step region is formed above the peripheral circuit, thereby relatively reducing the size of the step region in the stacked structure and improving the bit density of the three-dimensional memory.

[0029] Furthermore, according to at least one embodiment of this application, in the three-dimensional memory and its fabrication method provided in this application, the contacts of the peripheral circuits can be formed in a partial virtual channel structure (first virtual channel structure) of the three-dimensional memory. This not only provides structural support for the partial stacked structure facing the peripheral circuits during the formation of the gate layer, but also reduces the size of the step region in the stacked structure, thereby increasing the bit density of the three-dimensional memory. Attached Figure Description

[0030] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0031] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to one embodiment of this application;

[0032] Figures 2 to 12 These are schematic diagrams of a preparation method according to one embodiment of this application; and

[0033] Figure 13 This is a cross-sectional structural diagram of a three-dimensional memory according to one embodiment of this application. Detailed Implementation

[0034] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first stacked structure discussed herein may also be referred to as the second stacked structure, and vice versa.

[0036] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0037] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0038] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0041] Figure 1 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to one embodiment of this application. For example... Figure 1 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, comprising:

[0042] S1, a peripheral circuit is formed in a first region defined on the initial substrate, and a first fill layer is used to cover the first region.

[0043] S2, a groove is formed in the portion of the initial substrate other than the first region, and a first stacked structure is formed in the groove.

[0044] S3 forms a second stacked structure on the first stacked structure and the peripheral circuit.

[0045] S4 forms a channel structure that runs through the first and second stacked structures.

[0046] The following will combine Figures 2 to 12 The specific processes for each step of the above preparation method 1000 are described in detail.

[0047] Step S1

[0048] Figure 2 A cross-sectional schematic diagram of the structure formed after forming an initial substrate 100 and an initial peripheral circuit 700' according to one embodiment of the present application. Figure 3 A cross-sectional schematic diagram of the structure formed after forming the first filling layer 710 according to one embodiment of the preparation method of this application.

[0049] like Figures 2 to 3 As shown, step S1, which involves forming a peripheral circuit within a first region defined on the composite substrate and covering the first region with a first filler layer, may include, for example,: preparing an initial substrate 100; forming a peripheral circuit 700 within a first region 01 defined on the initial substrate 100; and covering the first region 01 with a first filler layer 710.

[0050] Specifically, such as Figure 2 As shown, in one embodiment of this application, the material used to prepare the initial substrate 100 can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds.

[0051] In one embodiment of this application, the initial substrate 100 for supporting the device structure thereon can be formed by sequentially depositing multiple layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0052] In one embodiment of this application, the initial substrate 100 may be a composite substrate, such as including a substrate, a substrate semiconductor layer and a substrate barrier layer formed sequentially.

[0053] The substrate semiconductor layer can be, for example, a polycrystalline silicon layer. Further, well regions can be formed in the substrate semiconductor layer by doping with N-type or P-type dopant via ion implantation or diffusion processes. The dopant can include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of this application, the well regions can be prepared using the same or different dopants; furthermore, the doping concentration of the well regions can be the same or different, and this application does not limit this.

[0054] Furthermore, the substrate barrier layer may be disposed on the outermost side of the initial substrate 100, and may include a single layer, multiple layers, or a suitable composite layer. Alternatively, when the substrate barrier layer is a composite layer, it may include any one or more of dielectric materials, semiconductor materials, and conductive materials.

[0055] A three-dimensional memory may include a memory array and peripheral circuitry. The array structure of the three-dimensional memory differs from the structure of the peripheral circuitry and must be manufactured separately. The peripheral circuitry may include high-voltage circuits, low-voltage circuits, and ultra-low-voltage circuits.

[0056] Refer again Figure 2 The initial substrate 100 may include a first region 01 for forming peripheral circuits and a second region 02 for forming a three-dimensional memory array. The second region 02 may specifically include a memory array region and a partial step region, and the first region 01 may specifically include a peripheral circuit region and a partial step region, wherein the partial step region may overlap with the peripheral circuit region. In subsequent processes, the channel structure, gate gap structure, etc., of the three-dimensional memory can be formed in the portion of the stacked structure located in the memory array region, and virtual channels, word line contacts, etc., can be formed in the portion of the stacked structure located in the step region (which can be understood as the step region of the three-dimensional memory provided in this application may include portions formed in the first region and portions formed in the second region). The step region is located at the periphery of the memory array region; in other words, the memory array region and the step region may be adjacent in a first direction (X direction), and the first region 01 and the second region 02 may be adjacent in the first direction.

[0057] Furthermore, the aforementioned peripheral circuitry may include one or more of page buffers, decoders (e.g., row decoders and column decoders), drivers, charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) required in the circuitry. In some embodiments, the peripheral circuitry may be formed using CMOS technology, but is not limited thereto, and will not be elaborated upon herein.

[0058] In one embodiment of this application, the initial substrate 100 has opposing first and second sides. After the initial substrate 100 is formed, a peripheral circuit 700 may be formed within a first region 01 of the initial substrate 100.

[0059] Alternatively, the peripheral circuitry 700 disposed on the initial substrate 100 may include any one or a combination of peripheral high-voltage circuitry, peripheral low-voltage circuitry, and peripheral ultra-low-voltage circuitry. Since the peripheral high-voltage circuitry requires a thicker substrate and is resistant to high temperatures, its fabrication process is easily compatible with the fabrication process of the three-dimensional memory array. In one embodiment of this application, the peripheral high-voltage circuitry and the three-dimensional memory array can be formed on the same substrate, while a relatively large number of peripheral low-voltage circuitry and peripheral ultra-low-voltage circuitry can be disposed on a peripheral circuitry chip, thereby effectively reducing the overall size of the three-dimensional memory and increasing its storage density.

[0060] Specifically, such as Figure 2 As shown, the fabrication process of the peripheral circuit can employ existing conventional processes, fabricated according to actual needs. A shallow trench isolation structure 701 of the peripheral circuit 700 can be formed in the first region 01, which can effectively isolate adjacent devices in the peripheral circuit 700. Subsequently, a gate structure 702 of the peripheral circuit 700 can be formed in the region between the shallow trench isolation structures 701. The gate structure 702 includes a gate dielectric layer formed on the initial substrate 100. A source region 703 and a drain region 704 are formed in the portions of the first region 01 located on both sides of the gate structure 702, thereby forming the initial peripheral circuit 700'.

[0061] like Figure 3 As shown, in forming the initial peripheral circuit 700' (e.g. Figure 2 Afterwards (as shown), a first filling layer 710 can be prepared to cover the first region 01 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Specifically, an initial first filling layer covering the surface of the initial substrate 100 can be formed first through the above process, and then the first filling layer 710 can be formed by removing the portion of the initial first filling layer other than the first region 01. The first filling layer 710 fully covers the first region 01, which can prevent plasma gas introduced during the manufacturing process of the three-dimensional memory device from diffusing into the peripheral circuit, thereby improving the reliability of the product.

[0062] Furthermore, combined Figure 2 and Figure 3In one embodiment of this application, the first filling layer 710 may include a first initial filling layer 708 and a second initial filling layer 709. After the initial peripheral circuit 700' is formed in the first region 01, a first initial filling layer 708 covering the initial peripheral circuit 700' may be formed in the first region 01 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The first initial filling layer 708 may be an insulating dielectric filling layer, for example, it may include one or more layers, which may include one or more materials. The materials used for the first initial filling layer 708 may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant dielectric materials such as aluminum oxide or hafnium oxide, etc., and this application is not limited thereto.

[0063] After the first initial fill layer 708 is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, or other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to form a first contact hole (not shown), a second contact hole (not shown) and a third contact hole (not shown) that penetrate the first initial fill layer 708 and expose a portion of the source region 703, a portion of the drain region 704 and a portion of the gate structure 702, respectively.

[0064] Subsequently, conductive material can be filled into the first contact hole, second contact hole, and third contact hole using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof to form the first contact 706, second contact 707, and third contact 705 respectively. The conductive material can be, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0065] After forming the first contact 706, the second contact 707, and the third contact 705, the first initial fill layer 708 can be covered by a second initial fill layer 709. The second initial fill layer 709 can be an insulating dielectric fill layer, for example, it can include one or more layers, which can include one or more materials. Materials used for the second initial fill layer 709 may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant dielectric materials such as aluminum oxide or hafnium oxide, etc., and this application is not limited thereto. Alternatively, the first initial fill layer 708 can be made of the same material as the second initial fill layer 709.

[0066] Furthermore, in one embodiment of this application, the first filling layer 710 further includes a barrier layer 711. The barrier layer 711 may be located between the first initial filling layer 708 and the second initial filling layer 709, and covers the top surface of the first contact 706, the top surface of the second contact 707, and the top surface of the third contact 705. The process for forming the barrier layer 711 may include thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The barrier layer 711 may include one or more layers, which may include one or more materials. The materials used for the barrier layer 711 may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant dielectric materials such as aluminum oxide or hafnium oxide, etc. Furthermore, in the method of fabricating a three-dimensional memory, the subsequent formation of a first virtual channel via may stop at the barrier layer 711, wherein the first virtual channel via is used to form a first virtual channel structure disposed above the peripheral circuit 700 and directly opposite any one of the first contact 706, the second contact 707, and the third contact 705.

[0067] Furthermore, in one embodiment of this application, the top surface of the first filling layer 710 (the surface away from the initial substrate 100) may be subjected to a chemical mechanical polishing process with a low grinding rate (Buffer CMP) to achieve planarization.

[0068] The first fill layer 710 isolates the peripheral circuitry from the subsequently formed three-dimensional memory array. This prevents substances such as hydrogen or other plasmas generated or used during the fabrication of the three-dimensional memory array from diffusing into the peripheral circuitry, thereby improving the overall reliability of the three-dimensional memory.

[0069] Step S2

[0070] Figure 4 A cross-sectional schematic diagram of the structure formed after forming the laminated structure 200 according to one embodiment of the present application.

[0071] like Figure 4 As shown, step S2, which forms a groove in the portion of the initial substrate other than the first region and forms a first stacked structure in the groove, may include, for example, forming a groove (not shown) in a second region 02 of the initial substrate 100; conformally covering the inner wall of the groove and the surface of the first filler layer 710 with a dielectric stack 201; and filling the remaining portion of the groove with the first stacked structure 202.

[0072] Specifically, in one embodiment of this application, the groove can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, or by performing other manufacturing processes, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to form a groove in the second region 02 of the initial substrate 100, so that the peripheral circuit and the subsequently formed three-dimensional memory array are formed on different horizontal planes of the same substrate, thereby reducing the aspect ratio of the contact holes of the subsequently formed peripheral circuit, which is beneficial to reducing the difficulty of the interconnection process of the three-dimensional memory.

[0073] After the groove is formed, a dielectric stack 201 can be used to conformally cover the inner wall of the groove and the surface of the first filling layer 710. The surface of 710 can be understood as the top surface and the side surface, with the top surface being away from and opposite to the initial substrate 100. The inner wall of the groove includes the inner side wall and the bottom surface of the groove. Multiple thin film deposition processes can be used to sequentially form the layers of the dielectric stack 201 on the above-mentioned surface. The thin film deposition processes can include, but are not limited to, CVD, PVD, ALD, or any combination thereof, and this application does not limit them.

[0074] In one embodiment of this application, the dielectric stack 201 may include a first barrier dielectric layer 11, a first semiconductor layer 12, a second barrier dielectric layer 13, and a second semiconductor layer 14 formed sequentially. Alternatively, the first semiconductor layer 12 and the second semiconductor layer 14 may be fabricated from a semiconductor material, such as polycrystalline silicon. Well regions formed by doping with N-type or P-type dopants via ion implantation or diffusion processes may be formed in the first semiconductor layer 12 and the second semiconductor layer 14. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of this application, the well regions may be fabricated using the same dopant or different dopants; furthermore, the doping concentration of the well regions may be the same or different, and this application does not limit this. The first barrier dielectric layer 11 and the second barrier dielectric layer 13 may include any one or more of dielectric materials, semiconductor materials, and conductive materials, such as any one or more of silicon oxide layers, silicon nitride layers, and silicon oxynitride layers. Alternatively, the first barrier dielectric layer 11 and the second barrier dielectric layer 13 may also include a high-dielectric-constant dielectric layer.

[0075] On the one hand, the dielectric stack 201 can form an isolation structure together with the already formed first fill layer 710 to isolate the peripheral circuits from the subsequently formed three-dimensional memory array, thereby further preventing the diffusion of substances such as hydrogen or other plasmas generated or used during the fabrication of the three-dimensional memory array into the peripheral circuits and improving the reliability of the three-dimensional memory. On the other hand, the dielectric stack 201 can serve as a partial substrate structure for the subsequent formation of memory array structures such as channel structures and gate gap structures. Furthermore, during the formation of the above structure, the first barrier dielectric layer 11 and the second barrier dielectric layer 13 can serve as stop layers for the etching process, thereby increasing the etching process window, preventing damage to the memory array structure from the etching process, and improving the performance of the three-dimensional memory.

[0076] Furthermore, a chemical mechanical polishing process with a low grinding rate can be performed to planarize the surface of the dielectric stack 201 away from the initial substrate 100.

[0077] After forming the dielectric stack 201, the remaining portion within the groove can be filled using the first stack structure 202. One or more thin-film deposition processes can be used to alternately deposit an insulating layer 210 and a gate sacrificial layer 220 on the dielectric stack 201 until the top surface of region 02 is not lower than the top surface 712 of the first filling layer 710. The thin-film deposition processes can include, but are not limited to, CVD, PVD, ALD, or any combination thereof, and this application does not limit them. Then, a CMP process is used to polish down to the second semiconductor layer 14, making the top surfaces of the first region 01 and the second region 02 flush, thus forming the first stack structure 202.

[0078] The first stacked structure 202 may include multiple pairs of insulating layers 210 and gate sacrificial layers 220 stacked alternately on top of each other. In some embodiments, the insulating layer 210 and the gate sacrificial layer 220 may each include a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials used to form the insulating layer 210 and the gate sacrificial layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, while the silicon nitride layer may be used as a sacrificial stack layer. The sacrificial stack layer may then be etched away and replaced with a conductive layer comprising a conductive material.

[0079] Step S3

[0080] Refer again Figure 4 Step S3, forming the second stacked structure on the first stacked structure and the peripheral circuit, may include, for example, planarizing the top surface 18 of the first stacked structure 201 and the top surface 712 of the first filler layer 710 to form a coplanar surface; and forming the second stacked structure 203 on the coplanar surface.

[0081] Specifically, the portion of the top surface 17 of the dielectric stack 201 located on the first filling layer 710, and the top surface 18 of the first stack structure 201, can be subjected to a chemical mechanical polishing process with a low grinding rate to obtain a flat coplanar surface. This facilitates the formation of the second stack structure 203 on the flat coplanar surface in subsequent steps, thereby improving the reliability of the three-dimensional memory.

[0082] One or more thin film deposition processes can be used to form the second stacked structure 203 on the above coplanar surface. The thin film deposition processes may include, but are not limited to, CVD, PVD, ALD or any combination thereof, and this application does not limit them.

[0083] The second stacked structure 203 may include multiple pairs of insulating layers 210' and gate sacrificial layers 220' stacked alternately. In some embodiments, the insulating layer 210' and gate sacrificial layer 220' may each include a third dielectric material and a fourth dielectric material different from the third dielectric material. Alternatively, the insulating layer 210' and gate sacrificial layer 220' of the second stacked structure 203 may be the same as the insulating layer 210 and gate sacrificial layer 220 of the first stacked structure 202. Exemplary materials used to form the insulating layer 210' and gate sacrificial layer 220' may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, while the silicon nitride layer may be used as a sacrificial stack layer. The sacrificial stack layer may then be etched away and replaced with a conductive layer comprising a conductive material.

[0084] The first stacked structure 202 and the second stacked structure 203 together constitute the stacked structure 200 of the three-dimensional memory. The channel structure, gate gap structure and step structure formed subsequently are all formed in the stacked structure 200.

[0085] As the demand for 3D memory storage continues to increase, the size of memory stacks is gradually increasing. To overcome the limitations of traditional processes, dual-stack or multi-stack techniques can be used to form a stacked structure 200 by sequentially stacking multiple sub-stacked structures in the thickness direction of the stacked structure 200. Each sub-stacked structure may include multiple alternately stacked insulating layers and gate sacrificial layers. The number of layers in each sub-stacked structure may be the same or different. Since the fabrication process of the dual-stacked structure described above is fully or partially applicable to the stacked structure described herein, which includes multiple sub-stacked structures, related or similar content will not be repeated. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on the multi-stacked or dual-stacked structure.

[0086] Step S4

[0087] Figure 5A cross-sectional schematic diagram of the structure formed after forming the channel structure 300 according to one embodiment of the present application.

[0088] like Figure 5 As shown, step S4, forming a channel structure that penetrates the first and second stacked structures, may include, for example, forming a channel hole 310 that penetrates the stacked structure 200; and sequentially forming a functional layer 320 and a channel layer 330 on the inner wall of the channel hole.

[0089] Specifically, the stacked structure 200 of the three-dimensional memory may include a memory array region and a step region, wherein the memory array region is used to form a channel structure 300, and the step region may form a step structure, word line contact, virtual channel structure, etc., and the step region may be located at the periphery of the memory array region. In one embodiment of this application, the step region includes a first step region 500-1 and a second step region 500-2. Alternatively, the first step region 500-1 and the second step region 500-2 are located on both sides of the channel structure 300 along the X direction, for example, at least a portion of the first step region 500-1 is located above the peripheral circuit 700 of the first region 01; at least another portion of the first step region 500-1 is located in the second region 02 and adjacent to the first region 01; and the second step region 500-2 is located in the second region 02 and away from the first region 01.

[0090] Therefore, as an alternative, in the three-dimensional memory structure provided in this application, the step structure of the three-dimensional memory may also include two parts, wherein the first step structure may be disposed in the first step region 500-1 and formed in the portion of the stacked structure 200 opposite to the first filling layer 710, and the second step structure may be disposed in the second step region 500-2 and formed on the side of the stacked structure 200 away from the peripheral circuit 700. Thus, the three-dimensional memory structure provided in this application can relatively reduce the size of the step region in the stacked structure and increase the bit density of the three-dimensional memory.

[0091] The first and second step structures can be formed simultaneously or in stages; this application does not limit this. Multiple trimming-etching cycles are performed on the edge portions of the stacked structure 200 to give the stacked structure 200 one or more inclined edges and a dielectric layer pair (such as the bottom layer, closer to the initial substrate 100) with a greater thickness than the bottom layer (closer to the initial substrate 100). Figure 4 The insulating layer 210 and gate sacrificial layer 220 (or insulating layer 210' and gate sacrificial layer 220') shown are shorter than the top (away from the initial substrate 100) dielectric layer pair. Any suitable etching process (including any combination of dry and wet etching processes) can be used in the step formation process. Furthermore, a dielectric layer may be formed to cover the step.

[0092] In some embodiments of this application, the channel structure 300 may be formed after the first step structure and the second step structure are formed. In some other embodiments, the channel structure 300 may be formed before the first step structure and the second step structure are formed. This application does not limit this to any particular embodiment.

[0093] The steps for forming the channel structure 300 can be specifically as follows: First, a channel hole 310 is formed in the second region 02 memory array area. The channel hole 310 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing. The channel hole 310 can have a cylindrical or columnar shape that penetrates the first stack structure 200 and extends to the dielectric stack 201.

[0094] Furthermore, after forming a stacked structure using dual-stack or multi-stack technology, the stacked structure may include N sub-stacked structures, and correspondingly, the channel holes may also include N×M sub-channel holes, wherein each sub-stacked structure may include M sub-channel holes, where M≥1 and N≥2. Forming vias in a stacked structure using dual-stack or multi-stack techniques may include: forming a first sub-stacked structure on one side of an initial substrate and forming M first sub-channels extending through the first sub-stacked structure and into the initial substrate; continuing to form subsequent sub-stacked structures and sub-channels until an Nth sub-stacked structure and M sub-channels located in the Nth sub-stacked structure are formed; then filling the corresponding sub-channels in the N-1 sub-stacked structures other than the Nth sub-stacked structure with a via-filling sacrificial layer; and removing the via-filling sacrificial layer in the N-1 sub-stacked structures based on the M sub-channels of the Nth sub-stacked structure, such that adjacent sub-channels in the N sub-stacked structures are at least partially aligned with each other to obtain M vias.

[0095] After the channel hole 310 is formed, a functional layer 320 and a channel layer 330 of the channel structure 300 can be formed in the channel hole 310. The functional layer 320 includes a barrier layer, a charge trapping layer and a tunneling layer sequentially disposed in the channel hole 310; and a channel plug and a filling medium layer are formed in the channel hole 310.

[0096] In one embodiment of this application, a barrier layer, a charge trapping layer and a tunneling layer may be sequentially formed on the inner wall of the channel hole 310, and a channel layer 330 may be formed on the surface of the tunneling layer.

[0097] The functional layer 320 and the channel layer 330 can be formed in the channel hole 310 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0098] Specifically, functional layer 320 may include a barrier layer that blocks charge outflow, a charge trapping layer on the surface of the barrier layer to store charge during operation of the three-dimensional memory, and a tunneling layer on the surface of the charge trapping layer. The barrier layer may include one or more layers, which may include one or more materials. Materials for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, or other wide-bandgap materials. The charge trapping layer may include one or more layers, which may include one or more materials. Materials for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, or other wide-bandgap materials. The tunneling layer may include one or more layers, which may include one or more materials. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as alumina or hafnium oxide, or other wide-bandgap materials.

[0099] In some embodiments, functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in other embodiments, functional layer 320 may have a structure different from the ONO configuration. For example, functional layer 320 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0100] The channel layer 330 can be used to transport the required charge (electrons or holes). According to an exemplary embodiment of this application, the channel layer 330 can be formed on the surface of the tunneling layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0101] In some embodiments, the channel layer 330 may comprise silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer 330 includes, but is not limited to, p-type doped polycrystalline silicon. Similar to the via 310, the channel layer 330 also extends through the stack structure 200 and into the dielectric stack 201.

[0102] Figure 6 A cross-sectional schematic diagram of the structure formed after forming the first virtual channel structure 600-1 according to one embodiment of the preparation method of this application. Figure 7 A cross-sectional view of the structure formed after forming a word line structure 171, a peripheral contact 172, and a conductive contact 173 of a peripheral circuit 700 according to one embodiment of the present application.

[0103] like Figure 6 and Figure 7As shown, after forming the channel structure 300 and the step structure 500, the fabrication method 1000 of the three-dimensional memory provided in this application further includes: forming a gate gap structure 400; forming a gate layer 230; forming a virtual channel structure including a first virtual channel structure 600-1; annealing conductive impurities located in the source region 703 and the drain region 704 in the peripheral circuit with the heat generated during the formation of the channel structure 300, the gate gap structure 400 and the step structure 500; and forming a word line structure 171, a peripheral contact 172 and a conductive contact 173 of the peripheral circuit 700.

[0104] Specifically, in one embodiment of this application, a virtual channel structure can also be formed in the step region of the stacked structure 200 to provide structural support for the removal of the gate sacrificial layer during the subsequent formation of the gate layer. Its formation process is similar to that of the channel structure 300 and will not be described in detail here.

[0105] Combination Figure 5 and Figure 6 Because the three-dimensional memory structure provided in this application includes two parts, 500-1 and 500-2, the first step region 500-1 can be disposed in the first region 01 and formed in the portion of the stacked structure 200 opposite to the peripheral circuit 700 (it can be understood that a small portion of the first step region 500-1 is located above the peripheral circuit 700), and the second step region can be disposed in the second region 02 and formed on the side of the stacked structure 200 away from the peripheral circuit 700. Therefore, the virtual channel structure provided in this application can be formed simultaneously in the first region 01 and the second region 02.

[0106] The virtual channel structure may include a first virtual channel structure 600-1 and a second virtual channel structure 600-2, wherein a plurality of first virtual channel structures 600-1 are located above the peripheral circuit 700 and are directly opposite any one of the first contact 706, the second contact 707, and the third contact 705. Specifically, refer again Figure 6 In order to form conductive contacts of the peripheral circuit 700 in the first virtual channel 600-1, thereby providing structural support for the part of the stacked structure facing the peripheral circuit 700 during the subsequent formation of the gate layer; and to reduce the size of the step region in the stacked structure 200 and increase the bit density of the three-dimensional memory, the first virtual channel structure 600-1 formed above the peripheral circuit 700 can be directly opposite one of the first contact 706, the second contact 707 and the third contact 705 respectively.

[0107] like Figure 7 As shown, in forming the first virtual channel 600-1 (as shown) Figure 6 (as shown) and the second virtual channel 600-2 (as shown) Figure 6(As shown) After that, a gate gap 410 having a spacing with the channel structure 300 in the first direction can be formed in the stacked structure 200.

[0108] The gate gap 410 extends through the stacked structure 200 and into the dielectric stack 201 in a direction perpendicular to the initial substrate 100. The gate gap 410 can be formed, for example, by a dry etching process or a combination of dry and wet etching processes.

[0109] Furthermore, the gate gap 410 can be used as a pathway to provide etchant and chemical precursors, and processes such as wet etching can be used to remove all gate sacrificial layers 220 and 220' in the stacked structure 200 (e.g., Figure 4 (As shown) to form a sacrificial gap.

[0110] After the sacrificial gap is formed, a gate layer 230 can be formed in the sacrificial gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The gate layer 230 can be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0111] Furthermore, prior to forming the gate layer 230, the method 1000 for fabricating a three-dimensional memory according to one embodiment of this application further includes forming a dielectric layer (not shown) on the inner wall of the sacrificial gap and the inner sidewall of the gate gap 410 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. As an option, the dielectric layer may be a high-dielectric-constant dielectric layer. Further, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may also be used to form a dielectric layer on the insulating layer 210 (or insulating layer 210', such as...). Figure 4 An adhesive layer (e.g., a titanium nitride TiN layer, not shown) is formed between the dielectric layer and the gate layer 230 or between the dielectric layer and the gate layer 230.

[0112] The gate layer 230 may extend laterally (perpendicular to the thickness direction of the stack structure 200) as a word line and terminate at one or more step structures 500-1 and 500-2 of the stack structure 200.

[0113] Furthermore, in some embodiments of this application, after forming the gate layer 230, a gate gap structure 400 can also be formed by filling the gate gap 410. Specifically, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the gate gap 410 with a dielectric layer to form the gate gap structure 400.

[0114] like Figures 5 to 7As shown, in the method 1000 for fabricating a three-dimensional memory provided in this application, the formation of the channel structure 300, gate gap structure 400, and stepped structure (including virtual channel structures 600-1 and 600-2) on one side of the initial substrate 100 requires extensive heat treatment and thermal processing, such as deep-hole etching processes for forming channel holes, gate gaps, and virtual channel holes. Furthermore, in the peripheral circuit 700 formed on the other side of the initial substrate 100, conductive impurities in the source region 703 and drain region 704 require rapid thermal annealing to achieve thermal activation and repair. Therefore, through the isolation structure between the three-dimensional memory array and the peripheral circuit, the heat generated by the aforementioned heat treatment and thermal processing can be transferred to the peripheral circuit on the same substrate, and the conductive impurities in the source and drain regions can be annealed. Further, the dimensions of the dielectric stack 201 in the first direction (word line direction) or its thickness in the direction perpendicular to the initial substrate 100 can be changed to allow the aforementioned heat to be transferred more uniformly to the peripheral circuit on the same substrate.

[0115] The three-dimensional memory also includes word line contacts 171 electrically connected to the gate layer 230, peripheral contacts 172 formed in the stacked structure 200 and forming ohmic contacts with the well layer of the dielectric stack 201, and conductive contacts 173 of the peripheral circuitry 700.

[0116] Specifically, in combination Figure 6 and Figure 7 After forming the gate line slot structure 400, openings for the peripheral contacts 172, word line contacts 171, and conductive contacts 173 of the peripheral circuit 700 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The conductive contacts 173 of the peripheral circuit 700 may include a first portion 173-2 and a second portion 173-1. The second portion 173-1 may be one of a first contact 706, a second contact 707, and a third contact 705. The first portion 173-2 penetrates the first virtual channel structure 600-1 and is electrically connected to the second portion 173-1, thereby forming the conductive contacts 173 of the peripheral circuit 700.

[0117] The openings for the peripheral contact 172, word line contact 171, and conductive contact 173 of the peripheral circuit 700 can then be filled with a conductive material using CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material forming the peripheral contact 172, word line contact 171, and conductive contact 173 of the peripheral circuit 700 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials. In some embodiments, when preparing the peripheral contact, word line contact, and conductive contact, a layer of conductive material (e.g., titanium nitride TiN) may be deposited as a contact layer before depositing another conductive material.

[0118] Furthermore, openings for vias can be formed using a dry etching process or a combination of dry and wet etching processes. Some vias are configured as conductive contacts 172, word line contacts 171, and peripheral circuitry 700. Other vias are configured as bit line contacts that electrically contact the upper end of the corresponding memory cell and individually address the corresponding memory cell. Similar to the via formation process, openings can be created and then filled to form contacts used for interconnection with peripheral devices. These contacts are electrically connected to the aforementioned vias. After forming the interconnect contacts, peripheral circuitry chips can be connected to the side of the stack-up structure 200 away from the initial substrate 100.

[0119] In the fabrication method of the three-dimensional memory provided in this application, the conductive contacts (conductive contacts 173) of the peripheral circuit can be formed in a portion of the virtual channel (first virtual channel structure 600-1) of the three-dimensional memory. This not only provides structural support for the portion of the stacked structure facing the peripheral circuit during the formation of the gate layer, but also reduces the size of the step region in the stacked structure, thereby increasing the bit density of the three-dimensional memory.

[0120] Figure 8 A cross-sectional view of a structure formed by connecting a peripheral circuit chip 3000 to the side of the stacked structure 200 away from the initial substrate 100, according to a method for preparing a method according to one embodiment of this application. Figure 9 A cross-sectional schematic diagram of the structure formed after removing a portion of the initial substrate 100 and the first barrier dielectric layer 11 according to an embodiment of this application. Figure 10 A cross-sectional schematic diagram of the structure formed after removing a portion of the first semiconductor layer 12 and the second barrier dielectric layer 13 according to one embodiment of the present application. Figure 11 A cross-sectional schematic diagram of the structure formed after forming the initial conductive layer 120' according to one embodiment of the present application. Figure 12 A cross-sectional schematic diagram of the structure formed after forming the conductive layer 120 according to one embodiment of the present application.

[0121] like Figures 7 to 12As shown, after forming the peripheral contact 172, word line contact 171, and conductive contact 173, the fabrication method 1000 of the three-dimensional memory provided in this application further includes: connecting a peripheral circuit chip 3000 to the side of the stacked structure 200 away from the initial substrate 100; removing a portion of the initial substrate 100 and a portion of the dielectric stack 201 containing the first barrier dielectric layer 11; removing a portion of the first semiconductor layer 12 and the second barrier dielectric layer 13, and retaining at least the portion of the first semiconductor layer 12 located on the surface of the first filling layer 710, thereby exposing the second semiconductor layer 14 and the functional layer 320; removing the exposed functional layer 320 to expose the corresponding channel layer 330; doping the exposed channel layer 330; forming an initial conductive layer 120' connected to the exposed channel layer 330 on the surface of the second semiconductor layer 14 and the remaining surface of the first semiconductor layer 12; and forming the conductive layer 120.

[0122] like Figure 8 As shown, after the interconnect contacts are formed, the peripheral circuit chip 3000 can be connected to the side of the stacked structure 200 away from the initial substrate 100. In one embodiment of this application, the peripheral circuit chip 3000 may include any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits.

[0123] Specifically, the peripheral circuit chip 3000 can be placed above the top surface of the memory device where contacts are provided. Then, an alignment step is performed and one surface of the peripheral circuit chip 3000 is bonded to the top surface of the stacked structure 200 by, for example, a bonding process.

[0124] By forming some of the peripheral circuitry (e.g., peripheral high-voltage circuitry) of the 3D memory on the same substrate as the 3D memory array, and placing some of the peripheral circuitry (e.g., peripheral low-voltage circuitry and peripheral ultra-low-voltage circuitry) of the 3D memory on another chip, the overall size of the peripheral chips can be relatively reduced, thereby improving the storage density and integrability of the 3D memory.

[0125] Figure 9 To be Figure 8 A cross-sectional view of the structure formed after the structure is flipped 180° and part of the initial substrate 100 and the first barrier dielectric layer 11 are removed. Combined with... Figure 8 and Figure 9The initial substrate 100 can be partially removed using processes such as chemical mechanical polishing (CMP), dry etching, or a combination of dry and wet etching to expose the first barrier dielectric layer 11. Alternatively, only the portion of the initial substrate 100 belonging to the peripheral circuit 700 can be retained. During the removal of the initial substrate 100, the first barrier dielectric layer 11 can be used as a stop layer for the etching process to increase the etching process window, avoid damage to the memory array structure during etching, and improve the performance of the three-dimensional memory.

[0126] Furthermore, processes such as chemical mechanical polishing (CMP), dry etching, or a combination of dry and wet etching can be used to further remove part of the first barrier dielectric layer 11, leaving only the portion located in the first region 01, so as to expose the portion of the first semiconductor layer 12 located in the second region 02.

[0127] Furthermore, in one embodiment of this application, after exposing the portion of the first semiconductor layer 12 located in the second region 02, an isolation protective layer 15 may be formed on the remaining initial substrate 100 (the portion located in the first region 01) to prevent damage to the peripheral circuit 700 by etching processes or the like in subsequent removal steps.

[0128] Combination Figure 8 and Figure 10 The first semiconductor layer 12 and the second barrier layer 13 can be further removed using processes such as chemical mechanical polishing (CMP), dry etching, or a combination of dry and wet etching to expose a portion of the second semiconductor layer 14 in the second region 02 and the portion of the channel layer 320 extending into the dielectric stack 201. During this removal process, the second barrier dielectric layer 13 can be used as a stop layer for the etching process to increase the etching process window, avoid damage to the memory array structure during etching, and improve the performance of the three-dimensional memory.

[0129] Furthermore, processes such as chemical mechanical polishing (CMP), dry etching, or a combination of dry and wet etching can be used to remove the exposed functional layer 320 to expose the corresponding 330.

[0130] Specifically, the exposed functional layer 320 can be removed to expose the channel layer 330 by employing multiple, for example, dry etching processes or a combination of dry and wet etching processes. In other words, the barrier layer, charge trapping layer, and tunneling layer of the exposed functional layer 320 can be removed sequentially by employing multiple, for example, dry etching processes or a combination of dry and wet etching processes until a portion of the channel layer 330 is exposed.

[0131] In some embodiments, the functional layer 320, which includes a barrier layer, a charge storage layer, and a tunneling layer, may have an oxide-nitride-oxide (ONO) structure surrounding the channel layer 330. An ONO removal process may be performed to sequentially remove each layer in the exposed functional layer 320 until a portion of the channel layer 330 is exposed.

[0132] Combination Figure 8 , Figure 11 and Figure 12 After the second semiconductor layer 14 and the channel layer 330 are exposed, a conductive layer 120 that contacts the exposed channel layer 330 can be formed on the surface of the exposed second semiconductor layer 14 and the remaining first semiconductor layer 12.

[0133] Specifically, an initial conductive layer 120' may be formed on the surface of the exposed second semiconductor layer 14 and the remaining first semiconductor layer 12, wherein the initial conductive layer 120' is in contact with the exposed channel layer 330. The initial conductive layer 120' may be formed using a thin film deposition process such as any one or any combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and metal-organic chemical vapor deposition (MOCVD).

[0134] Alternatively, the initial conductive layer 120' can be a composite structure formed by multiple thin film deposition processes and other processes, such as a composite structure formed by a semiconductor layer encapsulating an insulating layer.

[0135] Alternatively, the initial conductive layer 120' may also be a highly doped semiconductor layer formed using any one or a combination of processes including chemical vapor deposition, physical vapor deposition, atomic layer deposition, and metal-organic chemical vapor deposition. The semiconductor layer may be doped with any suitable, for example, N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. Further, the initial conductive layer 120' may be a polycrystalline silicon layer doped with, for example, an N-type dopant (e.g., P, Ar, or Sb).

[0136] like Figure 11 and Figure 12As shown, the surface of the initial conductive layer 120' can be planarized and processed, for example, by using a chemical mechanical polishing process (Buffer CMP) with a low abrasion rate to form the conductive layer 120.

[0137] Furthermore, in one embodiment of this application, to achieve a good and stable electrical connection between the channel layer 330 and the conductive layer 120, thereby improving the electrical performance of the three-dimensional memory, the exposed channel layer 330 can be heavily doped again before the step of forming the initial conductive layer 120. The exposed channel layer 330 can be doped, for example, by a process such as ion implantation (IMP). The aforementioned N-type doping can include any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. Figure 11 As shown, after the exposed channel layer 330 is highly doped again, the channel layer 330 may include a first channel layer 331 formed by a secondary doping process.

[0138] Figure 13 This is a cross-sectional view of a three-dimensional memory 2000 according to one embodiment of this application.

[0139] like Figure 13 As shown, another aspect of this application provides a three-dimensional memory 2000. This three-dimensional memory 2000 can be fabricated using any of the above-described fabrication methods. The three-dimensional memory 2000 may include: a substrate 100', peripheral circuitry 700, a dielectric stack 201', a stacked structure 200, and a channel structure 300. The peripheral circuitry 700 is formed on the substrate 100' and covered by a first filler layer 710. The dielectric stack 201' covers the surface of the first filler layer 710. The stacked structure 200 consists of multiple pairs of alternately stacked insulating layers (not shown) and gate layers 230, and includes a first stacked structure 202' and a second stacked structure 203' in the direction perpendicular to the X. The first stacked structure 202' is formed on the surface of the substrate 100' and the side surface of the dielectric stack 201' (which can be understood as the side surface being located in the direction perpendicular to the X). The top surface of the first stacked structure 202' (which can be understood as the top surface being away from the substrate 100' and opposite to the substrate 100') is flush and coplanar with the top surface of the dielectric stack 201' (which can be understood as the top surface being away from the substrate 100' and opposite to the substrate 100'). The second stacked structure 203' is disposed on the same plane. A channel structure 300 penetrates the stacked structure 200. The X direction is the first direction and can be understood as the extension direction of the gate 230.

[0140] According to the three-dimensional memory provided in this application, by forming the peripheral circuit and the three-dimensional memory array on different horizontal planes of the same substrate, the size of the peripheral circuit wafer can be effectively reduced while the aspect ratio of the contact holes of the peripheral circuit can be reduced, which in turn helps to reduce the interconnection process difficulty of the three-dimensional memory.

[0141] Furthermore, in one embodiment of this application, the first stacked structure 202' and the second stacked structure 203' may be composed of the first stacked structure 202 and the second stacked structure 203 (e.g., Figure 4 Remove gate sacrificial layers 220 and 220' (as shown) Figure 4 The gate layer 230 is formed by filling it with conductive material after (as shown).

[0142] Furthermore, in one embodiment of this application, the three-dimensional memory 2000 further includes a peripheral circuit chip 3000 disposed on the side of the stacked structure 200 away from the substrate 100'. In other words, in this embodiment, the peripheral circuit of the three-dimensional memory may include two parts, one part being peripheral circuits formed on a different horizontal plane of the same substrate as the three-dimensional memory array, which may specifically include any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits; the other part is formed on the peripheral circuit chip, which may also specifically include any one or a combination of peripheral high-voltage circuits, peripheral low-voltage circuits, and peripheral ultra-low-voltage circuits.

[0143] As an alternative, since the peripheral high-voltage circuit requires a thicker substrate that can withstand high temperatures, the fabrication process of the peripheral high-voltage circuit is easily compatible with the fabrication process of the three-dimensional memory array. Therefore, the peripheral high-voltage circuit and the three-dimensional memory array can be formed on the same substrate, while the relatively large number of peripheral low-voltage circuits and peripheral ultra-low-voltage circuits are placed on the peripheral circuit chip, thereby effectively reducing the overall size of the three-dimensional memory and increasing the storage density of the three-dimensional memory.

[0144] Furthermore, in the above embodiment, the stacked structure 200 is located between the substrate of the peripheral circuit chip 3000 and the substrate 100'. Therefore, optionally, the pad leads of the three-dimensional memory can also be disposed on the side of the substrate 100' away from the stacked structure 200.

[0145] The three-dimensional memory 2000 provided in this application arranges the peripheral circuits for controlling the input and output of the memory array on the peripheral circuit chip 3000 and the substrate 100', respectively. In other words, by forming some of the peripheral circuits (e.g., peripheral high-voltage circuits) on the same substrate as the three-dimensional memory array, and placing some of the peripheral circuits (e.g., peripheral low-voltage circuits and peripheral ultra-low-voltage circuits) on another chip, the overall size of the peripheral chips can be relatively reduced, thereby improving the storage density and integrability of the three-dimensional memory.

[0146] In addition, such as Figure 5 As shown, in one embodiment of this application, the substrate 100' can be divided along the X direction into a first region 01 and an adjacent second region 02. The stacked structure 200 includes a memory array region and a step region, wherein the memory array region is used to form a channel structure 300, and the step region is located at the periphery of the memory array region and includes a first step region 500-1 and a second step region 500-2, with at least a portion of the first step region 500-1 located above the peripheral circuit 700. Therefore, in the three-dimensional memory provided in this application, the step region may include a first step region and a second step region, wherein at least a portion of the first step region is formed above the peripheral circuit, which can relatively reduce the size of the step region in the stacked structure and improve the bit density of the three-dimensional memory.

[0147] like Figure 3 , Figure 6 and Figure 7 As shown, in one embodiment of this application, the peripheral circuit 700 may include a gate structure 702 formed on the substrate 100 and a source region 703 and a drain region 704 respectively formed in portions of the substrate 100 located on both sides of the gate structure 702. The three-dimensional memory 2000 further includes a virtual channel structure formed in the stepped region of the stacked structure 200. The virtual channel structure may include a first virtual channel structure 600-1 located above the peripheral circuit 700 and directly opposite any one of the first contact 706, the second contact 707 and the third contact 705, wherein the first contact 706, the second contact 707 and the third contact 705 are directly opposite the source region 703 and the drain region 704 and the gate structure 702 respectively and form an electrical connection.

[0148] Furthermore, the conductive contact 173 of the peripheral circuit 700 may include a first portion 173-2 of the conductive contact and a second portion 173-1 of the conductive contact, wherein the second portion 173-1 of the conductive contact may be any one of the first contact 706, the second contact 707 and the third contact 705, and the first portion 173-2 of the conductive contact penetrates the first virtual channel structure 600-1 and is electrically connected to any one of the first contact 706, the second contact 707 and the third contact 705.

[0149] The three-dimensional memory provided in this application allows the conductive contacts of the peripheral circuitry to be formed within a portion of the virtual channel structure (first virtual channel structure) of the three-dimensional memory. Therefore, not only can structural support be provided for the portion of the stacked structure facing the peripheral circuitry during the formation of the gate layer, but the size of the step region in the stacked structure can also be relatively reduced, thereby increasing the bit density of the three-dimensional memory.

[0150] In addition, refer to again Figure 13In one embodiment of this application, substrate 100' may include a first portion and a second portion made of different materials (the first portion may be, for example, a first region 01, and the second portion may be, for example, a second region 02). Peripheral circuitry 700 is disposed on the first portion of substrate 100' and covered by a first filler layer 710. The second portion of substrate 100' further includes a conductive layer 120. A dielectric stack 201' covers the surface of the first filler layer 710 and extends to contact the conductive layer 120, so that peripheral circuitry 700 and channel structure 300 are spaced apart on substrate 100' through the dielectric stack 201' and the first filler layer 710. Channel structure 300 is formed on the second portion of substrate 100' and extends through the stack 200 to connect with conductive layer 120.

[0151] like Figure 4 As shown, in one embodiment of this application, the dielectric stack 201 may include a first barrier dielectric layer 11, a first semiconductor layer 12, a second barrier dielectric layer 13, and a second semiconductor layer 14 formed sequentially. Alternatively, the first semiconductor layer 12 and the second semiconductor layer 14 may be made of a semiconductor material, such as polysilicon. In the first semiconductor layer 12 and the second semiconductor layer 14, well regions formed by doping with N-type or P-type dopants via ion implantation or diffusion processes may be formed. The dopants may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of this application, the well regions may be prepared with the same dopant or with different dopants. Furthermore, the doping concentration of the well regions may be the same or different, and this application does not limit this. The first barrier dielectric layer 11 and the second barrier dielectric layer 13 may include any one or more of dielectric materials, semiconductor materials, and conductive materials, such as any one or more of silicon oxide layers, silicon nitride layers, and silicon oxynitride layers. Alternatively, the first barrier dielectric layer 11 and the second barrier dielectric layer 13 may also include a high-dielectric-constant dielectric layer.

[0152] On the one hand, the dielectric stack can form an isolation structure together with the already formed first fill layer, isolating the peripheral circuitry from the subsequently formed three-dimensional memory array. This further prevents substances such as hydrogen or other plasmas generated or used during the fabrication of the three-dimensional memory array from diffusing into the peripheral circuitry, thereby improving the reliability of the three-dimensional memory. On the other hand, the dielectric stack can serve as a partial substrate structure, in which memory array structures such as channel structures and gate gap structures are formed. Furthermore, during the formation of the above structure, the first barrier dielectric layer 11 and the second barrier dielectric layer 13 can serve as stop layers for the etching process, increasing the etching process window, preventing damage to the memory array structure from the etching process, and improving the performance of the three-dimensional memory.

[0153] like Figure 13As shown, in one embodiment of this application, the conductive channel structure 300 of the three-dimensional memory 2000 may include a channel hole and a functional layer and a channel layer 330 sequentially formed on the inner wall of the channel hole. The channel layer 330 also includes a first channel layer 331 formed by secondary doping. In other words, the portion of the channel layer 330 extending into and adjacent to the conductive layer 120 is doped to a higher doping concentration than other portions of the channel layer 330 through a secondary doping process. The inclusion of the first channel layer formed by two doping processes in the channel layer 330 enables a good and stable electrical connection between the channel layer and the conductive layer, improving the electrical performance of the three-dimensional memory.

[0154] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0155] Although exemplary methods and structures for fabricating three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the materials of the layers described are merely exemplary.

[0156] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method of fabricating a three-dimensional memory, comprising: The method comprises: forming a peripheral circuit in a first region defined on an initial substrate, and covering the first region with a first fill layer, wherein the peripheral circuit is a peripheral high voltage circuit; forming a recess in a portion of the initial substrate other than the first region, and forming a first stack structure in the recess; forming a second stack structure on the first stack structure and the peripheral circuit, wherein the first stack structure and the second stack structure collectively constitute a stack structure of the memory; forming a channel structure through the stack structure; and connecting a peripheral circuit chip to a side of the stack structure distal to the initial substrate, wherein the peripheral circuit chip comprises any one or a combination of a peripheral low voltage circuit and a peripheral ultra-low voltage circuit.

2. The method of claim 1, wherein the first fill layer comprises a first initial fill layer and a second initial fill layer, characterized in that, forming a peripheral circuit in the first region, and covering the first region with the first fill layer comprises: forming a peripheral circuit in the first region; covering the first region with the first initial fill layer; forming a first contact, a second contact, and a third contact in electrical communication with a source region, a drain region, and a gate structure of the peripheral circuit, respectively; and covering the first initial fill layer with the second initial fill layer.

3. The method of claim 2, wherein the memory comprises a channel structure, a gate gap structure, and a step structure, and wherein: annealing conductive impurities located at the source region and the drain region by heat generated during formation of the channel structure, the gate gap structure, and the step structure.

4. The method of claim 1, wherein, the stack structure comprises a memory array region and a step region, and wherein: the memory array region is configured to form the channel structure, and the step region is located at a periphery of the memory array region; and the step region comprises a first step region and a second step region, and at least a portion of the first step region is located above the peripheral circuit.

5. The method of claim 2, wherein, After forming the channel structure, the method further comprises forming a dummy channel structure and forming a conductive contact of the peripheral circuit, and the method of forming the dummy channel structure and the conductive contact comprises: forming a first dummy channel structure directly above any one of the first contact, the second contact, and the third contact; and forming a first portion of the conductive contact through the first dummy channel structure, the first portion being in electrical communication with any one of the first contact, the second contact, and the third contact.

6. The method of claim 5, wherein: the first dummy channel structure comprises a first dummy channel hole; the first fill layer further comprises a barrier layer located between the first initial fill layer and the second initial fill layer, and covering a top surface of the first contact, a top surface of the second contact, and a top surface of the third contact; and the process of forming the first dummy channel hole stops at the barrier layer. forming a first stack structure in the recess comprises:

7. The method of claim 1, wherein, conformally covering an inner wall of the recess and a surface of the first fill layer with a dielectric stack; and forming the first stack structure in a remaining portion of the recess. ​ 8. The method of claim 7, wherein, The medium stack includes a first barrier medium layer, a first semiconductor layer, a second barrier medium layer, and a second semiconductor layer formed in sequence, and the channel structure penetrates through the stack structure and extends into the medium stack, the channel structure includes a channel hole and a functional layer and a channel layer arranged in sequence on the inner wall of the channel hole, after the channel structure is formed, the method further includes: removing part of the initial substrate and part of the medium stack to expose part of the functional layer extending into the medium stack, and at least retaining part of the first semiconductor layer on the surface of the first filling layer and the second semiconductor layer; removing the exposed functional layer to expose the channel layer corresponding thereto; and forming a conductive layer connected with the exposed channel layer on the surface of the second semiconductor layer and the surface of the remaining first semiconductor layer.

9. The method of claim 7, wherein, forming a second stack structure on the first stack structure and the peripheral circuit includes: planarizing the top surface of the first stack structure so that the top surface of the first stack structure is flush with the top surface of the part of the medium stack on the first filling layer, thereby forming a coplanar surface.

10. A three-dimensional memory, comprising: The memory includes: a substrate; a peripheral circuit formed on the substrate and covered with a first filling layer, wherein the peripheral circuit is a peripheral high-voltage circuit; a medium stack covering the surface of the first filling layer; a stack structure including a first stack structure and a second stack structure, wherein the first stack structure is formed on the surface of the substrate and the side surface of the medium stack, the top surface of the first stack structure is flush with the top surface of the medium stack, and the second stack structure is arranged on the coplanar surface; a channel structure penetrating through the stack structure; and a peripheral circuit chip located on the side of the stack structure away from the substrate, wherein the peripheral circuit chip includes any one or a combination of a peripheral low-voltage circuit and a peripheral ultra-low-voltage circuit.

11. The memory of claim 10, wherein, The stack structure includes a storage array area for forming the channel structure and a step area located at the periphery of the storage array area, wherein the step area includes a first step area and a second step area, and at least part of the first step area is located above the peripheral circuit.

12. The memory of claim 11, wherein, The peripheral circuit includes a gate structure formed on the substrate and a source region and a drain region formed in the parts of the substrate located on both sides of the gate structure, respectively, and the memory further includes: a virtual channel structure formed in the step area, the virtual channel structure includes a first virtual channel structure located above the peripheral circuit and directly opposite any one of a first contact, a second contact, and a third contact, wherein the first contact, the second contact, and the third contact are directly opposite and electrically connected to the source region, the drain region, and the gate structure, respectively.

13. The memory of claim 12, wherein, The peripheral circuit further includes: a conductive contact including a first part penetrating through the first virtual channel structure and electrically connected to any one of the first contact, the second contact, and the third contact.

14. The memory of claim 10, wherein, The medium stack includes: A first barrier medium layer, a first semiconductor layer, a second barrier medium layer and a second semiconductor layer are sequentially formed on the first filling layer.

15. The memory of claim 10, wherein, The substrate includes a first portion and a second portion of different materials, the peripheral circuit is formed on the first portion, and the second portion includes a conductive layer which is in contact with the dielectric stack and electrically connected with the channel structure.

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