Array substrate, manufacturing method thereof, and display device

Abstract

This disclosure provides an array substrate and its fabrication method, as well as a display device, relating to the field of display technology. The array substrate includes a substrate, a plurality of sub-pixels arranged in an array on the substrate, and thin-film transistors driving each sub-pixel. The array substrate includes pixel electrodes; the channel region of the thin-film transistors comprises a metal-oxide-semiconductor layer, and the pixel electrodes are conductive metal-oxide-semiconductor layers formed by conductiveizing the metal-oxide-semiconductor. The channel region of the thin-film transistors and the pixel electrodes are formed by patterning the same metal-oxide-semiconductor layer. In the embodiments of this disclosure, the semiconductor channel region and the conductive pixel electrodes can be formed by a single patterning step based on the same metal-oxide-semiconductor layer, reducing the mask patterning process, simplifying the process steps, and reducing the process complexity.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a method for fabricating the same, and a display device. Background Technology

[0002] Currently, thin film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, and lack of radiation.

[0003] In the current fabrication process of lateral electric field type TFT-LCD array substrates, the required patterns can be formed on each film layer through the mask process. In the current mainstream fabrication process, array substrates using bottom gate structure oxide TFTs require 6 mask processes, and array substrates using top gate structure oxide TFTs require 9 mask processes. This makes the fabrication process of array substrates too complicated, the production cycle is long, and the cost is high. Summary of the Invention

[0004] This disclosure provides an array substrate, including a substrate, a plurality of sub-pixels arranged in an array on the substrate, and thin-film transistors driving each of the sub-pixels, the array substrate including pixel electrodes;

[0005] The channel region of the thin-film transistor includes a metal oxide semiconductor layer, and the pixel electrode is a metal oxide conductive layer formed by conductor-forming the metal oxide semiconductor. The channel region of the thin-film transistor and the pixel electrode are formed by patterning the same metal oxide semiconductor layer.

[0006] Optionally, the thin-film transistor includes a gate located between the channel region and the substrate; the thin-film transistor includes a common electrode and an auxiliary layer, the auxiliary layer and the common electrode being formed through the same metal oxide semiconductor thin film, the auxiliary layer and the common electrode being an integral structure, the gate being disposed on the auxiliary layer, and the common electrode including at least a conductive layer formed by a conductorization process of the metal oxide semiconductor thin film not covered by the gate.

[0007] Optionally, the auxiliary layer is an IGZO semiconductor film, and the common electrode is an IGZO conductive layer.

[0008] Optionally, the thin-film transistor includes a source and a drain, the pixel electrode includes a plurality of strip electrodes, the channel region is connected to the strip electrode at one edge of the pixel electrode to form an integral structure, the source and drain are disposed on the channel region, the source and drain include a source and a drain, the drain covers a portion of the pixel electrode and overlaps with the pixel electrode.

[0009] Optionally, the array substrate includes a passivation layer that covers the source / drain electrodes, the channel region, and the unconductive metal-oxide-semiconductor layer of the exposed pixel electrode region, and the exposed metal-oxide-semiconductor layer is ion-implanted to form a conductive pixel electrode.

[0010] Optionally, the thin-film transistor includes a gate and a gate insulating layer, the channel region is located between the gate and the substrate, the gate insulating layer covers the channel region, and the gate is disposed on the gate insulating layer; the thin-film transistor further includes an auxiliary conductive layer connecting the channel region and the pixel electrode, the channel region is located between the auxiliary conductive layers, the auxiliary conductive layer, the channel region and the pixel electrode are formed through the same metal oxide semiconductor thin film, and the auxiliary conductive layer and the pixel electrode include conductive layers formed by a conductor-forming process on the metal oxide semiconductor thin film in the area of ​​the gate insulating layer not covered by the gate.

[0011] Optionally, the channel region is an IGZO semiconductor film layer, and the auxiliary conductive layer and the pixel electrode are IGZO conductive layers.

[0012] Optionally, the pixel electrode includes a plurality of strip electrodes, and the auxiliary conductive layer is connected to the strip electrode of one edge of the pixel electrode to form an integral structure.

[0013] Optionally, the thin-film transistor includes a common electrode, a patterned light-shielding portion formed on the common electrode, a patterned photoresist layer formed on the light-shielding portion, a first buffer layer covering the common electrode, the light-shielding portion and the photoresist layer, and the channel region and the pixel electrode formed on the first buffer layer.

[0014] Optionally, the thin-film transistor further includes a patterned interlayer insulating layer that covers the gate, the edge of the auxiliary conductive layer near the channel region, and partially covers the auxiliary conductive layer located on the side of the gate near the pixel electrode, wherein the orthographic projection of the pixel electrode on the substrate does not overlap with the orthographic projection of the interlayer insulating layer on the substrate.

[0015] Optionally, the thin-film transistor further includes a source / drain electrode and a second buffer layer. The source / drain electrode is disposed on the interlayer insulating layer and includes a source and a drain. The source is connected to the auxiliary conductive layer located on the side of the gate away from the pixel electrode and exposed to the interlayer insulating layer. The drain is connected to the auxiliary conductive layer located on the side of the gate near the pixel electrode and exposed to the interlayer insulating layer. The second buffer layer covers the source / drain electrode and part of the interlayer insulating layer. The orthographic projection of the pixel electrode on the substrate does not overlap with the orthographic projection of the second buffer layer on the substrate.

[0016] This disclosure also provides a method for fabricating an array substrate, the array substrate comprising a plurality of sub-pixels arranged in an array and thin-film transistors driving each of the sub-pixels, the method comprising:

[0017] A first metal oxide semiconductor layer is patterned using a halftone masking process; a shielding layer is provided on the side of the first metal oxide semiconductor layer away from the substrate;

[0018] Under the shielding layer, the first metal oxide semiconductor layer is made conductive. At least a portion of the first metal oxide semiconductor layer that is shielded by the shielding layer is not made conductive, forming the channel region of the thin film transistor. At least a portion of the first metal oxide semiconductor layer that is not shielded by the shielding layer is made conductive, forming the pixel electrode of the thin film transistor.

[0019] Optionally, before the first metal-oxide-semiconductor layer is patterned using a halftone mask process, the method further includes:

[0020] A second metal oxide semiconductor material layer is formed on the substrate;

[0021] A gate material layer is formed on the second metal oxide semiconductor material layer;

[0022] The second metal oxide semiconductor material layer is patterned to form the second metal oxide semiconductor layer using a halftone mask process, and the gate material layer is patterned to form the gate.

[0023] A gate insulating material layer is formed covering the second metal oxide semiconductor layer and the gate;

[0024] Under the shielding of the gate, the second metal oxide semiconductor layer is made conductive. The portion of the second metal oxide semiconductor layer not shielded by the gate is made conductive, and the conductive portion diffuses toward the gate to form a common electrode. The remaining portion of the second metal oxide semiconductor layer is not made conductive and forms an auxiliary layer.

[0025] The gate insulating material layer is patterned to form the gate insulating layer.

[0026] Optionally, the process of patterning the first metal-oxide-semiconductor layer using a halftone mask includes:

[0027] A first metal oxide semiconductor material layer is formed on the gate insulating layer;

[0028] A source / drain material layer is formed on the first metal oxide semiconductor material layer;

[0029] The first metal oxide semiconductor material layer is patterned to form the first metal oxide semiconductor layer using a halftone mask process, and the source and drain electrode material layer is patterned to form the source and drain electrode.

[0030] A passivation layer is formed by patterning; the passivation layer covers the source and drain electrodes and a portion of the first metal-oxide-semiconductor layer near the source and drain electrodes; the passivation layer is the shielding layer.

[0031] Optionally, the step of conductiveizing the first metal-oxide-semiconductor layer under the shielding layer, wherein at least a portion of the first metal-oxide-semiconductor layer shielded by the shielding layer is not conductive to form the channel region of the thin-film transistor, and at least a portion of the first metal-oxide-semiconductor layer not shielded by the shielding layer is conductive to form the pixel electrode of the thin-film transistor, includes:

[0032] Under the shielding of the passivation layer, the first metal oxide semiconductor layer is made conductive. The portion of the first metal oxide semiconductor layer not shielded by the passivation layer is made conductive, and the conductive portion diffuses toward the source and drain to form the pixel electrode of the thin film transistor. The remaining portion of the first metal oxide semiconductor layer is not made conductive and forms the channel region of the thin film transistor.

[0033] Optionally, before the first metal-oxide-semiconductor layer is patterned using a halftone mask process, the method further includes:

[0034] A common electrode material layer is formed on the substrate;

[0035] A light-shielding material layer is formed on the common electrode material layer;

[0036] The common electrode material layer is patterned to form a common electrode using a halftone mask process, and the light-shielding material layer is patterned to form a light-shielding layer; the photoresist required to form the light-shielding layer is retained, and a patterned photoresist layer is formed on the light-shielding layer;

[0037] A first buffer layer is formed covering the common electrode, the light-shielding portion, and the photoresist layer.

[0038] Optionally, the process of patterning the first metal-oxide-semiconductor layer using a halftone mask includes:

[0039] A first metal oxide semiconductor layer is patterned on the first buffer layer;

[0040] A gate insulating layer and a gate are patterned on the first metal oxide semiconductor layer; the gate is disposed on the gate insulating layer and the gate is the shielding layer.

[0041] Optionally, the step of conductiveizing the first metal-oxide-semiconductor layer under the shielding layer, wherein at least a portion of the first metal-oxide-semiconductor layer shielded by the shielding layer is not conductive to form the channel region of the thin-film transistor, and at least a portion of the first metal-oxide-semiconductor layer not shielded by the shielding layer is conductive to form the pixel electrode of the thin-film transistor, includes:

[0042] Under the shielding of the gate, the first metal-oxide-semiconductor layer is made conductive, and the portion of the first metal-oxide-semiconductor layer shielded by the gate is not made conductive, forming the channel region of the thin-film transistor. The remaining portion of the first metal-oxide-semiconductor layer is made conductive, forming an auxiliary conductive layer and the pixel electrode of the thin-film transistor. The auxiliary conductive layer connects the channel region and the pixel electrode, and the channel region is located between the auxiliary conductive layers.

[0043] Optionally, after the first metal-oxide-semiconductor layer is conductiveized under the shielding layer, and at least a portion of the first metal-oxide-semiconductor layer shielded by the shielding layer is not conductive to form the channel region of the thin-film transistor, and at least a portion of the first metal-oxide-semiconductor layer not shielded by the shielding layer is conductive to form the pixel electrode of the thin-film transistor, the method further includes:

[0044] An interlayer insulating material layer is patterned to form an interlayer insulating material layer; the interlayer insulating material layer covers the gate, the edge of the auxiliary conductive layer near the channel region, partially covers the auxiliary conductive layer located on the side of the gate near the pixel electrode, and the pixel electrode;

[0045] Source and drain electrodes are patterned on the interlayer insulating material layer; the source and drain electrodes include a source electrode and a drain electrode, the source electrode is connected to the auxiliary conductive layer located on the side of the gate away from the pixel electrode and exposed on the interlayer insulating material layer, and the drain electrode is connected to the auxiliary conductive layer located on the side of the gate close to the pixel electrode and exposed on the interlayer insulating material layer;

[0046] Form a second buffer material layer;

[0047] The second buffer material layer and the interlayer insulating material layer are patterned to form a second buffer layer and an interlayer insulating layer; the orthographic projection of the pixel electrode on the substrate does not overlap with the orthographic projection of the interlayer insulating layer and the second buffer layer on the substrate, and the second buffer layer covers the source and drain electrodes and the interlayer insulating layer.

[0048] This disclosure also provides a display device including the array substrate described above.

[0049] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 A cross-sectional view of an array substrate according to an embodiment of the present disclosure is shown;

[0052] Figure 2 A cross-sectional view of another array substrate according to an embodiment of the present disclosure is shown;

[0053] Figure 3 A flowchart illustrating the steps of a method for fabricating an array substrate according to an embodiment of the present disclosure is shown;

[0054] Figure 4-10 A cross-sectional view showing the fabrication process of an array substrate according to an embodiment of the present disclosure is shown;

[0055] Figure 11 Impedance data of IGZO before and after conductor formation and after baking are shown in the embodiments of this disclosure;

[0056] Figure 12 The transmittance data of IGZO before and after conductor formation and after baking are shown in the embodiments of this disclosure;

[0057] Figure 13 The following are some of the preparation conditions of IGZO and the lateral diffusion distance of IGZO conductor formation according to embodiments of the present disclosure;

[0058] Figure 14-22 A cross-sectional view showing the fabrication process of an array substrate according to an embodiment of the present disclosure is shown;

[0059] Figure 23-36 A cross-sectional view showing the fabrication process of an array substrate according to an embodiment of the present disclosure is shown. Specific Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0061] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The directional terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships based on the accompanying drawings; these relative positional relationships may also change accordingly when the absolute position of the described objects changes.

[0062] Figure 1 A cross-sectional view of an array substrate according to an embodiment of the present disclosure is shown. Figure 2 A cross-sectional view of another array substrate according to an embodiment of the present disclosure is shown, with reference to Figure 1 and Figure 2 The array substrate includes a substrate ( Figure 1 The Chinese character is marked as 200. Figure 2 The array substrate includes pixel electrodes (marked as 100), multiple sub-pixels arranged in an array on the substrate, and thin-film transistors driving each sub-pixel. Figure 1 The Chinese label is 204-3. Figure 2 (Identified as 105-2).

[0063] Among them, the channel region of the thin-film transistor (TFT) Figure 1 The Chinese identifier is 204-2. Figure 2 The image (marked as 105-1) contains a metal oxide semiconductor layer. The pixel electrode is a metal oxide conductive layer formed by conductor-forming a metal oxide semiconductor. The channel region of the thin film transistor and the pixel electrode are formed by patterning the same metal oxide semiconductor layer.

[0064] In this embodiment, the channel region of the thin-film transistor (TFT) and the pixel electrode can be formed by patterning the same metal-oxide-semiconductor (MOS) layer. The channel region of the TFT may include a non-conductive MOS layer, while the pixel electrode can be a conductive MOS layer formed by conductiveizing the MOS layer. Thus, the channel region and pixel electrode can be patterned once based on the same MOS material to form the MOS pattern for the channel region and the corresponding MOS pattern for the pixel electrode. Then, with the channel region pattern masked, the MOS pattern for the pixel electrode is conductiveized, thereby forming a semiconductor MOS channel region and a conductive MOS pixel electrode. In this embodiment, only one patterning step is required to form the channel region and pixel electrode, reducing the mask patterning process, simplifying the process steps, reducing process complexity, thereby lowering production costs, improving product market competitiveness, and showing broad application prospects.

[0065] In some alternative embodiments, refer to Figure 1 The thin-film transistor includes a gate 202, which may be located between the channel region 204-2 and the substrate 200.

[0066] In some optional embodiments, the array substrate can employ a bottom-gate oxide thin-film transistor (OTTFT), where the gate 202 is disposed close to the substrate 200, and the channel region 204-2 is located on the side of the gate 202 away from the substrate 200. In this embodiment, for an OTFT array substrate employing a bottom-gate structure, the channel region and pixel electrode can be formed in a single patterning step, thereby reducing the mask patterning process of the OTFT array substrate, simplifying the fabrication steps, and lowering the fabrication complexity.

[0067] The thin-film transistor includes a common electrode 201-2 and an auxiliary layer 201-1. The auxiliary layer 201-1 and the common electrode 201-2 are formed through the same metal oxide semiconductor thin film and are an integral structure. The gate 202 is disposed on the auxiliary layer 201-1. The common electrode 201-2 includes at least a conductive layer formed by a conductorization process on the metal oxide semiconductor thin film not covered by the gate 202.

[0068] The auxiliary layer 201-1 and the common electrode 201-2 can be an integral structure; therefore, they can be formed on the same metal-oxide-semiconductor layer. Furthermore, the gate 202 can be disposed on the auxiliary layer 201-1, and a portion of the common electrode 201-2 is not covered by the gate 202. Thus, the gate pattern and the common electrode pattern can be formed with only one patterning step. In this embodiment, only one patterning step is required to form the gate and the common electrode, thereby further reducing the mask patterning process, simplifying the process steps, and reducing the process complexity, based on the single patterning formation of the channel region and pixel electrode.

[0069] Specifically, in one optional implementation, the auxiliary layer 201-1 can be an IGZO (indium gallium zinc oxide) semiconductor film, and the common electrode 201-2 can be an IGZO conductive layer.

[0070] First, an IGZO material layer can be formed, then the IGZO material layer can be patterned, and then the patterned gate can be used as a shield to conduct the patterned IGZO material layer. The part of the IGZO material layer that is shielded by the gate and not conducted is used as an auxiliary layer 201-1, and the part of the IGZO material layer that is not shielded by the gate and is conducted is used as a common electrode 201-2.

[0071] In this implementation, the conductive IGZO diffuses laterally toward the gate 202, so that the gate 202 covers part of the conductive IGZO, that is, covers part of the common electrode 201-2. After the conductive IGZO diffuses laterally, it can form an ohmic contact with the gate 202, thus realizing the electrical connection between the gate 202 and the common electrode 201-2.

[0072] In another alternative implementation, both the auxiliary layer 201-1 and the common electrode 201-2 can be ITO (indium tin oxide) conductive layers.

[0073] First, an ITO material layer can be formed, and then the ITO material layer can be patterned. In conventional processes, after patterning, a baking process is required. After baking, the ITO material layer will be completely converted into a conductor, so that the auxiliary layer 201-1 and the common electrode 201-2 are both conductive ITO.

[0074] In this implementation, since the ITO material is baked and conductive simultaneously in the conventional baking process, there is no need to perform a separate conductive process for the common electrode, which further reduces the fabrication steps of the array substrate, simplifies the process, and reduces the complexity of the process.

[0075] In this implementation, the entire ITO layer is conductive, which can be seen as the gate 202 covering part of the conductive IGZO, that is, covering part of the common electrode 201-2.

[0076] Optionally, refer to Figure 1 The thin-film transistor includes source and drain electrodes 205. The pixel electrode 204-3 includes multiple strip electrodes. The channel region 204-2 is connected to the strip electrode on one edge of the pixel electrode 204-3 to form an integral structure. The source and drain electrodes 205 are disposed on the channel region 204-2. The source and drain electrodes 205 include a source electrode 205-1 and a drain electrode 205-2. The drain electrode 205-2 covers part of the pixel electrode 204-3 and overlaps with the pixel electrode 204-3.

[0077] In this embodiment, the source and drain electrodes 205 of the thin-film transistor are located on the channel region 204-2, and part of the pixel electrode 204-3 is not covered by the source and drain electrodes 205. Thus, the channel region 204-2, pixel electrode 204-3, and source and drain electrodes 205 can be formed with only one patterning step. In this embodiment, the channel region, pixel electrode, and source and drain electrodes are formed with only one patterning step, further reducing the mask patterning process, simplifying the process steps, and reducing process complexity. The pixel electrode is formed by conductive bonding of a metal-oxide-semiconductor layer, eliminating the need for source or drain vias to connect the pixel electrode. Therefore, it is suitable for the production of high PPI (pixel density) products, which helps improve the competitiveness of display products in the market.

[0078] Specifically, in one optional implementation, the channel region 204-2 is an IGZO semiconductor film layer, and the pixel electrode 204-3 is an IGZO conductive layer.

[0079] First, an IGZO material layer can be formed, then the IGZO material layer can be patterned, and then other film layers covering the channel region 204-2 and the source / drain electrode 205 and exposing part of the IGZO material can be used as shielding to conduct the patterned IGZO material layer. The part of the IGZO material layer that is shielded by other film layers and is not conducted is the channel region 204-2, and the part of the IGZO material layer that is not shielded by other film layers and is conducted is the pixel electrode 204-3.

[0080] In this implementation, the conductive IGZO diffuses laterally toward the source / drain electrode 205, so that the source / drain electrode 205 covers part of the conductive IGZO, that is, covers part of the pixel electrode 204-3. After the conductive IGZO diffuses laterally, it can form an ohmic contact with the source / drain electrode 205, thus achieving an electrical connection between the source / drain electrode 205 and the pixel electrode 204-3.

[0081] Alternatively, refer to Figure 1 The array substrate also includes a passivation layer 206, which covers the source and drain electrodes 205, the channel region 204-2, and the unconductive metal oxide semiconductor layer in the exposed pixel electrode region. The exposed metal oxide semiconductor layer is ion implanted to form a conductive pixel electrode 204-3.

[0082] In this example, the passivation layer 206 serves as a shielding layer. Specifically, after forming the corresponding patterns of the channel region 204-2, source / drain electrodes 205, and pixel electrodes 204-3, a passivation material layer is formed and patterned to form the passivation layer 206. Then, using the patterned passivation layer 206 as a shield, the patterned IGZO material layer is conductiveized. The portion of the IGZO material layer that is shielded by the passivation layer 206 and not conductiveized serves as the channel region 204-2, and the portion of the IGZO material layer that is not shielded by the passivation layer 206 and is conductiveized serves as the pixel electrode 204-3. The passivation layer can protect the channel region during the conductiveization process, preventing the channel region from becoming conductive, and it can also protect the fabricated source / drain electrodes, improving the performance of the array substrate.

[0083] In some alternative embodiments, refer to Figure 2 The thin-film transistor includes a gate 106 and a gate insulating layer 107, and the channel region 105-1 may be located between the gate 106 and the substrate 100.

[0084] In other alternative embodiments, the array substrate may employ a top-gate oxide thin-film transistor (OTTFT), with the channel region 105-1 disposed close to the substrate 100 and the gate 106 located on the side of the channel region 105-1 away from the substrate 100. In this embodiment, for an OTFT array substrate employing a top-gate structure, the channel region and pixel electrode can be formed in a single patterning step, thereby reducing the mask patterning process of the OTFT array substrate, simplifying the fabrication steps, and lowering the fabrication complexity.

[0085] The gate insulating layer 107 covers the channel region 105-1, and the gate 106 is disposed on the gate insulating layer 107. The thin film transistor also includes an auxiliary conductive layer 105-3 connecting the channel region 105-1 and the pixel electrode 105-2. The channel region 105-1 is located between the auxiliary conductive layers 105-3. The auxiliary conductive layer 105-3, the channel region 105-1, and the pixel electrode 105-2 are formed through the same metal oxide semiconductor thin film. The auxiliary conductive layer 105-3 and the pixel electrode 105-2 include conductive layers formed by a conductor-forming process in the area of ​​the gate insulating layer 107 not covered by the gate 106.

[0086] Reference Figure 2 The same metal-oxide-semiconductor (MOS) thin film can be conductively conductive using the gate 106 as a shield. The region of the MOS thin film shielded by the gate 106 and not conductive forms a channel region 105-1, while the conductive region forms an auxiliary conductive layer 105-3 and a pixel electrode 105-2. Most of the auxiliary conductive layer 105-3 is covered by other film layers and not exposed, while the pixel electrode 105-2 is not covered by other film layers and is exposed. The auxiliary conductive layer 105-3 provides electrical connection between the channel region 105-1 and the pixel electrode 105-2. The auxiliary conductive layer 105-3 is distributed on both sides of the channel region 105-1 and has source and drain contact regions.

[0087] Specifically, in one optional implementation, the channel region 105-1 is an IGZO semiconductor film layer, and the auxiliary conductive layer 105-3 and the pixel electrode 105-2 are IGZO conductive layers.

[0088] First, an IGZO material layer can be formed, then the IGZO material layer can be patterned, and then the patterned gate can be used as a shield to conduct the patterned IGZO material layer. The part of the IGZO material layer that is shielded by the gate and not conducted is used as the channel region 105-1, and the part of the IGZO material layer that is not shielded by the gate and is conducted is used as the auxiliary conductive layer 105-3 and the pixel electrode 105-2.

[0089] Optionally, refer to Figure 2 The pixel electrode 105-2 may include multiple strip electrodes, and the auxiliary conductive layer is connected to one of the strip electrodes on one edge of the pixel electrode to form an integral structure.

[0090] Next, taking the above-mentioned IGZO material layer forming a channel region 105-1, an auxiliary conductive layer 105-3, and a pixel electrode 105-2 as an example, the part of the IGZO material layer that is not blocked by the gate and is conductive serves as the auxiliary conductive layer 105-3 and the pixel electrode 105-2. Among them, the conductive part patterned into multiple strips is the pixel electrode 105-2. Apart from the unconductive channel region 105-1 and the conductive pixel electrode 105-2, the remaining metal oxide semiconductor thin film region is the conductive auxiliary conductive layer 105-3.

[0091] Optionally, the thin-film transistor includes a common electrode 101, a patterned light-shielding portion 102 formed on the common electrode 101, a patterned photoresist layer 103-3 formed on the light-shielding portion 102, a first buffer layer 104 covering the common electrode 101, the light-shielding portion 102 and the photoresist layer 103-3, and a channel region 105-1 and a pixel electrode 105-2 formed on the first buffer layer 104.

[0092] Reference Figure 2 The common electrode 101, the light-shielding portion 102, and the photoresist layer 103-3 all have gaps exposing the substrate 100. This gap design prevents the thin-film transistor and the common electrode from overlapping in the stacking direction of the display panel, reducing the coupling capacitance between the common electrode and the gate and source / drain electrodes of the thin-film transistor. Of course, those skilled in the art should understand that the embodiments disclosed herein do not limit the specific shape and position of the thin-film transistor, as long as they fulfill the function of separating the thin-film transistor from the pixel electrode of the sub-pixel and the common electrode below the pixel electrode. An insulating first buffer layer 104 is located between the common electrode 101 and the pixel electrode 105-2, preventing any conduction between the common electrode 101 and the pixel electrode 105-2.

[0093] Optionally, the thin-film transistor further includes a patterned interlayer insulating layer 108, which covers the gate 106, the edge of the auxiliary conductive layer 105-3 near the channel region 105-1, and partially covers the auxiliary conductive layer 105-3 located on the side of the gate 106 near the pixel electrode 105-2. The orthographic projection of the pixel electrode 105-2 on the substrate 100 does not overlap with the orthographic projection of the interlayer insulating layer 108 on the substrate 100.

[0094] Among them, the area of ​​the auxiliary conductive layer 105-3 exposed from the interlayer insulating layer 108 includes the connection area of ​​the source and the drain, and the pixel electrode 105-2 and the interlayer insulating layer 108 do not overlap in the stacking direction of the display panel, and the pixel electrode 105-2 is exposed from the interlayer insulating layer 108.

[0095] Optionally, the thin-film transistor further includes source and drain electrodes 109 and a second buffer layer 110. The source and drain electrodes 109 are disposed on the interlayer insulating layer 108 and include a source electrode 109-1 and a drain electrode 109-2. The source electrode 109-1 is connected to an auxiliary conductive layer 105-3 located on the side of the gate 106 away from the pixel electrode 105-2 and exposing the interlayer insulating layer 108. The drain electrode 109-2 is connected to an auxiliary conductive layer 105-3 located on the side of the gate 106 close to the pixel electrode 105-2 and exposing the interlayer insulating layer 108. The second buffer layer 110 covers the source and drain electrodes 109 and part of the interlayer insulating layer 108. The orthographic projection of the pixel electrode 105-2 on the substrate 100 does not overlap with the orthographic projection of the second buffer layer 110 on the substrate 110.

[0096] In this design, the source and drain electrodes 109 of the thin-film transistor are disposed on the interlayer insulating layer 108 and connected to the auxiliary conductive layer 105-3 exposed in the interlayer insulating layer 108. The portion of the auxiliary conductive layer connected to the source electrode 109-1 is located on the side of the gate 106 away from the pixel electrode 105-2, while the portion of the auxiliary conductive layer connected to the drain electrode 109-2 is located on the side of the gate 106 closer to the pixel electrode 105-2. Furthermore, the pixel electrode 105-2 and the second buffer layer 110 do not overlap in the stacking direction of the display panel, and the second buffer layer 110 only covers a portion of the interlayer insulating layer 108. Therefore, neither the second buffer layer 110 nor the interlayer insulating layer 108 obstructs the pixel electrode 105-2, allowing the pixel electrode 105-2 to be exposed.

[0097] In this embodiment, the channel region of the thin-film transistor (TFT) and the pixel electrode can be formed by patterning the same metal-oxide-semiconductor (MOS) layer. The channel region of the TFT may include a non-conductive MOS layer, while the pixel electrode can be a conductive MOS layer formed by conductiveizing the MOS layer. Thus, the TFT channel region and the pixel electrode can be patterned once based on the same MOS material to form the MOS pattern for the channel region and the corresponding MOS pattern for the pixel electrode. Then, with the channel region pattern masked, the MOS pattern for the pixel electrode is conductiveized, thereby forming a semiconductor MOS channel region and a conductive MOS pixel electrode. In this embodiment, only one patterning step is required to form the channel region and the pixel electrode, reducing the mask patterning process, simplifying the process steps, and lowering the process complexity.

[0098] Reference Figure 3 This diagram illustrates a step-by-step flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure. The array substrate includes a plurality of sub-pixels arranged in an array and thin-film transistors driving each sub-pixel. The fabrication method includes the following steps:

[0099] Step 101: A first metal oxide semiconductor layer is patterned using a halftone mask process; a masking layer is provided on the side of the first metal oxide semiconductor layer away from the substrate.

[0100] Step 102: Under the cover of the masking layer, the first metal oxide semiconductor layer is made conductive. At least a portion of the first metal oxide semiconductor layer that is covered by the masking layer is not made conductive, forming the channel region of the thin film transistor. At least a portion of the first metal oxide semiconductor layer that is not covered by the masking layer is made conductive, forming the pixel electrode of the thin film transistor.

[0101] In this embodiment, a first metal-oxide-semiconductor (MOS) layer can be patterned using a halftone masking process. Under the cover of a masking layer, the first MOS layer is then made conductive. At least a portion of the first MOS layer hidden by the masking layer is not conductive, thus forming the channel region of the thin-film transistor (TFT). At least a portion of the first MOS layer not hidden by the masking layer is conductive, thus forming the pixel electrode of the TFT. In this way, the channel region and pixel electrode of the TFT can be based on the same MOS material. First, a single patterning process is performed to form the MOS pattern for the channel region and the MOS pattern for the pixel electrode. Then, with the channel region pattern hidden, the MOS pattern for the pixel electrode is made conductive, thereby forming the semiconductor MOS channel region and the conductive MOS pixel electrode. In this embodiment, only one patterning process is required to form the channel region and the pixel electrode, reducing the mask patterning step, simplifying the process steps, and reducing process complexity.

[0102] For an array substrate of oxide thin-film transistors including a bottom gate structure, the following steps may also be included before step 101:

[0103] A second metal oxide semiconductor material layer is formed on the substrate;

[0104] A gate material layer is formed on the second metal oxide semiconductor material layer;

[0105] The second metal oxide semiconductor material layer is patterned to form the second metal oxide semiconductor layer using a halftone mask process, and the gate material layer is patterned to form the gate.

[0106] A gate insulating layer is formed covering the second metal oxide semiconductor layer and the gate;

[0107] With the gate shielding off, the second metal oxide semiconductor layer is made conductive. The portion of the second metal oxide semiconductor layer not shielded by the gate is made conductive, and the conductive portion diffuses toward the gate to form a common electrode. The remaining portion of the second metal oxide semiconductor layer is not made conductive and forms an auxiliary layer.

[0108] Specifically, for example, the substrate 200 can be a glass substrate, but this is merely exemplary and is not intended to be limiting.

[0109] Reference Figure 4First, a second metal-oxide-semiconductor material layer 201-1, such as IGZO or ITO, can be formed on the substrate 200. Then, a gate material layer 202-1 can be formed, covering the previously formed second metal-oxide-semiconductor material layer 201-1. The gate material layer 202-1 may include a double-layer structure of a protective metal and a gate metal, with the gate metal closer to the substrate. The protective metal can be, for example, titanium (Ti), silver (Ag), molybdenum (Mo), or molybdenum-niobium alloy (MoNb), while the gate metal can be, for example, copper (Cu). The protective metal protects the gate metal; in practical applications, the thickness of the protective metal is much smaller than that of the gate metal.

[0110] Then, refer to Figure 5 Photoresist can be coated on the gate material layer 202-1, and a halftone mask can be used to expose the photoresist to form a shape like... Figure 5 The photoresist pattern 001 shown has areas on the halftone mask that need to be retained after photolithography, and areas that need to be removed after photolithography, having different transmittance. In this step, the first photomask process is performed.

[0111] Then, the gate material layer 202-1 can be etched. In an optional example, Cu acid can be used to etch the gate material layer 202-1, and the etched pattern is as follows. Figure 6 As shown. Then, the second metal-oxide-semiconductor material layer 201-1 can be etched to obtain the second metal-oxide-semiconductor layer 201. In an optional example, oxalic acid can be used to etch the second metal-oxide-semiconductor material layer 201, and the etched pattern is shown. Figure 7 As shown. In practical applications, fluorine (F)-containing Cu acid can also be used to etch the gate material layer 202-1 and the second metal oxide semiconductor material layer 201-1 once to obtain... Figure 7 The pattern shown can save one etching process, simplify the process steps, and reduce the complexity of the process.

[0112] The thickness of the photoresist 001 varies at different locations corresponding to the second metal-oxide-semiconductor layer 201. Thicker areas of the photoresist 001 can be used to form the gate auxiliary layer, while thinner areas can be used to form the common electrode.

[0113] After etching, the photoresist 001 can be ashed, for example, by ashing the photoresist 001 with oxygen, thereby removing the thinner portion of the photoresist. The pattern of the ashed photoresist 002 is as follows. Figure 8 As shown. Then, the gate material layer 202-1 is etched again to obtain gate 202. The pattern after photoresist stripping is as follows. Figure 9 As shown. In an optional example, the gate material layer 202-1 can be etched again using Cu acid.

[0114] Then, refer to Figure 10 A gate insulating material layer 203-1 can be formed covering the second metal oxide semiconductor layer 201 and the gate 202, and then the second metal oxide semiconductor layer 201 can be made conductive.

[0115] Specifically, in some embodiments, the second metal-oxide-semiconductor layer 201 can be made of IGZO material. IGZO material remains a semiconductor after baking, therefore, it needs to be converted to a conductor through a subsequent conductive process. After the second metal-oxide-semiconductor layer 201 is conductiveized, the portion of the second metal-oxide-semiconductor layer not blocked by the gate 202 is conductiveized, and the conductiveized portion diffuses towards the gate 202 to form a common electrode 201-2. The remaining portion of the second metal-oxide-semiconductor layer is not conductiveized, forming an auxiliary layer 201-1. The auxiliary layer 201-1 is a non-conductive IGZO semiconductor film, and the common electrode 201-2 is a conductive IGZO conductive layer. The conductiveized portion diffuses towards the gate 202, with a lateral diffusion distance of L1. The conductiveized diffused portion is also part of the common electrode 201-2, such as... Figure 10 As shown.

[0116] For example, the second metal oxide semiconductor layer 201 of the IGZO material can be subjected to plasma treatment in a hydrogen environment to achieve the conductorization of the second metal oxide semiconductor layer 201, thereby improving the transmittance of the conductor-conducting IGZO.

[0117] Impedance data of IGZO before and after conductor formation and after baking are as follows: Figure 11 As shown, the transmittance data is as follows: Figure 12 As shown. Taking thick IGZO as an example, after treatment with 500W H2 plasma for 30 seconds and baking at 280℃, the sheet resistance of IGZO can be reduced to 150Ω and the transmittance can be increased to 87%, which can meet the conductivity and transmittance requirements of the common electrode.

[0118] Furthermore, the lateral diffusion distance L (including L1 and L2 in the figure) of IGZO conductor formation can be controlled by some process parameters, such as those shown in the figure. Figure 13 The lateral diffusion distance L of IGZO conductor formation can be controlled by controlling the oxygen content and annealing temperature during IGZO film formation. Figure 13 Only a few optional control parameters are listed; it is understood that other control parameters can also be determined using the single-variable method. For example, with Taking thick IGZO as an example, after 30 seconds of treatment with 300W H2 plasma, the lateral diffusion distance of IGZO conductor exceeds 3.7µm, and the lateral diffusion distance of IGZO conductor can increase with the increase of conductor power and time.

[0119] It should be noted that, Figure 13 The provided examples only illustrate some of the preparation conditions for IGZO samples and the actual range of the conductor-induced lateral diffusion distance L for these IGZO samples. It is understood that when other preparation conditions change, the measured results of the conductor-induced lateral diffusion distance L may not be as accurate. Figure 13 As shown.

[0120] Optionally, in other embodiments, the second metal oxide semiconductor layer 201 may also be made of ITO material. ITO material can become a conductor after baking. After the second metal oxide semiconductor layer 201 is patterned by halftone masking, the first metal oxide semiconductor sublayer formed is directly used as an auxiliary layer, and the second metal oxide semiconductor sublayer formed is directly used as a common electrode. Both the auxiliary layer and the common electrode are conductive ITO conductive layers.

[0121] In this way, the gate and common electrode can be formed by patterning only once, without the need for additional ion implantation conductor processing, reducing the mask patterning process, simplifying the process steps, and reducing the process complexity.

[0122] After the conductor treatment, the gate insulating material layer 203-1 can be patterned to form the gate insulating layer 203, as required. Figure 14 As shown. In this step, a second mask process was performed.

[0123] In some embodiments, step 101 may optionally include:

[0124] A first metal oxide semiconductor material layer is formed on the gate insulating layer;

[0125] A source / drain material layer is formed on the first metal-oxide-semiconductor material layer;

[0126] The first metal oxide semiconductor material layer is patterned to form the first metal oxide semiconductor layer using a halftone mask process, and the source and drain electrode material layer is patterned to form the source and drain electrode.

[0127] A passivation layer is formed by patterning; the passivation layer covers the source and drain electrodes, as well as a portion of the first metal-oxide-semiconductor layer near the source and drain electrodes; the passivation layer is a shielding layer.

[0128] Among them, reference Figure 15A first metal-oxide-semiconductor material layer 204-4, such as IGZO or ITO, can be formed on the gate insulating layer 203. Then, a source-drain material layer 205-1 can be formed, covering the previously formed first metal-oxide-semiconductor material layer 204-4. Similar to the gate material layer, the source-drain material layer 205-1 can also include a double-layer structure of a protective metal and a source-drain metal, with the source-drain metal closer to the substrate. The protective metal includes, but is not limited to, Ti, Ag, Mo, and MoNb alloys, while the source-drain metal can be, for example, Cu. The protective metal protects the source-drain metal; in practical applications, the thickness of the protective metal is much smaller than that of the source-drain metal.

[0129] Then, refer to Figure 16 Photoresist can be coated onto the source / drain material layer 205-1, and a halftone mask can be used to expose the photoresist to form a layer like... Figure 16 The photoresist pattern 003 shown has areas on the halftone mask that need to be retained after photolithography, which have different transmittance than areas that need to be removed after photolithography. A third photomask process was performed in this step.

[0130] Then, the source / drain material layer 205-1 can be etched. In an optional example, Cu acid can be used to etch the source / drain material layer 205-1, and the etched pattern is shown below. Figure 17 As shown. Then, the first metal-oxide-semiconductor material layer 204-4 can be etched to obtain the first metal-oxide-semiconductor layer 204-1. In an optional example, oxalic acid can be used to etch the first metal-oxide-semiconductor material layer 204-4, and the etched pattern is shown. Figure 18 As shown. In practical applications, the source / drain material layer 205-1 and the first metal-oxide-semiconductor material layer 204-4 can also be etched once using F-containing Cu acid to obtain the desired result. Figure 18 The pattern shown can save one etching process, simplify the process steps, and reduce the complexity of the process.

[0131] The thickness of the photoresist 003 varies at different locations. The thicker areas of the photoresist 003 can be used to form source and drain electrode locations, the thicker areas of the photoresist 003 and the thinner areas between the thicker areas can be used to form channel regions, and the remaining thinner areas of the photoresist 003 can be used to form pixel electrodes.

[0132] After etching, the photoresist 003 can be ashed, for example, by ashing the photoresist with oxygen, thereby removing the thinner portions of the photoresist. The ashed photoresist 004 pattern is as follows. Figure 19As shown. Then, the source / drain material layer 205-1 is etched again to obtain source / drain 205. The pattern after photoresist stripping is shown below. Figure 20 As shown. In an optional example, Cu acid etching of the source and drain material layer 205-1 can be used again.

[0133] Then, a passivation material layer can be formed, and the passivation material layer can be patterned to form passivation layer 206, as shown in the pattern. Figure 21 As shown, the passivation layer 206 covers the source / drain electrode 205, and a portion of the first metal-oxide-semiconductor layer 204-1 near the source / drain electrode 205. In this step, a fourth mask process is performed.

[0134] In this step, a passivation layer 206 can be formed first, and then the first metal-oxide-semiconductor layer 204-1 can be made conductive. The passivation layer 206 can protect the channel region during the conductive process, preventing the channel region from being conductive. Furthermore, the passivation layer 206 can also protect the fabricated source and drain electrodes 205, improving the performance of the array substrate. Additionally, if the top of the pixel electrode is covered by the passivation layer 206, the electric field formed by the pixel electrode and the common electrode will be very weak, with only a side electric field. Therefore, the patterned passivation layer can expose the pixel electrode, ensuring the strength of the electric field formed by the pixel electrode and the common electrode.

[0135] Wherein, the passivation layer 206 can serve as the shielding layer described in step 101, and correspondingly, step 202 may specifically include:

[0136] Under the shielding of the passivation layer 206, the first metal oxide semiconductor layer 204-1 is made conductive. The first metal oxide semiconductor layer 204-1 that is not shielded by the passivation layer 206 is made conductive, and the conductive portion diffuses toward the source and drain 205 to form the pixel electrode 204-3 of the thin film transistor. The remaining portion of the first metal oxide semiconductor layer 204-1 is not made conductive and forms the channel region 204-2 of the thin film transistor.

[0137] Reference Figure 22When the first metal-oxide-semiconductor layer 204-1 is made of IGZO material, it can be conductively treated by means of plasma processing in a hydrogen atmosphere, for example. The first metal-oxide-semiconductor layer 204-1 not shielded by the passivation layer 206 becomes conductive, forming the pixel electrode 204-3. The remaining portion of the first metal-oxide-semiconductor layer 204-1 is not conductive, forming the channel region 204-2. The channel region 204-2 is a non-conductive IGZO semiconductor film, and the pixel electrode 204-3 is a conductive IGZO layer. The conductive portion diffuses towards the source / drain electrode 205, with a lateral diffusion distance of L2. After the IGZO conductive lateral diffusion, it can form an ohmic contact with the source / drain electrode 205, achieving electrical connection between the source / drain electrode 205 and the pixel electrode 204-3. After the pixel electrode 204-3 is made conductive, the transmittance is improved. The channel region 204-2 will not be made conductive due to the protection of the passivation layer 206, and can maintain its semiconductor characteristics. At this point, the array substrate process is completed.

[0138] In this embodiment of the disclosure, the array substrate including the bottom gate structure oxide thin film transistor can be fabricated through only 4 patterning steps, that is, 4 masking processes. Compared with the current 6 masking processes for bottom gate structures, the masking patterning steps can be reduced, the process steps can be simplified, and the process complexity can be reduced.

[0139] It should be noted that each illustration of the embodiments of this disclosure shows only one pixel electrode and its corresponding thin-film transistor portion. The pixel electrode is shown in multiple portions because the pixel electrode is a hollow pattern, and the cross-sectional view shows multiple interrupted portions. This application does not impose any specific limitations.

[0140] Furthermore, it should be noted that portion A shown in the figures of the above embodiments represents the terminal area of ​​the array substrate, used for connection to the circuit board to input the required electrical signals to the display area of ​​the array substrate. The terminal area is located in the non-display area of ​​the array substrate. In practical applications, the film structure in the terminal area only needs to meet the requirements of electrical connection and electrical signal transmission. The terminal area shown in each figure is only an optional example, and only a part of the terminal area is shown. The embodiments disclosed herein are not intended to specifically limit the film structure of the terminal area.

[0141] For an array substrate of oxide thin-film transistors including a top-gate structure, the following steps may be included before step 101:

[0142] A common electrode material layer is formed on the substrate;

[0143] A light-shielding material layer is formed on the common electrode material layer;

[0144] The common electrode material layer is patterned to form the common electrode using a halftone mask process, and the light-shielding material layer is patterned to form the light-shielding layer. The photoresist required to form the light-shielding layer is retained, and a patterned photoresist layer is formed on the light-shielding layer.

[0145] A first buffer layer is formed covering the common electrode, the light-shielding part, and the photoresist layer.

[0146] Reference Figure 23 First, a common electrode material layer 101-1 can be formed on the substrate 100. Then, a light-shielding material layer 102-1 can be formed on the common electrode material layer 101-1.

[0147] Reference Figure 24 A first photoresist layer is formed on the light-shielding material layer 102-1, and a second photoresist layer 103 is formed by patterning the first photoresist layer using a halftone mask process. The second photoresist layer 103 includes a first region and a second region, the thickness of the second region being less than the thickness of the first region, and this second region is used to form a light-shielding portion in subsequent steps. In this step, a first mask process is performed.

[0148] Reference Figure 25 The light-shielding material layer 102-1 is etched based on the second photoresist layer 103 to form a light-shielding sublayer 102-2.

[0149] Reference Figure 26 The common electrode 101 is formed by etching the common electrode material layer 101-1 based on the second photoresist layer 103.

[0150] Reference Figure 27 The second photoresist layer 103 is subjected to a first ashing treatment to remove the second region and form the second photoresist sublayer 103-1.

[0151] Reference Figure 28 A light-shielding portion 102 is formed by wet etching of a light-shielding sublayer 102-2 based on a second photoresist sublayer 103-1. The light-shielding portion 102 includes a first light-shielding portion, and the orthogonal projection of the first light-shielding portion on the substrate 100 covers the orthogonal projection of the channel region of the thin film transistor to be formed on the substrate.

[0152] Reference Figure 29 The second photoresist sublayer 103-1 undergoes a second ashing treatment, causing it to shrink so that its orthogonal projection on the substrate 100 falls within the orthogonal projection of the light-shielding portion 102 on the substrate 100, leaving the remaining photoresist layer 103-3. In embodiments of this disclosure, it is not necessary to remove the remaining photoresist layer 103-3; retaining the remaining photoresist layer 103-3 can further reduce the coupling capacitance between the source / drain electrodes and the common electrode.

[0153] Reference Figure 30A first buffer layer 104 is formed on the remaining photoresist layer 103-3.

[0154] Next, step 101 may specifically include the following steps:

[0155] A first metal-oxide-semiconductor layer is patterned on the first buffer layer;

[0156] A gate insulating layer and a gate are patterned on a first metal oxide semiconductor layer; the gate is disposed on the gate insulating layer and the gate is a shielding layer.

[0157] Reference Figure 31 A first metal-oxide-semiconductor (MOS) material layer is formed on the first buffer layer 104, and the first MOS material layer is patterned to form a first MOS layer 105. The material of the first MOS layer 105 can be IGZO. A second masking process is performed in this step.

[0158] Reference Figure 32 A gate insulating material layer is formed on the first metal-oxide-semiconductor layer 105, and a gate material layer is formed on the gate insulating material layer. Then, a gate insulating layer 107 and a gate 106 are patterned in one step, with the gate 106 disposed on the gate insulating layer 107. The orthogonal projection of the gate 106 onto the substrate 100 covers the orthogonal projection of the first metal-oxide-semiconductor layer 105 onto the substrate 100. In this step, a third mask process is performed.

[0159] Wherein, gate 106 can serve as the shielding layer described in step 101, and correspondingly, step 202 may specifically include:

[0160] Under the shielding of the gate 106, the first metal oxide semiconductor layer 105 is made conductive. The first metal oxide semiconductor layer 105 shielded by the gate 106 is not made conductive, forming the channel region 105-1 of the thin film transistor. The remaining part of the first metal oxide semiconductor layer 105 is made conductive, forming the auxiliary conductive layer 105-3 and the pixel electrode 105-2 of the thin film transistor. The auxiliary conductive layer 105-3 connects the channel region 105-1 and the pixel electrode 105-2. The channel region 105-1 is located between the auxiliary conductive layers 105-3.

[0161] Reference Figure 33When the first metal-oxide-semiconductor layer 105 is made of IGZO material, it can be made conductive by means of plasma treatment in a hydrogen atmosphere, for example. The portion of the first metal-oxide-semiconductor layer 105 that is blocked by the gate 106 is not conductive, forming the channel region 105-1. The remaining portion of the first metal-oxide-semiconductor layer 105 is conductive, forming the auxiliary conductive layer 105-3 and the pixel electrode 105-2 of the thin-film transistor. The channel region 105-1 is a non-conductive IGZO semiconductor film, while the auxiliary conductive layer 105-3 and the pixel electrode 105-2 are conductive IGZO conductive layers.

[0162] Following step 202, the following steps may also be included:

[0163] An interlayer insulating material layer is patterned to form an interlayer insulating material layer; the interlayer insulating material layer covers the gate, the edge of the auxiliary conductive layer near the channel region, partially covers the auxiliary conductive layer located on the side of the gate near the pixel electrode, and the pixel electrode;

[0164] Source and drain electrodes are patterned on the interlayer insulating material layer. The source and drain electrodes include a source electrode and a drain electrode. The source electrode is connected to an auxiliary conductive layer located on the side of the gate away from the pixel electrode and exposed to the interlayer insulating material layer. The drain electrode is connected to an auxiliary conductive layer located on the side of the gate close to the pixel electrode and exposed to the interlayer insulating material layer.

[0165] Form a second buffer material layer;

[0166] The second buffer material layer and the interlayer insulating material layer are patterned to form the second buffer layer and the interlayer insulating layer; the orthogonal projection of the pixel electrode on the substrate does not overlap with the orthogonal projection of the interlayer insulating layer and the second buffer layer on the substrate, and the second buffer layer covers the source and drain electrodes and the interlayer insulating layer.

[0167] Among them, reference Figure 34 An interlayer insulating material layer 108-1 is deposited on the gate electrode 106 and patterned to expose the auxiliary conductive layer region that needs to be connected to the source and drain electrodes. At this point, the interlayer insulating material layer 108-1 covers the pixel electrode 105-2. In this step, a fourth mask process is performed.

[0168] Then, source and drain material layers are patterned on the interlayer insulating material layer 108-1, and then source and drain electrodes 109 are patterned. In this step, a fifth photomask process is performed.

[0169] The source and drain electrodes 109 are connected to the auxiliary conductive layer 105-3 of the exposed interlayer insulating material layer 108-1. The auxiliary conductive layer portion connected to the source electrode 109-1 is located on the side of the gate electrode 106 away from the pixel electrode 105-2, and the auxiliary conductive layer portion connected to the drain electrode 109-2 is located on the side of the gate electrode 106 closer to the pixel electrode 105-2.

[0170] Reference Figure 35 A second buffer material layer 110-1 can be formed, and the second buffer material layer 110-1 and the interlayer insulating material layer 108-1 can be patterned to obtain a patterned second buffer layer 110 and an interlayer insulating layer 108. The pixel electrode 105 exposes the second buffer layer 110 and the interlayer insulating layer 108 to form a thin-film transistor, such as... Figure 36 As shown. In this step, the sixth mask process was performed.

[0171] Furthermore, the following can be performed subsequently: the pixel electrode 105-2 can be made conductive, that is, the pixel electrode 105-2 can be made conductive a second time, thus obtaining... Figure 2 The array substrate is shown. The pixel electrode 105-2, after secondary conductor conversion, can have further improved transmittance and further reduced resistivity, exhibiting superior metallic properties.

[0172] In this embodiment of the disclosure, the array substrate including the top gate structure oxide thin film transistor can be fabricated through only 6 patterning steps, that is, 6 mask processes. Compared with the current 9 mask process for the top gate structure, the mask patterning process can be reduced, the process steps can be simplified, and the process complexity can be reduced.

[0173] It should be noted that in the above preparation methods, only positive photoresist is used as an example. It can be understood that negative photoresist can also be used in the above preparation methods, and this disclosure does not specifically limit it.

[0174] It should also be noted that, in the embodiments disclosed herein, since the top grid structure and the bottom grid structure are different structures, the film layers named with the same name in the two structures do not represent the same film layer, but rather film layers with the same or similar materials and the same or similar functions.

[0175] In addition, the above-mentioned preparation methods may also include other conventional steps, which are not specifically limited in this embodiment.

[0176] This disclosure also discloses a display device including the array substrate described above.

[0177] Since the array substrate included in the display device provided in this embodiment corresponds to the array substrate provided in the above-mentioned embodiments, the previous embodiments are also applicable to this embodiment, and will not be described in detail in this embodiment.

[0178] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0179] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0180] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0181] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. An array substrate, characterized in that, The array includes a substrate, a plurality of sub-pixels arranged in an array on the substrate, and thin-film transistors driving each of the sub-pixels, wherein the array substrate includes pixel electrodes; The channel region of the thin-film transistor includes a metal-oxide-semiconductor layer, and the pixel electrode is a metal-oxide-conductive layer formed by conductiveizing the metal-oxide-semiconductor. The channel region of the thin-film transistor and the pixel electrode are formed by patterning the same metal-oxide-semiconductor layer. The thin-film transistor includes a gate located between the channel region and the substrate; The thin-film transistor includes a common electrode; the common electrode includes at least a conductive layer formed by a conductor-forming process of the metal oxide semiconductor thin film not covered by the gate; the gate is electrically connected to the common electrode. The thin-film transistor includes an auxiliary layer, which is formed on the same metal oxide semiconductor thin film as the common electrode. The auxiliary layer and the common electrode are integral structures, and the gate is disposed on the auxiliary layer.

2. The array substrate according to claim 1, characterized in that, The auxiliary layer is an IGZO semiconductor film, and the common electrode is an IGZO conductive layer.

3. The array substrate according to claim 1, characterized in that, The thin-film transistor includes a source and a drain. The pixel electrode includes multiple strip electrodes. The channel region is connected to the strip electrode at one edge of the pixel electrode to form an integral structure. The source and drain are disposed on the channel region. The source and drain include a source and a drain. The drain covers a portion of the pixel electrode and overlaps with the pixel electrode.

4. The array substrate according to claim 3, characterized in that, The array substrate includes a passivation layer that covers the source / drain electrodes, the channel region, and the unconductive metal-oxide-semiconductor layer of the exposed pixel electrode region. Ion implantation is performed on the exposed metal-oxide-semiconductor layer to form conductive pixel electrodes.

5. A method for fabricating an array substrate, the array substrate comprising a substrate, and a plurality of sub-pixels arranged in an array on the substrate and thin-film transistors driving each of the sub-pixels, characterized in that, The method includes: A first metal oxide semiconductor layer is patterned using a halftone masking process; a shielding layer is provided on the side of the first metal oxide semiconductor layer away from the substrate; Under the shielding layer, the first metal oxide semiconductor layer is made conductive. At least a portion of the first metal oxide semiconductor layer that is shielded by the shielding layer is not made conductive, forming the channel region of the thin film transistor. At least a portion of the first metal oxide semiconductor layer that is not shielded by the shielding layer is made conductive, forming the pixel electrode of the thin film transistor. Before the first metal-oxide-semiconductor layer is patterned using a halftone mask process, the method further includes: A second metal oxide semiconductor material layer is formed on the substrate; A gate material layer is formed on the second metal oxide semiconductor material layer; The second metal oxide semiconductor material layer is patterned to form the second metal oxide semiconductor layer using a halftone mask process, and the gate material layer is patterned to form the gate. A gate insulating material layer is formed covering the second metal oxide semiconductor layer and the gate; Under the shielding of the gate, the second metal-oxide-semiconductor layer is made conductive. The portion of the second metal-oxide-semiconductor layer not shielded by the gate is made conductive, and the conductive portion diffuses toward the gate to form a common electrode. The remaining portion of the second metal-oxide-semiconductor layer is not made conductive and forms an auxiliary layer. The gate is electrically connected to the common electrode. The gate insulating material layer is patterned to form the gate insulating layer.

6. The method according to claim 5, characterized in that, The process of patterning and forming the first metal-oxide-semiconductor layer using a halftone mask includes: A first metal oxide semiconductor material layer is formed on the gate insulating layer; A source / drain material layer is formed on the first metal oxide semiconductor material layer; The first metal oxide semiconductor material layer is patterned to form the first metal oxide semiconductor layer using a halftone mask process, and the source and drain electrode material layer is patterned to form the source and drain electrode. A passivation layer is formed by patterning; the passivation layer covers the source and drain electrodes and a portion of the first metal-oxide-semiconductor layer near the source and drain electrodes; the passivation layer is the shielding layer.

7. The method according to claim 6, characterized in that, The first metal-oxide-semiconductor layer is conductiveized under the shielding layer, at least a portion of the first metal-oxide-semiconductor layer shielded by the shielding layer is not conductiveized to form the channel region of the thin-film transistor, and at least a portion of the first metal-oxide-semiconductor layer not shielded by the shielding layer is conductive to form the pixel electrode of the thin-film transistor, comprising: Under the shielding of the passivation layer, the first metal oxide semiconductor layer is made conductive. The portion of the first metal oxide semiconductor layer not shielded by the passivation layer is made conductive, and the conductive portion diffuses toward the source and drain to form the pixel electrode of the thin film transistor. The remaining portion of the first metal oxide semiconductor layer is not made conductive and forms the channel region of the thin film transistor.

8. A display device, characterized in that, Includes the array substrate as described in any one of claims 1-4.

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