Time-domain multiplexing of voltage pulses

Abstract

The embodiments provided herein generally include apparatus, plasma processing systems, and methods for generating waveforms for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having a voltage source circuit system, a first switch coupled between the voltage source circuit system and a first output node of the waveform generator, and a second switch coupled between the first output node and an electrical ground node, the first output node being configured to be coupled to the chamber. The waveform generator further includes a third switch coupled between the voltage source circuit system and a second output node of the waveform generator, and a fourth switch coupled between the second output node and an electrical ground node, the second output node being configured to be coupled to the chamber.

Description

[0001] background

[0002] field

[0003] The embodiments of this disclosure generally relate to systems used in semiconductor device manufacturing. More specifically, embodiments of this disclosure relate to plasma processing systems for handling substrates. Background Technology

[0004] Reliably generating high aspect ratio features is one of the key technological challenges for next-generation semiconductor devices. One method for forming high aspect ratio features uses a plasma-assisted etching process to bombard the material formed on the substrate surface through openings formed in a patterned mask layer formed on the substrate surface.

[0005] As technology nodes advance towards 2nm, the fabrication of smaller features with larger aspect ratios requires atomic precision for plasma processing. For etching processes where plasma ions play a dominant role, ion energy control has always been a challenge in developing reliable and repeatable device formation processes in the semiconductor equipment industry. In a typical plasma-assisted etching process, the substrate is positioned on an electrostatic chuck (ESC) positioned within a processing chamber, plasma forms above the substrate, and ions are accelerated from the plasma toward the substrate across a plasma shell (i.e., the electron-depleted region) formed between the plasma and the substrate surface. Traditionally, RF substrate biasing methods using sinusoidal RF waveforms to excite the plasma and form the plasma shell have not been satisfactory for forming these smaller device feature sizes. Recently, it has been found that delivering high-voltage pulses to one or more electrodes within the processing chamber can be used to reliably control the plasma shell formed above the substrate surface. However, generating mid- to high-frequency high-voltage pulses is challenging. Such pulses can be particularly difficult to generate using standard electrical components due to the heating of the switching components used to generate the high-voltage pulses.

[0006] Therefore, there is a need in the art for pulsed voltage sources and biasing methods capable of performing desired plasma-assisted processes on substrates. Summary of the Invention

[0007] The embodiments provided herein generally include apparatus, plasma processing systems, and methods for generating waveforms for plasma processing of a substrate in a processing chamber.

[0008] One embodiment of this disclosure relates to a waveform generator for plasma processing. The waveform generator typically includes: a voltage source circuit system; a first switch coupled between the voltage source circuit system and a first output node of the waveform generator, the first output node being configured to be coupled to a chamber; a second switch coupled between the first output node and an electrical ground node; a third switch coupled between the voltage source circuit system and a second output node of the waveform generator, the second output node being configured to be coupled to a chamber; and a fourth switch coupled between the second output node and an electrical ground node.

[0009] One embodiment of this disclosure relates to a method for waveform generation. The method generally includes: coupling a voltage source circuit system to a first output node of a waveform generator via a first switch, the first output node being coupled to a cavity; coupling the first output node to an electrical ground node via a second switch; coupling the voltage source circuit system to a second output node of the waveform generator via a third switch, the second output node being coupled to the cavity; and coupling the second output node to an electrical ground node via a fourth switch.

[0010] One embodiment of this disclosure relates to an apparatus for waveform generation. The apparatus typically includes a voltage source circuit system, one or more switches coupled to the voltage source circuit system, and a controller configured to control the one or more switches. The one or more switches include: a first switch coupled between the voltage source circuit system and a first output node of the waveform generator, the first output node being configured to be coupled to a chamber; a second switch coupled between the first output node and an electrical ground node; a third switch coupled between the voltage source circuit system and a second output node of the waveform generator, the second output node being configured to be coupled to the chamber; and a fourth switch coupled between the second output node and the electrical ground node. Attached Figure Description

[0011] To gain a more detailed understanding of the foregoing features of this disclosure, a more specific description of the disclosure, which has been briefly outlined above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it will be noted that the drawings illustrate exemplary embodiments only and should not be considered as limiting the scope of this disclosure, and that this disclosure may allow for other equivalent embodiments.

[0012] Figure 1 This is a schematic cross-sectional view of a processing system configured to practice the methods described herein, according to one or more embodiments.

[0013] Figure 2A The voltage waveform established on the substrate is shown as a result of the voltage waveform applied to the electrodes in the processing chamber.

[0014] Figure 2B The effect of increased plasma density on the voltage waveform established on the substrate, which is attributable to the voltage waveform of the electrodes applied to the processing chamber, is shown.

[0015] Figure 2C It shows the relationship with... Figure 2B The voltage waveform shows the effect of increased plasma density on the associated ion energy distribution (IED).

[0016] Figure 3 Example waveforms generated using time multiplexing of voltage pulses according to certain embodiments of this disclosure are shown.

[0017] Figure 4A An example waveform generator according to certain embodiments of this disclosure is shown.

[0018] Figure 4B It is a diagram. Figure 4A The timing diagram of the switching states of the waveform generator.

[0019] Figure 5 The following diagram illustrates certain embodiments of the present disclosure. Figure 3 The waveform shown is associated with the IED.

[0020] Figure 6 This is a process flow diagram illustrating the method used for waveform generation. Detailed Implementation

[0021] Some embodiments of this disclosure generally relate to techniques for generating waveforms that control ion energy distribution (IED) during plasma processing. For example, a pulsed voltage waveform can be generated by time-multiplexing voltage pulses from different sources (e.g., switches) and applied to one or more electrodes in a plasma processing chamber for plasma processing. In some embodiments, the pulsed voltage waveform can be generated using multiple switch pairs, allowing the pulsed voltage waveform to have a higher frequency compared to conventional implementations using a single switch pair. Due to physical and practical device limitations found in current conventional high-voltage switching components, the switching speed of these conventional high-voltage switches is limited to a “maximum practical switching speed” due to the heat generated in the component during use. During typical plasma processing, the high-voltage pulsed voltage waveform generated by high-voltage switches typically requires the switches to be repeatedly executed at voltage levels greater than about 200 volts, such as greater than about 500 volts, or greater than about 800 volts, or greater than about 1000 volts, or greater than about 5000 volts, throughout the lifetime of the device containing the switches. In one example, at switching voltages greater than approximately 800 volts, the maximum practical switching speed of conventional switches (such as metal-oxide-semiconductor field-effect transistors (MOSFETs)) is typically limited to approximately 2.5 microseconds (μs). However, using higher frequency voltage waveforms can reduce the voltage drop (droop) during the ion current phase of the voltage pulse used during plasma processing. As a result, a narrower IED can be achieved, thereby promoting greater accuracy in plasma processing, as described in more detail herein. As used herein, voltage drop generally refers to the increase in voltage established at the electrode during the negative voltage portion of the voltage pulse.

[0022] Example of a plasma processing system

[0023] Figure 1 This is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processing. However, it should be noted that the embodiments described herein can also be used with processing systems configured for use in other plasma-assisted processes, such as plasma-enhanced deposition processes, for example, plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), plasma-enhanced atomic layer deposition (PEALD), plasma processing, or plasma-based ion implantation processes, such as plasma doping (PLAD).

[0024] As shown, the processing system 10 is configured to form capacitively coupled plasma (CCP), wherein the processing chamber 100 includes an upper electrode (e.g., chamber cover 123) disposed in a processing volume 129, the upper electrode facing a lower electrode (e.g., substrate support assembly 136) also disposed in the processing volume 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically coupled to one of the upper or lower electrodes and delivers an RF signal configured to ignite and sustain the plasma (e.g., plasma 101). In this configuration, the plasma is capacitively coupled to each of the upper and lower electrodes and disposed in the processing region between the upper and lower electrodes. Typically, the opposite of the upper or lower electrodes is coupled to ground or a second RF power source. In one embodiment, one or more components of the substrate support assembly 136 (such as a support substrate 107) are electrically coupled to a plasma generator assembly 163 including the RF generator 118, and the chamber cover 123 is electrically coupled to ground. As shown in the figure, the processing system 10 includes a processing chamber 100, a support assembly 136, and a system controller 126.

[0025] Processing chamber 100 typically includes a chamber body 113, which includes a chamber cover 123, one or more sidewalls 122, and a chamber base 124 that collectively define a processing volume 129. The one or more sidewalls 122 and the chamber base 124 generally comprise a material that is dimensioned and shaped to form structural supports for the elements of processing chamber 100 and configured to withstand applied pressure and added energy during processing when plasma 101 is generated within the vacuum environment maintained in the processing volume 129 of processing chamber 100. In one example, the one or more sidewalls 122 and the chamber base 124 are formed of a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0026] A gas inlet 128, disposed through the chamber cover 123, is used to deliver one or more process gases from a process gas source 119 in fluid communication with the gas inlet 128 to the process volume 129. A substrate 103 is loaded into and removed from the process volume 129 through an opening (not shown) in one or more sidewalls 122, the opening being sealed with a slit valve (not shown) during plasma treatment of the substrate 103.

[0027] System controller 126 (also referred to herein as a processing chamber controller) includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. System controller 126 controls the process sequence for processing substrate 103, including the substrate biasing methods described herein. CPU 133 is a general-purpose computer processor configured for controlling the processing chamber and associated subprocessors in an industrial setting. Memory 134 (typically non-volatile memory) described herein may include random access memory, read-only memory, floppy disk or hard disk drive, or other suitable forms of local or remote digital storage. Support circuitry 135 is conventionally coupled to CPU 133 and includes cache, clock circuitry, input / output subsystems, power supply, and combinations thereof. Software instructions (programs) and data may be encoded and stored in memory 134 to instruct the processor within CPU 133. The software program (or computer instructions) readable by CPU 133 in system controller 126 determines which tasks the components in processing system 10 can perform.

[0028] Typically, the program, readable by the CPU 133 in the system controller 126, includes code that, when executed by the processor (CPU 133), performs tasks related to the plasma processing scheme described herein. The program may include instructions for controlling various hardware and electrical components within the processing system 10 to perform various process tasks and sequences for implementing the methods described herein. In one embodiment, the program includes instructions for performing the following... Figure 6 Instructions describing one or more operations.

[0029] The processing system may include a plasma generator assembly 163, a first pulse voltage (PV) source assembly 196 for establishing a first PV waveform at a bias electrode 104, and a second PV source assembly 197 for establishing a second PV waveform at an edge control electrode 115. The first or second PV waveform may be as described herein. Figure 3 , Figure 4A and Figure 4B A waveform generator is described in more detail. In some embodiments, plasma generator assembly 163 delivers an RF signal to a support substrate 107 (e.g., a power electrode or cathode), which can be used to generate (maintain and / or ignite) plasma 101 in a processing region disposed between substrate support assembly 136 and chamber cover 123. In some embodiments, RF generator 118 is configured to deliver an RF signal having a frequency greater than 1 MHz, or about 2 MHz, such as about 13.56 MHz or greater.

[0030] As discussed above, in some embodiments, a plasma generator assembly 163, including RF generator 118 and RF generator assembly 160, is typically configured to deliver a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal frequency to the support substrate 107 of the substrate support assembly 136 based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is configured to deliver RF power (e.g., RF signals) to the support substrate 107 disposed near the substrate support 105 and within the substrate support assembly 136. The RF power delivered to the support substrate 107 is configured to ignite and sustain a process plasma 101 of process gas disposed within the process volume 129.

[0031] In some embodiments, the support substrate 107 is electrically coupled to the RF electrodes of the RF generator 118 via an RF matching circuit 162 and a first filter assembly 161 (both disposed within the RF generator assembly 160). The first filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power delivery line 167 and damaging the RF generator 118. The first filter assembly 161 serves as a high impedance (e.g., high Z) to the PV signal generated by the PV pulse generator P1 within the PV waveform generator 150, and thus suppresses current flow to the RF matching circuit 162 and the RF generator 118.

[0032] In some embodiments, RF generator assembly 160 and RF generator 118 are used to ignite and sustain the process plasma 101 using a field generated by a process gas disposed in the process volume 129 and RF power (RF signal) delivered to the support substrate 107 via RF generator 118. The process volume 129 is fluidly coupled to one or more dedicated vacuum pumps via vacuum outlet 120, which maintain the process volume 129 under subatmospheric pressure conditions and extract process gas and / or other gases from the process volume 129. In some embodiments, a substrate support assembly 136 disposed in the process volume 129 is mounted on a support shaft 138, which is grounded and extends through the chamber substrate 124. However, in some embodiments, RF generator assembly 160 is configured to deliver RF power to a bias electrode 104 disposed in a substrate support 105 relative to the substrate substrate 107.

[0033] The substrate support assembly 136 (as briefly discussed above) typically includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, as further discussed below, the substrate support assembly 136 may additionally include an insulator plate 111 and a ground plane 112. The support base 107 is electrically isolated from the chamber base 124 via the insulator plate 111, and the ground plane 112 is inserted between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing.

[0034] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material, or a corrosion-resistant metal oxide or metal nitride material, for example, alumina (Al₂O₃), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y₂O₃), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in its dielectric material. In some embodiments, one or more characteristics for maintaining the RF power of the plasma 101 in the processing region above the bias electrode 104 are determined and / or monitored by measuring the RF waveform established at the bias electrode 104.

[0035] In one configuration, the bias electrode 104 is a clamping electrode used to secure (i.e., clamp) the substrate 103 to the substrate support surface 105A of the substrate support 105, and to bias the substrate 103 relative to the processed plasma 101 using one or more pulse voltage bias schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive portions, such as one or more metal meshes, foils, plates, or combinations thereof.

[0036] In some embodiments, the bias electrode 104 is electrically coupled to a clamping network 116, which provides a clamping voltage, such as a static DC voltage between approximately -5000V and approximately 5000V, to the bias electrode using an electrical conductor such as a coaxial power delivery line 106 (e.g., a coaxial cable). As will be discussed further below, the clamping network 116 includes a bias compensation circuit element 116A, a DC power supply 155, and a bias compensation module blocking capacitor (also referred to herein as blocking capacitor C5). The blocking capacitor C5 is disposed between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104.

[0037] The substrate support assembly 136 may further include an edge control electrode 115, which is positioned below the edge ring 114 and surrounds the bias electrode 104 and / or is disposed at a distance from the center of the bias electrode 104. Typically, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as Figure 1 As shown, the edge control electrode 115 is positioned within the region of the substrate support 105. In some embodiments, such as Figure 1 As shown, the edge control electrode 115 includes a conductive mesh, foil, and / or plate, which is positioned at a distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 similar to that of the bias electrode 104. In some other embodiments, the edge control electrode 115 includes a conductive mesh, foil, and / or plate positioned on or within a region of the quartz tube 110, the region surrounding at least a portion of the bias electrode 104 and / or the substrate support 105. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is positioned within or coupled to an edge ring 114 disposed on and adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed of a semiconductor or dielectric material (e.g., AlN, etc.).

[0038] Edge control electrode 115 can be biased using a different PV waveform generator than the PV waveform generator 150 used to bias bias electrode 104. In some embodiments, edge control electrode 115 can be biased using PV waveform generator 150, which is also used to bias bias electrode 104 by diverting a portion of the power to edge control electrode 115. In one configuration, a first PV waveform generator 150 of a first PV source assembly 196 is configured to bias bias electrode 104, and a second PV waveform generator 150 of a second PV source assembly 197 is configured to bias edge control electrode 115.

[0039] Power delivery line 157 electrically connects the output of the PV waveform generator 150 of the first PV source assembly 196 to the optional filter assembly 151 and the bias electrode 104. Although the following discussion primarily focuses on the power delivery line 157 for coupling the PV waveform generator 150 to the bias electrode 104 of the first PV source assembly 196, the power delivery line 158 for coupling the PV waveform generator 150 to the edge control electrode 115 of the second PV source assembly 197 will include the same or similar components. The electrical conductors(s) within the various portions of the power delivery line 157 may include: (a) a coaxial cable or combination of coaxial cables, such as a flexible coaxial cable connected in series with a rigid coaxial cable; (b) insulated high-voltage corona-resistant mounting wire; (c) bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical components in (a)-(e). Optional filter assembly 151 includes one or more electrical elements configured to substantially prevent current generated by the output of RF generator 118 from flowing through power delivery line 157 and damaging PV waveform generator 150. Optional filter assembly 151 serves as a high impedance (e.g., high Z) to the RF signal generated by RF generator 118 and thus suppresses current flow to PV waveform generator 150.

[0040] The second PV source assembly 197 includes a clamping network 116 such that the bias voltage applied to the edge control electrode 115 can be similarly configured to be applied to the bias electrode 104 via the clamping network 116 coupled within the first PV source assembly 196. Applying a similarly configured PV waveform and clamping voltage to the bias electrode 104 and the edge control electrode 115 can help improve plasma uniformity across the substrate surface during processing and thus improve the plasma processing results.

[0041] In some embodiments, the processing chamber 100 further includes a quartz conduit 110 or collar that at least partially surrounds multiple portions of the substrate support assembly 136 to prevent the substrate support 105 and / or support substrate 107 from contacting corrosive processing gases or plasmas, cleaning gases or plasmas, or their byproducts. Typically, the quartz conduit 110, insulator plate 111, and ground plane 112 are surrounded by a gasket 108. In some embodiments, a plasma shield 109 is positioned between the cathode gasket 108 and the sidewall 122 to prevent plasma formation in the volume below the plasma shield 109 between the gasket 108 and one or more sidewalls 122.

[0042] Figure 2AAn example voltage waveform 200 established at a substrate within a processing chamber (e.g., processing chamber 100) is shown. In this example, waveform 200 is generated by applying a waveform via a PV waveform generator 150 of a first PV source assembly 196. As shown, waveform 200 includes an ion current phase and a shell collapse phase. At the start of the ion current phase, a substrate voltage drop generated by a falling edge 204 creates a high-voltage shell formed over the substrate, thereby accelerating positive ions to the substrate. Positive ions bombarding the substrate surface during the ion current phase deposit positive charges on the substrate surface, which, if uncompensated, would cause a gradual positive increase in the substrate voltage during the ion current phase (i.e., a positive slope during phase 205 of voltage waveform 200), as shown. However, the uncontrolled accumulation of positive charges on the substrate surface undesirably and gradually discharges the shell and clamping capacitors, thereby slowly reducing the shell voltage drop and bringing the substrate potential closer to zero. The accumulation of positive charges results in a voltage drop in the voltage waveform established at the substrate (i.e., a positive slope during phase 205).

[0043] The voltage difference between the beginning and end of the ion current phase determines the width of the ion energy distribution function (IEDF). Figure 2B The effect of increased plasma density on a voltage waveform established on a substrate using a PV source (such as waveform generator 150) is illustrated. As shown, due to changes in one or more plasma processing parameters (e.g., RF power applied via plasma generator assembly 163), an increase in plasma density during plasma processing (i.e., the direction highlighted by the arrows) tends to increase the voltage difference from the beginning to the end of the ion current phase, and thus undesirably increase the voltage drop. The larger the voltage difference, the wider the IEDF width. For example, as... Figure 2C As shown, without compensating for the voltage rise of the substrate, the ion energy distribution (IED) 201 widens with increasing ion current. Therefore, by using the higher frequency voltage waveform technique disclosed herein, the voltage drop in the voltage waveform generated by the increased plasma density during plasma processing can be reduced, resulting in a narrower IED and thus leading to higher accuracy of the plasma processing results on the substrate.

[0044] In the reactor, plasma can be generated via an inductively coupled source (or peripheral coil) on top of the substrate. The coil can be placed on top of a ceramic cover (vacuum boundary), or, in the case of a capacitively coupled plasma reactor, by applying RF power to an electrostatic chuck or top electrode. As described, a waveform generator (e.g., waveform generator 150 of the first PV source assembly 196) outputs a bipolar and short, narrow positive pulse transitioning from a negative voltage to a positive voltage greater than zero, such as... Figure 2AAs shown. The duration of the positive voltage pulse is controlled and transitions back to the negative voltage baseline. The voltage remains negative, and is marked as T. 开启 The pulse transitions back to a positive pulse at the end of its time period. This transition occurs during the rising edge 202 portion of the voltage waveform 200. The duration of the positive segment of the pulse can vary, and in some embodiments, it occurs during the waveform period (T). P Between 1% and 20%, such as in the waveform period (T) P The period is between 5% and 15%. In one example, the waveform period can be about 5 μs and the frequency of waveform 200 can be about 200 kHz. In another example, the waveform period can be about 2.5 μs and the frequency of waveform 200 is about 400 kHz.

[0045] During a portion of the voltage waveform, plasma electrons are attracted to the substrate surface due to the rising edge 202 of the pulse step, but those electrons cannot establish a negative DC shell potential because of the equal amount of positive charge present on the electrodes (e.g., electrode 104). A substrate and dielectric disposed between the electrodes and the substrate support surface 105A form a capacitor having an effective capacitance C. esc This allows an equal amount of positive charge on the electrodes to counteract the field generated by electrons positioned on the substrate surface. At the falling edge 204 of the pulse step, the positive charge on the electrodes is neutralized by electrons from the waveform generator, and thus, a negative DC voltage is established on the substrate surface. If the formed DC voltage remains constant, single-energy ion bombardment is achieved. According to the following equation, the negative DC voltage (Vdc) can be obtained by using the amplitude (ΔV) of the falling edge, and C... esc With shell capacitance C 壳层 The ratio between them can be used to approximate:

[0046] Vdc=ΔV*C esc / (C esc +C 壳层 )

[0047] Waveform generation technology

[0048] As semiconductor device features shrink, atomic precision is frequently required during current substrate processing techniques such as plasma etching and plasma deposition. For etching processes where plasma ions play a dominant role, precise ion energy control is often necessary. Conventional radio frequency (RF) bias methods use sinusoidal waves to excite the plasma and accelerate ions. Ion energy distributions (IEDs) from conventional RF technologies typically exhibit a dual-mode shape. In recent years, pulsed techniques have also been explored to generate IEDs with a single energy peak.

[0049] In some implementations, due to system complexity and concerns about device cost, the positive ion current is not compensated during the ion current phase of the voltage waveform, and consequently, the negative voltage on the substrate decays over time (e.g., becomes less negative). In other words, as described with respect to waveform 200, without compensation, the substrate voltage rises during the ion current phase, also referred to herein as voltage drop. This trend worsens with increasing plasma density (e.g., increasing ion current), causing the IED to extend or broaden towards lower energy states, such as... Figure 2C As shown.

[0050] In some cases, a ramp voltage is generated by using a current source or multiple voltage sources coupled to the electrode (e.g., electrode 104) to compensate for this voltage rise during a portion of the ion current phase (e.g., at least during phase 205). However, at higher voltages (e.g., greater than 5 kV), generating a custom waveform with a ramp to compensate for this voltage rise is challenging.

[0051] In some embodiments, high-frequency voltage waveforms can be used to reduce the effects of this voltage rise (i.e., voltage drop) generated during the ion current phase. In the current state of high-voltage switches available on the market today, generating high-frequency voltage pulse trains at pulse repetition frequencies greater than 400 kHz is problematic due to physical and practical device limitations found in these conventional components. Consequently, as briefly discussed above, the switching speed of these conventional high-voltage switches is limited to a maximum practical switching speed due to damage caused by heat generated during use at mid- to high-frequency intervals. In some embodiments of this disclosure, time-domain multiplexing of voltage pulses is used to generate the voltage to be supplied to a composite load (e.g., an electrostatic chuck and plasma 101). Figure 1 The waveform allows the load to receive higher frequency pulses, thereby mitigating the effects of voltage drop at the substrate surface. For example, a positive voltage pulse at a frequency of approximately 400 kHz can be used to periodically establish a negative DC bias on the substrate, thereby obtaining an IED with a single energy peak. In other words, when the voltage at the substrate surface rises to a certain threshold during the ion current phase of the first voltage waveform pulse, a second voltage waveform pulse (e.g., from a different source or switch) can be applied to effectively reset the voltage at the substrate surface during subsequent pulse cycles, as described in more detail herein.

[0052] Figure 3A pulsed voltage bias scheme using waveform 300 according to certain embodiments of the present disclosure is illustrated. As shown, the first pulsed voltage cycle 320 and the second pulsed voltage cycle 322 can be time-multiplexed. For the electrostatic chuck and plasma 101, the frequency of the voltage pulses appears to have increased due to the interleaving of the first pulsed voltage cycle 320 and the second pulsed voltage cycle 322. As the substrate voltage begins to drop during the ion current phase of the first voltage cycle generated by the first PV source, a second pulse generated by the second PV source is applied, restoring the DC voltage bias (negative) on the substrate and recovering the decreased ion energy caused by the voltage drop.

[0053] In other words, such as Figure 3 As shown, waveform 300 may include a positive voltage pulse 302 and a negative voltage pulse 304 for a first pulse voltage cycle 320, followed by another positive voltage pulse 306 and another negative voltage pulse 308 for a second pulse voltage cycle 322. In some embodiments, the positive voltage pulse 302 and the negative voltage pulse 304 may use a switching pair (e.g., Figure 4A The positive voltage pulse 306 and the negative voltage pulse 308 can be generated using another switch pair (e.g., S1 and S3 in the original text), and another positive voltage pulse 306 and another negative voltage pulse 308 can be generated using another switch pair (e.g., S1 and S3 in the original text). Figure 4A The pulses are generated using switches S2 and S4. Compared to conventional implementations that use only a single switch pair to generate positive and negative pulses, using different switch pairs allows for higher frequency waveforms. In other words, each switch can be implemented using one or more transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). Each MOSFET may have a switching frequency limit (e.g., maximum practical switching speed) due to heating, thus preventing a single switch pair from generating high-frequency (e.g., 400 kHz) pulses. If the switches operate at frequencies greater than the switching frequency limit, the heat generated in the switches due to the presence of high switching voltages leads to an increase in switching resistance, potentially increasing the voltage drop across the switches. For example, depending on the switching frequency and switch type, the voltage drop across the switches can increase by 10% or more. Furthermore, if multiple switches are coupled in series, the voltage drop across the switches accumulates. In other words, if three switches are coupled in series (e.g., to implement switches S1, S2, S3, or S4), and the voltage drop across each switch increases by 10%, the total voltage drop across the switches can increase by 30%. It is also believed that when the voltage drop across the switch is limited by the switching frequency of the switch to the moment when the switch is first put into use at the same switch input voltage, a voltage drop across the switch of ≥10% may cause permanent damage to components within the switch (e.g., increasing switch resistance over time) and / or a significantly shorter lifespan than normal.

[0054] Figure 4AA waveform generator 400 for generating pulses during a first pulse voltage cycle 320 and a second pulse voltage cycle 322, according to certain embodiments of the present disclosure, is shown. The waveform generator 400 may be part of a PV waveform generator 150. Figure 4B This is a timing diagram 401 showing the switching states of the waveform generator 400.

[0055] As shown in the figure, switch S1 can be closed during a first phase, thereby coupling the waveform generator output node 402 to the voltage source V1 of the voltage source circuit system 410 and generating a positive voltage pulse 302. Switch S1 is then opened, and switch S3 is closed during a second phase, thereby grounding the output node 402. Grounding the output node 402 results in a negative voltage pulse 304. In other words, during the positive voltage pulse 302, the capacitor between the output node 402 and the substrate charges. After the positive voltage pulse 302, the output node 402 is coupled to the electrical ground node. Since the voltage across the capacitor between the output node 402 and the substrate cannot change instantaneously, the substrate voltage drops to a negative voltage in response to the closing of switch S3.

[0056] After switch S3 is opened, switch S2 closes during the third phase, thereby coupling voltage source V2 of voltage source circuit system 410 to output node 404, effectively implementing a positive voltage pulse 306. Switch S2 then opens, and switch S4 closes during the fourth phase, thereby coupling output node 404 to an electrical ground node to implement a negative voltage pulse 308. As illustrated by timing diagram 401, the first, second, third, and fourth phases are non-overlapping phases. As shown, repeatable phases can generate continuous time-multiplexed pulse waveforms delivered at a frequency greater than the maximum actual switching speed of each individual switch. In one example, if the maximum actual switching speed limit for each switch restricts the switching frequency of each switch to 400 kHz, a two-voltage source configuration containing the same switches can deliver a time-multiplexed pulse train with a frequency greater than 400 kHz and less than or equal to 800 kHz. In a non-limiting example, if the waveform generator 400 is required to generate an 800kHz pulse train, then correspondingly, switch combinations S1 / S3 and S2 / S4 are respectively used to provide a first pulse voltage cycle 320 and a second pulse voltage cycle 322, which will each have a period of 1.25μs (T). P However, they are spaced 2.5 μs apart and staggered in time to form the desired pulse train.

[0057] In some embodiments, output nodes 402 and 404 may be coupled to the same node in the chamber. For example, output nodes 402 and 404 may be coupled to electrode 104. In some embodiments, output nodes 402 and 404 may be coupled to different nodes in the chamber. For example, output node 402 may be coupled to electrode 104 and output node 404 may be coupled to electrode 115.

[0058] In some embodiments, the first voltage source circuit system 410 of the waveform generator 400 forms the PV waveform generator 150 of the first PV source component 196. Figure 1 In another embodiment, the first voltage source circuit system 410 of the waveform generator 400 forms part of the PV waveform generator 150 of the first PV source assembly 196, and the second voltage source circuit system 410 of the waveform generator 400 forms part of the PV waveform generator 150 of the second PV source assembly 197. In yet another embodiment, the first voltage source circuit system 410 of the waveform generator 400 forms part of the PV waveform generator 150 of the first PV source assembly 196, the second voltage source circuit system 410 of the waveform generator 400 forms part of the PV waveform generator 150 of the second PV source assembly 197, and / or the third voltage source circuit system 410 of the waveform generator 400 forms part of the PV waveform generator 150 of the third PV source assembly 198 coupled to the cover 123. In any of these configurations, and where appropriate, the output nodes 402, 404 of the first voltage source circuit system 410 are coupled to the electrode 104, the output nodes 402, 404 of the second voltage source circuit system 410 are coupled to the electrode 115, and / or the output nodes 402, 404 of the third voltage source circuit system 410 are coupled to the cover 123.

[0059] In some embodiments, the voltage source circuit system 410 may include a first voltage source V1 coupled to switch S1 and a second voltage source V2 coupled to switch S2. Each of the first and second voltage sources may be implemented using a capacitor element that is charged to a specific voltage by a power source. In some embodiments, the first voltage source V1 and the second voltage source V2 of each voltage source circuit system 410 may provide different voltages or the same voltage.

[0060] Although the examples provided herein have described two switch pairs to facilitate understanding, embodiments of this disclosure may be implemented using more than two switch pairs. For example, in addition to the first switch pair (e.g., S1 and S3) and the second switch pair (e.g., S2 and S4), a third switch pair may be implemented to generate positive and negative pulses, thereby allowing operation at higher frequencies. In other words, after switches S2 and S4 are used to generate positive voltage pulse 306 and negative voltage pulse 308, and before switches S1 and S3 are used to generate positive voltage pulse 302 and negative voltage pulse 304 again, the third switch pair may be used to generate another positive pulse and another negative pulse. Thus, in some embodiments, multiple switch pairs are utilized in a series and repeating loop to form a pulse train with a frequency greater than the maximum actual switching speed of each individual switch, such that the maximum frequency of the pulse train is equal to N times the maximum frequency of each switch, or at least N times the maximum frequency of the slowest switch among the multiple switches, where N is equal to the number of switch pairs in the multiple switch pairs. Operating each of the switch pairs during different phases of the generated pulse train allows for the implementation of high-frequency waveforms for plasma processing. Using higher frequency waveforms allows for a reduction in voltage drop (e.g., the voltage increase during the ion current phase), thereby increasing the accuracy of plasma processing.

[0061] Figure 5 The diagram illustrates the ion energy distribution (IED) associated with waveform 300 according to certain embodiments of the present disclosure. As shown, when a higher frequency waveform (e.g., 400 kHz) is generated, an IED associated with a lower frequency waveform (e.g., having a frequency of 200 kHz) can be obtained. Figure 2A The waveform (200) is narrower compared to a narrower IED. A narrower IED promotes greater feature formation accuracy, for example, during typical etch plasma processes.

[0062] Figure 6 This is a process flow diagram illustrating a method 600 for waveform generation. Method 600 can be performed by a waveform generation system, which includes a waveform generator (such as waveform generator 400) and a system controller (such as system controller 126).

[0063] At activity 602, method 600 begins with the waveform generation system coupling a voltage source circuit system (e.g., voltage source circuit system 410) to a first output node (e.g., output node 402) of the waveform generator (e.g., waveform generator 400) via a first switch (e.g., switch S1), the first output node being coupled to a chamber (e.g., chamber 100). At activity 604, the waveform generation system couples the first output node to an electrical ground node via a second switch (e.g., switch S3). At activity 606, the waveform generation system couples the voltage circuit system to a second output node (e.g., output node 404) of the waveform generator via a third switch (e.g., switch S2), the second output node being coupled to the chamber. At activity 608, the waveform generation system couples the second output node to an electrical ground node via a fourth switch (e.g., switch S4). In some embodiments, activities 602, 604, 606, and 608 may be repeated to generate waveforms for plasma processing.

[0064] In some embodiments, a first pulse voltage waveform (e.g., including a positive voltage pulse 302 and a negative voltage pulse 304) is generated in the chamber via coupling through a first switch and a second switch. Furthermore, a second pulse voltage waveform (e.g., including a positive voltage pulse 306 and a negative voltage pulse 308) is generated in the chamber via coupling through a third switch and a fourth switch. The first pulse voltage waveform may be phase-shifted (e.g., 180°) from the second pulse voltage waveform.

[0065] In some embodiments, coupling via the first, second, third, and fourth switches occurs during a non-overlapping phase. For example, the voltage source circuit system couples to the first output node during a first phase of the non-overlapping phase, and the first output node couples to an electrical ground node during a second phase of the non-overlapping phase, which follows the first phase. Furthermore, the voltage source circuit system couples to the second output node during a third phase of the non-overlapping phase, which follows the second phase, and the second output node couples to the electrical ground node during a fourth phase of the non-overlapping phase, which follows the third phase.

[0066] In some embodiments, the voltage source circuit system includes a first voltage source (e.g., voltage source V1) coupled to a first switch and a second voltage source (e.g., voltage source V2) coupled to a second switch. The first voltage source may include a first capacitor element, and the second voltage source may include a second capacitor element. Each of the first switch, the second switch, the third switch, and the fourth switch may include one or more transistors (e.g., MOSFETs).

[0067] In some embodiments, the waveform generation system can generate a first positive voltage pulse (e.g., positive voltage pulse 302) at a node in the cavity (e.g., at the substrate) by coupling a voltage source circuit system to a first output node, and generate a first negative voltage pulse (e.g., negative voltage pulse 304) at a node in the cavity by coupling the first output node to an electrical ground node. Furthermore, the waveform generation system can generate a second positive voltage pulse (e.g., positive voltage pulse 306) at a node in the cavity by coupling a voltage source circuit system to a second output node, and generate a second negative voltage pulse (e.g., negative voltage pulse 308) at a node in the cavity by coupling the second output node to an electrical ground node.

[0068] The term "coupling" is used in this article to refer to direct or indirect coupling between two objects. For example, if object A physically touches object B and object B touches object C, then object A and object C can still be considered coupled to each other—even if object A and object C do not directly physically touch each other. For example, object A can be coupled to object B even if object B never directly physically touches object C.

[0069] Although the foregoing relates to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, the scope of which is defined by the appended claims.

Claims

1. A waveform generator for plasma processing, comprising: Voltage source circuit system; A first switch is coupled between the voltage source circuit system and a first output node of the waveform generator, the first output node being configured to be coupled to the chamber. A second switch is coupled between the first output node and the electrical ground node; A third switch is coupled between the voltage source circuit system and the second output node of the waveform generator, the second output node being configured to be coupled to the chamber; as well as A fourth switch, coupled between the second output node and the electrical ground node, wherein: The first switch and the second switch are configured to generate a first pulse voltage waveform to be supplied to the chamber; as well as The third and fourth switches are configured to generate a second pulse voltage waveform to be supplied to the chamber, wherein the first pulse voltage waveform is phase-shifted from the second pulse voltage waveform.

2. The waveform generator of claim 1, wherein the first switch, the second switch, the third switch, and the fourth switch are configured to close during a non-overlapping phase.

3. The waveform generator as described in claim 2, wherein: The first switch is configured to close during the first phase of the non-overlapping phase; The second switch is configured to close during a second phase of the non-overlapping phase, which is after the first phase; The third switch is configured to close during a third phase of the non-overlapping phase, which is after the second phase; as well as The fourth switch is configured to close during the fourth phase of the non-overlapping phase, which is after the third phase.

4. The waveform generator of claim 1, wherein the voltage source circuit system includes a first voltage source coupled to the first switch and a second voltage source coupled to the second switch.

5. The waveform generator of claim 4, wherein the first voltage source comprises a first capacitor element, and wherein the second voltage source comprises a second capacitor element.

6. The waveform generator of claim 1, wherein each of the first switch, the second switch, the third switch, and the fourth switch comprises one or more transistors.

7. The waveform generator of claim 1, wherein the first output node is coupled to the second output node.

8. The waveform generator of claim 7, wherein the first output node and the second output node are coupled to an electrode disposed below the substrate support surface of a substrate support member disposed in the chamber.

9. The waveform generator of claim 8, wherein at least one of the first switch, the second switch, the third switch, or the fourth switch has a switching frequency limit, and wherein the waveform generator is configured to generate a waveform at the electrode having a frequency greater than the switching frequency limit.

10. A method for waveform generation, comprising the following steps: The voltage source circuit system is coupled to the first output node of the waveform generator via a first switch, and the first output node is coupled to the chamber. The first output node is coupled to the electrical ground node via the second switch; The voltage source circuit system is coupled to the second output node of the waveform generator via a third switch, and the second output node is coupled to the chamber. as well as The second output node is coupled to the electrical ground node via a fourth switch, wherein: The first pulse voltage waveform is generated in the chamber via the coupling between the first switch and the second switch; as well as The second pulse voltage waveform is generated in the chamber via the coupling of the third and fourth switches, and the first pulse voltage waveform is phase-shifted from the second pulse voltage waveform.

11. The method of claim 10, wherein the coupling via the first switch, the second switch, the third switch and the fourth switch is during a non-overlapping phase.

12. The method of claim 11, wherein: During the first phase of the non-overlapping phase, the voltage source circuit system is coupled to the first output node; During the second phase of the non-overlapping phase, the first output node is coupled to the electrical ground node, and the second phase occurs after the first phase. During the third phase of the non-overlapping phase, the voltage source circuit system is coupled to the second output node, the third phase being after the second phase; as well as During the fourth phase of the non-overlapping phase, the second output node is coupled to the electrical ground node, the fourth phase being after the third phase.

13. The method of claim 10, wherein the voltage source circuit system comprises a first voltage source coupled to the first switch and a second voltage source coupled to the third switch.

14. The method of claim 13, wherein the first voltage source comprises a first capacitor element, and wherein the second voltage source comprises a second capacitor element.

15. The method of claim 10, wherein each of the first switch, the second switch, the third switch, and the fourth switch comprises one or more transistors.

16. The method of claim 10, further comprising the following steps: A first positive voltage pulse is generated at the node in the chamber by coupling the voltage source circuit system to the first output node; A first negative voltage pulse is generated at the node in the chamber by coupling the first output node to the electrical ground node; A second positive voltage pulse is generated at the node in the chamber by coupling the voltage source circuit system to the second output node; as well as A second negative voltage pulse is generated at the node in the chamber by coupling the second output node to the electrical ground node.

17. The method of claim 10, wherein the first output node and the second output node are coupled to an electrode disposed below the substrate support surface of a substrate support disposed within the cavity.

18. The method of claim 17, wherein at least one of the first switch, the second switch, the third switch, or the fourth switch has a switching frequency limit, the method further comprising the step of: generating a waveform at the electrode having a frequency greater than the switching frequency limit.

19. An apparatus for waveform generation, comprising: Voltage source circuit system; One or more switches, said one or more switches being coupled to the voltage source circuit system; as well as A controller configured to control the one or more switches, wherein the one or more switches include: A first switch is coupled between the voltage source circuit system and a first output node of the device, the first output node being configured to be coupled to a chamber. A second switch is coupled between the first output node and the electrical ground node; A third switch, coupled between the voltage source circuit system and a second output node of the device, the second output node being configured to couple to the chamber; and A fourth switch, coupled between the second output node and the electrical ground node, in: The first switch and the second switch are configured to generate a first pulse voltage waveform to be supplied to the chamber; and The third and fourth switches are configured to generate a second pulse voltage waveform to be supplied to the chamber, wherein the first pulse voltage waveform is phase-shifted from the second pulse voltage waveform.

20. The device of claim 19, wherein the controller is configured to close the first switch, the second switch, the third switch, and the fourth switch during a non-overlapping phase.

21. The device of claim 20, wherein the controller is configured to: The first switch is closed during the first phase of the non-overlapping phase; The second switch is closed during the second phase of the non-overlapping phase, which is after the first phase. The third switch is closed during the third phase of the non-overlapping phase, which is after the second phase; as well as The fourth switch is closed during the fourth phase of the non-overlapping phase, which is after the third phase.

22. The device of claim 19, wherein the voltage source circuit system comprises a first voltage source coupled to the first switch and a second voltage source coupled to the third switch.

23. The device of claim 19, wherein the first output node and the second output node are coupled to an electrode disposed below the substrate support surface of a substrate support disposed within the cavity.

24. The device of claim 23, wherein at least one of the first switch, the second switch, the third switch, or the fourth switch has a switching frequency limit, and wherein the device is configured to generate a waveform at the electrode having a frequency greater than the switching frequency limit.

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