N-phase transmitter / receiver i / q imbalance calibration

Abstract

A measurement receiver is used to measure I / Q mismatch, where an RF phase shift is introduced to distinguish between transmitter I / Q mismatch and measurement receiver I / Q mismatch. Joint transmit and receive image calibration of N ≠ 4 N-phase Tx / MRx is performed. A combined communication signal, e.g., an RF signal having in-phase and quadrature components, is received by a receiver stage. A first N-phase baseband reference signal is generated from the received in-phase / quadrature components, where N is an integer equal to 3 or greater than 4. A second N-phase baseband signal is generated from the received in-phase / quadrature components. Mismatch between the first N-phase baseband reference signal and the second N-phase baseband signal is used to generate correction coefficients for the transmitter.

Description

Technical Field

[0001] This disclosure generally relates to the calibration of in-phase / quadrature transmitters. Background Technology

[0002] Linear in-phase / quadrature (I / Q) transmitters typically suffer from image distortion due to gain and phase imbalance between the in-phase and quadrature paths. This image distortion usually requires image calibration of the transmitter path using a measurement receiver. However, the measurement receiver itself also suffers from similar image distortion. One approach to distinguish between the transmitter and measurement receiver images during calibration is to insert an RF phase shifter between the transmitter and measurement receiver to provide a known RF phase shift. However, when designing such an RF phase shifter over a very wide frequency range covering multiple bands, achieving a near-constant phase shift over this wide frequency range using a single network becomes a challenging task, primarily due to the variability and uncontrollable behavior of layout parasitic effects across such a wide frequency range. Summary of the Invention

[0003] According to one aspect of this disclosure, a general aspect includes an apparatus having a local oscillator generation circuit. The apparatus further includes an N-phase receiver circuit configured to receive a communication signal and generate in-phase / quadrature signals and phase-shifted in-phase / quadrature signals from the communication signal, the phase shift being a known phase shift, where N is an integer equal to or greater than 3. The apparatus also includes an I / Q mismatch correction circuit configured to generate transmitter correction coefficients from a calculated mismatch using the known phase shift.

[0004] Implementation of this technology may include one or more of the following features of a device comprising an N-phase local oscillator switching circuit configured to generate a phase-shifted local oscillator signal from an N-phase local oscillator signal as an N-phase local oscillator signal with a known phase shift. The device may include means where N is 6, and the N-phase local oscillator switching circuit includes a plurality of latches configured as a non-50% duty cycle divide-by-3 circuit, each latch having an output coupled to a first input of a logic gate, each logic gate having a divide-by-3 clock signal as a second input, and the output of each logic gate creating one of a plurality of N non-overlapping signals. The device may include any of the foregoing means, wherein the N-phase local oscillator switching circuit includes at least one multiplexer associated with each logic gate, each multiplexer being adapted to select between inputs including first outputs from the plurality of latches and second outputs from the plurality of latches, the selection creating a known phase shift among the N non-overlapping signals. The device may include any of the foregoing devices, wherein each logic gate is configured to select between an input including a first output from a plurality of latches and a second output from a plurality of latches, the selection creating a known phase shift among n non-overlapping signals. The device may include any of the foregoing devices, wherein the I / Q mismatch correction circuitry is further configured to time-align in-phase / quadrature signals and phase-shifted in-phase / quadrature signals. The device may include any of the foregoing devices, wherein the device further includes a transmit stage, and the device is further configured to apply correction coefficients to the transmit stage. Implementation of the technology may include hardware, a method or process, or computer software on a computer-accessible medium.

[0005] One general aspect includes a method for correcting in-phase / quadrature mismatch, the method comprising receiving an RF communication signal having in-phase and quadrature components. The correction method may further include generating a first N-phase baseband reference signal from the in-phase / quadrature components of the received signal, where n is an integer equal to 3 or greater than 4. The correction method further includes generating a second N-phase baseband signal based on the received in-phase / quadrature components, the second N-phase baseband signal having a known phase shift created by changing the output phase of a local oscillator signal. The correction method may further include generating transmitter correction coefficients from a calculated mismatch based on the known phase shift.

[0006] The implementation may include one or more of the following features. The method may also include generating a first N-phase baseband reference signal from the received in-phase / quadrature components based on a local oscillator signal, and generating a second N-phase baseband signal from the received in-phase / quadrature components based on a known phase shift of the output phase of the local oscillator signal swapped in an oscillator switching circuit. The method may include implementations of any of the foregoing methods, where N is 6, and where the N-phase local oscillator switching circuit includes a plurality of latches configured as non-50% duty cycle divide-by-3 circuits, each latch having an output coupled to a first input of a logic gate, each logic gate having a divide-by-3 clock signal as a second input, and the output of each logic gate creating one of a plurality of n non-overlapping signals, wherein the method includes selecting a known phase shift by selecting a plurality of inputs from the logic gate inputs of the plurality of latches. The method may include implementations of any of the foregoing methods, wherein the method further includes selecting a plurality of inputs from the inputs of a logic gate by enabling selection bits in a plurality of multiplexers, one of the plurality of multiplexers associated with each logic gate, the selection creating a known phase shift among the n non-overlapping signals. This method may include implementations of any of the foregoing methods, wherein the method further includes selecting multiple inputs to the inputs of the logic gates by enabling selection bits in each logic gate, the selection creating a known phase shift among n non-overlapping signals. This method may include implementations of any of the foregoing methods, wherein the method further includes temporally aligning the in-phase / quadrature signals and the phase-shifted in-phase / quadrature signals prior to the calculation. This method may include implementations of any of the foregoing methods, wherein the method further includes applying correction coefficients to the transmit stage.

[0007] One general aspect includes a wireless communication system comprising a transmitting circuit configured to generate a first communication signal. The wireless communication system may further include a local oscillator generating circuit. The wireless communication system may also include an N-phase receiver circuit configured to receive a second communication signal and generate an in-phase / quadrature signal and a phase-shifted in-phase / quadrature signal from the second communication signal, wherein the phase shift of the phase-shifted in-phase / quadrature signal is a known phase shift, and N is an integer equal to or greater than 3. The wireless communication system may further include an I / Q mismatch correction circuit configured to generate transmitting circuit correction coefficients based on the known phase shift and further configured to apply the correction coefficients to the transmitting stage.

[0008] The implementation may include one or more of the following features. The system may also include a local oscillator generation circuit comprising an N-phase local oscillator switching circuit configured to output an N-phase local oscillator signal with a known phase shift based on a local oscillator signal from the local oscillator generation circuit. The system may also include a system comprising any of the foregoing features, where N is 6, and the N-phase local oscillator switching circuit comprises a plurality of latches configured as non-50% duty cycle divide-by-3 circuits, each latch having an output coupled to a first input of a NAND gate, each NAND gate having a divide-by-3 clock signal as a second input, and the output of each NAND gate creating one of a plurality of n non-overlapping signals. The system may also include a system comprising any of the foregoing features, wherein the N-phase local oscillator switching circuit comprises at least one multiplexer associated with each NAND gate, each multiplexer being adapted to select between inputs including first outputs from the plurality of latches and second outputs from the plurality of latches, the selection creating a known phase shift among the N non-overlapping signals. The system may also include a system comprising any of the foregoing features, wherein each NAND gate is configured to select between an input comprising a first output from a plurality of latches and a second output from a plurality of latches, the selection creating a known phase shift among n non-overlapping signals. The system may also include a system comprising any of the foregoing features, wherein the I / Q mismatch correction circuitry is further configured to time-align the in-phase / quadrature signals and the phase-shifted in-phase / quadrature signals. Implementation of the technique may include hardware, a method or process, or computer software on a computer-accessible medium.

[0009] This invention summary is provided to introduce a series of concepts in a simplified form, which are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that address any or all of the shortcomings mentioned in the background art. Attached Figure Description

[0010] Various aspects of this disclosure are shown by way of example and are not limited to the accompanying drawings, with the same reference numerals indicating elements in the drawings.

[0011] Figure 1A A wireless network used for data transmission is shown.

[0012] Figure 1B It is possible in the network, for example, in Figure 1A A block diagram of the wireless communication system used.

[0013] Figure 2 It provides information about Figure 1BA block diagram showing more details of the implementation of the transmitter section.

[0014] Figure 3 The four-phase local oscillator signal and the associated duty cycle errors α and β for each phase are shown.

[0015] Figure 4A A four-phase receiver stage is shown that receives a combined RF signal as input.

[0016] Figure 4B The imbalance of duty cycle errors at various phases of 0°, 90°, 180°, and 270° is shown.

[0017] Figure 5 The six-phase LO signals and the associated duty cycle errors α and β associated with the six phases 0°, 60°, 120°, 180°, 240° and 300° are shown.

[0018] Figure 6A A six-phase receiver stage is shown that receives a combined RF signal as input.

[0019] Figure 6B The balance between duty cycles α and β in a 6-phase LO switching receiver stage is shown.

[0020] Figure 7 A method is shown for estimating the transmit and receive IQ mismatch coefficients for Tx / MR digital image correction by incorporating a known phase shift into the MRx output using LO switching.

[0021] Figure 8A and Figure 8B A more detailed N-phase receiver is shown.

[0022] Figure 9 An implementation of an N-phase local oscillator generator is shown.

[0023] Figure 10 A second embodiment of the N-phase generator is shown.

[0024] Figure 11 A standard two-input NAND gate is shown.

[0025] Figure 12 The dual-input NAND gate enabled by the MUX is shown. Detailed Implementation

[0026] This disclosure will now be described with reference to the accompanying drawings, which generally relate to techniques for improving the calibration of in-phase / quadrature (I / Q) transmitter circuits and the time required for calibration. A measurement receiver is used to measure I / Q mismatch, wherein an RF phase shift is introduced to help distinguish between transmitter I / Q mismatch and measurement receiver I / Q mismatch. The I / Q mismatch in the transmitter and measurement receiver is calculated using known phase shifts, rather than assuming the amount of the introduced phase shift.

[0027] A technique is provided to achieve joint Tx / MRx image calibration of N-phase Tx / MRx with N ≠ 4 (e.g., N = 3, 5, 6, 8) without relying on phase shifters or requiring a dedicated MRx PLL. A local oscillator is "swapped" to generate a known phase shift for calculating I / Q mismatch. In this technique, a combined communication signal, such as an RF signal with in-phase and quadrature components, is received by a receiver stage. A first N-phase baseband reference signal is generated based on the received in-phase / quadrature components, where N is an integer equal to 3 or greater than 4. A second N-phase baseband signal is generated based on the known phase shift and the received in-phase / quadrature components. In one aspect, this is performed by changing or "swapping" the output phase of the local oscillator signal. The mismatch between the first N-phase baseband reference signal and the second N-phase baseband signal is calculated based on the known phase shift, and transmitter correction coefficients can be generated based on the calculated mismatch.

[0028] It should be understood that the embodiments of this disclosure presented can be implemented in many different forms, and the scope of the claims should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the innovative concept of implementation to those skilled in the art. In fact, this disclosure is intended to cover alternatives, modifications, and equivalents to these embodiments, which are included within the scope and spirit of this disclosure as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of the embodiments of this disclosure presented in order to provide a thorough understanding. However, it will be apparent to those skilled in the art that the embodiments of this disclosure presented can be practiced without these specific details.

[0029] Figure 1AA wireless network for transmitting data is shown. Communication system 10 includes, for example, user equipment 11A to 11C, radio access networks (RANs) 12A to 12B, a core network 13, a public switched telephone network (PSTN) 14, the Internet 15, and other networks 16. Additional or alternative networks include private and public packet networks, including corporate intranets. Although a specific number of these components or elements are shown in the figures, any number of these components or elements may be included in system 10.

[0030] In one implementation, the wireless network may be a fifth-generation (5G) network comprising at least one 5G base station, which communicates with the communication device using orthogonal frequency-division multiplexing (OFDM) and / or non-OFDM, and a transmission time interval (TTI) shorter than 1 ms (e.g., 100 microseconds or 200 microseconds). Typically, "base station" can also refer to either an eNB or a 5G BS (gNB). Additionally, the network may include a network server for processing information received from the communication device via at least one eNB or gNB.

[0031] System 10 enables multiple wireless users to send and receive data and other content. System 10 can implement one or more channel access methods, such as, but not limited to, code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

[0032] User equipment (UE) 11A to 11C are configured to operate and / or communicate in system 10. For example, UE 11A to 11C are configured to transmit and / or receive wireless or wired signals. Each UE 11A to 11C represents any suitable end-user device and may include such devices as (or may be referred to as) user equipment / devices, wireless transceiver units (UEs), mobile stations, fixed or mobile subscriber units, pagers, cellular phones, personal digital assistants (PDAs), smartphones, laptops, computers, touchpads, wireless sensors, wearable devices, or consumer electronics devices.

[0033] In the depicted implementation, RAN 12A to 12B each include one or more base stations 17A, 17B (collectively referred to as base station 17). Each of the base stations 17 is configured to radio interface with one or more UEs 11A, 11B, 11C to enable access to the core network 13, PSTN 14, Internet 15, and / or other networks 16. For example, base station (BS) 17 may include several known devices, such as base transceiver station (BTS), Node B (Node-B), evolved Node B (eNB), next (fifth) generation (5G) Node B (gNB), home Node B, home eNodeB, site controller, access point (AP), or wireless router, or server, router, switch, or other processing entity with wired or wireless networks, one or more.

[0034] In one implementation, base station 17A forms part of RAN 12A, which may include other base stations, elements, and / or devices. Similarly, base station 17B forms part of RAN 12B, which may include other base stations, elements, and / or devices. Each of the base stations 17 operates to transmit and / or receive radio signals within a specific geographic area or region (sometimes referred to as a "cell"). In some implementations, multiple-input multiple-output (MIMO) technology with multiple transceivers for each cell may be employed.

[0035] Base station 17 communicates with one or more user equipment 11A to 11C via one or more air interfaces (not shown) using wireless communication links. The air interfaces can utilize any suitable radio access technology.

[0036] It is anticipated that system 10 can utilize multi-channel access capabilities, including, for example, schemes in which base station 17 and user equipment 11A to 11C are configured to implement Long Term Evolution (LTE), LTE Advanced (LTE-A), and / or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, base station 17 and user equipment 11A to 11C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and radio protocols can be utilized.

[0037] RANs 12A to 12B communicate with core network 13 to provide voice, data, application, Voice over Internet Protocol (VoIP), or other services to user equipment 11A to 11C. As understood, RANs 12A to 12B and / or core network 13 may communicate directly or indirectly with one or more other RANs (not shown). Core network 13 may also serve as a gateway access for other networks (e.g., PSTN 14, Internet 15, and other networks 16). Additionally, some or all of user equipment 11A to 11C may include functionality for communicating with different wireless networks via different wireless links using different wireless technologies and / or protocols.

[0038] RANs 12A to 12B may also include millimeter and / or microwave access points (APs). An AP may be part of base station 17 or may be located remotely from base station 17. An AP may include, but is not limited to, a mmW connection point (mmW CP) or a base station 17 capable of mmW communication (e.g., an mmW base station). An mmW AP may transmit and receive signals in a frequency range, such as from 24 GHz to 100 GHz, but is not required to operate across that entire range. As used herein, the term base station is used to refer to both base stations and / or wireless access points.

[0039] although Figure 1A An example of a communication system is shown, but it is possible to... Figure 1AVarious modifications can be made. For example, communication system 10 may include any number of user equipments, base stations, networks, or other components in any suitable configuration. It should also be understood that the term user equipment can refer to any type of wireless device that communicates with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are target devices, device-to-device (D2D) user equipment, machine-type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptops, PDAs, iPads, tablets, mobile terminals, smartphones, laptop embedded equipped (LEE), laptop mounted equipment (LME), and USB dongles.

[0040] Figure 1B This is a block diagram of a wireless communication system 100, such as a mobile phone or user equipment 11A to 11C or base station 17, showing some of the elements discussed below. To transmit the output signal from the circuit elements of processor 111, transmitter (Tx) section 101 up-converts the output signal from one of the baseband or intermediate frequency (IF) range signals to a radio frequency (RF) range signal, and amplifies, filters, and may perform other processing before supplying the transmitted signal to antenna 105. The output signal is in in-phase / quadrature (I / Q) format as in-phase and quadrature signals I generated by Tx I / Q block 107. Tx and Q Tx It is provided to Tx section 101. To perform up-conversion of the signal in Tx section 101 (and, as discussed below, down-conversion in the measurement receiver MRx), phase-locked loop (PLL) 109 can provide the local oscillator frequency LO. Although PLL 109 and Tx I / Q section 107 are in Figure 1B The elements are shown as separate blocks from the Tx section 101, but according to the implementation, these elements can be combined differently as circuit elements and implemented in hardware, firmware, software or a combination thereof.

[0041] The signal received by antenna 105 is supplied to receiver (Rx) section 103. Before passing the signal to other components on the device represented by processor 111, Rx section 103 performs any necessary or desired signal processing, such as down-conversion and filtering from RF to IF or baseband. Phase-locked loop (PLL′) 129 can provide the local oscillator frequency LO′ for the down-conversion. Figure 1B In this implementation, the output of Rx section 103 is in I / Q format, and Rx I / Q section 117 converts it into a receive signal supplied to the processor. Although PLL′129 and Rx I / Q section 117 are in... Figure 1B The elements are shown as separate blocks from the Rx portion 103, but according to the implementation, these elements can be combined differently as circuit elements and implemented in hardware, firmware, software or a combination thereof.

[0042] Linear in-phase / quadrature (I / Q) transmitters, such as the Tx section, typically experience image distortion due to gain and phase imbalance between the in-phase and quadrature paths. This image distortion can be determined by using a measurement receiver (MRx) to perform image calibration on the transmitter path. However, the MRx itself (typically, direct-conversion, zero-IF I / Q downconverters) also experiences similar image distortion, making it necessary to isolate the MRx that introduces the image distortion in order to determine the distortion originating from the transmit path itself. One method to distinguish between the Tx and MRx images during calibration is to insert an RF phase shifter between the Tx and MRx to provide a known RF phase shift (e.g., typically 90 degrees). However, when such RF phase shifters are designed, for example, to operate over a very wide frequency range covering multiple bands (e.g., 600 MHz to 6 GHz) via an RC / CR network, it becomes a challenging task to design near-constant phase shifts over such a wide frequency range using a single network, mainly due to the variation and uncontrollable behavior of parasitic effects when layout over such a wide frequency range.

[0043] To help overcome this difficulty, multiple phase shifters can be used, each covering a specific frequency range. However, even this does not guarantee a near-constant phase shift, and due to modeling issues, it may be impossible to accurately capture a near-constant phase shift from the simulation during the design phase. This complicates the design and leads to additional design time / iterations and increased scope / cost.

[0044] Figure 2 It provides information about Figure 1B More details of the implementation of the Tx part 101 are provided in the block diagram to address these issues. Figure 2The block diagram shows a typical direct upconversion (DUCT) Tx I / Q transmitter stage 300 and a zero-IF (ZIF) measurement receiver MRx stage 400 for measuring and calibrating Tx damage. The Tx stage 300 receives in-phase and quadrature signals I... Tx and Q Tx The signal is directly up-converted (using the local oscillator signal LO (or LO switch 290)), amplified, filtered, and otherwise processed to generate the transmit signal Tx and supply it to the antenna 105.

[0045] The following technique is provided: a known phase shift is introduced into the LO to help distinguish between Tx and MRx images, while maintaining overall cascaded Tx and MRx system image distortion. In one embodiment, LO switching can occur in MRx stage 400; in an alternative embodiment, LO switching can occur in Tx stage. Figure 2 The LO phase switching circuit 290 is shown, which is shown to receive the LO output PLL 109 and output a known phase-shifted LO to the receiver stage 400.

[0046] exist Figure 2 In this implementation, the RF to IF downconversion can be a direct downconversion using the same local oscillator frequency LO from the same phase-locked loop as the one used in the direct upconversion by the Tx stage 300; however, other implementations may use a separate local oscillator signal source. The output of the MRx stage includes in-phase and quadrature signals I. MRx and Q MRx .

[0047] The LO phase-switching circuit 290 can be any arbitrary network that provides phase switching, as described herein. Implementations of the phase-switching circuit are discussed below.

[0048] To correct for I / Q imbalance in the transmit section, a transmit I / Q mismatch correction TxIQMC filter 203, shown here in the general form of a complex filter, introduces correction at adders 205 and 207 to counteract frequency-dependent image distortion. Similarly, to correct for I / Q imbalance in the MRx section, a measurement receiver I / Q mismatch correction MRxIQMC filter 213, also shown here in the general form of a complex filter, introduces correction at adders 215 and 217 to counteract frequency-dependent image distortion introduced by the measurement receiver.

[0049] The I / Q mismatch correction parameters TxIQMC and MRxIQMC of TxIQMC filter 203 and MRxIQMC filter 213 are provided by N-phase estimation circuit 211, which is based on I... MRx and QMRx The known phase shift introduced by the signal and LO phase switching is used to calculate the correction parameters of the TxIQMC filter and RxIQMC filter. In this technique, LO switching is used to help introduce the known phase shift into the transmit or receive stage to help distinguish between Tx and MRx images while maintaining the image distortion of the total cascaded Tx+MRx system. The phase estimation circuit, such as the N-phase estimation circuit 211, can include any known phase estimation circuit system configured to be based on the I and Q phase signals (here, I... MRx and Q MRx The signal generates correction parameters for the TxIOMC and RxIOMC filters.

[0050] Figure 3 Figure 4 illustrates the concept of LO switching in a four-phase system and is used to understand the application of this technique to an N-phase system, where N is an integer equal to or greater than 4.

[0051] Figure 3 The four-phase LO signal and the associated duty cycle errors α and β for each phase are shown. Figure 3 As shown, the duty cycle errors α and β are associated with four phases: 0°, 90°, 180°, and 270°.

[0052] Figure 4A A basic MRx receiver stage is shown, which receives the combined RF signal X supplied to mixers 402, 404, 406, and 408. RFin (t) is used as input. In the left-hand depiction of receiver stage 400, mixers 402, 404, 406, and 408 are supplied with LOs without any phase swapping. Mixers 402 and 404 provide intermediate frequency (IF) outputs at 0° and 180° to IF_0Deg stage 410, while mixers 406 and 408 provide intermediate frequency outputs at 90° and 270° to IF_90Deg stage 412. When these four-phase LO signals are applied to the four-phase MRx 400, as shown in Figure 4, I / Q image distortion will occur even if the IF stages (IF_0Deg and IF_90Deg) are the same.

[0053] exist Figure 4A On the right side, a 90-degree LO switch is shown at receiver stage 400'. In the depiction on the right side of receiver stage 400', mixers 402', 404', 406', and 408' are supplied with 90-degree phase-switched LOs from, for example, LO phase-switching circuit 290. Figure 4AIn the process, mixers 402' and 404' provide IF outputs at 90° and 270° to IF_0Deg stage 410, while mixers 406' and 408' provide IF outputs at 180° and 0° to IF_90Deg stage 412.

[0054] In receiver stage 400, LO-related I / Q image distortion is caused by the gain of each IF stage, which is scaled by the LO duty cycle. Therefore, the I path is scaled by α, while the Q path is scaled by β, and this creates a gain mismatch between the I and Q paths when α ≠ β. Therefore, a 90-degree LO swap in a 4-phase MRx stage will change the MRx image distortion because the I IF path and the Q IF path will be scaled by different duty cycles (α ≠ β), as... Figure 3 As shown in the image. This is in Figure 4B As shown in the figure, Figure 4B The imbalance of duty cycle errors at various phases of 0°, 90°, 180°, and 270° is shown.

[0055] However, this 90° LO switching cannot be used in 4-phase measurement receivers to distinguish between Tx and MRx images. In 4-phase Tx / MRx systems, to separate the Tx and MRx images, an RF phase shifter is inserted between the Tx and MRx channels, or a dedicated PLL is used to drive the MRx to achieve IF downconversion.

[0056] Figure 5 The six-phase LO signal and the associated duty cycle errors α and β associated with the six phases of 0°, 60°, 120°, 180°, 240°, and 300° are shown. While the subject matter is illustrated with respect to a six-phase system, this technique is applicable to any N-phase system, where N is an integer equal to or greater than 4.

[0057] Figure 6A An MRx receiver stage 600 is shown, which receives a combined RF signal X supplied to mixers 602, 604, 606, 608, 610, and 612. RFin (t) is used as input. In receiver stage 600, mixers 602, 604, 606, 608, 610, and 612 are supplied with LOs without any phase swapping. Mixers 602 and 604 provide IF outputs at 0° and 180° to IF_0Deg stage 620. Mixers 606 and 608 provide IF outputs at 60° and 240° to IF_60Deg stage 622. Mixers 610 and 612 provide IF outputs at 120° and 300° to IF_120Deg stage 624.

[0058] exist Figure 6AOn the upper right side, a 120° LO exchange is shown at MRx receiver stage 600'. The mixer receives the LO phase exchange provided by phase switching circuit 290, instead of the LO being input to mixers 602', 604', 606', 608', 610', and 612'. Figure 6A In this configuration, mixers 602' and 604' provide IF outputs at 120° and 300° to IF_0Deg stage 620. Mixers 606' and 608' provide IF outputs at 180° and 0° to IF_60Deg stage 622. Mixers 610' and 612' provide IF outputs at 240° and 60° to IF_120Deg stage 622.

[0059] When these 6-phase LO signals are applied to the 6-phase MRx, such as Figure 6A As shown, when all three IF levels (IF_0Deg, IF_60Deg, and IF_120Deg) are the same, it will not generate I / Q image distortion. Figure 5 As shown, all three IF stages are scaled equally by the LO duty cycle (α and β). This is in Figure 6B As shown in the figure, Figure 6B The balances of each phase (0°, 60°, 120°, 180°, 240°, and 300°) and the LO duty cycles α and β are shown.

[0060] exist Figure 6A The 120° LO swap shown on the right will not change the joint Tx / MRx image because all IF stages will be scaled by the same LO duty cycle. The LO swap will only introduce the desired (120°) phase shift to separate the Tx and MRx images. Note that... Figure 6A The LO switching in the diagram is merely a rearrangement of the LO connections, without altering the duty cycle error associated with each of the six LO signals. This can be achieved using a simple LO multiplexer or by simply inverting the inputs generated by the up to N-phase LOs, as described below.

[0061] Figure 7 A method is shown for estimating the Tx and MRx IQ mismatch coefficients for Tx / MR digital image correction by incorporating a known phase shift into the MRx output using LO switching. Figure 8A and Figure 8B A more detailed N-phase receiver is shown. Further reference will follow. Figure 8A and Figure 8B Let's discuss Figure 7 .

[0062] Reference Figure 7 At position 703, an N-phase receiver can be used, for example... Figure 2The RF signal is received at stage 400, where the number N of phases used in the system can be any integer other than 0 or 4. At 705, and referring to... Figure 8A An N-phase LO reference signal is generated based on the unexchanged LO signal. For example... Figure 8A As shown, MRx stage 800 includes a combined RF signal X supplied to mixers 802, 804, 806, 808, 810, and 812. RFin (t) As input, mixers 802, 804, 806, 808, 810, and 812 are also supplied with LO without any phase swapping. IF_0Deg stage 820, IF_60Deg stage 822, and IF_120Deg stage 822 provide their respective phased IF outputs to analog-to-digital converters 830, 832, and 834, respectively. The outputs of ADCs 830, 832, and 834 are coupled to adders 840 and 842 to provide the MRx baseband output I / Q signal y. bb1 (t)(described further below).

[0063] At 707, and refer to Figure 8B An N-phase MRx reference signal is generated based on the switched LO signal. For example... Figure 8B As shown, the LO switching MRx stage 800' includes a combined RF signal X supplied to mixers 802, 804, 806, 808, 810, and 812. RFin (t) As input, mixers 802, 804, 806, 808, 810, and 812 are supplied with phase-switched LO signals. (Note that the LO phase supplied to mixers 802, 804, 806, 808, 810, and 812 has been changed from...) Figure 8A (LO phase change shown). IF_0Deg stage 820, IF_60Deg stage 822, and IF_120Deg stage 822 again provide their respective phased IF outputs to analog-to-digital converters 830, 832, and 834, respectively. The outputs of analog-to-digital converters 830, 832, and 834 are combined at 840 and 842 to provide the (LO-switched) MRx baseband output I / Q signal y. bb2 (t)(described further below).

[0064] Return to Figure 7 At 709, the received MRx signal and the reference signal generated at 907 are aligned in time.

[0065] At 710, Tx image correction can be calculated. Four independent equations are needed to solve for the four IQ mismatch coefficients: K T1 &K T2 &K R1 &K R2The following Figure 6 shows an example of a 6-phase MRx before and after LO switching. Consider the following definitions:

[0066] x L (t): Tx complex baseband reference signal

[0067] Tx complex baseband reference image signal,

[0068] y bb (t): MRx complex baseband signal output.

[0069] K T1 &K T2 Tx IQ mismatch coefficient

[0070] K R1 &K R2 MRx IQ mismatch coefficient.

[0071] Tx RF output = MRx RF input is given by the following:

[0072]

[0073] Without phase shift (LO switching), the obtained MRx output is (assuming unity gain MRx without loss of generality):

[0074]

[0075] Furthermore, with a 120° phase shift (LO exchange), the resulting MRx output is:

[0076]

[0077] Note that y bb1 (t) and y bb2 The difference between the above equations for (t) is the term and item and Specifically, it comes from the 120Deg LO phase swap.

[0078] The received complex baseband signal ybb(t) and the Tx reference signal x are compared. L (t) After time alignment, the following four complex correlations can be performed:

[0079] Without LO swapping:

[0080]

[0081]

[0082] In the case of LO swapping:

[0083]

[0084]

[0085] The above four equations can be used to solve for the four unknowns K. T1 K R1 K T2 K R2 , Furthermore, Tx and MRx I / Q image corrections are calculated based on the following:

[0086]

[0087]

[0088] Therefore, with LO exchange, the Tx and MRx I / Q images can be separated for estimation and correction. At 711, correction can be applied to the Tx image, as per [reference to...]. Figure 2 The subject of discussion.

[0089] Figure 9 An embodiment of an N-phase LO generator is shown, which may include an LO generation circuit (replacing PLL 109 and LO phase switching circuit 290). Figure 9 In this circuit, N = 6. The 6-phase generator 900 consists of: six D-type latches 920, 922, 924, 926, 928, 930, a NAND 914, and an inverter 916 forming a non-50% duty cycle divide-3 circuit; and six 2-input NAND gates 932, 934, 936, 942, 944, 946 (each with a corresponding inverter 952, 954, 956, 962, 964, 966 coupled to it), which combine the latch outputs from the divide-3 circuit with the divide-3 clock signal 919 to create six non-overlapping signals φ1 to φ6, each with a 16.66% duty cycle. Figure 9In this implementation, the output Qb of each latch 920, 922, 924, 926, 928, 930 forms one input to each NAND gate 932, 934, 936, 942, 944, 946, with the clock signal 919 forming the other input. (For clarity, the connections between each of the Qb outputs of each of the latches 920, 922, 924, 926, 928, 930 are not shown, but it should be understood that each latch's marked output is an input to one of the NAND gates 932, 934, 936, 942, 944, 946. For example, the Qb1 output from latch 928 is an input to NAND 932.) A significant advantage of this implementation is that the six D-type latches do not introduce any phase noise to the six non-overlapping outputs because all output edge transitions are created solely by the input clock edge transitions. Therefore, all six D-type latch devices can be significantly reduced in size and power consumption can be significantly reduced.

[0090] Figure 10 A second embodiment of the N-phase generator is shown. (Compared to...) Figure 9 The same components Figure 10 The components in the array have the same numbering. For ease of TX / MRX image calibration, the LO signals labeled Φ1, Φ2, Φ3, Φ4, Φ5, and Φ6 must be phase-shifted by 120° while preserving the properties of each LO phase (e.g., duty cycle error). Since the properties of each LO phase are determined by the quality of the divided-3 clock signal, this can be achieved by rearranging the latch outputs Q connected to each of the six NAND gates. b1 To Q b6 To achieve a 120° phase shift.

[0091] exist Figure 10 In this configuration, multiplexers (MUX) 1052, 1054, 1056, 1062, 1064, and 1066 are respectively configured to one input of each NAND gate 932, 934, 936, 942, 944, and 946. Each MUX can be selected between two inputs (from the Qb output of the D-type latch) of the NAND gates 932, 934, 936, 942, 944, and 946. Each MUX input can be selected by... Figure 10 The selection bit, marked SEL, controls each 2-to-1 MUX to select normal (non-phase-shifted) operation or 120° phase-shifted operation. Each multiplexer can be implemented using only two n-channel switches, one n-channel switch per path.

[0092] exist Figure 11 The middle shows Figure 9 The standard 2-input NAND gate implementation of a 6-phase generator. Figure 11 It shows what is suitable for use Figure 9 The second implementation uses three dual-input NAND gates. The first NAND gate includes a shared NMOS transistor 1130, and PMOS transistors 1110, 1112, and NMOS 1122, with "a" and "clk" as inputs at the gates of transistors 1110, 1112, and NMOS 1122. The second NAND gate includes a shared NMOS transistor 1130, and PMOS transistors 1114, 1116, and NMOS 1124, with "b" and "clk" as inputs at the gates of transistors 1114, 1116, and 1124. The third NAND gate includes a shared NMOS transistor 1130, and PMOS transistors 1118, 1120, and 1126, with "c" and "clk" as inputs at the gates of transistors 1118, 1120, and 1126. The second implementation uses a combination of multiplexer / NAND circuitry.

[0093] In another implementation, a NAND gate with an embedded select bit can be used instead of... Figure 10 Each NAND gate input in the array provides a MUX. Figure 12 The diagram shows modifications made to embed a multiplexer within it. Figure 11 Three 2-input NAND gates. Figure 9 The same components Figure 10 The components in the MUX have the same numbering. Each NAND can be selected between two inputs. The MUX is implemented by a series of NMOS transistors 1210, 1212, 1214, 1216, 1218, and 1220, each with a SEL signal coupled to its respective gate and Signals. For example, including PMOS 1110 and NMOS transistors 1122, 1124, and a common NMOS 1130, the first NAND signal can be based on the signal applied to transistors 1210 and 1212. The signal is selected between inputs "a" and "b".

[0094] The techniques described herein can be implemented using hardware, firmware, software, or a combination thereof. The software or firmware used can be stored on one or more processor-readable storage devices for... Figure 2The components in one or more boxes are programmed to perform the functions described herein. Processor-readable storage devices may include computer-readable media, such as volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, computer-readable media may include computer-readable storage media and communication media. Computer-readable storage media may be implemented in any method or technique for storing information, such as computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include RAM, ROM, EEPROM, flash memory or other storage technologies, CD-ROM, digital versatile disk (DVD) or other optical disc storage devices, magnetic tape, magnetic tape, disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by the components described above. One or more computer-readable media do not include propagated, modulated, or transient signals.

[0095] Communication media typically embody computer-readable instructions, data structures, program modules, or other data in propagated, modulated, or transient data signals, such as carrier waves or other transmission mechanisms, and include any information transmission medium. The term "modulated data signal" refers to a signal whose characteristics are set or altered, for example, by encoding information in the signal. By way of example and not limitation, communication media include wired media such as wired networks or direct-line connections, and wireless media such as RF and other wireless media. Any combination of the foregoing is also included within the scope of computer-readable media.

[0096] In alternative implementations, some or all of the software or firmware may be replaced by dedicated hardware logic components. For example, but not limited to, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), dedicated computers, etc. In one implementation, software (stored on a storage device) implementing one or more implementations is used to program one or more processors. One or more processors may communicate with one or more computer-readable media / storage devices, peripheral devices, and / or communication interfaces.

[0097] It should be understood that this subject matter can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete, and will fully convey the contents of this disclosure to those skilled in the art. In fact, this subject matter is intended to cover alternatives, modifications, and equivalents to these embodiments, which are included within the scope and spirit of this subject matter as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of this subject matter in order to provide a thorough understanding of it. However, it will be apparent to those skilled in the art that this subject matter can be practiced without these specific details.

[0098] Aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via a processor of a computer or other programmable instruction execution apparatus, create mechanisms for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0099] This disclosure is presented for illustrative and descriptive purposes, but it is not intended to be exhaustive or limited to the form presented herein. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. Various aspects of this disclosure have been selected and described herein in order to best explain its principles and practical applications, and to enable those skilled in the art to understand it with various modifications suited to the intended particular purpose.

[0100] For the purposes of this document, each process associated with the disclosed technology can be performed sequentially and by one or more computing devices. Each step in the process can be performed by the same or different computing devices used in other steps, and each step need not be performed by a single computing device.

[0101] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as examples of implementing the claims.

Claims

1. An apparatus comprising: a local oscillator generation circuit; an N-phase receiver circuit configured to receive an RF signal and generate N in-phase / quadrature signals and phase-shifted N in-phase / quadrature signals from the RF signal, the phase-shift based on a phase-shifted local oscillator signal, where N is an integer equal to 3 or greater than 4; and an I / Q mismatch correction circuit configured to generate transmitter correction coefficients from a calculated mismatch using the phase-shift and the N in-phase / quadrature signals.

2. The apparatus of claim 1, wherein, the apparatus includes an N-phase local oscillator swapping circuit configured to generate the phase-shifted local oscillator signal from N-phase local oscillator signals generated by the local oscillator generation circuit as the N-phase local oscillator signals under the phase-shift.

3. The apparatus of claim 2, wherein, N is 6 and the N-phase local oscillator swapping circuit includes a plurality of latches configured as non-50% duty cycle divide-by-3 circuits, each latch having an output coupled to a first input of a logic gate, each logic gate having a divide-by-3 clock signal as a second input, an output of each logic gate creating one of N non-overlapping signals.

4. The apparatus of claim 3, wherein, the N-phase local oscillator swapping circuit includes at least one multiplexer associated with each logic gate, each multiplexer adapted to select between a first output from the plurality of latches outputting a local oscillator signal and a second output from the plurality of latches generating a known phase-shifted local oscillator signal and a known phase-shifted one of the N non-overlapping signals.

5. The apparatus of claim 4, wherein, each logic gate is configured to select between inputs including the first output from the plurality of latches and the second output from the plurality of latches, the selection creating a known phase-shifted one of the N non-overlapping signals.

6. The apparatus of any one of claims 1 to 5, wherein, the I / Q mismatch correction circuit is further configured to time align the in-phase / quadrature signals and phase-shifted in-phase / quadrature signals.

7. The apparatus of any one of claims 1 to 5, wherein, the apparatus further includes a transmit stage and the apparatus is further configured to apply the correction coefficients to the transmit stage.

8. A method of correcting for in-phase / quadrature mismatch comprising: receiving an RF signal having in-phase and quadrature components; generating a first N-phase baseband reference signal from the in-phase / quadrature components of the received RF signal, where N is an integer equal to 3 or greater than 4; generating a second N-phase baseband signal from the received in-phase / quadrature components, the second N-phase baseband signal having a known phase-shift, the known phase-shift created by altering an output phase of a local oscillator signal; and generating transmitter correction coefficients based on the known phase-shift and the first N-phase baseband reference signal.

9. The method of claim 8, further comprising generating the known phase-shift by swapping the output phase of a local oscillator signal in an oscillator swapping circuit.

10. The method of claim 9, wherein, N is 6, and wherein the local oscillator switching circuit comprises a plurality of latches configured as non-50% duty cycle divide-by-3 circuits, each latch having an output coupled to a first input of a logic gate, each logic gate having a divide-by-3 clock signal as a second input, an output of each logic gate creating one of N non-overlapping signals, the method comprising selecting the known phase shift by selecting one of the logic gate inputs from the plurality of latches.

11. The method of claim 10, wherein, The method further comprises selecting a plurality of the inputs into the logic gate inputs by enabling a select bit in a plurality of multiplexers, one of the plurality of multiplexers being associated with each logic gate, the selection creating the known phase shift in the N non-overlapping signals.

12. The method of claim 11, wherein, The method further comprises selecting a plurality of the inputs into the logic gate inputs by enabling a select bit in each logic gate, the selection creating the known phase shift in the N non-overlapping signals.

13. The method of any of claims 8 to 12, further comprising aligning in time the in-phase / quadrature signal and the phase-shifted in-phase / quadrature signal prior to the generating the transmitter correction coefficients.

14. The method of any of claims 8 to 12, further comprising applying the correction coefficients to a transmit stage.

15. A wireless communication system comprising: a transmit circuit configured to generate a first communication signal; a local oscillator generation circuit; an N-phase receiver circuit configured to receive a second communication signal and generate an in-phase / quadrature signal and a phase-shifted in-phase / quadrature signal from the second communication signal, the phase-shifted in-phase / quadrature signal having a known phase shift, wherein N is an integer equal to 3 or greater than 4; and an I / Q mismatch correction circuit configured to generate transmitter correction coefficients based on the known phase shift and the N in-phase / quadrature signal, and further configured to apply the correction coefficients to a transmit stage.

16. The system of claim 15, wherein, The local oscillator generation circuit comprises an N-phase local oscillator switching circuit configured to output an N-phase local oscillator signal at the known phase shift based on a local oscillator signal from the local oscillator generation circuit.

17. The system of claim 16, wherein, N is 6, and the N-phase local oscillator switching circuit comprises a plurality of latches configured as non-50% duty cycle divide-by-3 circuits, each latch having an output coupled to a first input of a NAND gate, each NAND gate having a divide-by-3 clock signal as a second input, an output of each NAND gate creating one of N non-overlapping signals.

18. The system of claim 17, wherein, The N-phase local oscillator switching circuit comprises at least one multiplexer associated with each NAND gate, each multiplexer adapted to select between inputs comprising a first output from the plurality of latches and a second output from the plurality of latches, the selection creating the known phase shift in the N non-overlapping signals.

19. The system of claim 18, wherein, Each NAND gate is configured to select between inputs comprising a first output from the plurality of latches and a second output from the plurality of latches, the selection creating the known phase shift in the N non-overlapping signals.

20. The system of any one of claims 15 to 18, wherein, The I / Q mismatch correction circuit is further configured to time align the in-phase / quadrature signal and the phase-shifted in-phase / quadrature signal.

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