Array substrate and manufacturing method and driving method thereof, display substrate, and display device

Abstract

The present application provides an array substrate and a manufacturing method and a driving method thereof, a display substrate, and a display device. The array substrate includes a substrate and a plurality of gate lines, a plurality of data lines, a first passivation layer, a pixel electrode layer, a second passivation layer, and a common electrode layer sequentially located on one side of the substrate; wherein the common electrode layer includes a plurality of common electrode blocks spaced along a first direction, and the common electrode blocks include a first common electrode block corresponding to the position of the pixel electrode layer, and a second common electrode block corresponding to the position of the data line; in the first direction, the width of each data line is greater than or equal to twice the width of each second common electrode block, and less than or equal to three times the width of each second common electrode block. By reducing the width of the data line, the light shielding of the data line is reduced, the light transmittance of the array substrate is improved, and the brightness of the display panel is increased without additionally increasing the manufacturing cost.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to an array substrate and a manufacturing method and a driving method thereof, a display substrate, and a display device. Background Art

[0002] Liquid crystal display panels have the advantages of low power consumption and soft images, and are widely used in display devices such as televisions, tablet computers, and mobile phones. In order to ensure the display quality, the brightness of the liquid crystal display panel needs to meet certain requirements. In order to improve the brightness of the liquid crystal display panel, the display panel in the prior art usually uses a high-brightness backlight film material, which has a high production cost. Summary of the invention

[0003] In view of the shortcomings of the existing methods, the present application proposes an array substrate and a manufacturing method and a driving method thereof, a display substrate, and a display device, so as to solve the problem of high manufacturing cost caused by increasing the brightness of the liquid crystal display panel in the prior art.

[0004] In a first aspect, an embodiment of the present application provides an array substrate, including:

[0005] substrate;

[0006] On one side perpendicular to the substrate, a plurality of gate lines, a gate insulating layer, a plurality of data lines, a first passivation layer, a pixel electrode layer, a second passivation layer and a common electrode layer are sequentially arranged, the plurality of data lines are arranged in parallel along a first direction, the plurality of gate lines are arranged in parallel along a second direction, and the first direction and the second direction intersect each other;

[0007] In which, the common electrode layer includes a plurality of common electrode blocks arranged at intervals along the first direction, and the common electrode blocks include a first common electrode block corresponding to the position of the pixel electrode layer, and a second common electrode block corresponding to the position of the data line. In the first direction, the width of each of the data lines is greater than or equal to twice the width of each of the second common electrode blocks, and the width of each of the data lines is less than or equal to three times the width of each of the second common electrode blocks.

[0008] Optionally, in the first direction, the width of each of the second common electrode blocks is less than or equal to 7.4 micrometers, and the width of each of the data lines is less than or equal to 2.8 micrometers.

[0009] Optionally, in the first direction, the width of each gate line is less than or equal to 3 micrometers.

[0010] Optionally, the array substrate also includes a plurality of touch electrode lines arranged in parallel along a first direction, the touch electrode lines and the data lines are arranged in the same layer, and in the first direction, the minimum spacing between the adjacent touch electrode lines and the data lines is greater than or equal to 2 microns and less than or equal to 3.3 microns.

[0011] In a second aspect, an embodiment of the present application provides a display substrate, including:

[0012] An array substrate, wherein the array substrate is the array substrate provided in an embodiment of the present application;

[0013] The opposite substrate is arranged opposite to the array substrate, and includes a black matrix arranged on a side close to the array substrate. The orthographic projections of the data lines, the gate lines and the touch electrode lines on the substrate overlap with the orthographic projections of the black matrix on the substrate.

[0014] Optionally, the black matrix includes a first black matrix, the position of the first black matrix corresponds to the position of the data line, in the first direction, the width of the first black matrix is ​​less than or equal to 5.5 microns, and the distance between the edge of the first black matrix and the edge of the data line is less than or equal to 1.35 microns.

[0015] Optionally, the black matrix includes a second black matrix, the position of the second black matrix corresponds to the position of the gate line, in the second direction, the width of the second black matrix is ​​less than or equal to 17.8 microns, and the distance between the edge of the second black matrix and the edge of the gate line is less than or equal to 7.4 microns.

[0016] Optionally, the black matrix includes a third black matrix, the position of the third black matrix corresponds to the position of two adjacent data lines and the touch electrode lines, in the first direction, the width of the third black matrix is ​​less than or equal to 11.3 microns, in the first direction, the spacing between the edge of the third black matrix and the edge of the data line is less than or equal to 0.6 microns; and / or, in the first direction, the spacing between the edge of the third black matrix and the edge of the touch electrode line is less than or equal to 0.6 microns.

[0017] In a third aspect, an embodiment of the present application provides a display device, including the display substrate provided by an embodiment of the present application.

[0018] In a fourth aspect, an embodiment of the present application provides a driving method of an array substrate, wherein the array substrate is the array substrate provided in the embodiment of the present application, and the array substrate includes a gate driving circuit electrically connected to the gate line, and a source driving circuit electrically connected to the data line, and the driving method includes:

[0019] The gate line receives a scan signal output by the gate driving circuit, the scan signal is a signal output by a clock signal, and the duty cycle of the clock signal is greater than or equal to 46% and less than or equal to 49%;

[0020] The data line receives a data signal output by the source driving circuit.

[0021] Optionally, the duty cycle of the clock signal is 48.7%.

[0022] In a fifth aspect, an embodiment of the present application provides a method for manufacturing an array substrate, comprising:

[0023] providing a substrate;

[0024] A plurality of gate lines, a gate insulating layer, a plurality of data lines, a first passivation layer, a pixel electrode layer, a second passivation layer and a common electrode layer are sequentially formed on a side perpendicular to the substrate, the plurality of data lines are arranged in parallel along a first direction, the plurality of gate lines are arranged in parallel along a second direction, and the first direction and the second direction intersect;

[0025] In which, the common electrode layer includes a plurality of common electrode blocks arranged at intervals along the first direction, and the common electrode blocks include a first common electrode block corresponding to the position of the pixel electrode layer, and a second common electrode block corresponding to the position of the data line. In the first direction, the width of each of the data lines is greater than or equal to twice the width of each of the second common electrode blocks, and the width of each of the data lines is less than or equal to three times the width of each of the second common electrode blocks.

[0026] Optionally, the step of sequentially manufacturing a plurality of gate lines, a gate insulating layer, a plurality of data lines, a first passivation layer, a pixel electrode layer, a second passivation layer and a common electrode layer on one side of the substrate includes:

[0027] Sequentially forming a plurality of gate lines and gate insulating layers on one side of the substrate;

[0028] A plurality of data lines and a plurality of touch electrode lines are manufactured on a side of the gate line away from the substrate, the plurality of touch electrode lines are arranged in parallel along the first direction, and in the first direction, a minimum spacing between adjacent touch electrode lines and data lines is greater than or equal to 2 microns and less than or equal to 3.3 microns.

[0029] Optionally, the step of manufacturing a plurality of data lines and a plurality of touch electrode lines on a side of the gate line away from the substrate includes:

[0030] Depositing a metal layer on a side of the gate line away from the substrate;

[0031] The metal layer is patterned to form a plurality of the data lines and a plurality of the touch electrode lines.

[0032] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0033] The array substrate in the embodiment of the present application includes a substrate and a plurality of gate lines, a plurality of data lines, a first passivation layer, a pixel electrode layer, a second passivation layer and a common electrode layer sequentially arranged on one side of the substrate, the plurality of data lines are arranged in parallel along a first direction, the plurality of gate lines are arranged in parallel along a second direction, and the first direction and the second direction intersect; wherein the common electrode layer includes a plurality of common electrode blocks arranged at intervals along the first direction, the common electrode blocks include a first common electrode block corresponding to the position of the pixel electrode layer, and a second common electrode block corresponding to the position of the data line, in the first direction, the width of each data line is greater than or equal to twice the width of each second common electrode block, and the width of each data line is less than or equal to three times the width of each second common electrode block. By reducing the width of the data line, the light shielding of the data line is reduced, the light transmittance of the array substrate is improved, and the brightness of the display panel is increased without additionally increasing the manufacturing cost.

[0034] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0036] Figure 1 A partial top view of the structure of a display substrate provided in an embodiment of the present application;

[0037] Figure 2 for Figure 1 Schematic diagram of the structure at the middle section A;

[0038] Figure 3 for Figure 1 Schematic diagram of the structure at the middle section B;

[0039] Figure 4 for Figure 1 Schematic diagram of the structure at the middle section C;

[0040] Figure 5 Schematic diagram of the waveform of the scanning signal output by the gate driving circuit in the embodiment of the present application;

[0041] Figure 6 A schematic diagram of the manufacturing process of the array substrate provided in the embodiment of the present application;

[0042] Figure 7a to Figure 7h A schematic diagram of the structures of different processes for manufacturing an array substrate provided in an embodiment of the present application.

[0043] In the figure:

[0044] 1-display substrate; 10-array substrate; 101-substrate; 102-gate line; 103-data line; 104-first passivation layer;

[0045] 105 - pixel electrode layer; 106 - second passivation layer; 107 - common electrode layer; 1070 - common electrode block; 1071 - first common electrode block; 1072 - second common electrode block; 108 - touch electrode line; 109 - gate insulating layer; 100 - thin film transistor;

[0046] 20 - opposite substrate; 201 - base; 202 - black matrix; 202a - first black matrix; 202b - second black matrix; 202c - third black matrix. DETAILED DESCRIPTION

[0047] The present application is described in detail below, and examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. In addition, if the detailed description of the known technology is unnecessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0048] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with those in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0049] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0050] The inventors of the present application have considered that in order to improve display quality and visual effects, the prior art generally adopts a method of providing a high-brightness backlight film material to increase the brightness of a liquid crystal display panel, but this will bring about the problem of high production costs.

[0051] The array substrate and its manufacturing method and driving method, display substrate, and display device provided in the present application are intended to solve the above technical problems in the prior art.

[0052] The array substrate and its manufacturing method and driving method, display substrate, and display device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0053] Combination Figure 1 , Figure 2 , Figure 3 and Figure 4 The embodiment of the present application provides an array substrate 10, including:

[0054] Substrate 101;

[0055] On one side of the vertical substrate 101, a plurality of gate lines 102, a gate insulating layer 109, a plurality of data lines 103, a first passivation layer 104, a pixel electrode layer 105, a second passivation layer 106 and a common electrode layer 107 are sequentially arranged, the plurality of data lines 103 are arranged in parallel along a first direction, the plurality of gate lines 102 are arranged in parallel along a second direction, and the first direction and the second direction intersect;

[0056] Among them, the common electrode layer 107 includes a plurality of common electrode blocks spaced apart along a first direction, the common electrode blocks 1071 include a first common electrode block 1071 corresponding to the position of the pixel electrode layer 105, and a second common electrode block 1072 corresponding to the position of the data line 103. In the first direction, the width of each data line 103 is greater than or equal to twice the width of each second common electrode block 1072, and the width of each data line 103 is less than or equal to three times the width of each second common electrode block 1072.

[0057] Specific, combined Figures 1 to 4 , the array substrate 10 includes a thin film transistor, a first passivation layer 104, a pixel electrode layer 105, a second passivation layer 106 and a common electrode layer 107 which are stacked in sequence, and the thin film transistor 100 includes a gate layer and a source-drain electrode layer, and the thin film transistors are distributed in an array. The backlight module (not shown in the figure) provides backlight for the array substrate 10, and the light emitted by it passes through the array substrate 10 to realize the display function. The common electrode layer 107 is patterned to form a plurality of first common electrode blocks 1071 and second common electrode blocks 1072 which are spaced apart in a first direction, wherein the position of the first common electrode block 1071 corresponds to the position of the pixel electrode layer 105, that is, the orthographic projection of the first common electrode block 1071 on the substrate 101 overlaps with the orthographic projection of the pixel electrode layer 105 on the substrate 101; the position of the second common electrode block 1072 corresponds to the position of the data line 103, that is, the orthographic projection of the second common electrode block 1072 on the substrate 101 overlaps with the orthographic projection of the data line 103 on the substrate.

[0058] The array substrate 10 further includes a data line 103 and a gate line 102 which are arranged crosswise, the data line 103 being arranged along a first direction, and the gate line 102 being arranged along a second direction. The gate line 102 is arranged in the same layer as the gate layer of the thin film transistor 100 and is electrically connected thereto, and the gate line 102 being arranged in the same layer as the gate layer means that the gate line 102 and the gate layer can be formed by a single patterning process during the manufacturing process of the array substrate 10; the data line 103 is arranged in the same layer as the source and drain electrode layer of the thin film transistor 100 and is electrically connected thereto, and the data line 103 is arranged in the same layer as the source and drain electrode layer means that the data line 103 and the source and drain electrode layer can be formed by a single patterning process during the manufacturing process of the array substrate 10. The pixel electrode layer 105 is electrically connected to the data line 103. The materials of the pixel electrode and the common electrode layer 107 include materials with good light transmittance and conductivity such as indium tin oxide (ITO). The materials of the gate layer, the gate line 102, the source and drain layer and the data line 103 include metals with good conductivity such as aluminum or copper.

[0059] In the embodiment of the present application, by making the width of each data line 103 in the first direction less than or equal to three times the width of each second common electrode block 1072, the width of each data line 103 in the first direction is reduced, thereby reducing the shielding of the light of the backlight module by the data line 103, improving the transmittance of the array substrate 10, and facilitating the increase of the brightness of the display panel, and only the line width needs to be changed, without additionally increasing the manufacturing cost. At the same time, by making the width of each data line 103 in the first direction greater than or equal to twice the width of each second common electrode block 1072, it is also avoided that when the width of the data line 103 is too small, the resistance of the data line 103 is large, affecting the signal transmission and display quality.

[0060] Optionally, in the embodiments of the present application, Figure 2 As shown, in the first direction, the width W11 of the first common electrode block 1071 is 2.3 microns, and the width W12 of the second electrode block is 7.4 microns, while in the conventional design, the width of the first electrode block is 2.5 microns, and the width of the second electrode block is 9.1 microns. In the embodiment of the present application, the distance D11 between the first common electrode block 1071 and the second common electrode block 1072 is 3.8 microns, and in the conventional design, the distance between the first common electrode block 1071 and the second common electrode block 1072 is usually 4.35 microns. In the embodiment of the present application, the distance D12 between two adjacent second common electrode blocks 1072 is 3.75 microns, while in the conventional design, the distance between two adjacent second common electrode blocks 1072 is 4.3 microns, thereby reducing the width of the first common electrode block 1071 and the second common electrode block 1072 in the first direction, and correspondingly, the width of the data line 103 can also be reduced.

[0061] Optionally, in the embodiments of the present application, Figure 2 As shown, the width W1 of the data line 103 is less than or equal to 2.8 microns, while in conventional designs, the width of the data line 103 in the first direction is usually 3 microns; the width W2 of the gate line 102 in the second direction is less than or equal to 3 microns, while in conventional designs, the width of the gate line 102 in the second direction is usually 3.5 microns. Since the data line 103 and the gate line 102 are usually made of metal materials, which have a shielding effect on light, by reducing the width of the gate line 102 and the data line 103, the shielding of the light of the backlight module by the gate line 102 and the data line 103 can be reduced, thereby improving the light transmittance of the array substrate 10. It should be noted that the width W11 of the second electrode block and the width W1 of the data line 103 can be adjusted and determined according to actual conditions, and are not limited here.

[0062] In addition, the embodiment of the present application increases the distance between the data line 103 and the common electrode layer 107 by disposing the first passivation layer 104 and the second passivation layer 106 between the data line 103 and the common electrode layer 107, reduces the coupling capacitance between the data line 103 and the common electrode layer 107, and helps to reduce the impact on the display quality caused by the large coupling capacitance. The material of the first passivation layer 104 and the second passivation layer 106 includes a material with good insulation properties such as silicon oxide.

[0063] It should be noted that the smaller the width of the data line 103 and the gate line 102, the less light is blocked, which is conducive to improving the brightness of the display panel. However, if the width of the data line 103 and the gate line 102 is too small, the resistance of the data line 103 and the gate line 102 will increase, and the delay will increase during signal transmission, which will affect the display quality. The width of the data line 103 and the gate line 102 can be determined according to actual conditions. Optionally, the width W1 of the data line 103 is 2.8 microns, and the width W2 of the gate line 102 is 3 microns.

[0064] In the embodiments of the present application, Figure 1 and Figure 4 As shown, the array substrate 10 also includes a plurality of touch electrode lines 108 arranged in parallel along a first direction. The touch electrode lines 108 and the data lines 103 are arranged in the same layer. In the first direction, the minimum spacing between adjacent touch electrode lines 108 and data lines 103 is greater than or equal to 2 microns and less than or equal to 3.3 microns.

[0065] Specifically, the array substrate 10 also includes a plurality of touch sensing blocks (not shown in the figure), which are used to detect the position of the finger according to the change of capacitance, thereby realizing the touch sensing function. The touch electrode line 108 corresponds to the plurality of touch sensing blocks one by one and is electrically connected to realize the transmission of the touch signal. The touch electrode line 108 is usually made of a metal material with good electrical conductivity, so it has a shielding effect on light. The width of the touch electrode line 108 in the first direction in the prior art is usually 6.6 microns. In the embodiment of the present application, the width W3 of the touch electrode line 108 can be made less than or equal to 4 microns, thereby reducing the shielding of the backlight by the touch electrode line 108, improving the transmittance of the array substrate 10, and being conducive to improving the brightness of the display panel, and the narrowing of the touch electrode line 108 will not increase the manufacturing cost.

[0066] It should be noted that the smaller the width W3 of the touch electrode line 108 is, the less light is blocked, but the resistance of the touch electrode line 108 will increase, which is not conducive to the transmission of the touch signal and has a certain impact on the touch performance. Optionally, the width of the touch electrode line 108 in the first direction is greater than or equal to 2.5 microns to avoid affecting the touch performance when the width is too small.

[0067] The specific position of the touch electrode line 108 in the array substrate 10 can be determined according to actual conditions. Optionally, in the embodiment of the present application, Figure 4 As shown, the touch electrode lines 108 and the data lines 103 are arranged in the same layer, that is, during the manufacturing process of the array substrate 10, the touch electrode lines 108 and the data lines 103 can be formed by one patterning process, thereby simplifying the manufacturing process of the array substrate 10 and reducing the manufacturing cost.

[0068] Optionally, in the embodiments of the present application, Figure 1 and Figure 4 In the first direction, the minimum spacing between adjacent touch electrode lines 108 and data lines 103 is less than or equal to 3.3 micrometers. Figure 1 As shown, the touch electrode lines 108 are arranged at intervals. Figure 1 The data lines 103 are arranged beside the touch electrode lines 108 on the left and the right in the figure. For the touch electrode lines 108 on the right, data lines 103 are arranged on the left and right sides thereof. The distance between the touch electrode lines 108 and the data lines 103 on the left is larger, and the distance between the touch electrode lines 108 and the data lines 103 on the right is smaller. The minimum distance between the touch electrode lines 108 and the data lines 103 refers to the distance between the touch electrode lines 108 and the data lines 103 on the right. Figure 1 As shown in the figure, for the touch electrode line 108 on the left, the minimum spacing between the touch electrode line 108 and the data line 103 refers to the distance D1 between the touch electrode line 108 and the data line 103 on the right thereof. By making the minimum spacing between the touch electrode line 108 and the data line 103 less than or equal to 3.3 microns, the touch electrode line 108 and the data line 103 are more compact, which can reduce the occupation of the effective display area by the touch electrode line 108, thereby reducing the shielding of the backlight by the touch electrode line 108, which is beneficial to improve the brightness of the display panel.

[0069] Based on the same inventive concept, the embodiment of the present application further provides a display substrate 1. Figure 2 , Figure 3 and Figure 4 As shown, the display substrate 1 includes an array substrate 10 and an opposing substrate 20. The array substrate 10 includes the above-mentioned array substrate 10 in the embodiment of the present application. The opposing substrate 20 can be a color filter substrate with a color filter layer or a substrate without a color filter layer.

[0070] Specifically, the counter substrate 20 is arranged opposite to the array substrate 10, and liquid crystal molecules (not shown in the figure) are arranged between the counter substrate 20 and the array substrate 10. The counter substrate 20 includes a black matrix 202 arranged on a side close to the array substrate 10, and the orthographic projections of the data lines 103, the gate lines 102, and the touch electrode lines 108 on the substrate 101 overlap with the orthographic projections of the black matrix 202 on the substrate 101. Since the display substrate 1 includes the above-mentioned array substrate 10 provided in the embodiment of the present application, the display substrate 1 has the same beneficial effects as the array substrate 10, which will not be repeated here.

[0071] When the counter substrate 20 is a color film substrate, it usually includes a substrate 201 and a color resist layer (including red, green and blue resist, not shown in the figure) and a black matrix 202 arranged on the substrate 201. The position of the black matrix 202 corresponds to the position of the data line 103, the gate line 102 and the touch electrode line 108, so as to shield the metal line and prevent the external ambient light from being reflected to the human eye after being irradiated to the metal line and affecting the display quality. The area of ​​the black matrix 202 can be determined according to the actual situation. It can be understood that the larger the area of ​​the black matrix 202, the better the effect of preventing the reflection of the ambient light, but it will also increase the shielding of the backlight and affect the brightness of the display panel.

[0072] like Figure 2 As shown, in the embodiment of the present application, the black matrix 202 includes a first black matrix 202a, and the position of the first black matrix 202a corresponds to the position of the data line 103 to achieve shielding of the data line 103. In the first direction, the width W4 of the first black matrix 202a is less than or equal to 5.5 microns, and the distance D2 between the edge of the first black matrix 202a and the edge of the data line 103 is less than or equal to 1.35 microns. It should be noted that, as Figure 2 As shown, the first black matrix 202a includes a left edge and a right edge, the data line 103 includes a left edge and a right edge, and the spacing D2 is less than or equal to 1.35 microns, which means that the spacing between the left edge of the first black matrix 202a and the left edge of the data line 103 is less than or equal to 1.35 microns, or, the spacing between the right edge of the first black matrix 202a and the right edge of the data line 103 is less than or equal to 1.35 microns.

[0073] In the prior art, in the first direction, the width of the first black matrix 202a is usually about 6 microns, and the distance between the edge of the first black matrix 202a and the edge of the data line 103 is usually about 1.5 microns. By reducing the width W4 of the first black matrix 202a and reducing the distance D2 between the edge of the first black matrix 202a and the edge of the data line 103, the area of ​​the first black matrix 202a can be reduced to reduce the shielding of the first black matrix 202a for light and improve the brightness of the display substrate 1. It should be noted that the width W4 and position of the first black matrix 202a can be adjusted according to the width W1 of the data line 103, and are not specifically limited here.

[0074] In the embodiments of the present application, Figure 3 As shown, the black matrix 202 includes a second black matrix 202b, and the position of the second black matrix 202b corresponds to the position of the gate line 102 to achieve shielding of the gate line 102. In the second direction, the width W5 of the second black matrix 202b is less than or equal to 17.8 microns, and the distance D3 between the edge of the second black matrix 202b and the edge of the gate line 102 is less than or equal to 7.4 microns. It should be noted that, as Figure 3 As shown, the second black matrix 202b includes a left edge and a right edge, the gate line 102 includes a left edge and a right edge, and the spacing D3 is less than or equal to 7.4 microns, which means that the spacing between the left edge of the second black matrix 202b and the left edge of the gate line 102 is less than or equal to 7.4 microns, or, the spacing between the right edge of the second black matrix 202b and the right edge of the gate line 102 is less than or equal to 7.4 microns.

[0075] In the prior art, in the second direction, the width of the second black matrix is ​​usually about 25.5 microns, and the spacing between the edge of the first black matrix 202a and the edge of the gate line 102 is usually about 11 microns. By reducing the width W5 of the second black matrix 202b and reducing the spacing D3 between the edge of the second black matrix 202b and the edge of the gate line 102, the area of ​​the second black matrix 202b can be reduced to reduce the shielding of the second black matrix 202b for light. It should be noted that the width W5 and position of the second black matrix 202b can be adjusted according to the width W2 of the gate line 102, and are not specifically limited here.

[0076] In the embodiments of the present application, Figure 4As shown, the black matrix 202 includes a third black matrix 202c, and the position of the third black matrix 202c corresponds to the position of two adjacent data lines 103 and touch electrode lines 108, so as to achieve shielding of the data lines 103 and the touch electrode lines 108. In the first direction, the width W6 of the third black matrix 202c is less than or equal to 11.3 microns, and in the first direction, the spacing D5 between the edge of the third black matrix 202c and the edge of the data line 103 is less than or equal to 0.6 microns; and / or, in the first direction, the spacing D4 between the edge of the third black matrix 202c and the edge of the touch electrode line 108 is less than or equal to 0.6 microns. It should be noted that the third black matrix 202c includes different edges, and the distances between different edges and the touch electrode lines 108 may be different. The spacing D4 is less than or equal to 0.6 microns, which means that the minimum spacing between the edge of the third black matrix 202c and the edge of the touch electrode line 108 is less than or equal to 0.6 microns.

[0077] In the prior art, in the first direction, the width of the third black matrix is ​​usually about 18.6 microns, and the distance between the edge of the third black matrix 202c and the edge of the touch electrode line 108 is usually about 3 microns. By reducing the width W6 of the third black matrix 202c and reducing the distance D4 between the edge of the third black matrix 202c and the edge of the touch electrode line 108, the area of ​​the third black matrix 202c can be reduced to reduce the shielding of the second black matrix 202b for light. The width W6 and position of the third black matrix 202c can be adjusted according to the width W3 of the touch electrode line 108, and are not specifically limited here.

[0078] Based on the same inventive concept, the embodiment of the present application also provides a display device, which includes the display substrate 1 provided in the embodiment of the present application. Since the display device includes the display substrate 1 provided in the embodiment of the present application, the display device has the same beneficial effects as the display substrate 1, which will not be described in detail here.

[0079] Based on the same inventive concept, the embodiment of the present application further provides a driving method of an array substrate, the array substrate is the array substrate 10 in the embodiment of the present application, the array substrate 10 includes a gate driving circuit (not shown in the figure) electrically connected to the gate line 102, and a source driving circuit (not shown in the figure) electrically connected to the data line 103, the driving method includes:

[0080] The gate line 102 receives a scanning signal output by a gate driving circuit, the scanning signal is a signal output by a clock signal, and the duty cycle of the clock signal is greater than or equal to 46% and less than or equal to 49%;

[0081] The data line 103 receives the data signal output by the source driving circuit.

[0082] Specifically, in the embodiment of the present application, the array substrate 10 includes a gate driving circuit (not shown in the figure) electrically connected to the gate line 102, and a source driving circuit (not shown in the figure) electrically connected to the data line 103. The gate driving circuit outputs a scan signal to the gate line 102 to turn on the thin film transistors row by row; the source driving circuit outputs a data signal to the data line 103. The scan signal is a signal output by a clock signal.

[0083] The inventor of the present application considers that when the width of the data line 103 and the gate line 102 in the array substrate 10 is reduced, the resistance of the metal line will increase, resulting in a larger resistance delay of the array substrate 10. The resistance delay will couple the common voltage on the common electrode, resulting in inconsistent pixel voltages on pixel units in different rows, affecting normal display. Actual tests show that near the border of the display device, the common voltage (Vcom) corresponding to the first few rows of pixel units is pulled up, and compared with the common voltage corresponding to the middle row of pixel units, the common voltage (Vcom) corresponding to the first few rows of pixel units increases. Since the pixel voltage is the difference between the source-drain voltage and the common voltage, the pixel voltage of the first few rows of pixel units decreases, which is manifested as dark lines in the macroscopic sense; compared with the middle row, the common voltage corresponding to the pixel units in the last few rows decreases, so the pixel voltage of the pixel units in the last few rows increases, which is manifested as bright lines in the macroscopic sense. Bright lines and dark lines are horizontal stripes, which are poor display.

[0084] In order to solve the problem of poor horizontal stripe display, the inventor of the present application has made various adjustments. First, the rising edge overlap width (CLK overlap) between clock signals of different rows is adjusted, so that when different frames are displayed, the rising edge overlap width is adjusted from 8H to 1H (H refers to the time when a row of thin film transistors is turned on). The smaller the rising edge overlap width, the finer the horizontal stripe. Therefore, reducing the rising edge overlap width between clock signals of different rows is conducive to improving the poor horizontal stripe display.

[0085] On the other hand, adjust the duty cycle of the clock signal (CLK duty) and observe the situation of horizontal stripes display defects under different duty cycles. Figure 5 As shown in the figure, the duty cycle of the clock signal is the ratio of the high level time of the clock signal to the entire clock signal cycle (the ratio of t1 and t2 in the figure). In the range of 40% to 50%, the duty cycle of the clock signal is gradually increased to observe the display effect under different duty cycles. When the duty cycle is between 46% and 49%, the problem of poor horizontal stripe display is improved.

[0086] The following table shows the display effect under different display screens as the duty cycle changes. In the table, L0.5 to L3 represent the judgment of horizontal stripes, L0.5 means that the horizontal stripes are slight (almost invisible), and L3 means that the horizontal stripes are very obvious. Considering different display screens, when the duty cycle of the clock signal is 48.7%, the improvement of the poor display of horizontal stripes is the best.

[0087] CLK DUTY 22.4％ 23％ 34.4％ 37.5％ 45％ 46.55％ 48％ 48.7％ Flicker value 2.2％ 1.8％ 2.3％ 1.5％ 3％ 2.3％ 1.6％ 1.4％ L48 Grayscale Invisible Invisible Invisible L0.5 L1 Invisible L0.5 L0.5 L64 Grayscale Invisible Invisible Invisible L0.5 L1 Invisible L0.5 L0.5 Gray and black L3 L3 L3 L3 L3 L3 L2 L1.5 Purple Green L3 L3 L3 L3 L3 L3 L3 L3

[0088] Table 1

[0089] In order to improve the problem of poor horizontal stripe display, the inventor of the present application has also made other adjustments, such as externally injecting Vcom voltage, lowering or raising the threshold voltage of the thin film transistor, etc., but the effects are not obvious.

[0090] Based on the same inventive concept, the present application embodiment also provides a method for manufacturing an array substrate 10, such as Figure 6 As shown, including:

[0091] S101, providing a substrate 101;

[0092] S102, a plurality of gate lines 102, a gate insulating layer 109, a plurality of data lines 103, a first passivation layer 104, a pixel electrode layer 105, a second passivation layer 106 and a common electrode layer 107 are sequentially manufactured on one side of the substrate 101, the plurality of data lines 103 are arranged in parallel along a first direction, the plurality of gate lines 102 are arranged in parallel along a second direction, and the first direction and the second direction intersect; wherein the common electrode layer 107 comprises a plurality of common electrode blocks 1070 spaced apart along the first direction, the common electrode blocks 1070 comprise a first common electrode block 1071 corresponding to the position of the pixel electrode layer 105, and a second common electrode block 1072 corresponding to the position of the data line 103, in the first direction, the width of each data line 103 is greater than or equal to twice the width of each second common electrode block 1072, and the width of each data line 103 is less than or equal to three times the width of each second common electrode block 1072.

[0093] In the manufacturing method of the array substrate 10 provided in the embodiment of the present application, by making the width of each data line 103 in the first direction less than or equal to three times the width of each second common electrode block 1072, the width of each data line 103 in the first direction is reduced, thereby reducing the shielding of the light of the backlight module by the data line 103, improving the transmittance of the array substrate 10, and facilitating the increase of the brightness of the display panel, and only needing to change the line width, without additionally increasing the manufacturing cost. At the same time, by making the width of each data line 103 in the first direction greater than or equal to twice the width of each second common electrode block 1072, it is also avoided that the width of the data line 103 is too small, and the resistance of the data line 103 is large, which affects the signal transmission and display quality.

[0094] Specifically, in the embodiment of the present application, a plurality of gate lines 102, a gate insulating layer 109, a plurality of data lines 103, a first passivation layer 104, a pixel electrode layer 105, a second passivation layer 106 and a common electrode layer 107 are sequentially manufactured on one side of a substrate 101, including:

[0095] A plurality of gate lines 102 and a gate insulating layer 109 are sequentially formed on one side of the substrate 101;

[0096] A plurality of data lines 103 and a plurality of touch electrode lines 108 are fabricated on a side of the gate line 102 away from the substrate 101. The plurality of touch electrode lines 108 are arranged in parallel along a first direction. In the first direction, a minimum spacing between adjacent touch electrode lines and data lines is greater than or equal to 2 microns and less than or equal to 3.3 microns.

[0097] In a specific implementation, in the embodiment of the present application, the data line 103 and the touch electrode line 108 are formed on a side of the gate line 102 away from the substrate 101, including:

[0098] Depositing a metal layer on a side of the gate line 102 away from the substrate 101;

[0099] The metal layer is patterned to form the data lines 103 and the touch electrode lines 108 .

[0100] The specific process of manufacturing the array substrate 10 in this specific embodiment is described below in conjunction with the accompanying drawings. The patterning process in the embodiment of the present application includes the coating, exposure, development, etching of photoresist and the removal of part or all of the photoresist.

[0101] like Figure 7a As shown, a substrate 101 is first provided.

[0102] like Figure 7b As shown, next, a gate line 102 and a gate layer of a thin film transistor (not shown in the figure) are manufactured on the substrate 101 by a patterning process, and the gate line 102 and the gate layer are electrically connected.

[0103] like Figure 7c As shown, next, a gate insulating layer 109 is formed on the side of the gate line 102 and the gate layer (not shown in the figure) away from the substrate 101. It should be noted that after the gate insulating layer 109 is formed, other parts of the thin film transistor (not shown in the figure) need to be formed on the side of the gate insulating layer 109 away from the substrate 101, including an active layer, an interlayer dielectric layer, etc. (the specific film layers are not shown in the figure).

[0104] like Figure 7dAs shown, then, the data line 103, the touch electrode line 108 and the source and drain layer of the thin film transistor (not shown in the figure) are formed on the side of the gate insulating layer 109 away from the substrate 101 through a patterning process.

[0105] like Figure 7e As shown, next, a first passivation layer 104 is formed on a side of the gate insulating layer 109 away from the substrate 101, and the first passivation side covers the data line 103 and the touch electrode line 108. The material of the first passivation layer 104 includes a material with good insulation performance such as silicon oxide.

[0106] like Figure 7f As shown, next, a pixel electrode layer 105 is formed on a side of the first passivation layer 104 away from the substrate 101 by a patterning process. The material of the pixel electrode layer 105 includes a material with good light transmittance and conductivity such as indium tin oxide (ITO).

[0107] like Figure 7g As shown, next, a second passivation layer 106 is formed on a side of the first passivation layer 104 away from the substrate 101 , and the second passivation layer 106 covers the pixel electrode layer 105 . The material of the second passivation layer 106 includes a material with good insulation properties such as silicon oxide.

[0108] like Figure 7h As shown, a common electrode layer 107 is then formed on the side of the second passivation layer 106 away from the substrate 101 by patterning to complete the array substrate 10. The common electrode layer 107 includes materials with good light transmittance and conductivity such as indium tin oxide (ITO).

[0109] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0110] 1. The array substrate in the embodiment of the present application comprises a substrate and a plurality of gate lines, a plurality of data lines, a first passivation layer, a pixel electrode layer, a second passivation layer and a common electrode layer sequentially arranged on one side of the substrate, wherein the plurality of data lines are arranged in parallel along a first direction, the plurality of gate lines are arranged in parallel along a second direction, and the first direction and the second direction intersect; wherein the common electrode layer comprises a plurality of common electrode blocks arranged at intervals along the first direction, the common electrode blocks comprise a first common electrode block corresponding to the position of the pixel electrode layer, and a second common electrode block corresponding to the position of the data line, and in the first direction, the width of each data line is greater than or equal to twice the width of each second common electrode block, and the width of each data line is less than or equal to three times the width of each second common electrode block. By reducing the width of the data line, the light shielding of the data line is reduced, the light transmittance of the array substrate is improved, and the brightness of the display panel is increased without additionally increasing the manufacturing cost.

[0111] 2. The embodiment of the present application increases the distance between the data line 103 and the common electrode layer 107 by setting the first passivation layer 104 and the second passivation layer 106 between the data line 103 and the common electrode layer 107, reduces the coupling capacitance between the data line 103 and the common electrode layer 107, and helps to reduce the impact on the display quality caused by the large coupling capacitance.

[0112] 3. In the embodiment of the present application, by making the width of the touch electrode line 108 less than or equal to 4 microns, the shielding of the backlight by the touch electrode line 108 is reduced, thereby improving the transmittance of the array substrate 10, which is beneficial to improving the brightness of the display panel, and the narrowing of the touch electrode line 108 does not increase the manufacturing cost. At the same time, the width of the touch electrode line 108 is greater than or equal to 2.5 microns, which avoids the influence of the touch performance on the touch electrode line 108 when the width is too small.

[0113] 4. In the embodiment of the present application, a scanning signal is output to the gate line 102 through a gate driving circuit. By making the duty cycle range of the scanning signal on the gate line 102 between 46% and 49%, the problem of poor horizontal display caused by increased resistance delay in the array substrate 10 due to the reduction in the width of the gate line 102 is improved.

[0114] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0115] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0116] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0117] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; On one side perpendicular to the substrate, a plurality of gate lines, a gate insulating layer, a plurality of data lines, a first passivation layer, a pixel electrode layer, a second passivation layer and a common electrode layer are sequentially arranged, the plurality of data lines are arranged in parallel along a first direction, the plurality of gate lines are arranged in parallel along a second direction, and the first direction and the second direction intersect each other; The common electrode layer includes a plurality of common electrode blocks spaced apart along the first direction, the common electrode blocks include a first common electrode block corresponding to the position of the pixel electrode layer, and a second common electrode block corresponding to the position of the data line, an orthographic projection of the first common electrode block on the substrate overlaps with an orthographic projection of the pixel electrode layer on the substrate, an orthographic projection of the second common electrode block on the substrate overlaps with an orthographic projection of the data line on the substrate, and in the first direction, a width of each of the second common electrode blocks is greater than or equal to twice a width of each of the data lines, and a width of each of the second common electrode blocks is less than or equal to three times a width of each of the data lines; The array substrate further includes a plurality of touch electrode lines arranged in parallel along a first direction, the touch electrode lines are arranged in the same layer as the data lines, and the width of the touch electrode lines is less than or equal to 4 micrometers.

2. The array substrate according to claim 1, characterized in that: In the first direction, the width of each of the second common electrode blocks is less than or equal to 7.4 micrometers, and the width of each of the data lines is less than or equal to 2.8 micrometers.

3. The array substrate according to claim 2, characterized in that: In the first direction, the width of each of the gate lines is less than or equal to 3 micrometers.

4. The array substrate according to claim 1, characterized in that: In the first direction, a minimum spacing between the touch electrode lines and the data lines that are adjacent to each other is greater than or equal to 2 micrometers and less than or equal to 3.3 micrometers.

5. A display substrate, characterized in that: include: An array substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 4; The opposite substrate is arranged opposite to the array substrate, and includes a black matrix arranged on a side close to the array substrate. The orthographic projections of the data lines, the gate lines and the touch electrode lines on the substrate overlap with the orthographic projections of the black matrix on the substrate.

6. The display substrate according to claim 5, characterized in that: The black matrix includes a first black matrix, the position of the first black matrix corresponds to the position of the data line, in the first direction, the width of the first black matrix is ​​less than or equal to 5.5 microns, and the distance between the edge of the first black matrix and the edge of the data line is less than or equal to 1.35 microns.

7. The display substrate according to claim 5, characterized in that: The black matrix includes a second black matrix, the position of the second black matrix corresponds to the position of the gate line, in the second direction, the width of the second black matrix is ​​less than or equal to 17.8 microns, and the distance between the edge of the second black matrix and the edge of the gate line is less than or equal to 7.4 microns.

8. The display substrate according to claim 5, characterized in that: The black matrix includes a third black matrix, the position of the third black matrix corresponds to the positions of two adjacent data lines and the touch electrode lines, in the first direction, the width of the third black matrix is ​​less than or equal to 11.3 microns, in the first direction, the distance between the edge of the third black matrix and the edge of the data line is less than or equal to 0.6 microns; and / or, in the first direction, the distance between the edge of the third black matrix and the edge of the touch electrode line is less than or equal to 0.6 microns.

9. A display device, characterized in that: A display substrate comprising any one of claims 5 to 8.

10. A method for driving an array substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 4, and the array substrate comprises a gate driving circuit electrically connected to the gate line and a source driving circuit electrically connected to the data line, wherein: include: The gate line receives a scan signal output by the gate driving circuit, the scan signal is a signal output by a clock signal, and the duty cycle of the clock signal is greater than or equal to 46% and less than or equal to 49%; The data line receives a data signal output by the source driving circuit.

11. The driving method according to claim 10, characterized in that: The duty cycle of the clock signal is 48.7%.

12. A method for manufacturing an array substrate, characterized in that: include: providing a substrate; A plurality of gate lines, a gate insulating layer, a plurality of data lines, a first passivation layer, a pixel electrode layer, a second passivation layer and a common electrode layer are sequentially formed on a side perpendicular to the substrate, the plurality of data lines are arranged in parallel along a first direction, the plurality of gate lines are arranged in parallel along a second direction, and the first direction and the second direction intersect; The common electrode layer includes a plurality of common electrode blocks spaced apart along the first direction, the common electrode blocks include a first common electrode block corresponding to the position of the pixel electrode layer, and a second common electrode block corresponding to the position of the data line, an orthographic projection of the first common electrode block on the substrate overlaps with an orthographic projection of the pixel electrode layer on the substrate, an orthographic projection of the second common electrode block on the substrate overlaps with an orthographic projection of the data line on the substrate, and in the first direction, a width of each of the second common electrode blocks is greater than or equal to twice a width of each of the data lines, and a width of each of the second common electrode blocks is less than or equal to three times a width of each of the data lines; The array substrate further includes a plurality of touch electrode lines arranged in parallel along a first direction, the touch electrode lines are arranged in the same layer as the data lines, and the width of the touch electrode lines is less than or equal to 4 micrometers.

13. The manufacturing method according to claim 12, characterized in that: The method of sequentially manufacturing a plurality of gate lines, a gate insulating layer, a plurality of data lines, a first passivation layer, a pixel electrode layer, a second passivation layer and a common electrode layer on one side of the substrate comprises: Sequentially forming a plurality of gate lines and gate insulating layers on one side of the substrate; A plurality of data lines and a plurality of touch electrode lines are manufactured on a side of the gate line away from the substrate, the plurality of touch electrode lines are arranged in parallel along the first direction, and in the first direction, a minimum spacing between adjacent touch electrode lines and data lines is greater than or equal to 2 microns and less than or equal to 3.3 microns.

14. The method according to claim 13, characterized in that: The step of manufacturing a plurality of data lines and a plurality of touch electrode lines on a side of the gate line away from the substrate comprises: Depositing a metal layer on a side of the gate line away from the substrate; The metal layer is patterned to form a plurality of the data lines and a plurality of the touch electrode lines.

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