Active matrix substrate and display device

Abstract

An active matrix substrate and a display device reduce the number of connection portions. The active matrix substrate includes: a plurality of first wirings including a first conductive film, extending along a first direction, and arranged at intervals in a second direction; a second wiring including a second conductive film arranged on an upper layer side of a first insulating film, extending along the second direction, and intersecting with the plurality of first wirings; a plurality of third wirings including a portion of the first conductive film different from the first wiring, extending along the second direction, and overlapping with the second wiring, sandwiching the first wiring in the second direction; a first connection electrode arranged on an upper layer side of a second insulating film, intersecting with a part of the first wiring, and connected to two third wirings sandwiching the first wiring; and a second connection electrode arranged on an upper layer side of the second insulating film, intersecting with a first wiring different from the first wiring intersected by the first connection electrode, and connected to the third wiring and the second wiring connected to the first connection electrode.

Description

Technical Field

[0001] The technology disclosed in this specification relates to an active matrix substrate and a display device. Background Art

[0002] Conventionally, as an example of a display device including an active matrix substrate, a liquid crystal display device described in Patent Document 1 below is known. The liquid crystal display device described in Patent Document 1 includes: a transparent insulating substrate; gate lines formed on the insulating substrate in a first direction; auxiliary repair lines formed of the same material as the gate lines in a second direction on the same layer as the gate lines, including a plurality of parts separated by the gate lines; a first insulating layer covering the gate lines and the auxiliary repair lines; and data lines formed on the first insulating layer in the second direction along the auxiliary repair lines. In this liquid crystal display device, a transparent conductive connection pattern is formed of the same material as the pixel electrode across the auxiliary repair lines, the intersection of the gate lines and the data lines, and other auxiliary repair lines. The transparent conductive connection pattern is connected to the end portions of the auxiliary repair lines that protrude obliquely from the side of the data lines through contact holes opened in the gate insulating film and the protective insulating film, and is connected to the data lines through contact holes opened in the protective insulating film above the data lines.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Laid-Open No. 11-194369 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] In the liquid crystal display device described in Patent Document 1 above, a total of three contact holes are arranged near the gate wiring: two contact holes for connecting the transparent conductive connection pattern to two auxiliary repair lines; and one contact hole for connecting the transparent conductive connection pattern to the data line. Since these three contact holes are arranged for each gate wiring, the number of contact holes arranged along the second direction will be the number obtained by multiplying the number of gate wirings by 3, and the arrangement number of the contact holes is excessive. Near the contact holes, the alignment of liquid crystal molecules is likely to be disordered, so there is a tendency to easily cause display defects. In order to avoid display defects, it is necessary to take measures to expand the light-shielding range of the black matrix, which may lead to a decrease in the aperture ratio.

[0008] The technology described in this specification is completed based on the above situation, and aims to reduce the number of connection parts.

[0009] Solutions for Solving the Problems

[0010] (1) The active matrix substrate related to the technology described in this specification includes: a plurality of first wirings, which include a first conductive film, extend along a first direction, and are arranged at intervals in a second direction intersecting with the first direction; a first insulating film, which is arranged on the upper layer side of the first conductive film; a second wiring, which includes a second conductive film arranged on the upper layer side of the first insulating film, extends along the second direction, and intersects with the plurality of first wirings with the first insulating film therebetween; a plurality of third wirings, which include a part of the first conductive film different from the first wiring, extend along the second direction, and at least a part thereof overlaps with the second wiring with the first insulating film therebetween, and the plurality of third wirings are arranged to sandwich the first wiring in the second direction; a second insulating film, which is arranged on the upper layer side of the second conductive film; a first connection electrode, which is arranged on the upper layer side of the second insulating film, intersects with a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween, and is connected to two third wirings sandwiching the first wiring; and a second connection electrode, which is arranged on the upper layer side of the second insulating film, intersects with a first wiring different from the first wiring intersected by the first connection electrode with the first insulating film and the second insulating film therebetween, and is connected to the third wiring and the second wiring connected to the first connection electrode.

[0011] (2) Additionally, it may also be that, based on the above (1), the active matrix substrate includes: a position detection electrode, which is arranged on the upper layer side of the second insulating film; and a position detection wiring, which extends along the second direction and is connected to the position detection electrode, and the second wiring includes the position detection wiring.

[0012] (3) Additionally, it may also be that, based on the above (2), the plurality of first wirings include the first wirings that overlap with the position detection electrode connected to the position detection wiring and intersect with the position detection wiring with the first insulating film therebetween, and include a third connection electrode, which is arranged on the upper layer side of the second insulating film, overlaps with the position detection electrode, and intersects with the first wiring intersecting with the position detection wiring with the first insulating film and the second insulating film therebetween, and is connected to the position detection wiring and the position detection electrode.

[0013] (4) Alternatively, on the basis of the above (2) or (3), the active matrix substrate may further include: a switching element disposed on the lower layer side of the second insulating film; a pixel electrode disposed on the upper layer side of the second insulating film and connected to the switching element; and a third insulating film disposed on the upper layer side of the second insulating film. The position detection electrode includes a first transparent electrode film, and the pixel electrode includes a second transparent electrode film, which is configured to overlap the position detection electrode with the third insulating film therebetween. The first connection electrode and the second connection electrode include a portion of the first transparent electrode film and the second transparent electrode film disposed on the upper layer side of the third insulating film, which is different from the position detection electrode or the pixel electrode.

[0014] (5) Alternatively, on the basis of the above (4), the first connection electrode and the second connection electrode include a portion of the second transparent electrode film that is different from the pixel electrode.

[0015] (6) Alternatively, on the basis of any one of the above (2) to (5), the active matrix substrate may further include: a switching element; a pixel electrode connected to the switching element; a scanning wiring extending along the first direction and connected to the switching element; and a signal wiring extending along the second direction and connected to the switching element. The first wiring includes the scanning wiring, and the signal wiring includes a portion of the second conductive film that is different from the second wiring and is configured to be arranged at intervals in the first direction with respect to the position detection wiring.

[0016] (7) Alternatively, on the basis of any one of the above (2) to (6), the active matrix substrate may further include a connection wiring configured to overlap the position detection electrode, extend along the second direction, and at least two end portions thereof are connected to the overlapped position detection electrode. The second wiring includes the connection wiring.

[0017] (8) Alternatively, on the basis of the above (7), the first wiring includes a first wiring that overlaps the position detection electrode connected to the connection wiring and crosses the connection wiring with the first insulating film therebetween, and includes a fourth connection electrode. The fourth connection electrode is disposed on the upper layer side of the second insulating film, overlaps the position detection electrode, and crosses the first wiring that crosses the connection wiring with the first insulating film and the second insulating film therebetween, and is connected to the connection wiring and the position detection electrode.

[0018] (9) Alternatively, on the basis of the above (8), in the active matrix substrate, a plurality of the first wirings include a plurality of the first wirings that cross the connection wiring with the first insulating film therebetween and are arranged at intervals in the second direction, a plurality of the third wirings include a plurality of the third wirings arranged such that at least a part thereof overlaps the connection wiring with the first insulating film therebetween, the fourth connection electrodes include two fourth connection electrodes that cross two first wirings respectively crossing two end portions in the second direction of the connection wiring, the second connection electrodes include two second connection electrodes located on the central side in the second direction of the connection wiring with respect to the two fourth connection electrodes, and the first connection electrodes include a plurality of the first connection electrodes located on the central side in the second direction of the connection wiring with respect to the two second connection electrodes.

[0019] (10) Alternatively, on the basis of any one of the above (1) to (9), the active matrix substrate includes dummy wirings, the dummy wirings include a portion different from the first wiring in the first conductive film, extend along the second direction, and at least a part thereof overlaps the second wiring with the first insulating film therebetween, and the dummy wirings are arranged such that the first wiring crossing the second connection electrode is sandwiched between the dummy wirings and the third wiring connected to the second connection electrode in the second direction, and are not connected to the second connection electrode.

[0020] (11) Alternatively, on the basis of any one of the above (1) to (10), the second connection electrode is connected to the second wiring at a position where the first wiring is sandwiched between the second connection electrode and the third wiring connected thereto in the second direction.

[0021] (12) Alternatively, the above active matrix substrate, based on any one of the above (1) to (11), further includes: a switching element having a first electrode, a second electrode, and a third electrode; a scanning wiring extending along the first direction and connected to the first electrode; a signal wiring extending along the second direction and connected to the second electrode; and a pixel electrode connected to the third electrode. The first wiring includes the scanning wiring, the signal wiring includes a portion of the second conductive film different from the second wiring, the first electrode is formed by a portion of the scanning wiring, the second electrode is formed by a portion of the signal wiring, and is arranged to overlap with the first electrode with the first insulating film therebetween. A plurality of the switching elements are arranged in a manner that they are not locally arranged in the plane of the active matrix substrate, thereby forming a configuration region where the switching elements are arranged and a non-configuration region where the switching elements are not arranged. The scanning wiring includes a first scanning wiring passing through the configuration region and the non-configuration region, and a second scanning wiring passing through the configuration region and the non-configuration region and having a shorter distance passing through the non-configuration region than the first scanning wiring. The overlapping area of the first scanning wiring and the second wiring is larger than the overlapping area of the second scanning wiring and the second wiring.

[0022] (13) Alternatively, the above active matrix substrate, based on any one of the above (1) to (12), further includes: a switching element having a first electrode, a second electrode, and a third electrode; a scanning wiring extending along the first direction and connected to the first electrode; a signal wiring extending along the second direction and connected to the second electrode; and a pixel electrode connected to the third electrode. The first wiring includes the scanning wiring, the signal wiring includes a portion of the second conductive film different from the second wiring, the first electrode is formed by a portion of the scanning wiring, the second electrode is formed by a portion of the signal wiring, and is arranged to overlap with the first electrode with the first insulating film therebetween. A plurality of the switching elements are arranged in a manner that they are not locally arranged in the plane of the active matrix substrate, thereby forming a configuration region where the switching elements are arranged and a non-configuration region where the switching elements are not arranged. The scanning wiring includes a first scanning wiring passing through the configuration region and the non-configuration region, and a second scanning wiring passing through the configuration region and the non-configuration region and having a shorter distance passing through the non-configuration region than the first scanning wiring. The overlapping area of the first connection electrode connected to the two third wirings sandwiching the first scanning wiring and the first scanning wiring is larger than the overlapping area of the first connection electrode connected to the two third wirings sandwiching the second scanning wiring and the second scanning wiring.

[0023] (14) The display device related to the technology described in this specification includes: an active matrix substrate described in any one of the above (1) to (13); and a counter substrate configured to face the active matrix substrate.

[0024] Effects of the Invention

[0025] According to the technology described in this specification, the number of connection parts can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a top view showing a touch electrode, touch wiring, etc. of the liquid crystal panel of Embodiment 1.

[0027] Figure 2 It is a top view showing the pixel arrangement of the array substrate constituting the liquid crystal panel.

[0028] Figure 3 It is a top view showing an enlarged view of the vicinity of the TFT and the first connection electrode in the array substrate.

[0029] Figure 4 It is a Figure 2 cross-sectional view taken along line A-A of the liquid crystal panel.

[0030] Figure 5 It is a Figure 2 cross-sectional view taken along line B-B of the liquid crystal panel.

[0031] Figure 6 It is a top view showing the pattern of the first metal film in the array substrate in the Figure 2 same range.

[0032] Figure 7 It is a top view showing the pattern of the second metal film in the array substrate in the Figure 2 same range.

[0033] Figure 8 It is a top view showing the pattern of the second transparent electrode film in the array substrate in the Figure 2 same range.

[0034] Figure 9 It is a top view showing the pattern of the first transparent electrode film in the array substrate in the Figure 2 same range.

[0035] Figure 10 It is a top view schematically showing the connection form of touch electrodes, touch wiring, sub-wiring, etc. in the array substrate.

[0036] Figure 11 It is a top view showing the pattern of the first metal film, the second metal film, and the second transparent electrode film in the array substrate in theFigure 3 Top view of the same range.

[0037] Figure 12 It is of the liquid crystal panel Figure 3 Cross-sectional view taken along the C-C line.

[0038] Figure 13 Top view showing the patterns of the first metal film, the second metal film, and the second transparent electrode film near one of the second connection electrodes in the array substrate.

[0039] Figure 14 Top view showing the pattern of the first transparent electrode film near one of the second connection electrodes in the array substrate.

[0040] Figure 15 It is of the liquid crystal panel Figure 13 Cross-sectional view taken along the D-D line.

[0041] Figure 16 Top view showing the patterns of the first metal film, the second metal film, and the second transparent electrode film near the other second connection electrode in the array substrate.

[0042] Figure 17 It is of the liquid crystal panel Figure 16 Cross-sectional view taken along the E-E line.

[0043] Figure 18 Top view showing the patterns of the first metal film, the second metal film, and the second transparent electrode film near the third connection electrode in the array substrate.

[0044] Figure 19 Top view showing the pattern of the first transparent electrode film near the third connection electrode in the array substrate.

[0045] Figure 20 It is of the liquid crystal panel Figure 18 Cross-sectional view taken along the F-F line.

[0046] Figure 21 Top view schematically showing the connection forms of touch electrodes, touch wirings, sub-wirings, second connection wirings, etc. in the array substrate according to Embodiment 2.

[0047] Figure 22 Top view showing the structure near the end in the Y-axis direction of the liquid crystal panel according to Embodiment 3.

[0048] Figure 23 Top view of the enlarged notch portion in the array substrate.

[0049] Figure 24 Top view of the enlarged curved portion in the array substrate.

[0050] Figure 25 It is a top view showing the pattern of the first gate wiring, TFT, and the second metal film near the first connection electrode in the array substrate.

[0051] Figure 26 It is a top view showing the pattern of the second gate wiring, TFT, and the second metal film near the first connection electrode in the array substrate.

[0052] Figure 27 It is a top view showing the pattern of the first gate wiring, TFT, and the second transparent electrode film near the first connection electrode in the array substrate.

[0053] Figure 28 It is a top view schematically showing the connection form of touch electrodes, touch wirings, sub-wirings, etc. in the array substrate according to Embodiment 4.

[0054] Figure 29 It is a top view schematically showing the connection form of touch electrodes, touch wirings, sub-wirings, etc. in the array substrate according to Embodiment 5.

[0055] Figure 30 It is a top view schematically showing the connection form of a driver, touch electrodes, touch wirings, sub-wirings, etc. in the array substrate according to Embodiment 6.

[0056] Figure 31 It is a top view schematically showing the connection form of source wirings, sub-wirings, etc. in the array substrate according to Embodiment 7.

[0057] Figure 32 It is a top view schematically showing the connection form of common wirings, sub-wirings, etc. in the array substrate according to Embodiment 8.

[0058] Explanation of Reference Numerals

[0059] 10…Liquid crystal panel (display device), 20…CF substrate (opposite substrate), 21, 121, 221, 321, 421, 521, 621, 721…Array substrate (active matrix substrate), 23, 223…TFT (switching element), 23A, 223A…Gate electrode (first electrode), 23B, 223B…Source electrode (second electrode), 23C, 223C…Drain electrode (third electrode), 24, 124, 224, 324…Pixel electrode, 26, 126, 226, 326, 426, 526…Gate wiring (first wiring, scanning wiring), 27, 227, 627…Source wiring (signal wiring, second wiring), 30, 130, 330, 430, 530…Touch electrode (position detection electrode), 31, 131, 231, 331, 431, 531…Touch wiring (second wiring, position detection wiring), 32, 132, 232, 332, 432, 532, 632, 732…Sub-wiring (third wiring), 33, 133, 233, 333, 533, 633, 733…First connection electrode, 34, 134, 334, 434, 534, 634, 734…Second connection electrode, 35, 135, 735…Third connection electrode, 36, 136, 536…First dummy wiring (dummy wiring), 39, 239…Second connection wiring (second wiring, connection wiring), 40…Fourth connection electrode, 44…Common wiring (second wiring), 226α…First gate wiring (first scanning wiring), 226β…Second gate wiring (second scanning wiring), AA…Display area (arrangement area), F1…First metal film (first conductive film), F2…Gate insulating film (first insulating film), F4…Second metal film (second conductive film), F5…First interlayer insulating film (second insulating film), F6…First transparent electrode film, F7…Second interlayer insulating film (third insulating film), F8…Second transparent electrode film, NAA…Non-display area (non-arrangement area). Detailed implementation manners

[0060] <Embodiment 1>

[0061] According to Figures 1 to 20 to describe Embodiment 1. In this embodiment, a liquid crystal panel (display device) 10 having an image display function and a touch panel function (position input function, position detection function) is exemplified. In addition, the X-axis, Y-axis, and Z-axis are shown in a part of each drawing, and the directions of the respective axes are drawn so as to be the directions shown in each drawing. In addition, with Figure 4 , Figure 5 , Figure 12 , Figure 15 , Figure 17 and Figure 20 the upper side being the front side and the lower side of the drawing being the back side.

[0062] Figure 1 is a schematic top view of the liquid crystal panel 10. As Figure 1 shown, the planar shape of the liquid crystal panel 10 is generally a horizontally long and roughly square shape as a whole. The short side direction of the liquid crystal panel 10 coincides with the Y-axis direction, the long side direction coincides with the X-axis direction, and the plate thickness direction (the normal direction of the plate surfaces of the respective substrates 20 and 21) coincides with the Z-axis direction. In the present embodiment, the Y-axis direction is the "first direction" and the X-axis direction is the "second direction". The liquid crystal panel 10 can display an image using illumination light irradiated from a backlight device (lighting device) disposed on the inner side thereof. The backlight device is disposed on the inner side (back side) with respect to the liquid crystal panel 10 and has, for example, a light source (such as an LED or the like) and an optical member that converts the light from the light source into planar light by imparting an optical action thereto.

[0063] As Figure 1 shown, the central side portion of the screen of the liquid crystal panel 10 is set as a display area (the range enclosed by a single-dot chain line in Figure 1 ) AA for displaying an image. In contrast, the outer peripheral side portion of the screen of the liquid crystal panel 10 that surrounds the display area AA and has a border shape (frame shape) is set as a non-display area NAA where no image is displayed. The liquid crystal panel 10 is formed by bonding a pair of substrates 20 and 21. The front (front side) substrate of the pair of substrates 20 and 21 is set as a CF substrate (opposite substrate) 20, and the inner (back side) substrate is set as an array substrate (active matrix substrate) 21. Both the CF substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface side of a glass substrate. In addition, polarizing plates are attached to the outer surface sides of the two substrates 20 and 21, respectively.

[0064] As Figure 1As shown, the short side dimension of the CF substrate 20 is shorter than that of the array substrate 21, and the CF substrate 20 is bonded to the array substrate 21 in a form where one end in the short side direction (Y-axis direction) is aligned. Therefore, the other end in the short side direction of the array substrate 21 is provided as a protruding portion 21A that protrudes laterally with respect to the CF substrate 20 and does not overlap with the CF substrate 20. A driver (signal supply unit) 11 and a flexible substrate 12 for supplying various signals related to the display function and touch panel function described later are mounted on the protruding portion 21A. The driver 11 is mounted on the protruding portion 21A of the array substrate 21 in a COG (Chip On Glass) manner. The driver 11 includes an LSI chip having a drive circuit inside and processes various signals transmitted by the flexible substrate 12. In addition, it can be said that the driver 11 is arranged on one end side in the Y-axis direction with respect to the display area AA in the array substrate 21. The flexible substrate 12 is configured to have a plurality of wiring patterns formed on a base material including a synthetic resin material (such as a polyimide-based resin, etc.) having insulation and flexibility. One end side portion of the flexible substrate 12 is connected to the array substrate 21, and the other end side portion is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 10 via the flexible substrate 12. In addition, in the non-display area NAA of the array substrate 21, a pair of gate circuit portions 13 are provided in a form that sandwiches the display area AA from both sides in the X-axis direction. The gate circuit portion 13 is used to supply a scan signal to a gate wiring 26 described later and is provided monolithically on the array substrate 21.

[0065] The liquid crystal panel 10 according to the present embodiment has both a display function of displaying an image and a touch panel function of detecting the position (input position) where the user makes an input based on the displayed image. In the liquid crystal panel 10, the touch panel pattern for realizing the touch panel function is integrated (embedded). The touch panel pattern is a so-called projected capacitive type, and its detection method is a self-capacitance method. As Figure 1As shown, the touch panel pattern includes a plurality of touch electrodes (position detection electrodes) 30 arranged in a matrix within the plate surface of the liquid crystal panel 10. The touch electrodes 30 are arranged in the display area AA of the liquid crystal panel 10. Therefore, the display area AA of the liquid crystal panel 10 substantially coincides with the touch area (position input area) capable of detecting the input position. In addition, the non-display area NAA substantially coincides with the non-touch area (non-position input area) where the input position cannot be detected. When the user brings a position input body such as the user's finger as a conductor or a touch pen operated by the user close to the surface (display surface) of the liquid crystal panel 10 based on the image displayed in the display area AA of the liquid crystal panel 10, a static capacitance is formed between the position input body and the touch electrodes 30. Thus, the static capacitance detected by the touch electrodes 30 located near the position input body changes as the position input body approaches, becoming different from the static capacitance of the touch electrodes 30 located far from the position input body. The detection circuit described later can detect the input position based on this difference in static capacitance.

[0066] As Figure 1 shown, in the display area AA, a plurality of touch electrodes 30 are arranged at intervals along the X-axis direction (first direction) and the Y-axis direction (second direction) respectively. For example, 80 touch electrodes 30 are arranged along the X-axis direction, and 50 touch electrodes 30 are arranged along the Y-axis direction. The touch electrodes 30 are substantially square in plan view, and the size of one side is set to about several mm. The size of the touch electrodes 30 in plan view is much larger than the pixels PX described later, and they are arranged in a range spanning a plurality of (about several tens to several hundreds) pixels PX in the X-axis direction and the Y-axis direction. In addition, specific values such as the size of one side of the touch electrodes 30 and the number of settings in the touch area can be appropriately changed in addition to the above. The detailed configuration of the touch electrodes 30 will be described later.

[0067] As Figure 1 shown, a plurality of touch wirings (second wirings, position detection wirings, main touch wirings) 31 provided on the liquid crystal panel 10 are selectively connected to the plurality of touch electrodes 30. The touch wirings 31 generally extend along the Y-axis direction. One end side portion of the touch wirings 31 in the Y-axis direction is connected to the driver 11 in the non-display area NAA. The other end side portion of the touch wirings 31 in the Y-axis direction is connected to a specific touch electrode 30 among the plurality of touch electrodes 30 arranged along the Y-axis direction in the display area AA. The formation range of the touch wirings 31 in the Y-axis direction is limited to the range from the driver 11 to the touch electrode 30 to be connected, and on the side opposite to the side closer to the driver 11 ( Figure 1 the lower side) ( Figure 1On the upper side) is not provided. In addition, according to the number of touch wirings 31 provided, only one touch wiring 31 can be connected to one touch electrode 30, or multiple touch wirings 31 can be connected to one touch electrode 30. Also, the number of touch wirings 31 connected to one touch electrode 30 can vary depending on the position of the touch electrode 30. In this case, for example, it is preferable that the number of touch wirings 31 connected to the touch electrode 30 far from the driver 11 is more than the number of touch wirings 31 connected to the touch electrode 30 close to the driver 11, but it does not necessarily have to be limited to this. In addition, in Figure 1 the connection part of the touch wiring 31 and the touch electrode 30 is shown as a black dot. Moreover, the touch wiring 31 is connected to the detection circuit. The detection circuit can be provided in the driver 11, or can be provided outside the liquid crystal panel 10 via the flexible substrate 12. The detailed structure of the touch wiring 31 will be described separately later.

[0068] Figure 2 is a top view of the display area AA of the array substrate 21 constituting the liquid crystal panel 10. Figure 3 is to Figure 2 a magnified top view of the vicinity of the TFT 23 described later in Figure 2 and Figure 3 the respective films F1, F3, F4, F8 provided in the array substrate 21 are shown in different shaded patterns. In Figure 2 and Figure 3 for the sake of ensuring easy visibility, the illustration of the first transparent electrode film F6 and the like described later is omitted. In Figure 2 for the sake of ensuring easy visibility, the illustration of the light-shielding portion 29 of the CF substrate 20 is omitted. As in Figure 2 and Figure 3As shown, on the inner surface side of the display area AA of the array substrate 21 constituting the liquid crystal panel 10, TFTs (thin film transistors, switching elements) 23 and pixel electrodes 24 are provided. The TFTs 23 and pixel electrodes 24 are arranged in a matrix with a plurality of them spaced apart along the X-axis direction and the Y-axis direction in the display area AA. The TFTs 23 and pixel electrodes 24 are not arranged in the non-display area NAA. Among them, the pixel electrode 24 constitutes a pixel PX as a display unit. Around these TFTs 23 and pixel electrodes 24, gate wirings (first wirings, scanning wirings) 26 and source wirings (image wirings) 27 that are substantially orthogonal (cross) to each other are arranged. The gate wiring 26 extends substantially linearly along the X-axis direction and the line width changes midway. In contrast, the source wiring 27 extends substantially along the Y-axis direction and repeatedly bends in a zigzag shape. The gate wiring 26 is connected to gate electrodes (first electrodes) 23A of a plurality of TFTs 23 arranged along the X-axis direction. A plurality of gate wirings 26 are arranged at intervals in the Y-axis direction. The source wiring 27 is connected to source electrodes (second electrodes) 23B of a plurality of TFTs 23 arranged along the Y-axis direction. A plurality of source wirings 27 are arranged at intervals in the X-axis direction. The TFTs 23 are driven based on various signals respectively supplied to these gate wirings 26 and source wirings 27. Along with the driving of the TFTs 23, the supply of potential to the pixel electrode 24 connected to the drain electrode (third electrode) 23C of the TFTs 23 is controlled. In addition, the TFTs 23 are located Figure 2 and Figure 3 on the right side of, and relative to the pixel electrode 24 which is set as its connection object, the TFTs 23 are located Figure 2 and Figure 3 on the lower side of.

[0069] On the CF substrate 20 side, a light-shielding portion (inter-pixel light-shielding portion, black matrix) 29 shown by a thick double-dot dash line in Figure 3 is formed. As Figure 3 shown, the planar shape of the light-shielding portion 29 is substantially lattice-shaped to separate adjacent pixel electrodes 24. The light-shielding portion 29 has a pixel opening 29A at a position where it overlaps most of the pixel electrode 24 in a top view. The pixel opening 29A transmits the transmitted light of the pixel electrode 24 and emits it to the outside of the liquid crystal panel 10. The light-shielding portion 29 is arranged to overlap at least the gate wiring 26 and the source wiring 27 on the array substrate 21 side in a top view.

[0070] Figure 4 is a cross-sectional view near the central portion of the pixel PX in the liquid crystal panel 10 ( Figure 2 cross-sectional view taken along line A-A of). As Figure 4As shown, the liquid crystal panel 10 has a liquid crystal layer (dielectric layer) 22 disposed between a pair of substrates 20 and 21 and containing liquid crystal molecules which are substances whose optical properties change with the application of an electric field. On the inner surface side of the display region AA of the CF substrate 20 constituting the liquid crystal panel 10, color filters 28 presenting three colors of blue (B), green (G), and red (R) are provided. A plurality of color filters 28 presenting different colors are repeatedly arranged along the extending direction (X-axis direction) of the gate wiring 26 and extend along the extending direction (substantially Y-axis direction) of the source wiring 27, so that they are arranged in a stripe pattern as a whole. These color filters 28 are arranged to overlap with the respective pixel electrodes 24 on the array substrate 21 side in a plan view. The color filters 28 adjacent in the X-axis direction and presenting different colors are arranged such that their boundaries (color boundaries) overlap with the source wiring 27 and the light-shielding portion 29. In this liquid crystal panel 10, the R, G, and B color filters 28 arranged along the X-axis direction and the three pixel electrodes 24 opposed to the respective color filters 28 constitute pixels PX of three colors. Further, in this liquid crystal panel 10, the display pixels capable of performing color display of a specified gray level are constituted by the pixels PX of the three colors of R, G, and B adjacent in the X-axis direction. The arrangement pitch of the pixels PX in the Y-axis direction is set to be about three times the arrangement pitch in the X-axis direction. The light-shielding portion 29 is arranged in a form of separating the adjacent color filters 28. On the upper layer side (liquid crystal layer 22 side) of the color filter 28, a coating film OC is provided which is arranged in a planar manner over substantially the entire area of the CF substrate 20 for flattening. Further, alignment films for aligning the liquid crystal molecules contained in the liquid crystal layer 22 are respectively formed on the innermost surfaces (uppermost layers) of the two substrates 20 and 21 in contact with the liquid crystal layer 22.

[0071] Next, the common electrode 25 will be described with reference to Figure 4 as follows. As Figure 4As shown, on the inner surface side of the display area AA of the array substrate 21, a common electrode 25 is formed on the lower layer side of the pixel electrodes 24 in a form overlapping all the pixel electrodes 24. The common electrode 25 extends over substantially the entire area of the display area AA. The common electrode 25 is supplied with a common potential signal (reference potential signal) of a common potential (reference potential) except during a period (sensing period) when a touch signal (position detection signal) is supplied to detect the input position of the position input body. When the pixel electrode 24 is charged, a potential difference is generated between the overlapping pixel electrode 24 and the common electrode 25. Then, an edge electric field (tilted electric field) is generated between the opening edge of the slit 24A1 in the pixel electrode 24 and the common electrode 25, and this edge electric field includes not only a component along the plane of the array substrate 21 but also a component in the direction normal to the plane of the array substrate 21. The alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled by utilizing this edge electric field. That is, the operation mode of the liquid crystal panel 10 according to the present embodiment is set to the FFS (Fringe Field Switching) mode.

[0072] And, as Figure 1 shown, the common electrode 25 constitutes the touch electrode 30 described above. Slits 25A configured to separate between adjacent touch electrodes 30 are formed in the common electrode 25. The slits 25A are generally in a lattice shape in a top view. The slits 25A include: a first slit 25A1 that extends across the entire length of the common electrode 25 substantially along the X-axis direction; and a second slit 25A2 that extends through the entire length of the common electrode 25 substantially along the Y-axis direction. The common electrode 25 includes a plurality of touch electrodes 30 that are divided into a substantially checkerboard pattern by the slits 25A in a top view and are electrically independent of each other. The touch electrodes 30 arranged along the Y-axis direction are separated by the first slit 25A1. The touch electrodes 30 arranged along the X-axis direction are separated by the second slit 25A2. A common potential signal related to the image display function and a touch signal (position detection signal) related to the touch panel function are supplied to the touch wiring 31 connected to such touch electrodes 30 from the driver 11 in a time-division manner. The timing for supplying the common potential signal from the driver 11 to the touch wiring 31 is the display period. The timing for supplying the touch signal from the driver 11 to the touch wiring 31 is the sensing period (position detection period). The common potential signal is transmitted to all the touch wirings 31 at the same timing (display period), so that all the touch electrodes 30 become a reference potential based on the common potential signal and function as the common electrode 25.

[0073] Here, with reference to Figure 5 the various films laminated and formed on the inner surface side of the array substrate 21 will be described. Figure 5 is a cross-sectional view near the TFT 23 in the liquid crystal panel 10 (Figure 2 Cross-sectional view taken along line B-B). As Figure 5 shown, on the array substrate 21, the following are sequentially stacked from the lower layer side (glass substrate side): a first metal film (first conductive film) F1, a gate insulating film (first insulating film) F2, a semiconductor film F3, a second metal film (second conductive film) F4, a first interlayer insulating film (second insulating film) F5, a first transparent electrode film (third conductive film) F6, a second interlayer insulating film (third insulating film) F7, and a second transparent electrode film (fourth conductive film) F8. The first metal film F1 and the second metal film F4 are each provided as a single-layer film including one metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a stacked film or alloy including different types of metal materials, so as to have conductivity and light-shielding properties. The first metal film F1 constitutes the gate wiring 26 or the gate electrode 23A of the TFT 23, etc. The second metal film F4 constitutes the source wiring 27, the source electrode 23B and the drain electrode 23C of the TFT 23, the touch wiring 31, etc. The semiconductor film F3 includes, for example, a thin film using an oxide semiconductor, amorphous silicon, etc. as a material, and constitutes the channel portion 23D of the TFT 23, etc. The first transparent electrode film F6 and the second transparent electrode film F8 include a transparent electrode material (for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), etc.). The first transparent electrode film F6 constitutes the common electrode 25 (touch electrode 30), etc. The second transparent electrode film F8 constitutes the pixel electrode 24, etc.

[0074] The gate insulating film F2, the first interlayer insulating film F5, and the second interlayer insulating film F7 each include silicon nitride (SiN x) Inorganic materials such as silicon dioxide (SiO2). The gate insulating film F2 insulates the lower-layer first metal film F1 from the upper-layer semiconductor film F3 and the second metal film F4. For example, the crossing portion of the gate wiring 26 including the first metal film F1 and the source wiring 27 including the second metal film F4 is insulated by the gate insulating film F2. In addition, the overlapping portion of the gate electrode 23A including the first metal film F1 and the channel portion 23D including the semiconductor film F3 is insulated by the gate insulating film F2. The first interlayer insulating film F5 insulates the lower-layer semiconductor film F3 and the second metal film F4 from the upper-layer first transparent electrode film F6. For example, the overlapping portion of the source wiring 27 and the touch wiring 31 including the second metal film F4 and the common electrode 25 (touch electrode 30) including the first transparent electrode film F6 is insulated by the first interlayer insulating film F5. The second interlayer insulating film F7 insulates the lower-layer first transparent electrode film F6 from the upper-layer second transparent electrode film F8. For example, the overlapping portion of the common electrode 25 (touch electrode 30) including the first transparent electrode film F6 and the pixel electrode 24 including the second transparent electrode film F8 is insulated by the second interlayer insulating film F7. At positions in the first interlayer insulating film F5 and the second interlayer insulating film F7 that overlap both the drain electrode 23C including the second metal film F4 and a part of the pixel electrode 24 (the pixel connection portion 24B described later), a first contact hole CH1 is formed. The drain electrode 23C and the pixel electrode 24 are connected through the first contact hole CH1.

[0075] Next, mainly with reference to Figures 5 to 7 the structure of the TFT23 will be described. Figure 6 is a top view showing the same range as Figure 2 and is a top view showing the pattern of the first metal film F1 (gate wiring 26, etc.). Figure 7 is a top view showing the same range as Figure 2 and is a top view showing the pattern of the second metal film F4 (source wiring 27, etc.). As Figure 5 and Figure 6 show, the TFT23 has a gate electrode 23A. The gate electrode 23A is composed of a part of the gate wiring 26 (near the crossing portion with the source wiring 27). The gate electrode 23A is formed by locally widening the gate wiring 26. The gate electrode 23A drives the TFT23 based on the scan signal supplied to the gate wiring 26. As Figure 5 and Figure 7 show, the TFT23 is arranged relative to the connected source wiring 27 at Figure 5 and Figure 7The right side as shown. The TFT 23 has a source electrode 23B. The source electrode 23B is formed by a part (the crossing part with the gate wiring 26) of the source wiring 27 to be connected. The source electrode 23B is formed by locally widening the source wiring 27. The source electrode 23B is arranged at one end in the X-axis direction of the TFT 23 ( Figure 5 and Figure 7 the left end as shown). Substantially the entire area of the source electrode 23B overlaps with a part of the gate electrode 23A and is connected to the channel part 23D. The TFT 23 has a drain electrode 23C. The drain electrode 23C is arranged at a position spaced apart from the source electrode 23B, that is, at the other end in the X-axis direction of the TFT 23 ( Figure 5 and Figure 7 the right end as shown). The drain electrode 23C is arranged to overlap with a part of the gate electrode 23A, and the overlapping part with the gate electrode 23A is connected to the channel part 23D. One end of the drain electrode 23C on the side opposite to the connection part with the channel part 23D is connected to the pixel electrode 24.

[0076] As Figure 5 shown, the TFT 23 has a channel part (semiconductor part) 23D. The channel part 23D overlaps with the gate electrode 23A with the gate insulating film F2 therebetween. The channel part 23D overlaps with a part of the gate electrode 23A and extends along the X-axis direction. One end side part of the channel part 23D is connected to the source electrode 23B. The other end side part of the channel part 23D is connected to the drain electrode 23C. And when the TFT 23 becomes in a conducting state based on the scanning signal supplied to the gate electrode 23A, the image signal (data signal) supplied to the source wiring 27 is supplied from the source electrode 23B to the drain electrode 23C via the channel part 23D including the semiconductor film F3. As a result, the pixel electrode 24 is charged to the potential based on the image signal.

[0077] Mainly with reference to Figure 2 , Figure 5 and Figure 8 the constitution of the pixel electrode 24 will be described. Figure 8 is a top view showing the same range as Figure 2 , and is a top view showing the pattern of the second transparent electrode film F8 (such as the pixel electrode 24). As Figure 2 and Figure 8 shown, the pixel electrode 24 has a pixel electrode main body 24A with a substantially square planar shape that is longitudinally long. The long side of the pixel electrode main body 24A extends along the source wiring 27. Specifically, both side edges on the long side of the pixel electrode main body 24A are slightly inclined with respect to the Y-axis direction. A plurality of (in Figure 2 and Figure 8Among them, there are two (in the figure) slit 24A1. In addition, the specific number of slits 24A1 provided, shape, formation range, etc. can be appropriately changed other than as shown in the figure. In addition, the pixel electrode 24 has a pixel connection portion 24B that protrudes unidirectionally from the pixel electrode main body 24A along the Y-axis direction. The pixel connection portion 24B is arranged to protrude downward from the pixel electrode main body 24A and overlap a part of the drain electrode 23C. As Figure 2 and Figure 8 shown, the pixel connection portion 24B is connected to the drain electrode 23C through the first contact hole CH1. Figure 5 As shown, the pixel connection portion 24B is connected to the drain electrode 23C through the first contact hole CH1.

[0078] Refer to Figure 9 to describe the structure of the common electrode 25. Figure 9 is a top view showing the same range as Figure 2 and is a top view showing the pattern of the first transparent electrode film F6 (common electrode 25, etc.). As Figure 9 shown, the common electrode 25 is arranged in a full-face manner in substantially the entire display area AA. In addition to the slit 25A described above, a plurality of opening portions 25B and a plurality of opening portions 25C are formed in the common electrode 25. A plurality of first opening portions 25B are respectively formed in portions of the common electrode 25 that overlap with a plurality of TFTs 23 (particularly the first contact holes CH). The first opening portion 25B has a substantially rectangular shape that is horizontally long. A plurality of second opening portions 25C are respectively formed in portions of the common electrode 25 that overlap with most of the plurality of touch wirings 31 described later (portions other than the portions that cross the respective gate wirings 26). The second opening portion 25C has a longitudinally long slit shape that extends along the touch wiring 31. The length of the second opening portion 25C is set to be slightly smaller than the interval between the two gate wirings 26 that sandwich the pixel electrode 24 in the Y-axis direction (the arrangement interval of the pixels PX in the Y-axis direction). Through this second opening portion 25C, the parasitic capacitance that may be generated between the touch wiring 31 and the touch electrode 30 that is not connected to the touch wiring 31 is reduced. As a result, the detection sensitivity when detecting the input position of a finger or the like becomes good. In addition, Figure 9 the range shown does not include the slit 25A, so the slit 25A is not shown in Figure 9 .

[0079] Next, mainly using Figure 2 , Figure 4 and Figure 7 to describe the structure of the touch wiring 31. As Figure 2 , Figure 4 and Figure 7As shown, the touch wiring 31 and the source wiring 27 etc. include the same second metal film F4. That is to say, the touch wiring 31 includes the part of the second metal film F4 that is different from the source wiring 27, the source electrode 23B, the drain electrode 23C, etc. The touch wiring 31 is arranged to be adjacent to the source wiring 27 with a space in the X-axis direction. The space between the touch wiring 31 and the source wiring 27 is shorter than the short side dimension of the pixel electrode 24 and is set to the line width degree of most of the touch wiring 31. Thus, a short circuit between the source wiring 27 and the touch wiring 31, both of which include the second metal film F4, is avoided. If the configuration in the X-axis direction is described in detail, the touch wiring 31 is arranged to be adjacent to the source wiring 27 with a space on the side opposite to the side ( Figure 4 and Figure 7 shown on the right side) where the source wiring 27 is connected to the TFT23 ( Figure 4 and Figure 7 shown on the left side). The touch wiring 31 is sandwiched in the X-axis direction between the source wiring 27 adjacent with a space and the TFT23 and the pixel electrode 24 located on the side opposite to the side where the source wiring 27 is connected to the TFT23. The TFT23 and the pixel electrode 24 that sandwich the touch wiring 31 in the X-axis direction with the source wiring 27 are connected to a source wiring 27 different from the source wiring 27 adjacent to the touch wiring 31 with a space. In addition, the source wiring 27 adjacent to the touch wiring 31 with a space is arranged to be sandwiched in the X-axis direction between the pixel electrode 24 connected to itself via the TFT23 and the touch wiring 31.

[0080] The touch wiring 31 extends substantially along the Y-axis direction and bends repeatedly in a zigzag manner in the same way as the source wiring 27. That is to say, the touch wiring 31 is parallel to the source wiring 27 while keeping the space between the touch wiring 31 and the adjacent source wiring 27 substantially fixed. Although most of the touch wiring 31 is set to a fixed line width, the line width of a part thereof becomes narrower. The line width of most of the touch wiring 31 is larger than the line width of the source wiring 27.

[0081] The touch wiring 31 is not arranged adjacent to all the source wirings 27, but is arranged adjacent to specific source wirings 27. Specifically, the touch wiring 31 is intermittently arranged, for example, at a ratio of one touch wiring 31 for every three source wirings 27. Therefore, the number of touch wirings 31 provided is set to, for example, about 1 / 3 of the number of source wirings 27 provided. The arrangement interval in the X-axis direction of the plurality of touch wirings 31 is set to, for example, the amount of three pixels PX. In addition, the number of touch wirings 31 provided and the arrangement interval can be appropriately changed in addition to the above.

[0082] As Figure 10As shown, a sub-wiring (third wiring) 32 electrically connected to the touch wiring 31 is provided on the array substrate 21 according to this embodiment. Figure 10 is a top view schematically showing the connection configurations of the touch electrodes 30, touch wirings 31, sub-wirings 32, etc. in the array substrate 21. In Figure 10 , the connection portions (each contact hole CH2 to CH6) of the touch electrodes 30, touch wirings 31, sub-wirings 32, etc. are illustrated by black dots. In Figure 10 , one touch wiring 31 and the sub-wiring 32 connected to the touch wiring 31 are representatively shown. Further, in Figure 10 , the planar shapes of the touch wiring 31 and sub-wiring 32, etc. are simplified and illustrated as simple straight lines, and the outer shape of the pixel electrode 24 is simplified and illustrated as a simple rectangle. Further, in Figure 10 , in order to ensure easy visibility, the set numbers of the gate wirings 26, pixel electrodes 24, and sub-wirings 32 are reduced from the set numbers in the actual product.

[0083] Use Figure 4 , Figure 6 and Figure 10 to explain the sub-wiring 32 in detail. As Figure 4 , Figure 6 and Figure 10 show, the sub-wiring 32 includes the same first metal film F1 as the gate wiring 26, etc. That is, the sub-wiring 32 includes a portion of the first metal film F1 that is different from the gate wiring 26, gate electrode 23A, etc. The sub-wiring 32 extends substantially along the Y-axis direction (the extending direction of the touch wiring 31). The sub-wiring 32 is arranged such that most of it overlaps with the touch wiring 31 in a top view. Therefore, the gate insulating film F2 is interposed between the sub-wiring 32 including the first metal film F1 and the touch wiring 31 including the second metal film F4. Thus, the two wirings 31, 32 are kept insulated from each other (especially refer to Figure 4 ). Thus, compared with the case where the two wirings are arranged not to overlap, an expansion of the range where there is no wiring is achieved, which is preferable in terms of increasing the aperture ratio of the pixel PX. As Figure 6 shows, a plurality of sub-wirings 32 are arranged to sandwich the gate wiring 26 in the Y-axis direction. Between the sub-wiring 32 and the adjacent gate wiring 26, a gap is provided in the Y-axis direction, and the gap is set to the line width of the gate wiring 26. Thus, a short circuit between the gate wiring 26 and the sub-wiring 32, both of which include the first metal film F1, is avoided. The sub-wirings 32 and the gate wiring 26 are alternately arranged repeatedly in the Y-axis direction.

[0084] As Figure 10As shown, a first connection electrode (first connection portion) 33 is provided on the array substrate 21, and the first connection electrode 33 is connected to two sub-wiring lines 32 arranged sandwiching the gate wiring 26 as described above. In addition, a second connection electrode (second connection portion) 34 that is connected to the sub-wiring line 32 connected to the first connection electrode 33 and the touch wiring 31 is provided on the array substrate 21. Further, a third connection electrode (third connection portion) 35 that is connected to the touch electrode 30 and the touch wiring 31 is provided on the array substrate 21. In addition, in Figure 10 the planar shapes of the first connection electrode 33, the second connection electrode 34, and the third connection electrode 35 are simplified and illustrated. Further, in Figure 10 a representative illustration shows the first connection electrode 33, the second connection electrode 34, and the third connection electrode 35, where the first connection electrode 33 is connected to one touch wiring 31 and the sub-wiring line 32 connected to the touch wiring 31.

[0085] Using Figure 8 、 Figure 10 、 Figure 11 and Figure 12 to illustrate the first connection electrode 33 in detail. Figure 11 is a top view showing the same range as Figure 3 , and is a top view showing the patterns of the first metal film F1 (such as the gate wiring 26 and the sub-wiring line 32), the second metal film F4 (such as the source wiring 26 and the touch wiring 31), and the second transparent electrode film F8 (such as the pixel electrode 24 and the first connection electrode 33). In Figure 11 the first metal film F1, the second metal film F4, and the second transparent electrode film F8 are illustrated with different shading. Figure 12 is Figure 3 's cross-sectional view taken along the C-C line. As Figure 8 , Figure 10 and Figure 11 shown, the first connection electrode 33 is located on the upper layer side relative to the first interlayer insulating film F5 and includes the same second transparent electrode film F8 as the pixel electrode 24. That is, the first connection electrode 33 includes a portion of the second transparent electrode film F8 that is different from the pixel electrode 24. The first connection electrode 33 extends along the Y-axis direction. The first connection electrode 33 is arranged to cross a part of the plurality of gate wirings 26 existing in the display area AA. As Figure 12 shown, the gate insulating film F2, the first interlayer insulating film F5, and the second interlayer insulating film F7 are interposed between the mutually crossing first connection electrode 33 and the gate wiring 26. Thereby, the mutually crossing first connection electrode 33 and the gate wiring 26 are kept in an insulated state.

[0086] As Figure 11As shown, two end portions of the first connection electrode 33 in the Y-axis direction are each formed with a large width. Two large-width portions in the first connection electrode 33 constitute two contact portions 33A that are respectively connected to two sub-wiring lines 32. The two contact portions 33A are arranged such that, although they do not overlap with the gate wiring 26, they overlap with the end portions of the sub-wiring line 32 to be connected. Here, the sub-wiring line (first sub-wiring line) 32 connected to the first connection electrode 33 is arranged such that, although most of it (the central-side portion) except for the two end portions in the Y-axis direction overlaps with the touch wiring 31, the two end portions in the Y-axis direction do not overlap with the touch wiring 31. The two end portions of the sub-wiring line 32 in the Y-axis direction are each of a large width, and these large-width portions constitute the contact portions 32A connected to the first connection electrode 33. In addition, a portion of the touch wiring 31 adjacent to the contact portion 32A of the sub-wiring line 32 is a local narrow-width portion 31A. Thus, the touch wiring 31 is arranged not to overlap with the contact portion 32A of the sub-wiring line 32. As Figure 12 shown, at positions where both the contact portions 33A of the first connection electrode 33 and the contact portions 32A of the sub-wiring line 32 overlap in the gate insulating film F2, the first interlayer insulating film F5, and the second interlayer insulating film F7, second contact holes CH2 are respectively formed by opening. The two contact portions 32A and 33A are connected through the second contact holes CH2.

[0087] Use Figure 10 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 to describe the second connection electrode 34 in detail. Figure 13 And Figure 16 are top views showing the same range as Figure 3 , and are top views showing the patterns of the first metal film F1 (such as the gate wiring 26 and the sub-wiring line 32), the second metal film F4 (such as the source wiring 26 and the touch wiring 31), and the second transparent electrode film F8 (such as the pixel electrode 24 and the second connection electrode 34). In Figure 13 and Figure 16 , the first metal film F1, the second metal film F4, and the second transparent electrode film F8 are shown in different shaded states. Figure 14 is a top view showing the same range as Figure 3 , and is a top view showing the pattern of the first transparent electrode film F6 (such as the common electrode 25, etc.). Figure 15 Is Figure 13 's cross-sectional view taken along line D-D. Figure 17 Is Figure 16 's cross-sectional view taken along line E-E. As Figure 10 , Figure 13 and Figure 16As shown, the second connection electrode 34 is located on the upper side of the first interlayer insulating film F5 and includes the same second transparent electrode film F8 as the pixel electrode 24 and the first connection electrode 33. That is, the second connection electrode 34 includes a portion of the second transparent electrode film F8 that is different from the pixel electrode 24 and the first connection electrode 33. The second connection electrode 34 extends in the Y-axis direction. The second connection electrode 34 is configured to cross a gate wiring 26 different from the gate wiring 26 crossed by the first connection electrode 33 among the plurality of gate wirings 26 existing in the display area AA. As Figure 15 and Figure 17 shown, the gate insulating film F2, the first interlayer insulating film F5, and the second interlayer insulating film F7 are interposed between the mutually crossing second connection electrode 34 and the gate wiring 26. Thereby, the mutually crossing second connection electrode 34 and the gate wiring 26 are kept in an insulating state.

[0088] As Figure 13 and Figure 16 shown, both end portions of the second connection electrode 34 in the Y-axis direction are formed with a large width. One of the two large-width portions of the second connection electrode 34 constitutes a first contact portion 34A connected to the sub-wiring 32, and the other large-width portion constitutes a second contact portion 34B connected to the touch wiring 31. The first contact portion 34A is configured to overlap with the end portion of the sub-wiring 32 to be connected although it does not overlap with the gate wiring 26. The second contact portion 34B is configured to overlap with a part of the touch wiring 31 to be connected although it does not overlap with the gate wiring 26. The sub-wiring (second sub-wiring) 32 connected to the second connection electrode 34 is configured in the same manner as the sub-wiring 32 connected to the first connection electrode 33 described above. The contact portion 32A at one end of the sub-wiring 32 connected to the second connection electrode 34 in the Y-axis direction is connected to the first contact portion 34A of the second connection electrode 34. In contrast, the contact portion 32A at the other end of the sub-wiring 32 connected to the second connection electrode 34 in the Y-axis direction is connected to the contact portion 33A of the first connection electrode 33 (refer to Figures 10 to 12 ). As Figure 15 and Figure 17 shown, at a position where both the first contact portion 34A of the second connection electrode 34 and the contact portion 32A of the sub-wiring 32 overlap in the gate insulating film F2, the first interlayer insulating film F5, and the second interlayer insulating film F7, a third contact hole CH3 is formed as an opening. The two contact portions 32A, 34A are connected through the third contact hole CH3.

[0089] As Figure 13 and Figure 16As shown, the touch wiring 31 has a portion overlapping with the second contact portion 34B of the second connection electrode 34. The overlapping portion of the touch wiring 31 with the second contact portion 34B is locally set to a large width. The large-width portion of the touch wiring 31 overlapping with the second contact portion 34B constitutes the first contact portion 31B connected to the second connection electrode 34. As Figure 15 and Figure 17 shown, at the position where both the second contact portion 34B of the second connection electrode 34 and the first contact portion 31B of the touch wiring 31 overlap in the first interlayer insulating film F5 and the second interlayer insulating film F7, a fourth contact hole CH4 is formed by opening. The two contact portions 31B and 34B are connected through the fourth contact hole CH4.

[0090] As Figure 10 shown, the above-mentioned second connection electrode 34 includes two types of second connection electrodes 34 in which the arrangement of the first contact portion 34A and the second contact portion 34B is reversed. The two types of second connection electrodes 34 include one second connection electrode 34α and the other second connection electrode 34β. As Figure 10 , Figure 13 and Figure 15 shown, the first contact portion 34A of the one second connection electrode 34α is located on the upper side of Figure 10 and Figure 13 , and the second contact portion 34B is located on the lower side of Figure 10 and Figure 13 . As Figure 10 , Figure 16 and Figure 17 shown, the first contact portion 34A of the other second connection electrode 34β is located on the lower side of Figure 10 and Figure 16 , and the second contact portion 34B is located on the upper side of Figure 10 and Figure 16 .

[0091] Use Figure 10 , Figure 18 , Figure 19 and Figure 20 to illustrate the third connection electrode 35 in detail. Figure 18 is a top view showing the same range as Figure 3 , and is a top view showing the patterns of the first metal film F1 (gate wiring 26, sub-wiring 32, etc.), the second metal film F4 (source wiring 26, touch wiring 31, etc.), and the second transparent electrode film F8 (pixel electrode 24, third connection electrode 35, etc.). In Figure 18 , the first metal film F1, the second metal film F4, and the second transparent electrode film F8 are shown in different shaded states. Figure 19 is a view showing the same range as Figure 3A plan view of the same range, which is a plan view showing the pattern of the first transparent electrode film F6 (common electrode 25, etc.). Figure 20 is Figure 18 a cross-sectional view taken along line F-F. As Figure 10 and Figure 18 shown, the third connection electrode 35 is located on the upper layer side of the first interlayer insulating film F5 and includes the same second transparent electrode film F8 as the pixel electrode 24, the first connection electrode 33, and the second connection electrode 34. That is, the third connection electrode 35 includes a part of the second transparent electrode film F8 that is different from the pixel electrode 24, the first connection electrode 33, and the second connection electrode 34. The third connection electrode 35 extends along the Y-axis direction. The third connection electrode 35 is configured to cross a gate wiring 26 different from the gate wirings 26 that the first connection electrode 33 and the second connection electrode 34 cross among the plurality of gate wirings 26 existing in the display area AA. As Figure 20 shown, the gate insulating film F2, the first interlayer insulating film F5, and the second interlayer insulating film F7 are interposed between the intersecting third connection electrode 35 and the gate wiring 26. Thus, the intersecting third connection electrode 35 and the gate wiring 26 are kept in an insulating state. As Figure 19 and Figure 20 shown, the third connection electrode 35 is configured such that at least a part of it overlaps with the touch electrode 30, and the second interlayer insulating film F7 is interposed between the third connection electrode 35 and the touch electrode 30.

[0092] As Figure 18 shown, the entire length of the third connection electrode 35 in the Y-axis direction is set to have a substantially fixed width. One of the two end portions of the third connection electrode 35 in the Y-axis direction constitutes a first contact portion 35A connected to the touch wiring 31, and the other end portion constitutes a second contact portion 35B connected to the touch electrode 30. The first contact portion 35A is configured to overlap with a part of the touch wiring 31 to be connected although it does not overlap with the gate wiring 26. The second contact portion 35B is configured to overlap with a part of the touch electrode 30 to be connected although it does not overlap with the gate wiring 26.

[0093] As Figure 18 shown, the touch wiring 31 has a part that overlaps with the first contact portion 35A of the third connection electrode 35. The overlapping portion of the touch wiring 31 with the first contact portion 35A is locally set to have a large width. The large-width portion of the touch wiring 31 that overlaps with the first contact portion 35A constitutes a second contact portion 31C connected to the third connection electrode 35. As Figure 20As shown, at the position where both the first contact portion 35A of the third connection electrode 35 and the second contact portion 31C of the touch wiring 31 overlap in the first interlayer insulating film F5 and the second interlayer insulating film F7, a fifth contact hole CH5 is formed by opening. The two contact portions 31C and 35A are connected through the fifth contact hole CH5.

[0094] As Figure 19 and Figure 20 shown, the touch electrode 30 has a portion that overlaps with the second contact portion 35B of the third connection electrode 35. The overlapping portion of the touch electrode 30 with the second contact portion 35B of the third connection electrode 35 constitutes the first contact portion 30A connected to the second contact portion 31C. The first contact portion 30A of the touch electrode 30 is ensured by narrowing the formation range of a specific second opening portion 25C of the common electrode 25. As Figure 20 shown, at the position where both the second contact portion 35B of the third connection electrode 35 and the first contact portion 30A of the touch electrode 30 overlap in the second interlayer insulating film F7, a sixth contact hole CH6 is formed by opening. The two contact portions 30A and 35B are connected through the sixth contact hole CH6.

[0095] As Figure 10 , Figure 13 , Figure 15 , Figure 16 and Figure 17 shown, a first dummy wiring (dummy wiring) 36 that is not connected to the second connection electrode 34 is provided on the array substrate 21. The first dummy wiring 36 is configured to be substantially the same as the sub-wiring 32. The first dummy wiring 36 and the gate wiring 26 etc. include the same first metal film F1. That is, the first dummy wiring 36 includes a portion of the first metal film F1 that is different from the gate wiring 26, the gate electrode 23A, and the sub-wiring 32 etc. The first dummy wiring 36 extends substantially along the Y-axis direction. The first dummy wiring 36 is arranged such that most of it overlaps with the touch wiring 31 in a top view. Therefore, the gate insulating film F2 is interposed between the first dummy wiring 36 including the first metal film F1 and the touch wiring 31 including the second metal film F4. Thus, the two wirings 31 and 36 are kept insulated from each other (especially refer to Figure 15 and Figure 17 ). The first dummy wiring 36 is arranged such that the gate wiring 26 that intersects the second connection electrode 34 is sandwiched between it and the sub-wiring 32 connected to the second connection electrode 34 in the Y-axis direction. The first dummy wiring 36 has a planar shape that is substantially the same as the sub-wiring 32, and both end portions in the Y-axis direction are formed with large widths. One of the two large-width portions of the first dummy wiring 36 overlaps with the second contact portion 34B of the second connection electrode 34 (34α) located on the Figure 10 upper side (refer to Figure 13and Figure 15 ). The other large-width portion of the two large-width portions of the first dummy wiring 36 overlaps with the second contact portion 34B of the second connection electrode 34(34β) located on the lower side of Figure 10 (see Figure 16 and Figure 17 ). However, the two large-width portions of the first dummy wiring 36 are both set not to be connected to the second connection electrode 34.

[0096] As Figure 10 , Figure 18 and Figure 20 show, a second dummy wiring 37 that is not connected to the third connection electrode 35 is provided on the array substrate 21. The second dummy wiring 37 is configured to have substantially the same structure as the sub-wiring 32 and the first dummy wiring 36. The second dummy wiring 37 includes the same first metal film F1 as the gate wiring 26 and the like. That is, the second dummy wiring 37 includes a portion of the first metal film F1 that is different from the gate wiring 26, the gate electrode 23A, the sub-wiring 32, and the first dummy wiring 36. The second dummy wiring 37 extends substantially along the Y-axis direction. The second dummy wiring 37 is arranged such that most of it overlaps with the touch wiring 31 in a top view. Therefore, the gate insulating film F2 is interposed between the second dummy wiring 37 including the first metal film F1 and the touch wiring 31 including the second metal film F4. Thus, the two wirings 31 and 37 are kept insulated from each other (especially refer to Figure 20 ). Two second dummy wirings 37 are arranged so as to sandwich the gate wiring 26 that intersects the third connection electrode 34 in the Y-axis direction. The second dummy wiring 37 has substantially the same planar shape as the sub-wiring 32 and the first dummy wiring 36, and both end portions in the Y-axis direction are formed into large-width portions. The two large-width portions of the second dummy wiring 37 overlap with the first contact portion 35A and the second contact portion 35B of the third connection electrode 35 respectively (see Figure 20 ). However, the two large-width portions of the second dummy wiring 37 are both set not to be connected to the third connection electrode 35.

[0097] Next, Figure 10 is used to illustrate the arrangement of the first connection electrode 33, the second connection electrode 34, and the third connection electrode 35 in a plurality of touch electrodes 30 arranged along the Y-axis direction. Hereinafter, one touch wiring 31 representatively shown in Figure 10 will be described, but the same applies to other touch wirings 31 not shown in Figure 10 . The second connection electrode 34 is arranged near the end portion in the Y-axis direction of the touch electrode 30. Specifically, one second connection electrode 34α is arranged to straddle two adjacent ones in the Y-axis direction that are both connected to Figure 10The first slit 25A1 that separates two touch electrodes 30 not connected to the touch wiring 31. One second connection electrode 34α is arranged to cross the gate wiring 26 arranged in the first slit 25A1. The gate wiring 26 that crosses the one second connection electrode 34α is arranged so as not to overlap with the touch electrode 30. The other second connection electrode 34β is arranged to cross the gate wiring 26 that is spaced apart from the gate wiring 26 arranged in the first slit 25A1 that separates two touch electrodes 30 adjacent in the Y-axis direction by a space in the Figure 10 lower side and adjacent at an interval. The gate wiring 26 that crosses the other second connection electrode 34β is arranged to overlap with the touch electrode 30. Between the one second connection electrode 34α and the other second connection electrode 34β located above the one second connection electrode 34α Figure 10 there is a space that is slightly shorter than one side of the touch electrode 30. Based on the arrangement of the second connection electrode 34 as described above, the first dummy wiring 36 is arranged as follows: It is sandwiched in the Y-axis direction between the gate wiring 26 arranged in the first slit 25A1 that separates two touch electrodes 30 adjacent in the Y-axis direction and the gate wiring 26 that crosses the other second connection electrode 34β.

[0098] The first connection electrode 33 is arranged in a plurality of ways so as to cross respectively with Figure 10 most of the gate wirings 26 that overlap with the touch electrodes 30 not connected to the touch wiring 31 (all except the gate wiring 26 that crosses the other second connection electrode 34β). The number of the first connection electrodes 33 provided in each touch electrode 30 is the number obtained by subtracting 1 from the total number of the gate wirings 26 that overlap with one touch electrode 30. A plurality of sub-wirings 32 are arranged so as to sandwich respectively in the Y-axis direction the gate wirings 26 that cross the respective first connection electrodes 33. Figure 10 The number of the sub-wirings 32 provided in the touch electrodes 30 not connected to the touch wiring 31 is one more than the number of the first connection electrodes 33. Between the one second connection electrode 34α and the other second connection electrode 34β located above the one second connection electrode 34α Figure 10 the sub-wirings 32 and the gate wirings 26 are alternately arranged in the Y-axis direction. In this way, being sandwiched between the one second connection electrode 34α and the other second connection electrode 34β located above the one second connection electrode 34α Figure 10A plurality of sub-wiring lines 32 between the other second connection electrodes 34β on the upper side of constitute one wiring group. Two sub-wiring lines 32 located at both ends in the Y-axis direction among the plurality of sub-wiring lines 32 constituting one wiring group are connected to the first connection electrode 33 and the second connection electrode 34. Among the plurality of sub-wiring lines 32 located on the central side other than both ends in the Y-axis direction among the plurality of sub-wiring lines 32 constituting one wiring group, all are connected only to the first connection electrode 33. The plurality of sub-wiring lines 32 constituting one wiring group and the plurality of first connection electrodes 33 connected to each sub-wiring line 32 can be regarded as one wiring (hereinafter referred to as the first connection wiring 38) having a length slightly shorter than one side of the touch electrode 30. Both ends of the first connection wiring 38 are connected to the touch wiring 31 by the second connection electrode 34. The wiring resistance of the touch wiring 31 connected to the first connection wiring 38 decreases, and the redundancy is improved. The number of the first connection wirings 38 connected to the touch wiring 31 is the same as the number of touch electrodes 30 that the touch wiring 31 crosses until it reaches the touch electrode 30 to be connected from the driver 11. Therefore, the longer the wiring length of the touch wiring 31 from the driver 11 until it reaches the touch electrode 30 to be connected, the more the number of the first connection wirings 38 connected thereto. As a result, the wiring resistance of the touch wiring 31 with a large wiring length decreases sufficiently, and high redundancy can be obtained. Since the wiring resistance of the touch wiring 31 is reduced as described above, the line width of the touch wiring 31 can be narrowed. If the line width of the touch wiring 31 becomes narrow, the range where there is no wiring in the plane of the array substrate 21, that is, the region where the pixels PX are arranged is enlarged. As a result, the aperture ratio of the liquid crystal panel 10 becomes high.

[0099] The third connection electrode 35 is arranged in a plurality of ways so as to cross all the gate wirings 26 overlapping with Figure 10 the touch electrodes 30 connected to the touch wiring 31. Figure 10 The number of the third connection electrodes 35 provided in the touch electrodes 30 connected to the touch wiring 31 is the same as the total number of the gate wirings 26 overlapping one touch electrode 30. A plurality of second dummy wirings 37 are arranged so as to sandwich each gate wiring 26 crossing each third connection electrode 35 in the Y-axis direction, respectively. Figure 10 The number of the second dummy wirings 37 provided in the touch electrodes 30 connected to the touch wiring 31 is one more than the number of the third connection electrodes 35.

[0100] And, as Figure 10As shown, the first connection electrode 33 is connected to two sub-wiring lines 32 sandwiching the gate wiring 26. Therefore, near the gate wiring 26 that intersects the first connection electrode 33, there are two connection portions (second contact holes CH2) of the first connection electrode 33. The second connection electrode 34 is connected to the sub-wiring line 32 connected to the first connection electrode 33 and the touch wiring 31. Therefore, near the gate wiring 26 that intersects the second connection electrode 34, there are two connection portions (third contact hole CH3, fourth contact hole CH4) of the second connection electrode 34. The third connection electrode 35 is connected to the touch electrode 30 and the touch wiring 31 at a position sandwiching the gate wiring 26. Therefore, near the gate wiring 26 that intersects the third connection electrode 35, there are two connection portions (fifth contact hole CH5, sixth contact hole CH6) of the third connection electrode 35. Thus, the number of each of the contact holes CH2 to CH6, which are the connection portions existing near the gate wiring 26, is two each. Therefore, compared with the case where there are three contact ports each as connection portions near each gate wiring as in the past, the number of connection portions existing near each gate wiring 26 can be reduced. If the number of connection portions is reduced, it is less likely that the alignment disorder of liquid crystal molecules is caused by each of the contact holes CH2 to CH6 as connection portions. As a result, defects such as display defects are less likely to occur. In addition, there is no need to take countermeasures such as expanding the light-shielding portion 29 to avoid defects caused by the connection portions. If the light-shielding portion 29 does not need to be expanded, the area where the pixel PX is arranged can be expanded. As a result, the aperture ratio of the liquid crystal panel 10 becomes higher.

[0101] As described above, the array substrate (active matrix substrate) 21 of the present embodiment includes: gate wirings 26 included in a plurality of first wirings, the plurality of first wirings including a first metal film (first conductive film) F1, extending along a first direction, and being arranged at intervals in a second direction intersecting the first direction; a gate insulating film (first insulating film) F2 disposed on the upper side of the first metal film F1; touch wirings 31 included in second wirings, the second wirings including a second metal film (second conductive film) F4 disposed on the upper side of the gate insulating film F2, extending along the second direction intersecting the first direction, and intersecting with the plurality of gate wirings 26 included in the plurality of first wirings with the gate insulating film F2 therebetween; sub-wirings 32 included in a plurality of third wirings, the plurality of third wirings including a portion of the first metal film F1 different from the gate wirings 26 included in the first wirings, extending along the second direction, and at least a part thereof overlapping with the touch wirings 31 included in the second wirings with the gate insulating film F2 therebetween, the plurality of third wirings being arranged to sandwich the gate wirings 26 included in the first wirings in the second direction; a first interlayer insulating film (second insulating film) F5 disposed on the upper side of the second metal film F4; a first connection electrode (first connection portion) 33 disposed on the upper side of the first interlayer insulating film F5, intersecting with the gate wirings 26 included in a part of the first wirings among the plurality of first wirings with the gate insulating film F2 and the first interlayer insulating film F5 therebetween, and connected to two sub-wirings 32 included in two third wirings sandwiching the gate wirings 26 included in the first wirings; and a second connection electrode (second connection portion) 34 disposed on the upper side of the first interlayer insulating film F5, intersecting with the gate wirings 26 included in the first wirings different from the gate wirings 26 intersected by the first connection electrode 33 with the gate insulating film F2 and the first interlayer insulating film F5 therebetween, and connected to the sub-wirings 32 included in the third wirings connected to the first connection electrode 33 and the touch wirings 31 included in the second wirings.

[0102] In this way, the touch wirings 31 included in the second wirings are electrically connected to the two sub-wirings 32 included in the two third wirings via the first connection electrode 33 and the second connection electrode 34. Thereby, a reduction in the wiring resistance of the touch wirings 31 included in the second wirings is achieved. In addition, the sub-wirings 32 included in the third wirings including a portion of the first metal film F1 different from the gate wirings 26 included in the first wirings are arranged such that at least a part thereof overlaps with the touch wirings 31 included in the second wirings with the gate insulating film F2 therebetween. Thereby, an expansion of the range where there is no wiring is achieved. Further, the sub-wirings 32 included in the third wirings and the gate wirings 26 included in the first wirings are arranged not to overlap as described above, thereby avoiding a short circuit.

[0103] The first connection electrode 33 is connected to two sub-wiring lines 32 included in two third wirings that sandwich the gate wiring 26 included in the first wiring. Therefore, there are two connection portions of the first connection electrode 33 near the gate wiring 26 included in the first wiring that intersects the first connection electrode 33. The second connection electrode 34 is connected to the sub-wiring line 32 included in the third wiring connected to the first connection electrode 33 and the touch wiring 31 included in the second wiring. Therefore, there are two connection portions of the second connection electrode 34 near the gate wiring 26 included in the first wiring that intersects the second connection electrode 34. Thus, the number of connection portions existing near each gate wiring 26 is two each. Therefore, compared with the case where there are three contact ports each as connection portions near each gate wiring as in the past, the number of connection portions existing near each gate wiring 26 can be reduced. If the number of connection portions is reduced, defects caused by the connection portions are less likely to occur. In addition, there is no need to take measures to avoid defects caused by the connection portions.

[0104] In addition, it includes: a touch electrode (position detection electrode) 30 disposed on the upper layer side of the first interlayer insulating film F5; and a touch wiring (position detection wiring) 31 extending along the second direction and connected to the touch electrode 30. The second wiring includes the touch wiring 31. In this way, the wiring resistance of the touch wiring 31 included in the second wiring is reduced. As a result, the signal supplied from the touch wiring 31 to the touch electrode 30 is less likely to be dulled. Therefore, the position detection sensitivity is improved.

[0105] In addition, a plurality of first wirings include gate wirings 26 as the first wirings that overlap with touch electrodes 30 connected to touch wirings 31 and cross the touch wirings 31 with a gate insulating film F2 therebetween, and include third connection electrodes (third connection portions) 35. The third connection electrodes 35 are disposed on the upper layer side of the first interlayer insulating film F5, overlap with the touch electrodes 30, and cross the gate wirings 26 as the first wirings that cross the touch wirings 31 with the gate insulating film F2 and the first interlayer insulating film F5 therebetween, and are connected to the touch wirings 31 and the touch electrodes 30. In this way, signals transmitted to the touch wirings 31 are supplied to the touch electrodes 30 via the third connection electrodes 35. Similar to the first connection electrodes 33 and the second connection electrodes 34, the third connection electrodes 35 are disposed to cross the gate wirings 26 as the first wirings with the gate insulating film F2 and the first interlayer insulating film F5 therebetween. Therefore, the connection portions of the touch wirings 31 and the touch electrodes 30 with the third connection electrodes 35 are configured similarly to the connection portions of the two sub-wirings 32 included in the two third wirings with the first connection electrodes 33 and the connection portions of the touch wirings 31 included in the second wiring and the sub-wirings 32 included in the third wiring with the second connection electrodes 34. As a result, the connection portions of the third connection electrodes 35 are less likely to be conspicuous.

[0106] In addition, it includes: a TFT (switching element) 23 disposed on the lower layer side of the first interlayer insulating film F5; a pixel electrode 24 disposed on the upper layer side of the first interlayer insulating film F5 and connected to the TFT 23; and a second interlayer insulating film (third insulating film) F7 disposed on the upper layer side of the first interlayer insulating film F5. The touch electrode 30 includes a first transparent electrode film F6, and the pixel electrode 24 includes a second transparent electrode film F8, which is configured to overlap the touch electrode 30 with the second interlayer insulating film F7 therebetween. The first connection electrode 33 and the second connection electrode 34 include a portion of the second transparent electrode film F8, which is the transparent electrode film disposed on the upper layer side of the second interlayer insulating film F7, different from the pixel electrode 24, among the first transparent electrode film F6 and the second transparent electrode film F8. In order to connect the electrodes disposed on the upper layer side of the second interlayer insulating film F7 in the pixel electrode 24 and the touch electrode 30 to a connection object (TFT 23 or touch wiring 31), for example, an opening can be provided in the second interlayer insulating film F7 between the electrode and the connection object. Similarly, in order to connect the first connection electrode 33 and the second connection electrode 34 to the wiring to be connected, for example, an opening can be provided in the insulating film between the first connection electrode 33 and the second connection electrode 34 and the wiring to be connected. Here, the first connection electrode 33 and the second connection electrode 34 include a portion of the second transparent electrode film F8, which is the transparent electrode film disposed on the upper layer side of the second interlayer insulating film F7, different from the pixel electrode 24, among the first transparent electrode film F6 and the second transparent electrode film F8. Therefore, at least in the second interlayer insulating film F7, an opening for connecting the first connection electrode 33 and the second connection electrode 34 to the wiring to be connected and an opening for connecting the electrodes disposed on the upper layer side of the second interlayer insulating film F7 in the pixel electrode 24 and the touch electrode 30 to the connection object can be provided together. Thereby, the manufacturing becomes easy. The formation range of the pixel electrode 24 is limited compared to the touch electrode 30. Therefore, if the first connection electrode 33 and the second connection electrode 34 are formed of the portion of the second transparent electrode film F8 different from the pixel electrode 24, the first connection electrode 33 and the second connection electrode 34 can be provided without reducing the formation range of the pixel electrode 24.

[0107] In addition, it includes: a TFT 23; a pixel electrode 24 connected to the TFT 23; a gate wiring (scanning wiring) 26 extending along a first direction and connected to the TFT 23; and a source wiring (signal wiring) 27 extending along a second direction and connected to the TFT 23. The first wiring includes the gate wiring 26. The source wiring 27 includes a portion in the second metal film F4 that is different from the touch wiring 31 included in the second wiring, and is configured to be arranged at intervals in the first direction with respect to the touch wiring 31. When the TFT 23 is driven based on a signal supplied by the gate wiring 26, the pixel electrode 24 is charged to a potential based on the signal supplied to the source wiring 27. Since the source wiring 27 includes a portion in the second metal film F4 that is different from the touch wiring 31 included in the second wiring, the number of layers in the array substrate 21 can be reduced. On the other hand, since the source wiring 27 and the touch wiring 31 are arranged at intervals in the first direction, there is a problem that the range where there is no wiring is reduced. In this regard, since the touch wiring 31 included in the second wiring is connected to the sub-wiring 32 included in the third wiring through the first connection electrode 33 and the second connection electrode 34, the wiring resistance is reduced. As a result, even if the line width of the touch wiring 31 is narrowed, a sufficiently low wiring resistance can be ensured, and thus the range where there is no wiring can be sufficiently ensured.

[0108] In addition, it includes a first dummy wiring (dummy wiring) 36. The first dummy wiring 36 includes a portion in the first metal film F1 that is different from the gate wiring 26 included in the first wiring, extends along the second direction, and at least a part of it overlaps with the touch wiring 31 included in the second wiring with a gate insulating film F2 therebetween. The first dummy wiring 36 is configured such that in the second direction, the gate wiring 26, which is the first wiring intersecting with the second connection electrode 34, is sandwiched between the first dummy wiring 36 and the sub-wiring 32 included in the third wiring connected to the second connection electrode 34, and the first dummy wiring 36 is not connected to the second connection electrode 34. In this way, since the first dummy wiring 36 is not connected to the second connection electrode 34, it does not contribute to reducing the resistance of the touch wiring 31 included in the second wiring. However, since the first dummy wiring 36 has the same structure as the sub-wiring 32 included in the third wiring, the uneven shapes of the films on the upper layer side of the first dummy wiring 36 can be made the same as the uneven shapes of the films on the upper layer side of the sub-wiring 32 included in the third wiring. As a result, the coverage rates of the films F2 to F8 on the upper layer side of the first metal film F1 can be ensured well. In addition, when performing photo-alignment treatment on the alignment film, it is not easy to generate differences in the alignment treatment near the sub-wiring 32 and near the first dummy wiring 36.

[0109] In addition, the second connection electrode 34 is connected to the touch wiring 31 included in the second wiring at a position where the sub-wiring 32 included in the third wiring to which the second connection electrode 34 is connected sandwiches the gate wiring 26 as the first wiring in the second direction. In this way, the connection portions of the second connection electrode 34 with the touch wiring 31 included in the second wiring and the sub-wiring 32 included in the third wiring are arranged with the gate wiring 26 as the first wiring sandwiched therebetween. This arrangement is similar to the arrangement in which the connection portions of the first connection electrode 33 with the two sub-wirings 32 included in the two third wirings sandwich the gate wiring 26 as the first wiring. Therefore, the connection portions of the second connection electrode 34 are less likely to be conspicuous.

[0110] In addition, the liquid crystal panel (display device) 10 according to the present embodiment includes: the array substrate 21 described above; and a CF substrate (opposing substrate) 20 that is arranged to oppose the array substrate 21. According to such a liquid crystal panel 10, defects caused by connection portions are less likely to occur, and countermeasures for avoiding defects caused by connection portions are not required. As a result, improvement in display quality is achieved, and improvement in aperture ratio is achieved.

[0111] <Embodiment 2>

[0112] According to Figure 21 Embodiment 2 will be described. In this Embodiment 2, a case where a second connection wiring (second wiring, connection wiring) 39 and the like are added is shown. In addition, redundant descriptions of the same structures, operations, and effects as those in the above Embodiment 1 are omitted.

[0113] As Figure 21 shown, a second connection wiring (second wiring, connection wiring) 39 is provided on the array substrate 121 according to the present embodiment. The second connection wiring 39 is arranged to overlap the touch electrode 130 and is connected to the overlapping touch electrode 130. Figure 21 is a top view schematically showing the connection forms of the touch electrode 130, touch wiring 131, sub-wiring 132, second connection wiring 39, etc. in the array substrate 121. In Figure 21 , among the three touch electrodes 130 arranged in the Y-axis direction, the touch electrode 130 at the center in the Y-axis direction is connected to the touch wiring 131 shown at the left end. In Figure 21 , among the three touch electrodes 130 arranged in the Y-axis direction, the lower touch electrode 130 is connected to the touch wiring 131 shown at the center in the left-right direction. In addition, in Figure 21 , among the three touch electrodes 130 arranged in the Y-axis direction, the upper touch electrode 130 is connected to the touch wiring 131 that is not shown in Figure 21 . In Figure 21In order to ensure easy visibility, the number of gate wirings 126, pixel electrodes 124, touch wirings 131, sub-wirings 132, and second connection wirings 39 is reduced from the number in the actual product. Additionally, in Figure 21 as in Figure 10 similarly, the planar shapes of the respective wirings 131, 132, 39 or the outer shapes of the pixel electrodes 124, etc. are simplified and illustrated.

[0114] The second connection wiring 39 and the source wiring 27, the touch wiring 131, etc. include the same second metal film F4 (refer to Figure 12 ). That is, the second connection wiring 39 includes the part of the second metal film F4 that is different from the source wiring 27, the touch wiring 131, etc. The second connection wiring 39 is configured to overlap with the touch electrode 130 that is on the side opposite to the driver side ( Figure 21 the lower side) in the Y-axis direction with respect to the touch electrode 130 connected to the touch wiring 131 ( Figure 21 the upper side). The second connection wiring 39 is arranged in the X-axis direction to be consistent with the touch wiring 131 connected to the touch electrode 130. That is, the second connection wiring 39 is located on the extension line of the touch wiring 131 connected to the touch electrode 130, on the side opposite to the driver side in the Y-axis direction. The second connection wiring 39 extends substantially along the Y-axis direction and bends repeatedly in a zigzag manner, similar to the touch wiring 131. The second connection wiring 39 is arranged to be sandwiched between the pixel electrode 124 and the source wiring 27 in the X-axis direction, and detailed description is omitted (refer to Figure 2 ). The formation range of the second connection wiring 39 in the Y-axis direction is the formation range of the touch electrode 130 it overlaps, which is different from the touch wiring 131 in this regard. And the two end side portions of the second connection wiring 39 in the Y-axis direction are connected to the overlapping touch electrode 130.

[0115] A fourth connection electrode (fourth connection portion) 40 connected to the second connection wiring 39 and the touch electrode 130 is provided on the array substrate 121. The fourth connection electrode 40 and the pixel electrode 124, the first connection electrode 133, the second connection electrode 134, and the third connection electrode 135 include the same second transparent electrode film F8 (refer to Figure 12 ). That is, the fourth connection electrode 40 includes the part of the second transparent electrode film F8 that is different from the pixel electrode 124, the first connection electrode 133, the second connection electrode 134, and the third connection electrode 135. The fourth connection electrode 40 extends along the Y-axis direction in the same way as the respective connection electrodes 133 to 135 and crosses the gate wiring 126 including the first metal film F1 (refer to Figure 12)。The gate wiring 126 that intersects the fourth connection electrode 40 is configured to intersect the second connection wiring 39 including the second metal film F4 and overlap the touch electrode 130 connected to the second connection wiring 39. Two fourth connection electrodes 40 are arranged so as to intersect two gate wirings 126 that respectively intersect the two end portions in the Y-axis direction of the second connection wiring 39. The interval between the two fourth connection electrodes 40 is set to a length slightly shorter than one side of the touch electrode 130.

[0116] The objects connected to the fourth connection electrode 40 are the second connection wiring 39 having the same structure as the touch wiring 131 and the touch electrode 130. Therefore, the structure of the fourth connection electrode 40 is substantially the same as that of the third connection electrode 135. The fourth connection electrode 40 is arranged such that at least a part of it overlaps the touch electrode 130. One end portion in the Y-axis direction of the fourth connection electrode 40 constitutes a first contact portion connected to the second connection wiring 39, and the other end portion constitutes a second contact portion connected to the touch electrode 130. The second connection wiring 39 has a portion that overlaps the first contact portion of the fourth connection electrode 40. The portion of the second connection wiring 39 that overlaps the first contact portion of the fourth connection electrode 40 constitutes the first contact portion connected to the fourth connection electrode 40. At the position where both the first contact portion of the fourth connection electrode 40 and the first contact portion of the second connection wiring 39 overlap in the first interlayer insulating film F5 and the second interlayer insulating film F7, a seventh contact hole CH7 is formed (refer to Figure 20 ). The second connection wiring 39 and the fourth connection electrode 40 are connected through the seventh contact hole CH7. The touch electrode 130 has a portion that overlaps the second contact portion of the fourth connection electrode 40. The overlapping portion of the touch electrode 130 with the second contact portion of the fourth connection electrode 40 constitutes the second contact portion connected to the second contact portion of the fourth connection electrode 40. At the position where both the second contact portion of the fourth connection electrode 40 and the second contact portion of the touch electrode 130 overlap in the second interlayer insulating film F7, an eighth contact hole CH8 is formed (refer to Figure 20 ). The fourth connection electrode 40 and the touch electrode 130 are connected through the eighth contact hole CH8.

[0117] On the array substrate 121, a third dummy wiring 41 that is not connected to the fourth connection electrode 40 is provided. The third dummy wiring 41 is configured to have substantially the same structure as the sub-wiring 132, the first dummy wiring 136, and the second dummy wiring 137. The third dummy wiring 41 includes the same first metal film F1 as the gate wiring 126 and the like. That is, the third dummy wiring 41 includes a portion of the first metal film F1 that is different from the gate wiring 126, the sub-wiring 132, the first dummy wiring 136, and the second dummy wiring 137. The third dummy wiring 41 extends substantially along the Y-axis direction. The third dummy wiring 41 is arranged such that most of it overlaps with the second connection wiring 39 in a top view. Therefore, the gate insulating film F2 is interposed between the third dummy wiring 41 including the first metal film F1 and the second connection wiring 39 including the second metal film F4 (see ​ ). The third dummy wiring 41 is arranged adjacent to the gate wiring 126 that intersects the fourth connection electrode 40 on the ​ lower side. The two end portions of the third dummy wiring 41 in the Y-axis direction overlap with the first contact portion and the second contact portion of the fourth connection electrode 40, respectively. However, the two end portions of the third dummy wiring 41 in the Y-axis direction are both set to be not connected to the fourth connection electrode 40.

[0118] On the array substrate 121, in addition to the above-described fourth connection electrode 40, a sub-wiring 132, a first connection electrode 133, and a second connection electrode 134 that are electrically connected to the second connection wiring 39 are provided. The sub-wiring 132 is arranged such that most of it overlaps with the second connection wiring 39 in a top view. Therefore, the gate insulating film F2 is interposed between the sub-wiring 132 including the first metal film F1 and the second connection wiring 39 including the second metal film F4 (see ​)。Two second connection electrodes 134 are arranged in such a manner that they are located on the central side in the Y-axis direction of the second connection wiring 39 with respect to the two fourth connection electrodes 40 described above. The two second connection electrodes 134 are arranged to cross two gate wirings 126 that are adjacent to the two gate wirings 126 that cross the two fourth connection electrodes 40 with a space therebetween on the central side in the Y-axis direction. A plurality of first connection electrodes 133 are arranged in such a manner that they are located on the central side in the Y-axis direction of the second connection wiring 39 with respect to the two second connection electrodes 134 described above. The plurality of first connection electrodes 133 are arranged to cross all the gate wirings 126 that are located on the central side in the Y-axis direction with respect to the two gate wirings 126 that cross the two second connection electrodes 134, respectively. A plurality of sub-wirings 132 are arranged in such a manner that they sandwich the respective gate wirings 126 that cross the respective first connection electrodes 133 in the Y-axis direction. The plurality of sub-wirings 132 are sandwiched between the two second connection electrodes 134 in the Y-axis direction and constitute a wiring group. The plurality of sub-wirings 132 that constitute the wiring group and the plurality of first connection electrodes 133 connected to the plurality of sub-wirings 132 constitute a first connection wiring 138. Both ends of the first connection wiring 138 are connected to the second connection wiring 39 by the second connection electrodes 134. The wiring resistance of the second connection wiring 39 connected to the first connection wiring 138 is reduced, and the redundancy is improved. In addition, two third dummy wirings 41 are arranged in such a manner that they are adjacent to the two fourth connection electrodes 40 described above on the central side in the Y-axis direction. In addition, the first dummy wiring 136 is arranged at a position where it sandwiches the gate wiring 126 in the Y-axis direction between the two third dummy wirings 41 described above, with the lower third dummy wiring 41 being one of them.

[0119] As described above, according to the present embodiment, the second connection wiring (connection wiring) 39 is provided. The second connection wiring 39 is arranged to overlap with the touch electrode 130, extends along the second direction, and at least the end portions on both sides are connected to the overlapping touch electrode 130. The second wiring includes the second connection wiring 39. In this way, since the wiring resistance of the second connection wiring 39 included in the second wiring is reduced, the resistance distribution of the touch electrode 130 connected to the second connection wiring 39 is less likely to be biased. Thereby, the position detection sensitivity is improved.

[0120] In addition, the first wiring includes a gate wiring 126 as the first wiring that overlaps with a touch electrode 130 connected to a second connection wiring 39 and crosses the second connection wiring 39 with a gate insulating film F2 therebetween. The fourth connection electrode (fourth connection portion) 40 is provided. The fourth connection electrode 40 is disposed on the upper layer side of the first interlayer insulating film F5, overlaps with the touch electrode 130, and crosses the gate wiring 126 as the first wiring that crosses the second connection wiring 39 with the gate insulating film F2 and the first interlayer insulating film F5 therebetween, and is connected to the second connection wiring 39 and the touch electrode 130. In this way, similar to the first connection electrode 133 and the second connection electrode 134, the fourth connection electrode 40 is disposed to cross the gate wiring 126 as the first wiring with the gate insulating film F2 and the first interlayer insulating film F5 therebetween. Therefore, each connection portion of the second connection wiring 39 and the touch electrode 130 with the fourth connection electrode 40 becomes an arrangement similar to each connection portion of the sub-wiring 132 included in the two third wirings with the first connection electrode 133, and each connection portion of the touch wiring 131 and the sub-wiring 132 included in the second wiring and the third wiring with the second connection electrode 134. As a result, the connection portion of the fourth connection electrode 40 is not likely to be conspicuous.

[0121] In addition, the plurality of first wirings include a plurality of gate wirings 126 as the first wirings that cross the second connection wiring 39 with a gate insulating film F2 therebetween and are arranged at intervals in the second direction. The plurality of third wirings include a plurality of sub-wirings 132 as the third wirings that are arranged to overlap at least a part of the second connection wiring 39 with a gate insulating film F2 therebetween. The fourth connection electrode 40 includes two fourth connection electrodes 40 that cross two gate wirings 126 as the first wirings that cross the two end portions in the second direction of the second connection wiring 39 respectively. The second connection electrode 134 includes two second connection electrodes 134 located on the central side in the second direction of the second connection wiring 39 with respect to the two fourth connection electrodes 40. The first connection electrode 133 includes a plurality of first connection electrodes 133 located on the central side in the second direction of the second connection wiring 39 with respect to the two second connection electrodes 134. In this way, the portion of the second connection wiring 39 on the central side with respect to the two end portions connected to the touch electrode 130 by the two fourth connection electrodes 40 is connected to the plurality of sub-wirings 132 as the third wirings through the two second connection electrodes 134 and the plurality of first connection electrodes 133. As a result, a reduction in the wiring resistance of the second connection wiring 39 is achieved. In addition, in the case where a disconnection occurs in the second connection wiring 39, redundancy is also achieved through the sub-wiring 132 as the third wiring, the first connection electrode 133, and the second connection electrode 134.

[0122] <Embodiment 3>

[0123] According to​ Embodiment 3 will be described. Embodiment 3 shows a case where the outer shape of liquid crystal panel 210 is changed from that of Embodiment 1. In addition, about the same structure, function and effect as that of Embodiment 2, the repeated description is omitted.

[0124] ​ 2 is a plan view showing the structure of the liquid crystal panel 210 near the end portion in the Y-axis direction. ​ In order to ensure easy viewing, a portion of the gate wiring 226 and the source wiring 227 are representatively shown, and other components (TFT223, pixel electrode 224, touch wiring 231, etc.) are omitted. ​ In FIG. 1 , the outer shape of the display area AA is shown by a thick single-dot chain line. ​ As shown, in the outer shape of the liquid crystal panel 210 involved in this embodiment, the Y-axis direction is parallel to the driver 11 (see ​ ) includes a notch 42 and a curved portion 43. That is, the outer shape of the liquid crystal panel 210 is a non-rectangular shape (irregular shape). The notch 42 is formed so that the central side portion of the above-mentioned end of the liquid crystal panel 210 in the X-axis direction is oriented to ​ The liquid crystal panel 210 is formed in such a way that it is open in the upward direction (the direction opposite to the driver 11) and is concave when viewed from above. A camera or a speaker or other equipment can be arranged in the gap space formed by the notch 42. Two curved portions 43 are arranged at two corner positions in the X-axis direction in the above-mentioned end of the liquid crystal panel 210. The curved portion 43 can also be arranged at the end on the side opposite to the driver 11 in the Y-axis direction of the liquid crystal panel 210. The liquid crystal panel 210 has a shape with rounded corners. The display area (configuration area) AA of the liquid crystal panel 210 is set to a plane shape similar to the shape of the liquid crystal panel 210. In other words, the shape of the display area AA reflects the shape of the notch 42 and the curved portion 43 included in the shape of the liquid crystal panel 210, and becomes a non-rectangular shape (special shape). The shape of the display area AA includes the notch AA1 and the curved portion AA2. The notch 42 and the curved portion 43 included in the shape of the liquid crystal panel 210 are also reflected in the shape of the non-display area (non-configuration area) NAA. Although the TFT 223 connected to the pixel electrode 224 is arranged in the display area AA as described in Embodiment 1, it is not arranged in the non-display area NAA. Therefore, the display area AA is a configuration area where the TFT 223 connected to the pixel electrode 224 is arranged, and the non-display area NAA is a non-configuration area where the TFT 223 connected to the pixel electrode 224 is not arranged.

[0125] like ​As shown, there are two types of gate wirings 226 with different distances passing through the non-display area NAA where the TFT 223 connected to the pixel electrode 224 is not disposed. That is, the gate wiring 226 includes: a first gate wiring (first scanning wiring) 226α that passes through the display area AA and the non-display area NAA; and a second gate wiring (second scanning wiring) 226β that passes through the display area AA and the non-display area NAA and has a shorter distance passing through the non-display area NAA than the first gate wiring 226α. Among the plurality of gate wirings 226 arranged in the Y-axis direction, the plurality of gate wirings 226 located at the position of the edge on the upper side (the notch portion 42 and the curved portion 43 side) in the Y-axis direction are the first gate wirings 226α. The plurality of first gate wirings 226α include a plurality of first gate wirings 226α in which not only both end portions in the X-axis direction are disposed in the non-display area NAA but also the central side portion in the X-axis direction is disposed in the non-display area NAA. The central side portions of most of the first gate wirings 226α among the plurality of first gate wirings 226α in which the central side portion is disposed in the non-display area NAA are bent along the notch portion 42. Some of the first gate wirings 226α (the first gate wirings 226α located at the position closer to the center in the Y-axis direction) among the plurality of first gate wirings 226α in which the central side portion is disposed in the non-display area NAA are not bent along the notch portion 42. The plurality of first gate wirings 226α include a plurality of first gate wirings 226α that cross the curved portion AA2 of the display area AA. The central side portions of all or most of the first gate wirings 226α among the plurality of first gate wirings 226α that cross the curved portion AA2 of the display area AA are disposed in the non-display area NAA. The plurality of first gate wirings 226α that cross the curved portion AA2 of the display area AA may also include first gate wirings 226α in which the central side portion is not disposed in the non-display area NAA. ​ The plurality of first gate wirings 226α located at the position of the edge on the upper side (the notch portion 42 and the curved portion 43 side) in the Y-axis direction among the plurality of gate wirings 226 arranged in the Y-axis direction are the first gate wirings 226α. The plurality of first gate wirings 226α include a plurality of first gate wirings 226α in which not only both end portions in the X-axis direction are disposed in the non-display area NAA but also the central side portion in the X-axis direction is disposed in the non-display area NAA. The central side portions of most of the first gate wirings 226α among the plurality of first gate wirings 226α in which the central side portion is disposed in the non-display area NAA are bent along the notch portion 42. Some of the first gate wirings 226α (the first gate wirings 226α located at the position closer to the center in the Y-axis direction) among the plurality of first gate wirings 226α in which the central side portion is disposed in the non-display area NAA are not bent along the notch portion 42. The plurality of first gate wirings 226α include a plurality of first gate wirings 226α that cross the curved portion AA2 of the display area AA. The central side portions of all or most of the first gate wirings 226α among the plurality of first gate wirings 226α that cross the curved portion AA2 of the display area AA are disposed in the non-display area NAA. The plurality of first gate wirings 226α that cross the curved portion AA2 of the display area AA may also include first gate wirings 226α in which the central side portion is not disposed in the non-display area NAA.

[0126] As ​As shown, all of the plurality of gate wirings 226 arranged in the Y-axis direction, except for the first gate wiring 226α, are the second gate wirings 226β. Both end portions of the second gate wiring 226β in the X-axis direction are disposed in the non-display area NAA, and all portions (including the central-side portion) other than the both end portions are disposed in the display area AA. The second gate wiring 226β intersects with the linear portion AA3 along the Y-axis direction in the outer shape of the display area AA, and does not intersect with the curved portion AA2. The first gate wiring 226α having the central-side portion disposed in the non-display area NAA has a longer distance passing through the non-display area NAA than the amount by which the central-side portion is disposed in the non-display area NAA compared to the second gate wiring 226β. The first gate wiring 226α intersecting with the curved portion AA2 of the display area AA has a longer distance passing through the non-display area NAA from the gate circuit portion 213 to the display area AA than the second gate wiring 226β. The reason therefor is that the linear distance along the X-axis direction from the gate circuit portion 213 to the curved portion AA2 is longer than the linear distance along the X-axis direction from the gate circuit portion 213 to the linear portion AA3. Thus, the distance that the second gate wiring 226β passes through the non-display area NAA is shorter than the distance that any of the first gate wirings 226α passes through the non-display area NAA.

[0127] On the other hand, as ​ shown, the plurality of source wirings 227 include a plurality of source wirings 227 that intersect with the notch portion AA1 of the display area AA. The source wirings 227 intersecting with the notch portion AA1 are disposed in the central-side portion in the X-axis direction in the display area AA, and are arranged such that the arrangement in the X-axis direction overlaps with the notch portion AA1. The source wirings 227 intersecting with the notch portion AA1 are connected to the driver 11 (refer to ​)The end portions on the opposite side are located in the non-display area NAA and cross the first gate wiring 226α in the non-display area NAA. The plurality of source wirings 227 include a plurality of source wirings 227 arranged in the X-axis direction and overlapping with the curved portion AA2 of the display area AA. The source wirings 227 arranged in the X-axis direction and overlapping with the curved portion AA2 are arranged at both end portions in the X-axis direction in the display area AA. The end portions on the upper side in the Y-axis direction (the side opposite to the driver 11) of the source wirings 227 arranged in the X-axis direction and overlapping with the curved portion AA2 do not lie in the non-display area NAA. That is, the lengths in the Y-axis direction of the plurality of source wirings 227 arranged in the X-axis direction and overlapping with the curved portion AA2 are different according to the arrangement in the X-axis direction. For example, the source wiring 227 located at the edge in the X-axis direction has the shortest length in the Y-axis direction. The source wirings 227 arranged in the X-axis direction and overlapping with the curved portion AA2 cross the first gate wiring 226α in the display area AA. The number of the first gate wirings 226α crossed by the plurality of source wirings 227 arranged in the X-axis direction and overlapping with the curved portion AA2 is different according to the arrangement in the X-axis direction. For example, the source wiring 227 located at the edge in the X-axis direction crosses the fewest number of the first gate wirings 226α. In addition, ​ The relationship between the touch wiring 231 (the illustration of which is omitted) and the gate wiring 226 is the same as the relationship between the source wiring 227 and the gate wiring 226 described above.

[0128] ​ is a top view showing an enlarged view of the vicinity of the notch portion 42 in the array substrate 221. ​ is a top view showing an enlarged view of the vicinity of the curved portion 43 in the array substrate 221. In ​ and ​ , for the sake of easy viewing, a part of the gate wiring 226, the source wiring 227, and the touch wiring 231 are representatively shown, and the illustration of other components (such as the drain electrode 223C, the channel portion 23D, and the pixel electrode 224, etc.) is omitted. In addition, in ​ and ​ , the outer shape of the display area AA is shown by a thick single-dot chain line. As ​As shown, the central side portion in the X-axis direction of the first gate wiring 226α that passes through the non-display area NAA does not have a portion constituting the gate electrode 223A. Therefore, the line width of the central side portion of the first gate wiring 226α that passes through the non-display area NAA is set to be substantially fixed. On the other hand, since the central side portion in the X-axis direction of the second gate wiring 226β passes through the display area AA, it has a portion constituting the gate electrode 223A. Therefore, the line width of the central side portion of the second gate wiring 226β changes midway, such that the portion constituting the gate electrode 223A has a larger width compared to other portions. According to the above configuration, the overlapping area of the source wiring 227 that intersects the notch portion AA1 of the display area AA with the first gate wiring 226α is smaller than the overlapping area of the source wiring 227 with the second gate wiring 226β.

[0129] On the other hand, as ​ shown, the end side portion of the first gate wiring 226α has a longer distance passing through the non-display area NAA compared to the end side portion of the second gate wiring 226β. Therefore, the first gate wiring 226α intersects with a smaller number of source wirings 227 compared to the second gate wiring 226β. Moreover, among the plurality of first gate wirings 226α, the first gate wiring 226α located ​ on the upper side (the side farther from the driver 11) of ​ intersects with a smaller number of source wirings 227 compared to the first gate wiring 226α located

[0130] on the lower side (the side closer to the driver 11) of ​ and ​ shown, if the first gate wiring 226α and the second gate wiring 226β are compared with respect to the sum of the overlapping areas of the gate wiring 226 and the source wiring 227, the sum of the overlapping areas related to the latter is larger than the sum of the overlapping areas related to the former. Therefore, the parasitic capacitance formed between the second gate wiring 226β and the source wiring 227 is larger than the parasitic capacitance formed between the first gate wiring 226α and the source wiring 227.

[0131] In the present embodiment, in order to alleviate the difference in parasitic capacitance generated between the first gate wiring 226α and the second gate wiring 226β as described above, a characteristic structure as ​ shown is provided. ​ is a top view showing the second connection wiring 239 that intersects the first gate wiring 226α in the array substrate 221. In ​ , the pattern of the second metal film F4 is selectively shown in a shaded state. ​ is a top view showing the second connection wiring 239 that intersects the second gate wiring 226β in the array substrate 221. In​ In the figure, the pattern of the second metal film F4 is selectively shown in a shaded state. ​ It is a top view showing the first connection electrode 233 that intersects the first gate wiring 226α in the array substrate 221. ​ In the figure, the pattern of the second transparent electrode film F8 is selectively shown in a shaded state.

[0132] As ​ shown, the second connection wiring 239 that intersects the first gate wiring 226α is configured such that the portion intersecting the first gate wiring 226α is wider than other portions. Specifically, the portion of the second connection wiring 239 that intersects the first gate wiring 226α is wider than the portion overlapping the sub-wiring 232 and is the widest width among the second connection wirings 239. In this way, the wide-width portion 239A of the second connection wiring 239 having the wide-width portion 239A intersects the first gate wiring 226α. In contrast, as ​ shown, the second connection wiring 239 that intersects the second gate wiring 226β is configured such that the portion intersecting the second gate wiring 226β is narrower than other portions. Specifically, the portion of the second connection wiring 239 that intersects the second gate wiring 226β is narrower than the portion overlapping the sub-wiring 232 and is the narrowest width among the second connection wirings 239. In this way, the second connection wiring 239 having the narrow-width portion 239B intersects the second gate wiring 226β at the narrow-width portion 239B. According to the above configuration, the overlapping area between the first gate wiring 226α and the second connection wiring 239 is larger than the overlapping area between the second gate wiring 226β and the second connection wiring 239. As a result, the parasitic capacitance formed between the intersecting first gate wiring 226α and the second connection wiring 239 is larger than the parasitic capacitance formed between the intersecting second gate wiring 226β and the second connection wiring 239. Therefore, it is possible to reduce the possible difference between the following two: the sum of the parasitic capacitance formed between the first gate wiring 226α and the source wiring 227 and the parasitic capacitance formed between the second connection wiring 239 and the first gate wiring 226α; and the sum of the parasitic capacitance formed between the second gate wiring 226β and the source wiring 227 and the parasitic capacitance formed between the second connection wiring 239 and the second gate wiring 226β.

[0133] As ​As shown, the first connection electrode 233 that crosses the first gate wiring 226α is configured such that the portion that crosses the first gate wiring 226α has a larger width than other portions. Specifically, the portion of the first connection electrode 233 that crosses the first gate wiring 226α has a larger width than each contact portion 233A and is the largest width among the first connection electrodes 233. In contrast, the first connection electrode 233 that crosses the second gate wiring 226β is provided such that the portion that crosses the second gate wiring 226β has a narrower width than each contact portion 233A (see ​ ). Since the large-width portion 233B of the first connection electrode 233 crosses the first gate wiring 226α, the overlapping area between the first gate wiring 226α and the first connection electrode 233 is larger than the overlapping area between the second gate wiring 226β and the first connection electrode 233. Thus, the parasitic capacitance formed between the mutually crossing first connection electrode 233 and the first gate wiring 226α is larger than the parasitic capacitance formed between the mutually crossing first connection electrode 233 and the second gate wiring 226β. Here, the connection object of the two sub-wirings 232 to which the first connection electrode 233 having the large-width portion 233B is connected is the second connection wiring 239. Therefore, it is possible to reduce the difference that may occur between the sum of the parasitic capacitance formed between the first gate wiring 226α and the source wiring 227 and the parasitic capacitance formed between the second connection wiring 239 and the first gate wiring 226α; and the sum of the parasitic capacitance formed between the second gate wiring 226β and the source wiring 227 and the parasitic capacitance formed between the second connection wiring 239 and the second gate wiring 226β.

[0134] As described above, according to the present embodiment, it includes: a TFT 223 having a gate electrode (first electrode) 223A, a source electrode (second electrode) 223B, and a drain electrode (third electrode) 223C; a gate wiring 226 extending along a first direction and connected to the gate electrode 223A; a source wiring 227 extending along a second direction and connected to the source electrode 223B; and a pixel electrode 224 connected to the drain electrode 223C. The first wiring includes the gate wiring 226, the source wiring 227 includes a portion different from the second connection wiring 239 included in the second wiring, the gate electrode 223A is constituted by a portion of the gate wiring 226, the source electrode 223B is constituted by a portion of the source wiring 227, and is arranged to overlap with the gate electrode 223A with a gate insulating film F2 therebetween. A plurality of TFTs 223 are arranged in such a manner that they are not locally arranged within the plane of the array substrate 221, thereby forming a display area (arrangement area) AA where the TFTs 223 are arranged and a non-display area (non-arrangement area) NAA where the TFTs 223 are not arranged. The gate wiring 226 includes a first gate wiring (first scanning wiring) 226α passing through the display area AA and the non-display area NAA, and a second gate wiring (second scanning wiring) 226β passing through the display area AA and the non-display area NAA and having a shorter distance passing through the non-display area NAA than the first gate wiring 226α. The overlapping area of the first gate wiring 226α and the second connection wiring 239 included in the second wiring is larger than the overlapping area of the second gate wiring 226β and the second connection wiring 239 included in the second wiring.

[0135] In this way, when the TFT 223 is driven based on a signal supplied by the gate wiring 226, the pixel electrode 224 is charged to a potential based on the signal supplied to the source wiring 227. The second gate wiring 226β travels a shorter distance through the non-display area NAA where the TFT 223 is not disposed, as compared with the first gate wiring 226α. In contrast, the gate electrode 223A of the TFT 223 disposed in the display area AA and not disposed in the non-display area NAA is formed of a part of the gate wiring 226, for example, by locally widening the gate wiring 226. Therefore, when comparing the first gate wiring 226α and the second gate wiring 226β in terms of the sum of the overlapping areas between the gate wiring 226 and the source wiring 227, the sum of the overlapping areas related to the latter is larger than the sum of the overlapping areas related to the former. Thus, the parasitic capacitance formed between the second gate wiring 226β and the source wiring 227 is larger than the parasitic capacitance formed between the first gate wiring 226α and the source wiring 227. In contrast, the overlapping area between the first gate wiring 226α and the second connection wiring 239 included in the second wiring is larger than the overlapping area between the second gate wiring 226β and the second connection wiring 239 included in the second wiring. Accordingly, the parasitic capacitance formed between the first gate wiring 226α and the second connection wiring 239 included in the second wiring is larger than the parasitic capacitance formed between the second gate wiring 226β and the second connection wiring 239 included in the second wiring. Therefore, it is possible to reduce the difference that may occur between the following two sums: the sum of the parasitic capacitance formed between the first gate wiring 226α and the source wiring 227 and the parasitic capacitance formed between the second connection wiring 239 included in the second wiring and the first gate wiring 226α; and the sum of the parasitic capacitance formed between the second gate wiring 226β and the source wiring 227 and the parasitic capacitance formed between the second connection wiring 239 included in the second wiring and the second gate wiring 226β.

[0136] In addition, it includes: a TFT 223 having a gate electrode 223A, a source electrode 223B, and a drain electrode 223C; a gate wiring 226 extending along a first direction and connected to the gate electrode 223A; a source wiring 227 extending along a second direction and connected to the source electrode 223B; and a pixel electrode 224 connected to the drain electrode 223C. The first wiring includes the gate wiring 226, the source wiring 227 includes a portion different from a second connection wiring 239 included in the second wiring in a second metal film F4, the gate electrode 223A is constituted by a portion of the gate wiring 226, the source electrode 223B is constituted by a portion of the source wiring 227, and is configured to overlap with the gate electrode 223A with a gate insulating film F2 therebetween. A plurality of TFTs 223 are arranged in such a manner that they are not locally arranged within the plane of the array substrate 221, thereby forming a display area AA where the TFTs 223 are arranged and a non-display area NAA where the TFTs 223 are not arranged. The gate wiring 226 includes a first gate wiring 226α passing through the display area AA and the non-display area NAA, and a second gate wiring 226β passing through the display area AA and the non-display area NAA and having a shorter distance passing through the non-display area NAA than the first gate wiring 226α. The overlapping area between a first connection electrode 233 connected to two sub-wirings 232 as a third wiring sandwiching the first gate wiring 226α and the first gate wiring 226α is larger than the overlapping area between the first connection electrode 233 connected to two sub-wirings 232 as a third wiring sandwiching the second gate wiring 226β and the second gate wiring 226β.

[0137] In this way, when the TFT 223 is driven based on the signal supplied by the gate wiring 226, the pixel electrode 224 is charged to the potential based on the signal supplied to the source wiring 227. The second gate wiring 226β has a shorter distance passing through the non-display area NAA where the TFT 223 is not arranged than the first gate wiring 226α. In contrast, the gate electrode 223A of the TFT 223 that is arranged in the display area AA and not in the non-display area NAA is formed by a part of the gate wiring 226. For example, it is formed by locally widening the gate wiring 226. Therefore, if the sum of the overlapping areas between the gate wiring 226 and the source wiring 227 is compared between the first gate wiring 226α and the second gate wiring 226β, the sum of the overlapping areas related to the latter is larger than the sum of the overlapping areas related to the former. Thus, the parasitic capacitance formed between the second gate wiring 226β and the source wiring 227 is larger than the parasitic capacitance formed between the first gate wiring 226α and the source wiring 227. In contrast, the overlapping area between the first connection electrode 233 connected to the two sub-wirings 232 as the third wiring sandwiching the first gate wiring 226α and the first gate wiring 226α is larger than the overlapping area between the first connection electrode 233 connected to the two sub-wirings 232 as the third wiring sandwiching the second gate wiring 226β and the second gate wiring 226β. Thus, the parasitic capacitance formed between the first connection electrode 233 connected to the two sub-wirings 232 as the third wiring sandwiching the first gate wiring 226α and the first gate wiring 226α is larger than the parasitic capacitance formed between the first connection electrode 233 connected to the two sub-wirings 232 as the third wiring sandwiching the second gate wiring 226β and the second gate wiring 226β. Here, the sub-wiring 232 as the third wiring is connected to the second connection wiring 239 included in the second wiring by the second connection electrode 34 (refer to ​ ). Therefore, it is possible to reduce the possible difference between the following two sums: the sum of the parasitic capacitance formed between the first gate wiring 226α and the source wiring 227 and the parasitic capacitance formed between the second connection wiring 239 included in the second wiring and the first gate wiring 226α; and the sum of the parasitic capacitance formed between the second gate wiring 226β and the source wiring 227 and the parasitic capacitance formed between the second connection wiring 239 included in the second wiring and the second gate wiring 226β.

[0138] <Embodiment 4>

[0139] According to ​ Embodiment 4 will be described. In this Embodiment 4, a case where the setting number of the second connection electrode 334 is changed from the above Embodiment 1 is shown. In addition, for the same structures, operations, and effects as those in the above Embodiment 1, repeated descriptions are omitted.

[0140] ​ It is a top view schematically showing the connection forms of touch electrodes 330, touch wirings 331, sub-wirings 332, etc. in the array substrate 321. ​ The shown touch wiring 331 is connected to a touch electrode 330 located at a position above the touch electrode 330 shown at the uppermost part in ​ . Except for the touch wiring 331, ​ The content illustrated in ​ is the same. For the sake of easy viewing, each component is simplified, etc.

[0141] As ​ shown, the second connection electrode 334 according to the present embodiment is arranged not only near the end portion in the Y-axis direction of the touch electrode 330 but also near the center in the Y-axis direction of the touch electrode 330. Specifically, near the center in the Y-axis direction of the touch electrode 330, one second connection electrode 334α and the other second connection electrode 334β are each arranged one. The one second connection electrode 334α and the other second connection electrode 334β are arranged near the center in the Y-axis direction of the touch electrode 330 so as to cross two gate wirings 326 that are in a relationship of sandwiching one pixel electrode 324 in the Y-axis direction respectively. The one second connection electrode 334α is located above the other second connection electrode 334β in ​ . Therefore, the one second connection electrode 334α is connected to the sub-wiring 332 adjacent to the upper side of the gate wiring 326 that crosses the one second connection electrode 334α in ​ . The other second connection electrode 334β is connected to the sub-wiring 332 adjacent to the upper side of the gate wiring 326 that crosses the other second connection electrode 334β in ​The sub-wiring 332 adjacent to the lower side. One second connection electrode 334α and the other second connection electrode 334β are respectively connected to the portions of the touch wiring 331 that are sandwiched between two gate wirings 326 that cross each of the second connection electrodes 334α and 334β. Between one second connection electrode 334α near the center in the Y-axis direction of the touch electrode 330 and the other second connection electrode 334β near the upper end in the Y-axis direction of the touch electrode 330, the sub-wiring 332 and the gate wiring 326 are alternately arranged in the Y-axis direction. A plurality of sub-wirings 332 sandwiched between these two second connection electrodes 334α and 334β and a plurality of first connection electrodes 333 connected to each sub-wiring 332 form one first connection wiring 338. Similarly, between the other second connection electrode 334β near the center in the Y-axis direction of the touch electrode 330 and one second connection electrode 334α near the lower end in the Y-axis direction of the touch electrode 330, the sub-wiring 332 and the gate wiring 326 are alternately arranged in the Y-axis direction. A plurality of sub-wirings 332 sandwiched between these two second connection electrodes 334α and 334β and a plurality of first connection electrodes 333 connected to each sub-wiring 332 form one first connection wiring 338. In this way, the portion of the touch wiring 331 that crosses one touch electrode 330 is connected to two first connection wirings 338. The touch wiring 331 connected to the two first connection wirings 338 has further improved redundancy compared to Embodiment 1. In addition, the lengths of the two first connection wirings 338 are set to be slightly shorter than half of one side of the touch electrode 330.

[0142] <Embodiment 5>

[0143] According to ​ to describe Embodiment 5. In this Embodiment 5, a case where the configuration of the second connection electrode 434 is changed from the above Embodiment 1 is shown. In addition, for the same structures, operations, and effects as those in the above Embodiment 1, repeated descriptions are omitted.

[0144] ​ is a top view schematically showing the connection form of the touch electrode 430, the touch wiring 431, the sub-wiring 432, etc. in the array substrate 421. ​ The shown touch wiring 431 is connected to the touch electrode 430 located at a position above the touch electrode 430 shown at the uppermost part in ​ In addition to the touch wiring 431, ​ The content illustrated in ​ is the same, and each component is simplified, etc. for easy viewing.

[0145] In this embodiment, as ​As shown, compared with the above-described Embodiment 1, the arrangement of one second connection electrode 434α and the other second connection electrode 434β is reversed. Specifically, the other second connection electrode 434β is arranged to straddle the first slit 425A1 that separates two touch electrodes 430 that are adjacent in the Y-axis direction and are not connected to the ​ touch wiring 431. The other second connection electrode 434β is arranged to cross the gate wiring 426 disposed in the first slit 425A1. One second connection electrode 434α is arranged to cross the gate wiring 426 that is spaced apart from the gate wiring 426 disposed in the first slit 425A1 that separates two touch electrodes 430 adjacent in the Y-axis direction by an interval on the ​ upper side. Even if the second connection electrode 434 is arranged as shown in ​ , the same functions and effects as those of Embodiment 1 can be obtained.

[0146] <Embodiment 6>

[0147] According to ​ , Embodiment 6 will be described. In this Embodiment 6, a case where the number of the second connection electrodes 534 is changed from that in the above-described Embodiment 1 is shown. In addition, the description of the same structures, functions, and effects as those in the above-described Embodiment 1 is omitted.

[0148] ​ is a top view schematically showing the connection form of the driver 511, the touch electrodes 530, the touch wiring 531, the sub-wiring 532, etc. in the array substrate 521. ​ The content illustrated in is the same as that in ​ except that the driver 511 is illustrated, and each component is simplified, etc. for easy viewing.

[0149] As ​As shown, the second connection electrodes 534 involved in this embodiment are designed such that two second connection electrodes 534 are connected to one touch wiring 531. The two second connection electrodes 534 are respectively arranged near the end portion on the side closer to the driver 511 and near the end portion on the side closer to the touch electrode 530 to be connected in the touch wiring 531. Specifically, one of the two second connection electrodes 534 included in the two second connection electrodes 534, i.e., the second connection electrode 534α, is arranged to cross the gate wiring 526 closest to the driver 511 in the Y-axis direction. The gate wiring 526 crossing the one second connection electrode 534α overlaps with the touch electrode 530 closest to the driver 511 in the Y-axis direction. The other second connection electrode 534β included in the two second connection electrodes 534 is arranged to cross the gate wiring 526 second closest to the touch electrode 530 to be connected to the touch wiring 531 in the Y-axis direction. The gate wiring 526 crossing the other second connection electrode 534β is arranged to be adjacent to the gate wiring 526 of the first slit 525A1 with a space on the driver 511 side: the first slit 525A1 separates the touch electrode 530 to be connected to the touch wiring 531 and the touch electrode 530 adjacent to the driver 511 side in the Y-axis direction. A plurality of sub-wirings 532 sandwiched between the two second connection electrodes 534 in the Y-axis direction are connected to the two second connection electrodes 534 and a plurality of first connection electrodes 533. The plurality of sub-wirings 532 and the plurality of first connection electrodes 533 constitute one first connection wiring 538. The length of the first connection wiring 538 is longer than one side of the touch electrode 530 and becomes a value close to the length of the touch wiring 531 from the driver 511 to the touch electrode 530 to be connected. Compared with the first connection wiring 38 (refer to ​ ) described in Embodiment 1, the number of sub-wirings 532 and first connection electrodes 533 constituting the first connection wiring 538 is respectively larger, and the number of first dummy wirings 536 is smaller. Therefore, the wiring resistance of the touch wiring 531 connected to the first connection wiring 538 becomes lower than that in Embodiment 1. Further, in this embodiment, the plurality of first connection electrodes 533 include the first connection electrodes 533 straddling the first slit 525A1 that separates the touch electrodes 530 adjacent in the Y-axis direction.

[0150] <Embodiment 7>

[0151] According to ​ to describe Embodiment 7. In this Embodiment 7, a case where the connection object of the second connection electrode 634 is changed to the source wiring (second wiring) 627 from the above-described Embodiment 1 is shown. In addition, for the same structures, operations, and effects as those in the above-described Embodiment 1, repeated descriptions are omitted.

[0152] ​ It is a top view schematically showing the connection form of the source wiring 627, the sub-wiring 632, etc. in the array substrate 621. ​ The content shown in the figure is the same as that in ​ except that the source wiring 627 is shown instead of the touch wiring 31 and the touch electrode 30 is not shown. Similarly, each component is simplified for easy viewing.

[0153] As ​ shown, the source wiring 627 according to this embodiment is connected to the second connection electrode 634. The source wiring 627 has a contact portion connected to the second connection electrode 634. The second connection electrode 634 is connected to the source wiring 627 and the sub-wiring 632. The sub-wiring 632 is arranged to overlap with the source wiring 627 with the gate insulating film F2 therebetween (refer to ​ ). One second connection electrode 634α and the other second connection electrode 634β are arranged to sandwich a plurality of sub-wirings 632 and a plurality of first connection electrodes 633 in the Y-axis direction. The plurality of sub-wirings 632 and the plurality of first connection electrodes 633 sandwiched between the one second connection electrode 634α and the other second connection electrode 634β constitute one first connection wiring 638. The source wiring 627 is connected to a plurality of first connection wirings 638. Thus, the wiring resistance of the source wiring 627 is reduced and the redundancy is improved. Since the reduction of the wiring resistance of the source wiring 627 is achieved in this way, the line width of the source wiring 627 can be narrowed. If the line width of the source wiring 627 becomes narrow, the area where there is no wiring in the plane of the array substrate 621, that is, the area where the pixels PX are arranged is enlarged. Thus, the aperture ratio becomes high. In addition, the source wiring 627 is not connected to the third connection electrode 35.

[0154] <Embodiment 8>

[0155] According to ​ Embodiment 8 will be described. In this Embodiment 8, a case where a common wiring (second wiring) 44, etc. is added to the above-described Embodiment 1 is shown. In addition, for the same structures, operations, and effects as those in the above-described Embodiment 1, repeated descriptions are omitted.

[0156] Figure 32 It is a top view schematically showing the connection form of the common wiring 44, etc. in the array substrate 721. Figure 32 The content shown in the figure is the same as that in Figure 10 except that the common wiring 44 is shown instead of the touch wiring 31 and the touch electrode 30 is not shown. Similarly, each component is simplified for easy viewing.

[0157] As Figure 32As shown, a common wiring 44 connected to a common electrode 25 (refer to Figure 4 ) is provided on the array substrate 721 according to this embodiment. In the array substrate 721 according to this embodiment, the common electrode 25 has a non-divided structure, and no touch wiring 31 is provided. That is, the liquid crystal panel 10 according to this embodiment does not have a touch panel function. The common wiring 44 supplies a common potential signal from a signal supply source (such as the driver 11) to the common electrode 25. The common wiring 44 includes a portion different from the source wiring 27 and the like in the second metal film F4 (refer to Figure 4 ). The common wiring 44 is connected to the second connection electrode 734 and the third connection electrode 735. The common wiring 44 has a first contact portion connected to the second connection electrode 734 and a second contact portion connected to the third connection electrode 735. The third connection electrode 735 is connected to the common electrode 25 and the common wiring 44.

[0158] The second connection electrode 734 is connected to the common wiring 44 and the sub-wiring 732. The sub-wiring 732 is arranged to overlap the common wiring 44 with the gate insulating film F2 therebetween (refer to Figure 12 ). One second connection electrode 734α and the other second connection electrode 734β are arranged to sandwich a plurality of sub-wirings 732 and a plurality of first connection electrodes 733 in the Y-axis direction. A plurality of sub-wirings 732 and a plurality of first connection electrodes 733 sandwiched between the one second connection electrode 734α and the other second connection electrode 734β constitute one first connection wiring 738. The common wiring 44 is connected to a plurality of first connection wirings 738. Thus, the wiring resistance of the common wiring 44 is reduced and the redundancy is improved. Since the reduction of the wiring resistance of the common wiring 44 is achieved in this way, the line width of the common wiring 44 can be narrowed. If the line width of the common wiring 44 becomes narrower, the area where there is no wiring in the plane of the array substrate 721, that is, the area where the pixels PX are arranged, is enlarged. Thus, the aperture ratio becomes higher.

[0159] <Other Embodiments>

[0160] The technology disclosed in this specification is not limited to the embodiments described according to the above description and drawings. For example, the following embodiments are also included in the technical scope.

[0161] (1) In the configurations of Embodiments 1 to 6, the specific number of the second connection electrodes 34, 134, 334, 434, 534 connected to one touch wiring 31, 131, 231, 331, 431, 531 can be appropriately changed in addition to the illustration. The larger the number of the second connection electrodes 34, 134, 334, 434, 534 connected to one touch wiring 31, 131, 231, 331, 431, 531, the more preferable it is in terms of improving the redundancy.

[0162] (2) In the configuration of Embodiment 2, the specific number of the second connection electrodes 134 connected to one second connection wiring 39 can be appropriately changed in addition to what is shown in the drawings. The larger the number of the second connection electrodes 134 connected to one second connection wiring 39, the more preferable it is in terms of improving redundancy.

[0163] (3) In the configuration of Embodiment 7, the specific number of the second connection electrodes 634 connected to one source wiring 627 can be appropriately changed in addition to what is shown in the drawings. The larger the number of the second connection electrodes 634 connected to one source wiring 627, the more preferable it is in terms of improving redundancy.

[0164] (4) In the configuration of Embodiment 8, the specific number of the second connection electrodes 734 connected to one common wiring 44 can be appropriately changed in addition to what is shown in the drawings. The larger the number of the second connection electrodes 734 connected to one common wiring 44, the more preferable it is in terms of improving redundancy.

[0165] (5) In the configurations of Embodiments 1 to 6, it is also possible that the first connection electrodes 33, 133, 233, 333, 533 or the second connection electrodes 34, 134, 334, 434, 534 are arranged to cross any one of the plurality of gate wirings 26, 126, 226, 326, 426, 526 that overlap with the touch electrodes 30, 130, 330, 430, 530 connected to the touch wirings 31, 131, 231, 331, 431, 531. In this case, the arrangement of the first connection electrodes 33, 133, 233, 333, 533, the second connection electrodes 34, 134, 334, 434, 534, and the third connection electrodes 35, 135 with respect to the portions of the touch wirings 31, 131, 231, 331, 431, 531 that pass through the connected touch electrodes 30, 130, 330, 430, 530 can be set to be the same as the arrangement of the first connection electrode 133, the second connection electrode 134, and the fourth connection electrode 40 with respect to the second connection wiring 39 described in Embodiment 2 (refer to Figure 21 ) but can also be other arrangements.

[0166] (6) In the configurations of Embodiment 1 to Embodiment 6, it is also possible that the second connection electrodes 34, 134, 334, 434, 534 are arranged not to straddle the first slits 25A1, 425A1, 525A1 that separate the touch electrodes 30, 130, 330, 430, 530 adjacent in the Y-axis direction. That is to say, it is also possible that all the second connection electrodes 34, 134, 334, 434, 534 are arranged to cross the gate wirings 26, 126, 226, 326, 426, 526 that overlap with the touch electrodes 30, 130, 330, 430, 530.

[0167] (7) In the configurations of Embodiment 1 to Embodiment 5, it is also possible that the plurality of first connection electrodes 33, 133, 233, 333 include the first connection electrodes 33, 133, 233, 333 arranged in a manner that straddles the first slits 25A1, 425A1 that separate the touch electrodes 30, 130, 330, 430, 530 adjacent in the Y-axis direction.

[0168] (8) In the configurations of Embodiment 1 to Embodiment 6, it is also possible that the second connection electrodes 34, 134, 334, 434, 534 (the first connection wirings) are connected to a part of the plurality of touch wirings 31, 131, 231, 331, 431, 531, and the second connection electrodes 34, 134, 334, 434, 534 are not connected to the remaining touch wirings 31, 131, 231, 331, 431, 531. For example, the second connection electrodes 34, 134, 334, 434, 534 can be connected to the touch wirings 31, 131, 231, 331, 431, 531 with a large distance from the drivers 11, 511 to the connected touch electrodes 30, 130, 330, 430, 530, and the second connection electrodes 34, 134, 334, 434, 534 are not connected to the touch wirings 31, 131, 231, 331, 431, 531 with a small distance from the drivers 11, 511 to the connected touch electrodes 30, 130, 330, 430, 530. The touch wirings 31, 131, 231, 331, 431, 531 with a large distance from the drivers 11, 511 to the connected touch electrodes 30, 130, 330, 430, 530 tend to have a higher wiring resistance compared to the touch wirings 31, 131, 231, 331, 431, 531 with a small distance from the drivers 11, 511 to the connected touch electrodes 30, 130, 330, 430, 530. Therefore, the second connection electrodes 34, 134, 334, 434, 534 can be connected to appropriately achieve a decrease in the wiring resistance.

[0169] (9)In the configurations of Embodiments 1 to 6, the arrangement intervals of the touch wirings 31, 131, 231, 331, 431, 531 in the X-axis direction can be appropriately changed. For example, the touch wirings 31, 131, 231, 331, 431, 531 may also be arranged to be adjacently spaced apart from all the source wirings 27, 227 with a clearance.

[0170] (10)In the configuration of Embodiment 2, the arrangement or setting number of the first connection electrode 133, the second connection electrode 134, and the fourth connection electrode 40 electrically connected to the second connection wiring 39 can be appropriately changed in addition to the illustration.

[0171] (11)In the configuration of Embodiment 3, the second connection wiring 239 having the large-width portion 239A (see Figure 25 ), the second connection wiring 239 having the narrow-width portion 239B (see Figure 26 ), and the first connection electrode 233 having the large-width portion 233B (see Figure 27 ) can be omitted, any one or two of them.

[0172] (12)In the configuration of Embodiment 3, it may also be that the portion of the touch wiring 231 that crosses the first gate wiring 226α and crosses the first gate wiring 226α is formed in a large-width shape.

[0173] (13)In the configuration of Embodiment 3, it may also be that the portion of at least one of the connection electrodes, i.e., the second connection electrode 34, the third connection electrode 35, and the fourth connection electrode 40, that crosses the first gate wiring 226α and crosses the first gate wiring 226α is formed in a large-width shape.

[0174] (14)In the configuration of Embodiment 3, it may also be that the connection objects of the two sub-wirings 232 connected to the first connection electrode 233 having the large-width portion 233B are the touch wiring 231.

[0175] (15)In the configuration of Embodiment 3, it may also be that the portion of the touch wiring 231 that crosses the second gate wiring 226β and crosses the second gate wiring 226β is formed in a narrow-width shape.

[0176] (16)In the configuration of Embodiment 3, it may also be that the portion of at least one of the connection electrodes, i.e., the first connection electrode 233, the second connection electrode 34, the third connection electrode 35, and the fourth connection electrode 40, that crosses the second gate wiring 226β and crosses the second gate wiring 226β is formed in a narrow-width shape.

[0177] (17)In the configuration of Embodiment 3, the source wiring 227 and the touch wiring 231 may be arranged to penetrate above the curved portion AA2 of the display area AA.

[0178] (18)The configurations of Embodiments 3 to 6 can also be applied to any one of the second connection wiring 39 described in Embodiment 2, the source wiring 627 described in Embodiment 7, and the common wiring 44 described in Embodiment 8.

[0179] (19)In the configuration of Embodiment 7, the common electrode 25 may be a non-divided structure, and the touch wiring 31 may not be arranged.

[0180] (20)Alternatively, the pixel electrodes 24, 124, 224, 324 may be formed of the first transparent electrode film F6, and the common electrode 25 (touch electrodes 30, 130, 330, 430, 530) may be formed of the second transparent electrode film F8. In this case, the first connection electrodes 33, 133, 233, 333, 533, 633, 733, the second connection electrodes 34, 134, 334, 434, 534, 634, 734, and the third connection electrodes 35, 135, 735 are formed of portions of the second transparent electrode film F8 different from the common electrode 25.

[0181] (21)Alternatively, the first connection electrodes 33, 133, 233, 333, 533, 633, 733, the second connection electrodes 34, 134, 334, 434, 534, 634, 734, and the third connection electrodes 35, 135, 735 may be formed of portions of the first transparent electrode film F6 different from the common electrode 25.

[0182] (22)It may also be arranged such that two gate wirings 26, 126, 226, 326, 426, 526 are sandwiched between two adjacent pixel electrodes 24, 124, 224, 324 in the Y-axis direction. Accordingly, the number of source wirings 27, 227, 627 provided can be reduced. In this case, a space where no source wirings 27, 227, 627 are arranged is generated between two adjacent pixel electrodes 24, 124, 224, 324 in the X-axis direction, so the touch wirings 31, 131, 231, 331, 431, 531 can be arranged using this space. In this configuration, the first connection electrodes 33, 133, 233, 333, 533, 633, 733, the second connection electrodes 34, 134, 334, 434, 534, 634, 734, the third connection electrode 35, and the fourth connection electrode 40 respectively cross the two gate wirings 26, 126, 226, 326, 426, 526.

[0183] (23) The semiconductor film F3 can also be made to include polysilicon (LTPS).

[0184] (24) The display mode of the liquid crystal panel 10 can also be an IPS mode or the like.

[0185] (25) The touch panel pattern can also be a mutual capacitance type in addition to the self-capacitance type.

[0186] (26) The planar shape of the liquid crystal panel 10 can also be a vertically long rectangle, square, circle, semi-circle, oblong, ellipse, trapezoid, etc.

[0187] (27) The liquid crystal panel 10 can also be a reflective type or a semi-transmissive type in addition to the transmissive type.

[0188] (28) It can also be a display panel of a type other than the liquid crystal panel 10 (such as an organic EL (ElectroLuminescence) display panel) or an EPD (display panel of a microcapsule type electrophoresis method).

[0189] (29) It can also be the array substrates 21, 121, 221, 321, 421, 521, 621, 721 provided in a device other than the display panel (such as an X-ray detection device).

Claims

1. An active matrix substrate, characterized in that, Comprising: A plurality of first wirings, which include a first conductive film, extend along a first direction, and are arranged at intervals in a second direction intersecting the first direction; A first insulating film, which is arranged on the upper layer side of the first conductive film; A second wiring, which includes a second conductive film arranged on the upper layer side of the first insulating film, extends along the second direction, and intersects with the plurality of first wirings with the first insulating film therebetween; A plurality of third wirings, which include a portion of the first conductive film different from the first wiring, extend along the second direction, and at least a part thereof overlaps with the second wiring with the first insulating film therebetween, and the plurality of third wirings are arranged to sandwich the first wiring in the second direction; A second insulating film, which is arranged on the upper layer side of the second conductive film; A first connection electrode, which is arranged on the upper layer side relative to the second insulating film, intersects with a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween, and is connected to two of the third wirings sandwiching the first wiring; and A second connection electrode, which is arranged on the upper layer side relative to the second insulating film, intersects with a first wiring different from the first wiring intersected by the first connection electrode with the first insulating film and the second insulating film therebetween, and is connected to the third wiring and the second wiring connected to the first connection electrode.

2. The active matrix substrate according to claim 1, wherein: Comprising: a position detection electrode, which is arranged on the upper layer side relative to the second insulating film; and A position detection wiring, which extends along the second direction and is connected to the position detection electrode, The second wiring includes the position detection wiring.

3. The active matrix substrate according to claim 2, wherein: The plurality of first wirings include the first wirings that overlap with the position detection electrode connected to the position detection wiring and intersect with the position detection wiring with the first insulating film therebetween, Comprising a third connection electrode, which is arranged on the upper layer side relative to the second insulating film, overlaps with the position detection electrode, and intersects with the first wiring intersecting with the position detection wiring with the first insulating film and the second insulating film therebetween, and is connected to the position detection wiring and the position detection electrode.

4. The active matrix substrate according to claim 2 or claim 3, wherein: Comprising: a switching element, which is arranged on the lower layer side relative to the second insulating film; A pixel electrode, which is arranged on the upper layer side relative to the second insulating film and is connected to the switching element; And A third insulating film, which is arranged on the upper layer side relative to the second insulating film, The position detection electrode includes a first transparent electrode film, The pixel electrode includes a second transparent electrode film, which is arranged to overlap with the position detection electrode with the third insulating film therebetween, The first connection electrode and the second connection electrode include a portion of the first transparent electrode film and the second transparent electrode film arranged on the upper layer side of the third insulating film, which is different from the position detection electrode or the pixel electrode.

5. The active matrix substrate according to claim 4, wherein, the first connection electrode and the second connection electrode include portions of the second transparent electrode film different from the pixel electrode.

6. The active matrix substrate according to any one of claims 2 to 5, wherein, it includes: a switching element; a pixel electrode connected to the switching element; a scan wiring extending along the first direction and connected to the switching element; and a signal wiring extending along the second direction and connected to the switching element, the first wiring includes the scan wiring, the signal wiring includes a portion of the second conductive film different from the second wiring, and is arranged at an interval in the first direction from the position detection wiring.

7. The active matrix substrate according to any one of claims 2 to 6, wherein, it includes a connection wiring configured to overlap with the position detection electrode, extending along the second direction, and at least two end-side portions thereof are connected to the overlapped position detection electrode, the second wiring includes the connection wiring.

8. The active matrix substrate according to claim 7, wherein, the first wiring includes the first wiring that overlaps with the position detection electrode to which the connection wiring is connected and crosses the connection wiring with the first insulating film therebetween, it includes a fourth connection electrode arranged on the upper layer side relative to the second insulating film, overlapping with the position detection electrode, and crossing the first wiring that crosses the connection wiring with the first insulating film and the second insulating film therebetween, and connected to the connection wiring and the position detection electrode.

9. The active matrix substrate according to claim 8, wherein, the plurality of first wirings include a plurality of first wirings that cross the connection wiring with the first insulating film therebetween and are arranged at an interval in the second direction, the plurality of third wirings include a plurality of third wirings configured to overlap at least a part of the connection wiring with the first insulating film therebetween, the fourth connection electrode includes two fourth connection electrodes that cross two first wirings respectively crossing the two end portions in the second direction of the connection wiring, the second connection electrode includes two second connection electrodes located on the central side in the second direction of the connection wiring relative to the two fourth connection electrodes, the first connection electrode includes a plurality of first connection electrodes located on the central side in the second direction of the connection wiring relative to the two second connection electrodes.

10. The active matrix substrate according to any one of claims 1 to 9, wherein, it includes dummy wirings, the dummy wirings include a portion of the first conductive film different from the first wiring, extend along the second direction, and at least a part thereof overlaps with the second wiring with the first insulating film therebetween. The dummy wiring is arranged such that the first wiring that crosses the second connection electrode is sandwiched between the dummy wiring and the third wiring connected to the second connection electrode in the second direction, and the dummy wiring is not connected to the second connection electrode.

11. The active matrix substrate according to any one of claims 1 to 10, wherein the second connection electrode is connected to the second wiring at a position where the first wiring is sandwiched between the second connection electrode and the third wiring to which the second connection electrode is connected in the second direction.

12. The active matrix substrate according to any one of claims 1 to 11, wherein comprises: a switching element having a first electrode, a second electrode, and a third electrode; a scanning wiring extending along the first direction and connected to the first electrode; a signal wiring extending along the second direction and connected to the second electrode; and a pixel electrode connected to the third electrode, the first wiring includes the scanning wiring, the signal wiring includes a portion of the second conductive film different from the second wiring, the first electrode is constituted by a part of the scanning wiring, the second electrode is constituted by a part of the signal wiring and is arranged to overlap the first electrode with the first insulating film therebetween, a plurality of the switching elements are arranged in such a manner that they are not locally arranged in the plane of the active matrix substrate, thereby forming an arrangement region where the switching elements are arranged and a non-arrangement region where the switching elements are not arranged, the scanning wiring includes a first scanning wiring passing through the arrangement region and the non-arrangement region, and a second scanning wiring passing through the arrangement region and the non-arrangement region and having a shorter distance passing through the non-arrangement region than the first scanning wiring, the overlapping area of the first scanning wiring and the second wiring is larger than the overlapping area of the second scanning wiring and the second wiring.

13. The active matrix substrate according to any one of claims 1 to 12, wherein comprises: a switching element having a first electrode, a second electrode, and a third electrode; a scanning wiring extending along the first direction and connected to the first electrode; a signal wiring extending along the second direction and connected to the second electrode; and a pixel electrode connected to the third electrode, the first wiring includes the scanning wiring, the signal wiring includes a portion of the second conductive film different from the second wiring, the first electrode is constituted by a part of the scanning wiring, the second electrode is constituted by a part of the signal wiring and is arranged to overlap the first electrode with the first insulating film therebetween, a plurality of the switching elements are arranged in such a manner that they are not locally arranged in the plane of the active matrix substrate, thereby forming an arrangement region where the switching elements are arranged and a non-arrangement region where the switching elements are not arranged, the scanning wiring includes a first scanning wiring passing through the arrangement region and the non-arrangement region, and a second scanning wiring passing through the arrangement region and the non-arrangement region and having a shorter distance passing through the non-arrangement region than the first scanning wiring, The overlapping area of the first connection electrode connected to the two third wirings sandwiching the first scan wiring and the first scan wiring is larger than the overlapping area of the first connection electrode connected to the two third wirings sandwiching the second scan wiring and the second scan wiring.

14. A display device, characterized in that, Comprising: The active matrix substrate according to any one of claims 1 to 13; and A counter substrate configured to face the active matrix substrate.

Images