Method for optimizing execution efficiency of mixed-signal systems with black-box subsystems

Abstract

The present invention proposes a method for optimizing the execution efficiency of a mixed signal system with a black box subsystem. The method comprises: for a black box model, all input ports are denoted as I, |I| represents the number of input ports, and |I| inputs are constructed using a one-hot encoding method, denoted as M |I| ; Let all the output ports of the black box model be O, |O| represents the number of output ports. For each one-hot encoded input, run the black box model and record the corresponding output signal R |I| ; According to the relationship between the obtained one-hot encoding input and each output port, δ(p1,p2) is established to represent the dependency of output port p2 on input port p1; according to the dependency, all black box models are converted into port-to-port graphs; finally, the priority scheduling execution order corresponding to all models is obtained by establishing the topological sorting of the entire dependency graph. This method provides a more complete and efficient mixed signal system simulation execution method.

Description

Technical Field

[0001] The present invention belongs to the technical field of system optimization, and in particular relates to a method for optimizing the execution efficiency of a mixed signal system with a black box subsystem. Background Art

[0002] The present invention is applied to heterogeneous modeling, simulation and design systems of concurrent systems oriented to models (Actors). The Actor-oriented design framework emphasizes concurrency and data communication between components. Each Actor has a defined abstract interface, which encapsulates its internal state and behavior and restricts the interaction mode with its environment. An Actor has one or more ports, which are divided into input ports and output ports. The Actor receives (sends) messages at the input (output) ports. Messages are also called signals. A collection of signals at each port is called the behavior of the Actor. Actors with continuous behavior and Actors with discrete behavior together constitute a mixed signal system.

[0003] Multiple Actors can be assembled into a composite Actor by establishing connectors between their ports. The connector from ActorA's output port a1 to Actor B's input port b1 indicates that the signal will flow from A's a1 port to B's b1 port.

[0004] In graphical modeling languages, Actors are often represented by boxes and triangles (ports). Triangle vertices pointing inside the box represent input ports, and triangle vertices pointing outside the box represent output ports. Connectors are represented by lines.

[0005] An Actor is said to be functional if it receives a specific input and gives a specific output. An Actor represents a function of the following form:

[0006] Fα:S |I| →S |O|

[0007] Where S represents the signal set, |I| represents the number of input ports, and |O| represents the number of output ports. If each Actor in the composite Actor is functional, then the composite Actor is functional.

[0008] An Actor with only output ports is called a signal source, and an Actor with only input ports is called a signal output module.

[0009] A composite Actor is also an Actor. If its internal structure is visible to the outside, it can be regarded as a white box; if its internal structure is not visible to the outside, it is regarded as a black box. The black box design is very important for protecting the intellectual property rights of model designers, so it is necessary to support the black box design.

[0010] An Actor with a feedback structure has its behavior described as a fixed-point problem, i.e., Fa(s) = s. When the prefix order of signals is a complete partial order (CPO), the semantics of the graph is the least fixed point. However, even if there is a unique fixed point and it can be found, the result may not be desirable. For example, when each port is an empty signal, it can also be the least fixed point, and in this case, the system is in a deadlock state.

[0011] The causal relationship interface theory can analyze whether there is a deadlock in the system and help the scheduler optimize the scheduling execution order. The causal interface of an Actor is expressed as:

[0012] δ: P i ×P o →D

[0013] where P i is the input port, P o is the output port, and D is an ordered set containing the operator . It satisfies the commutative law, associative law, and distributive law, and contains the additive identity element 0 and multiplicative identity element 1. The relational operator ≤ on the set D represents a partial order. D represents the dependency relationship and satisfies:

[0014]

[0015]

[0016] δ(p1, p2) represents the dependency relationship of port p2 on port p1. When representing the dependency relationship with a boolean type, D = {true, false}, represents logical AND, represents logical OR, false < true, 0 = true, 1 = false. When representing the dependency relationship with real numbers, D = R + ∪ {∞}, represents finding the minimum value, represents the addition operation, < is the size relationship, 0 = ∞, 1 = 0.

[0017] The first step in causal analysis of a model is to convert the model into a port-to-port graph. The two ends of the connector always have causality 1. The causality between any two ports is obtained by all the paths between the two ports. The causality between two ports without a path is 0, and the series combination is Calculation, the parallel combination is given by Calculation. An addition unit of 0 indicates that there is no dependency between the two ports, otherwise it indicates that there is a dependency. If the dependency from a port to itself in a cyclic path is 1, it indicates that there is a deadlock (causal loop).

[0018] In the process of model scheduling and execution, the ideal situation is that when each Actor is executed, the data of all its input ports are complete, which helps to reach the fixed point with fewer iterations. The dependency graph is obtained through causal analysis, and then the Actor corresponding to the execution port that should be scheduled first is obtained through topological sorting of the dependency graph. At present, the white box model in the prior art is defined as each component of the system including its parameters and connections are visible; while the black box model can only see the ports it contains in the outer layer, but does not know the components and connections included. In the case of white boxes, the above analysis method can obtain a complete dependency graph. However, when a black box exists in the system, the system cannot judge its causality. Summary of the invention

[0019] The purpose of the present invention is to solve the problems in the prior art and to propose a method for optimizing the execution efficiency of a mixed signal system with a black box subsystem.

[0020] The present invention is implemented by the following technical solution. The present invention proposes a method for optimizing the execution efficiency of a mixed signal system with a black box subsystem. The method comprises the following steps:

[0021] Step 1: For a black box model, let all input ports be I, where |I| represents the number of input ports. Use the one-hot encoding method to construct |I| inputs, denoted as M. |I| ;

[0022] Step 2: All output ports of the black box model are recorded as O, where |O| represents the number of output ports. For each unique hot encoded input in step 1, run the black box model and record the corresponding output signal R |I| ;

[0023] Step 3: Based on the relationship between the one-hot encoded input and each output port obtained in step 2, establish δ(p1,p2) to represent the dependency of output port p2 on input port p1;

[0024] Step 4: According to the dependency relationship, convert all black box models into port-to-port graphs;

[0025] Step 5. Finally, the priority scheduling execution order corresponding to all models is obtained by establishing the topological sorting of the entire dependency graph.

[0026] Furthermore, there are 5 input ports.

[0027] Furthermore, when there are 5 input ports, construct the one-hot encoding input M |I| It is {000001,000010,000100,001000,010000,100000}, where 0 means no input is provided and 1 means a specific input value is provided.

[0028] Furthermore, for the input 000010, the three outputs of the Actor are 101; 0 means that there is no way to determine the output value, and 1 means that the output value can be determined.

[0029] Furthermore, the number of output signals is consistent with the number of one-hot encoded inputs.

[0030] Furthermore, the establishment of the dependency relationship is specific: the input use case starts with all 0s, and the test is performed in sequence by setting a certain 1 bit to 1, setting a certain 2 bits to 1, and so on. All input use cases form a tree. During the test, only the groups with different output values ​​from the parent node test are focused on. If a certain bit of the output value changes from 0 to 1, the output port represented by the bit has a dependency relationship with the port represented by 1 in the input value.

[0031] Furthermore, the tree structure is specifically as follows: 001, 010, and 100 are all child nodes of 000, and 011 and 101 are child nodes of 001.

[0032] Furthermore, when a black box exists in a system, the system is an opaque subsystem or a component introduced by an external program in an attempt to perform a joint simulation.

[0033] The present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the method for optimizing the execution efficiency of a mixed signal system with a black box subsystem are implemented.

[0034] The present invention provides a computer-readable storage medium for storing computer instructions. When the computer instructions are executed by a processor, the steps of the method for optimizing the execution efficiency of a mixed signal system with a black box subsystem are implemented.

[0035] Beneficial effects of the present invention:

[0036] The present invention proposes a method for optimizing the execution efficiency of a mixed signal system with a black box subsystem, which can solve the problem that the traditional scheduling method can only perform causal analysis on the white box system but cannot perform causal analysis on the black box subsystem. The method of the present invention provides a more complete and efficient mixed signal system simulation execution method. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0038] Figure 1 Flowchart of the method for optimizing scheduling order in the presence of a black box model. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] In view of the problems in the background technology, the present invention needs to try to give some simple inputs to test its outputs, estimate its causal properties indirectly, and then optimize the execution efficiency of the system.

[0041] Combination Figure 1 The present invention proposes a method for optimizing the execution efficiency of a mixed signal system with a black box subsystem, the method comprising the following steps:

[0042] Step 1: For a black box model, let all input ports be I, where |I| represents the number of input ports. Use the One-Hot Encoding method to construct |I| inputs, denoted as M. |I| ;

[0043] Step 2: All output ports of the black box model are recorded as O, where |O| represents the number of output ports. For each uniquely encoded input in step 1, run the black box model and record the corresponding output signal R |I| ;

[0044] Step 3: Based on the relationship between the one-hot encoded input and each output port obtained in step 2, establish δ(p1,p2) to represent the dependency of output port p2 on input port p1;

[0045] Step 4: According to the dependency relationship, convert all black box models into port-to-port graphs;

[0046] Step 5. Finally, the priority scheduling execution order corresponding to all models is obtained by establishing the topological sorting of the entire dependency graph.

[0047] Furthermore, there are 5 input ports.

[0048] Furthermore, when there are 5 input ports, construct the one-hot encoding input M |I| It is {000001,000010,000100,001000,010000,100000}, where 0 means no input is provided and 1 means a specific input value is provided.

[0049] Furthermore, for the input 000010, the three outputs of the Actor are 101; 0 means that there is no way to determine the output value, and 1 means that the output value can be determined.

[0050] Furthermore, the number of output signals is consistent with the number of one-hot encoded inputs.

[0051] Furthermore, the establishment of the dependency relationship is specific: the input use case starts with all 0s, and the test is performed in sequence by setting a certain 1 bit to 1, setting a certain 2 bits to 1, and so on. All input use cases form a tree. During the test, only the groups with different output values ​​from the parent node test are focused on. If a certain bit of the output value changes from 0 to 1, the output port represented by the bit has a dependency relationship with the port represented by 1 in the input value.

[0052] Furthermore, the tree structure is specifically as follows: 001, 010, and 100 are all child nodes of 000, and 011 and 101 are child nodes of 001.

[0053] Furthermore, when a black box exists in a system, the system is an opaque subsystem or a component introduced by an external program in an attempt to perform a joint simulation.

[0054] The present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the method for optimizing the execution efficiency of a mixed signal system with a black box subsystem are implemented.

[0055] The present invention provides a computer-readable storage medium for storing computer instructions. When the computer instructions are executed by a processor, the steps of the method for optimizing the execution efficiency of a mixed signal system with a black box subsystem are implemented.

[0056] The memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DRRAM). It should be noted that the memory of the method described in the present invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0057] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a high-density digital video disc (DVD)), or a semiconductor medium (eg, a solid state disc (SSD)).

[0058] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0059] It should be noted that the processor in the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiment can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor can be combined and performed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0060] The above is a detailed introduction to the method for optimizing the execution efficiency of a mixed signal system with a black box subsystem proposed in the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for optimizing the execution efficiency of a mixed signal system with a black box subsystem. An Actor has one or more ports, which are divided into input ports and output ports. The Actor receives or sends messages at the input or output ports, and the messages are also called signals. A set of signals at each port is called the behavior of the Actor. Actors with continuous behaviors and Actors with discrete behaviors together constitute a mixed signal system. Multiple Actors are assembled into a composite Actor by establishing connectors between ports. The connector from the output port a1 of ActorA to the input port b1 of ActorB indicates that the signal will flow from the a1 port of ActorA to the b1 port of ActorB. It is characterized in that When a black box exists in the system, the system is an opaque subsystem or a component introduced by an external program to attempt to perform a joint simulation; the method comprises the following steps: Step 1: For a black box model, let all input ports be I, where |I| represents the number of input ports. Use the one-hot encoding method to construct |I| inputs, denoted as M. |I| ; Step 2: All output ports of the black box model are recorded as O, where |O| represents the number of output ports. For each uniquely encoded input in step 1, run the black box model and record the corresponding output signal R |I| ; Step 3: Based on the relationship between the one-hot encoded input and each output port obtained in step 2, establish δ(p1,p2) to represent the dependency of output port p2 on input port p1; Step 4: According to the dependency relationship, convert all black box models into port-to-port graphs; Step 5. Finally, the priority scheduling execution order corresponding to all models is obtained by establishing the topological sorting of the entire dependency graph.

2. The method according to claim 1, characterized in that There are five input ports.

3. The method according to claim 2, characterized in that When there are 5 input ports, construct a one-hot encoding input M |I| It is {000001,000010,000100,001000,010000,100000}, where 0 means no input is provided and 1 means a specific input value is provided.

4. The method according to claim 3, characterized in that For input 000010, the three outputs of the Actor are 101; 0 means there is no way to determine the output value, and 1 means the output value can be determined.

5. The method according to claim 4, characterized in that The number of output signals is the same as the number of one-hot encoded inputs.

6. The method according to claim 1, characterized in that The establishment of the dependency relationship is specific as follows: the input use case starts with all 0s, and the test is carried out in sequence by setting a certain 1 bit to 1, setting a certain 2 bits to 1, and so on. All input use cases form a tree. During the test, only the groups with different output values ​​from the parent node test are focused on. If a certain bit of the output value changes from 0 to 1, the output port represented by this bit has a dependency relationship with the port represented by 1 in the input value.

7. The method according to claim 6, characterized in that The tree structure is specifically as follows: 001, 010, and 100 are all child nodes of 000, and 011 and 101 are child nodes of 001.

8. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

9. A computer-readable storage medium for storing computer instructions, characterized in that: When the computer instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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