A MOSFET device and a method of manufacturing the same

Abstract

The application discloses a MOSFET device and a manufacturing method thereof, and relates to the technical field of semiconductor integrated circuit manufacturing. The manufacturing method of the MOSFET device comprises the following steps: providing a substrate; manufacturing an epitaxial layer containing a first preset number of P+ columns on the surface of the substrate; manufacturing a second preset number of P-columns between each P+ column in the gate region of the surface of the epitaxial layer, so that each P+ column in the gate region is connected through each P-column; manufacturing a gate oxide layer on the surface of the epitaxial layer, depositing polysilicon on the surface of the gate oxide layer to form a polysilicon layer, and etching the polysilicon layer; manufacturing a metal layer of the MOSFET device to obtain the MOSFET device; when the body diode of the MOSFET is in a reverse recovery state, the structure that the P+ columns and the P-columns are alternately connected can effectively inhibit and relieve the peak electric field at the place, thereby improving the ability to inhibit dynamic avalanche.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a MOSFET device and a manufacturing method thereof. BACKGROUND

[0002] The reverse recovery performance of the body diode of the power MOSFET device is much lower than that of the fast recovery diode and the Schottky diode, and the reverse recovery charge is much larger, so the reverse recovery characteristics are poor; the switching loss of the diode is increased, the efficiency of the system is reduced, and at the same time, a higher ring is generated, which affects the safe operation of the power MOSFET device.

[0003] In order to solve the above problems, a super junction type MOSFET device is invented, which is a new type of power device with high current density and low on-resistance; for the traditional high-voltage power super junction type MOSFET device, the currently used way is to introduce a complex center in the MOSFET device body, through electron / neutron irradiation or heavy metal source diffusion, using impurity hole defects or heavy metal deep level impurity ions to introduce defects in the MOSFET device body, to reduce the minority carrier lifetime, and then to improve the body diode reverse recovery rate; however, the MOSFET device manufactured by this method still uses P-N columns in an alternating manner to maintain charge balance, and due to the large area of the P-N junction, the maximum value of the diode transient reverse current (Irrm) and the integral value of the diode current reverse part and time (Qrr) increase sharply, which causes avalanche effect and makes the MOS device fail. SUMMARY

[0004] Therefore, it is necessary to provide a MOSFET device and a manufacturing method thereof to solve the problem that the MOSFET device in the prior art can cause the maximum value of the diode transient reverse current (Irrm) and the integral value of the diode current reverse part and time (Qrr) to increase sharply, which causes avalanche effect and makes the MOS device fail.

[0005] In a first aspect, the present application provides a manufacturing method of a MOSFET device, comprising:

[0006] providing a substrate;

[0007] forming an epitaxial layer containing a first preset number of P+ columns on the surface of the substrate;

[0008] forming a second preset number of P- columns between each of the P+ columns in the gate region on the surface of the epitaxial layer, so that each of the P+ columns in the gate region is connected by each of the P- columns.

[0009] A gate oxide layer is made on the surface of the epitaxial layer, a polysilicon layer is formed by depositing polysilicon on the surface of the gate oxide layer, and the polysilicon layer is etched;

[0010] A metal layer of the MOSFET device is made, and a MOSFET device is obtained.

[0011] The above scheme has the following beneficial effects:

[0012] The manufacturing method of the MOSFET device of the application makes P- columns connected to the P+ columns between the P+ columns in the gate region, and the structure that the P+ columns and the P- columns are alternately connected can effectively inhibit and relieve the peak electric field at this place when the body diode of the MOSFET is in a reverse recovery state, thereby improving the ability to inhibit dynamic avalanche.

[0013] Optionally, an epitaxial layer containing a first preset number of P+ columns is made on the surface of the substrate, including:

[0014] A first epitaxial layer with a preset thickness is deposited on the surface of the substrate;

[0015] Photoresist is applied on the surface of the first epitaxial layer;

[0016] The photoresist is exposed, and the exposed photoresist is etched by photolithography using a P+ mask, to form a hard mask with a first preset number of windows on the surface;

[0017] P-type ions are implanted at the positions of the windows of the hard mask to form a first preset number of initial P+ columns in the first epitaxial layer;

[0018] The photoresist is removed, and a plurality of layers of epitaxial layers with P+ columns are repeatedly made on the surface of the first epitaxial layer, and after the last layer of epitaxial layer is made, high-temperature annealing is performed to form an epitaxial layer containing a first preset number of P+ columns.

[0019] Optionally, a first epitaxial layer with a preset thickness is deposited on the surface of the substrate, including:

[0020] N-type impurities are deposited on the surface of the substrate by chemical vapor deposition to form an N- epitaxial layer with a preset thickness.

[0021] Optionally, a second preset number of P- columns are made between each of the P+ columns in the gate region on the surface of the epitaxial layer, so that each of the P+ columns in the gate region is connected through each of the P- columns, including:

[0022] A photo mask is made by photoresist on the gate region of the epitaxial layer surface, the photo mask covers each P+ column of the gate region, and exposes the region between each P+ column of the gate region;

[0023] P-type ions are injected above the photo mask, the P-type ions are injected into the region between each P+ column of the gate region through the exposed region of the photo mask, and each P- column is formed.

[0024] Optionally, after etching the polysilicon layer, the method comprises:

[0025] An insulating medium layer is made on the surface of the polysilicon layer;

[0026] A metal layer is made on the surface of the insulating medium layer.

[0027] In a second aspect, the present application provides a MOSFET device, comprising:

[0028] A substrate;

[0029] An epitaxial layer above the substrate;

[0030] A first preset number of P+ columns and a second preset number of P- columns are arranged in the epitaxial layer, each P+ column extends a preset distance into the epitaxial layer from the surface of the epitaxial layer, each P- column is arranged between each P+ column of the gate region, and the two sides of each P- column are connected to adjacent P+ columns;

[0031] A gate oxide layer above the epitaxial layer;

[0032] A polysilicon layer above the gate oxide layer;

[0033] A metal layer on the surface of the MOSFET device.

[0034] The above scheme has the following beneficial effects:

[0035] The MOSFET device of the present application sets P- columns connected to P+ columns between the P+ columns of the gate region, and the structure of the alternating connection of the P+ columns and the P- columns can effectively suppress and alleviate the peak electric field at this point when the body diode of the MOSFET is in the reverse recovery state, thereby improving the ability to suppress dynamic avalanche.

[0036] Optionally, the MOSFET device further comprises:

[0037] An insulating medium layer above the polysilicon layer.

[0038] Optionally, the thickness of the epitaxial layer ranges from 70 μm to 110 μm.

[0039] Optionally, the P+ column extends into the epitaxial layer by a distance greater than the distance by which the P- column extends into the epitaxial layer.

[0040] Optionally, the upper surface of the P+ column is in the same plane as the upper surface of the P- column. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings described in the following description are only some of the embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0042] Figure 1 is a flowchart of a manufacturing method of a MOSFET device provided in an embodiment of the present application;

[0043] Fig. 2(a) is a structural diagram of manufacturing an epitaxial layer with a P+ column on a substrate provided in an embodiment of the present application;

[0044] Fig. 2(b) is a structural diagram of manufacturing a P- column on the epitaxial layer provided in an embodiment of the present application;

[0045] Fig. 2(c) is a structural diagram of manufacturing a gate oxide layer and a polysilicon layer on the epitaxial layer provided in an embodiment of the present application;

[0046] Fig. 2(d) is a structural diagram of manufacturing an insulating medium layer and a metal layer on the gate oxide layer provided in an embodiment of the present application;

[0047] Figure 3 is a structural diagram of a MOSFET device provided in an embodiment of the present application;

[0048] The symbols are explained as follows:

[0049] 1, substrate; 2, epitaxial layer; 3, P+ column; 4, P- column; 5, gate oxide layer; 6, polysilicon layer; 7, insulating medium layer; 8, metal layer; 9, cell region P- region. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments.

[0051] It should be understood that the embodiments set forth herein represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best modes of practicing the embodiments. Upon reading the following description, those skilled in the art will understand how to implement the concepts described herein and will realize the scope of the disclosure and will realize the applicability of the concepts described herein to other applications. It should be understood that these concepts and applications fall within the scope of the disclosure and the following claims.

[0052] It should also be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0054] It should also be understood that the terms "upper", "lower", "left", "right", "front", "rear", "bottom", "intermediate", "middle", "top", and the like, can be used in this document to describe various elements as their orientation or position relationship based on the orientation or position relationship shown in the drawings, only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore these elements should not be limited by these clauses.

[0055] These terms are only used to distinguish one element from another. For example, a first element can be referred to as an "upper" element, and similarly, a second element can be referred to as an "upper" element according to the relative orientation of these elements, without departing from the scope of the present disclosure.

[0056] It is further understood that the terms "including", "including", "including" and / or "including" as used herein specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that the terms used herein should be interpreted as having the same meaning as they mean in the context of this specification and related art, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0058] In one embodiment, a method such as Figure 1 The method for manufacturing a MOSFET device shown includes the following steps:

[0059] Step S100: Provide a substrate.

[0060] In this embodiment, referring to Figure 2(a), a substrate 1 is first provided. The substrate 1 can be silicon (Si) based, and generally silicon (Si) or silicon dioxide (SiO2) is used as the substrate. The silicon (Si) or silicon dioxide (SiO2) substrate is formed on the silicon surface by thermal oxidation process to form a silicon dioxide (SiO2) insulating layer on the silicon substrate; a wafer can also be used as the substrate of the MOSFET device.

[0061] Step S200: An epitaxial layer containing a first predetermined number of P+ pillars is formed on the surface of the substrate.

[0062] Referring to Figure 2(a), an epitaxial layer 2 containing a first predetermined number of P+ pillars 3 is fabricated on the surface of substrate 1. The fabrication of the epitaxial layer 2 containing P+ pillars 3 is carried out using a multi-step epitaxial fabrication method, which includes the following steps:

[0063] Step S201: Deposit a first epitaxial layer of a predetermined thickness on the surface of the substrate.

[0064] In this embodiment, N-type impurities are deposited on the surface of substrate 1 by low-pressure chemical vapor deposition (LPVCD) to form a first epitaxial layer of a predetermined thickness. This epitaxial layer is an N-type epitaxial layer. Low-pressure chemical vapor deposition is widely used for the deposition of silicon oxide, nitrides, and polysilicon. The process is performed in a tube furnace and requires a very high temperature.

[0065] Step S202: Apply photoresist to the surface of the first epitaxial layer.

[0066] After the first epitaxial layer on the surface of substrate 1 is fabricated, photoresist is applied to the surface of the first epitaxial layer. This photoresist can be used to fabricate a hard mask with a first preset number of windows.

[0067] Step S203: Expose photoresist, etch the exposed photoresist using P+ photomask mask photoetching to form a hard mask with a first predetermined number of windows on the surface.

[0068] After the photoresist is applied, the applied photoresist is exposed, and then the pre-prepared P+ photomask mask is placed on the exposed photoresist. The exposed photoresist is etched by laser, the position of the P+ column 3 is set on the surface of the exposed photoresist, and then the window is opened at the position of the photoresist corresponding to each P+ column 3. The number of windows is the same as the number of P+ columns, that is, the first predetermined number.

[0069] Step S204: Perform P-type ion implantation at the position of each window to form a first predetermined number of initial P+ columns in the first epitaxial layer.

[0070] P+ ion doping is performed on the surface of the hard mask formed by the photoresist by ion implantation. During P+ ion implantation, P+ ions pass through the window opened on the photoresist into the epitaxial layer 2 to form a first predetermined number of initial P+ columns. In this embodiment, the P+ ion can be phosphorus (P), and the P+ ion implantation concentration is about 1E13 / cm 2 , and the implantation energy is 40KeV-70KeV.

[0071] Step S205: Remove the photoresist and repeatedly produce several layers of epitaxial layers with P+ columns on the surface of the first epitaxial layer. After the last layer of epitaxial layer is produced, high-temperature annealing is performed to form an epitaxial layer containing a first predetermined number of P+ columns.

[0072] The first epitaxial layer is produced by the above steps, and then the photoresist on the surface of the first epitaxial layer is removed. The second epitaxial layer is produced in the same way. When producing the second epitaxial layer, the position of the window opened again needs to be the same as the position of the window opened the first time to ensure that the positions of the P+ columns in each layer are consistent. After the second layer of epitaxial layer is produced, the third layer is produced, and so on, until the thickness of the epitaxial layer 2 reaches the predetermined thickness and the thickness of the epitaxial layer 2 reaches the applicable withstand voltage of the device. Finally, the impurities of the buried layer ions in each layer are activated by a high-temperature drive-in step. The P+ ions move and connect to each other in a high-temperature environment to form a P+ columnar structure, forming an epitaxial layer 2 containing a first predetermined number of P+ columns 3 as shown in FIG. 2(a).

[0073] In this embodiment, the epitaxial layer is grown 9-11 times, and the thickness of each growth is 8μm-10μm. The thickness of the epitaxial layer 2 is 70μm-110μm.

[0074] Step S300: A second preset number of P- pillars are made between each P+ pillar in the gate region on the surface of the epitaxial layer, so that each P+ pillar in the gate region is connected by each P- pillar.

[0075] Referring to Fig. 2(b), after the P+ pillars are made, the P- pillars 4 in the gate region and the P- region 9 in the cell region need to be made, and the making method includes the following steps:

[0076] Step S301: A photoresist is made on the surface of the epitaxial layer in the gate region, and the photoresist covers each P+ pillar in the gate region, exposing the area between each P+ pillar in the gate region.

[0077] In this embodiment, when the terminal structure layout is designed, the terminal expansion area of the original main junction in the periphery is reduced, and the source metal hole in the terminal structure area is taken as the starting point, and the terminal at the right edge of the polysilicon gate trace is taken as the end, covering 4-7 P+ pillars 3; according to the above terminal structure layout design, a photoresist is made on the surface of the epitaxial layer 2, and the photoresist covers 4-7 P+ pillars 3 in the gate region, and exposes the area between the P+ pillars 3 in the gate region; at the same time, the P- region 9 in the right cell region is exposed.

[0078] Step S302: P-type ions are injected above the photoresist, so that the P-type ions are injected into the area between each P+ pillar in the gate region through the exposed area of the photoresist, forming each P- pillar.

[0079] After the photoresist is made, the photoresist is used as a barrier to prevent P-type ions from being injected into the P+ pillars 3, so that the P-type ions are only injected into the exposed area of the photoresist, i.e. the area between the P+ pillars 3 in the gate region and the area in the cell region; the P- ion injection energy is about 60KeV-85KeV, and the P- ion injection concentration is about 1E12 / cm 2 -1E14 / cm 2 .

[0080] The final step is high-temperature annealing, which pushes the P- ions to a specific position to form P- pillars 4 between the P+ pillars 3 in the gate region, so that the two sides of the P- pillars 4 are connected to the adjacent P+ pillars 3 respectively, forming a structure in which P+ pillars and P- pillars are alternately connected, as a body region structure of a MOSFET device.

[0081] In this embodiment, in addition to the above-described steps, other steps in the process of manufacturing the MOSFET device are also included, and the existing manufacturing process is used for manufacturing, which will not be described here.

[0082] Step S400: A gate oxide layer is made on the surface of the epitaxial layer, a polysilicon layer is deposited on the surface of the gate oxide layer, and the polysilicon layer is etched.

[0083] Referring to Fig. 2(c), the gate oxide layer 5 is grown on the surface of the epitaxial layer 2, then the polysilicon layer 6 is deposited on the surface of the gate oxide layer, and then the polysilicon layer 6 is etched according to the design photolithography.

[0084] After the polysilicon deposition is completed, the P-body region needs to be made, and on the basis of the previous P-region, the polysilicon layer 6 is used as an implantation barrier layer to perform P-body fine-tuning manufacturing, so as to ensure that the device channel opening length is not affected, and then through normal process, the N+ well and other process structure manufacturing are completed.

[0085] Step S500: manufacturing a metal layer of the MOSFET device to obtain the MOSFET device.

[0086] Referring to Fig. 2(d), the insulating medium layer 7 is made on the surface of the polysilicon layer 6 and the gate oxide layer 5, the metal layer 8 is made on the surface of the insulating medium layer 7, and each electrode of the MOSFE device and other process manufacturing are made to obtain the manufactured MOSFET device.

[0087] The manufacturing method of the MOSFET device of the embodiment has the following characteristics:

[0088] (1) The field limiting ring structure (FLR) of the embodiment is different from the traditional Pbody rectangular electric field structure. The P+ column structure region between the terminal is formed by ion implantation, and then the P-type ion implantation region is connected by the Pbody annealing process to form the structure of the P+ column and the P-column alternately arranged. In this way, a dynamic field limiting ring structure is formed, that is, starting from the source metal hole of the terminal structure region, to the end of the right side of the polysilicon gate trace, covering 4-7 P+ columns. Its purpose is to replace the traditional Pbody structure formed by the P+ column and the P-column alternately spaced. When static blocking, the structure has the same function as the Pbody region and can realize the function of main junction depletion. When the body diode of the MOS tube is in the reverse recovery state, the peak electric field of the traditional Pbody structure will rapidly rise to form a dynamic avalanche, and the P+ column and the P-column alternately arranged structure can effectively suppress and link the peak electric field here, thereby achieving the ability to suppress the dynamic avalanche.

[0089] (2) The manufacturing of the MOSFET device of the embodiment can be realized on the basis of the existing super-junction MOSFET device manufacturing process, without additional manufacturing cost.

[0090] (3) Without affecting the performance of the device, the phenomenon of uneven free carrier extraction caused by the high-speed current change rate di / dt in the reverse recovery process of the body diode of the MOSFET device is effectively solved.

[0091] In one embodiment, there is provided a MOSFET device as shown in the drawings, comprising: a substrate 1; an epitaxial layer 2, wherein the epitaxial layer 2 is located above the substrate 1; a first preset number of P+ columns 3 and a second preset number of P- columns 4 are arranged in the epitaxial layer 2, each P+ column 3 extends into the epitaxial layer 2 by a preset distance from the surface of the epitaxial layer 2, each P- column 4 is arranged between each P+ column 3 in the gate region, and the two sides of each P- column 4 are connected to the adjacent P+ columns 3, respectively; a gate oxide layer 5, wherein the gate oxide layer 5 is located above the epitaxial layer 2; a polysilicon layer 6, wherein the polysilicon layer 6 is located above the gate oxide layer 5; and a metal layer 8, wherein the metal layer 8 is located on the surface of the MOSFET device. Figure 3

[0092] Further, the MOSFET device further comprises: an insulating medium layer 7, wherein the insulating medium layer 7 is located above the gate oxide layer 5 and serves as an insulating function.

[0093] Further, the thickness of the epitaxial layer 2 is in the range of 70 μm-110 μm.

[0094] Further, the distance that the P+ column extends into the epitaxial layer 2 is greater than the distance that the P- column extends into the epitaxial layer 2, so that the P- column is connected to the upper part of the P+ column.

[0095] Further, the upper surface of the P+ column and the upper surface of the P- column are in the same plane.

[0096] The MOSFET device of the present embodiment has the following features:

[0097] (1) The P+ column and the P- column are arranged alternately, and when static blocking, the structure has the same function as the P-body region, which can realize the function of main junction depletion; when the body diode of the MOS tube is in a reverse recovery state, the peak electric field of the traditional P-body structure will rapidly rise to form a dynamic avalanche, and the P+ column and the P- column alternately arranged structure can effectively suppress and link the peak electric field here, thereby achieving the ability to suppress dynamic avalanche.

[0098] (2) Without affecting the performance of the device, the phenomenon of uneven extraction of free carriers caused by high-speed current rate di / dt in the reverse recovery process of the body diode of the MOSFET device is effectively solved.

[0099] ​The above-described embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for manufacturing a MOSFET device, characterized in that, Applied to the terminal area, including: Provide a substrate; An N-epitaxial layer containing a first predetermined number of P+ pillars is formed on the surface of the substrate; A second predetermined number of P-pillars are formed between each of the P+ pillars in the gate region on the surface of the epitaxial layer, such that each of the P+ pillars in the gate region is connected through each of the P-pillars. A gate oxide layer is formed on the surface of the epitaxial layer, and polysilicon is deposited on the surface of the gate oxide layer to form a polysilicon layer, and the polysilicon layer is etched. A metal layer is fabricated to obtain the MOSFET device; the metal layer is located on the surface of the MOSFET device. The distance by which the P+ pillar extends into the epitaxial layer is greater than the distance by which the P- pillar extends into the epitaxial layer; the upper surface of the P+ pillar and the upper surface of the P- pillar are on the same plane.

2. The method for manufacturing a MOSFET device according to claim 1, characterized in that, Fabricating an epitaxial layer containing a first predetermined number of P+ pillars on the surface of the substrate includes: A first epitaxial layer of a predetermined thickness is deposited on the surface of the substrate; Photoresist is applied to the surface of the first epitaxial layer; The photoresist is exposed, and the exposed photoresist is etched using a P+ photomask to form a hard mask with the first preset number of windows on its surface. P-type ion implantation is performed at the locations of each window of the hard mask to form a first predetermined number of initial P+ pillars within the first epitaxial layer; Remove the photoresist, and repeatedly fabricate several epitaxial layers with P+ pillars on the surface of the first epitaxial layer. After the last epitaxial layer is fabricated, perform high-temperature annealing to form an epitaxial layer containing a first preset number of P+ pillars.

3. The method for manufacturing a MOSFET device according to claim 2, characterized in that, A first epitaxial layer of a predetermined thickness is deposited on the surface of the substrate, comprising: N-type impurities are deposited on the surface of the substrate using chemical vapor deposition to form an N-epitaxial layer of a predetermined thickness.

4. The method for manufacturing a MOSFET device according to claim 1, characterized in that, A second predetermined number of P-pillars are formed between each of the P+ pillars in the gate region on the surface of the epitaxial layer, such that the P+ pillars in the gate region are connected through each of the P-pillars, including: A photomask is fabricated using photoresist on the gate region of the epitaxial layer surface. The photomask covers each of the P+ pillars of the gate region, exposing the area between each of the P+ pillars of the gate region. P-type ions are injected above the photomask, allowing the P-type ions to pass through the exposed area of ​​the photomask and be injected into the area between each of the P+ pillars in the gate region, forming each of the P- pillars.

5. The method for manufacturing a MOSFET device according to claim 1, characterized in that, After etching the polysilicon layer, the process includes: An insulating dielectric layer is formed on the surface of the polycrystalline silicon layer; A metal layer is formed on the surface of the insulating dielectric layer.

6. A MOSFET device, characterized in that, Applied to the terminal area, including: Substrate; N-Epipolar layer, the epitaxial layer being located above the substrate; The epitaxial layer is provided with a first preset number of P+ pillars and a second preset number of P- pillars. Each P+ pillar extends a preset distance from the surface of the epitaxial layer into the epitaxial layer. Each P- pillar is disposed between each P+ pillar in the gate region. The two sides of each P- pillar are respectively connected to the adjacent P+ pillar. A gate oxide layer, wherein the gate oxide layer is located above the epitaxial layer; A polysilicon layer, the polysilicon layer being located above the gate oxide layer; A metal layer located on the surface of the MOSFET device; The distance by which the P+ pillar extends into the epitaxial layer is greater than the distance by which the P- pillar extends into the epitaxial layer; the upper surface of the P+ pillar and the upper surface of the P- pillar are on the same plane.

7. The MOSFET device according to claim 6, characterized in that, The MOSFET device further includes: An insulating dielectric layer is located above the polycrystalline silicon layer.

8. The MOSFET device according to claim 6, characterized in that, The thickness of the epitaxial layer ranges from 70 μm to 110 μm.

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