analog-to-digital converter

Abstract

The application relates to the field of integrated circuits and discloses an analog-to-digital converter, which comprises an integrator and a sub-analog-to-digital conversion structure coupled with the integrator, the sub-analog-to-digital conversion structure comprising a comparator array and a resistance network. n‑1 The comparator array comprises two comparators, the first input end of each comparator is connected with an input voltage, and the output end of each comparator is connected with a decoder. n‑1 The resistance network comprises two 2R resistors connected in series. n‑1 Each 2R resistor is sequentially connected between the second input ends of adjacent comparators in the two comparators. n‑1 One end of the first 2R resistor is connected with a first reference voltage through a first control switch, a 1R resistor and a second control switch, and one end of the last 2R resistor is connected with a second reference voltage through a 2R resistor, a first control switch, a 1R resistor and a second control switch. The application can significantly reduce the power consumption and area of the sub-ADC, so that the overall power consumption and area of the sigma-delta ADC can be further reduced.

Description

Technical Field

[0001] This invention generally relates to the field of integrated circuit technology, and particularly to an analog-to-digital converter. Background Technology

[0002] Sigma-delta analog-to-digital converters (ADCs) are widely used in medical, sensor, and battery management system (BMS) fields. Many applications are battery-powered and require low power consumption. Meanwhile, cost is also a major concern for consumer and medical applications. Low-order multi-bit quantization (such as second-order 4-bit) sigma-delta structures can achieve high precision, low cost, and low power consumption. However, traditional multi-bit quantization sub-ADCs use Flash ADCs, and the large number of comparators results in significant power consumption and area limitations, restricting further reductions in overall ADC area and power consumption.

[0003] High-precision, low-power, and low-cost ADCs typically employ low-order multi-bit Sigma-delta ADCs. Lower-order ADCs use fewer integrators, saving area and power. However, to achieve high precision, multi-bit quantization is necessary. For example, a 24-bit ADC often uses second-order 4-bit or second-order 5-bit quantization. Implementing multi-bit quantization in a sub-ADC requires a larger number of comparators, contributing significantly to area and power consumption.

[0004] Therefore, achieving a low-cost, low-power sub-ADC is the problem that this solution needs to solve. Summary of the Invention

[0005] The purpose of this specification is to provide an analog-to-digital converter that, based on a Flash ADC, proposes a two-step time-division multiplexing comparator structure, which can significantly reduce the power consumption and area of ​​the sub-ADC, thereby further reducing the overall power consumption and area of ​​the sigma-delta ADC.

[0006] This application discloses an analog-to-digital converter, comprising:

[0007] Integrator;

[0008] The sub-analog-to-digital converter structure coupled to the integrator includes:

[0009] Comparator array, the comparator array comprising 2 n-1 There are 1 comparator, wherein the first input terminal of each comparator is connected to the input voltage, and the output terminal of each comparator is connected to the decoder;

[0010] as well as

[0011] A resistor network, the resistor network comprising 2 resistors connected in series n-1 -1 2R resistor, the 2 n-1-1 2R resistors, each of which is connected sequentially to the 2 n-1 Between the second input terminals of adjacent comparators in the comparator, one end of the first 2R resistor is connected to the first reference voltage through a first control switch, an R resistor, and a second control switch, respectively. One end of the last 2R resistor is connected to the second reference voltage through a 2R resistor, a first control switch, an R resistor, and a second control switch, respectively.

[0012] In a preferred embodiment, the decoder includes 2 n-1 One latch, the 2 n-1 The output of each comparator is connected to the data terminal of a latch.

[0013] In a preferred embodiment, when the first control switch is closed and the second control switch is open, the 2 n-1 The output voltage of each comparator in the 2 comparators is stored by a corresponding latch. When the second control switch is closed and the first control switch is open, the voltage is controlled by the 2... n-1 The outputs of the comparators constitute an even number of bits, and the 2... n-1 The outputs of the latches form an odd-number combination of 2. n Bit output.

[0014] In a preferred embodiment, the integrator samples in the first phase and establishes in the second phase. The comparison time required for the comparator array to complete one comparison is t1. At least 2*t1 before the end of the second phase, the first control switch is closed and the second control switch is opened. After the comparator array completes one comparison, the second control switch is closed and the first control switch is opened.

[0015] This application discloses an analog-to-digital converter, comprising:

[0016] Integrator;

[0017] The sub-analog-to-digital converter structure coupled to the integrator includes:

[0018] Comparator array, the comparator array comprising 2 n-1 There are 1 comparator, wherein the first input terminal of each comparator is connected to the input voltage, and the output terminal of each comparator is connected to the decoder;

[0019] as well as

[0020] A resistor network, the resistor network comprising 2 resistors connected in series n-1 -1 2R resistor and two 0.5R resistors located at both ends, the 2 n-1 -1 2R resistors, each of which is connected sequentially to the 2n-1 Between the second input terminals of adjacent comparators in the comparator, one end of the first 0.5R resistor is connected to the first reference voltage through a first control switch, an R resistor, and a second control switch, respectively. One end of the second 0.5R resistor is connected to the second reference voltage through an R resistor, a first control switch, and a second control switch, respectively.

[0021] In a preferred embodiment, the integrator samples in the first phase and establishes in the second phase. The comparison time required for the comparator array to complete one comparison is t1. At least 2*t1 before the end of the second phase, the first control switch is closed and the second control switch is opened. After the comparator array completes one comparison, the second control switch is closed and the first control switch is opened.

[0022] This application discloses an analog-to-digital converter, comprising:

[0023] Integrator;

[0024] The sub-analog-to-digital converter structure coupled to the integrator includes:

[0025] Comparator array, the comparator array comprising 2 n-1 A comparator, wherein the first input terminal of each comparator is connected to a first input voltage, the second input terminal of each comparator is connected to a second input voltage, and the output terminal of each comparator is connected to a decoder;

[0026] A first resistor network, the first resistor network comprising 2 resistors connected in series n-2 -1 2R resistor, one R resistor, and two 0.5R resistors located at both ends, the 2 n-2 One end of the i-th 2R resistor in the -1 2R resistor is connected to the positive reference voltage of the 2i comparators and the negative reference voltage of the 2i-1 comparators respectively. A first control switch is connected in parallel across the two ends of the R resistor. One end of the second 0.5R resistor is connected to the first reference voltage through an R resistor, the first control switch, and a second control switch respectively.

[0027] The second resistor network, the second resistor network comprising 2 resistors connected in series n-2 -1 2R resistor, one R resistor, and two 0.5R resistors located at both ends, the 2 n-2One end of the i-th 2R resistor in the -1 2R resistor is connected to the negative reference voltage of the 2i comparators and the positive reference voltage of the 2i-1 comparators respectively. The two ends of the R resistor are connected in parallel with the first control switch. One end of the first 0.5R resistor is connected to one end of the first 0.5R resistor in the first resistor network. One end of the second 0.5R resistor is connected to the second reference voltage through an R resistor, the first control switch and the second control switch respectively.

[0028] In a preferred embodiment, the decoder includes 2 n-1 There are 10 latches, and the output of each comparator is connected to the data terminal of one latch.

[0029] In a preferred embodiment, when the first control switch is closed and the second control switch is open, the 2 n-1 The output voltage of each comparator in the 2 comparators is stored by a corresponding latch. When the second control switch is closed and the first control switch is open, the voltage is controlled by the 2... n-1 The outputs of the comparators constitute an even number of bits, and the 2... n-1 The outputs of the latches form an odd-number combination of 2. n Bit output.

[0030] In a preferred embodiment, the integrator samples in the first phase and establishes in the second phase. The comparison time required for the comparator array to complete one comparison is t1. At least 2*t1 before the end of the second phase, the first control switch is closed and the second control switch is opened. After the comparator array completes one comparison, the second control switch is closed and the first control switch is opened.

[0031] Compared with the prior art, the analog-to-digital converter of this application has at least the following differences and effects:

[0032] This application proposes a two-step time-division multiplexing comparator structure, which can complete two comparisons before the falling edge of the ph2 stage of the integrator setup, and combine the results of the two comparisons to obtain the final comparison result. Compared with the traditional 2 n By reducing the number of comparators by half, the power consumption and area of ​​the sub-ADC can be significantly reduced, allowing for further reduction in the overall power consumption and area of ​​the sigma-delta ADC.

[0033] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of an analog-to-digital converter in one embodiment of this application.

[0035] Figure 2 This is a schematic diagram of the sub-analog-to-digital converter structure in one embodiment of this application.

[0036] Figure 3 This is a schematic diagram of the decoder structure in one embodiment of this application.

[0037] Figure 4 This is a timing diagram of an integrator in one embodiment of this application.

[0038] Figure 5 This is a schematic diagram of the sub-analog-to-digital converter structure in another embodiment of this application.

[0039] Figure 6 This is a schematic diagram of the sub-analog-to-digital converter structure in another embodiment of this application. Detailed Implementation

[0040] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0042] This application discloses an analog-to-digital converter. Figure 1 A schematic diagram of an analog-to-digital converter (ADC) in one embodiment is shown. The ADC includes an integrator 101, a sub-ADC 102, and a digital-to-analog converter 103, which are coupled in sequence.

[0043] refer to Figure 2 As shown, the sub-ADC structure 102 includes a comparator array 201 and a resistor network 202. The comparator array 201 includes 2 n-1 There are comparators 203, wherein the first input terminal of each comparator 203 is connected to the input voltage V. IN The output of each comparator 203 is connected to the decoder 204. For example, the positive input of comparator 203 is connected to the input voltage V. IN .

[0044] The resistor network 202 includes 2 resistors connected in series. n-1 -1 2R resistor, the 2 n-1 -1 2R resistors, each of which is connected sequentially to the 2 n-1 The second input terminals (e.g., negative input terminals) of adjacent comparators 203 in the comparator 203 are connected. For example, one end of the first 2R resistor is connected between the negative input terminals of the first comparator 203.1 and the second comparator 203.2, and one end of the second 2R resistor is connected between the negative input terminals of the second comparator 203.2 and the third comparator, and so on. One end of the first 2R resistor is connected to the first reference voltage V through a first control switch, an R resistor, and a second control switch. REFN One end of the last 2R resistor is connected to the second reference voltage V through a 2R resistor and the first control switch, and an R resistor and the second control switch. REFP .

[0045] It should be noted that the first control switch refers to the switch that closes when the control signal CT is high (e.g., "1"), and the second control switch refers to the switch that closes when the control signal CT is low (e.g., "0"). Furthermore, in other embodiments of this application, one end of the first 2R resistor can also be connected to the first reference voltage V via an R resistor. REFN Furthermore, resistor R is connected in parallel with a first control switch.

[0046] refer to Figure 3 As shown, the decoder 204 includes 2 n-1 One latch 205, the 2 n-1The output of each comparator 203 in the comparators is connected to the data terminal D of a latch 205. In one embodiment, when the first control switch is closed and the second control switch is open (i.e., CT = 1), the 2 n-1 The output voltage of each comparator 203 in the comparators is stored by a corresponding latch 205. When the second control switch is closed and the first control switch is open (i.e., CT = 0), the voltage is stored by the 203. n-1 The output of each comparator 203 in the comparators constitutes an even number of bits, and the 2 n-1 The outputs of latch 205 form an odd-number combination of 2. n Bit output. It should be understood that when CT=1, 2 n-1 Each comparator performs a comparison once, and the comparison result is stored in 2. n-1 In latch 205, 2 n-1 Each latch 205 is used to store the comparison results of an odd number of bits, such as T1, T3, ..., T... 2^n-1 Furthermore, when CT=0, 2 n-1 Each comparator performs another comparison, and the comparison results are T2, T4, ..., T... 2^n This makes the result of latch 205 combine to form 2. n Bit.

[0047] Figure 4 This is a timing diagram of an integrator in one embodiment of this application. The integrator 101 samples in the first phase phase ph1 and establishes in the second phase phase ph2. Assuming the comparison time required for the comparator array 201 to complete one comparison is t1, at least 2*t1 before the end of the second phase phase ph2, the first control switch is closed and the second control switch is open (i.e., CT=1). After the comparator array 201 completes one comparison, the second control switch is closed and the first control switch is open (i.e., CT=0), thereby the comparator array 201 completes the second comparison.

[0048] Specifically, in the ph2 phase, the integrator is established first, and then the comparison is performed. Generally, most of the ph2 phase is spent on integrator setup, with the comparison occurring a short time before the falling edge of ph2. The comparison is performed based on the comparator's speed, for example, 0.5ns. In this scheme, CT = 1 ns before the end of the falling edge of ph2, causing the comparator array to perform its first comparison. After the first comparison, CT = 0, meaning the second comparison begins 0.5ns before the falling edge of ph2, thus completing two comparisons before the falling edge of ph2. Then, the results of the first and second comparisons are combined to obtain the final comparison result.

[0049] It should be noted that in order to obtain 2 n This application only requires 2 bits of output. n-1 One comparator, compared to the traditional 2 n The number of comparators is reduced by half, which significantly reduces the power consumption and area of ​​the sub-ADC, allowing for further reduction in the overall power consumption and area of ​​the sigma-delta ADC.

[0050] Figure 5 This is a schematic diagram of a sub-analog-to-digital converter structure in another embodiment of this application. The sub-analog-to-digital converter structure includes a comparator array 501 and a resistor network 502.

[0051] The comparator array 501 includes 2 n-1 There are 503 comparators, wherein the first input terminal of each comparator 503 is connected to the input voltage V. IN The output of each comparator 503 is connected to the decoder 204. For example, the positive input of comparator 503 is connected to the input voltage V. IN .

[0052] The resistor network 502 includes 2 resistors connected in series. n-1 -1 2R resistor and two 0.5R resistors located at both ends, the 2 n-1 -1 2R resistors, each of which is connected sequentially to the 2 n-1 The second input terminals (e.g., negative input terminals) of adjacent comparators in comparator 503 are connected. For example, one end of the first 2R resistor is connected between the negative input terminals of the first comparator 503.1 and the second comparator 503.2, and one end of the second 2R resistor is connected between the negative input terminals of the second comparator 503.2 and the third comparator, and so on. One end of the first 0.5R resistor is connected to the first reference voltage V through the first control switch, and an R resistor and a second control switch, respectively. REFN One end of the second 0.5R resistor is connected to the second reference voltage V via an R resistor, the first control switch, and the second control switch. REFP .

[0053] The first control switch refers to the switch that closes when the control signal CT is high (e.g., "1"), and the second control switch refers to the switch that closes when the control signal CT is low (e.g., "0"). Furthermore, in other embodiments of this application, one end of the first 0.5R resistor can also be connected to the first reference voltage V via an R resistor. REFN Furthermore, a first control switch is connected in parallel with resistor R. One end of the second 0.5R resistor can also be connected to the first reference voltage V through another resistor R. REFNFurthermore, a second control switch is connected in parallel with resistor R.

[0054] It should be understood that 2R resistor, R resistor and 0.5R resistor refer to 2 unit resistance, 1 unit resistance and 0.5 unit resistance respectively.

[0055] In one embodiment, the decoder 504 includes 2 n-1 One latch, the 2 n-1 The output of each comparator is connected to the data terminal of a latch. The structure of the decoder 504 can be the same as that of the decoder 204, and will not be described in detail here.

[0056] In one embodiment, when the first control switch is closed and the second control switch is open (i.e., CT = 1), the 2 n-1 The output voltage of each comparator is stored by a corresponding latch. When the second control switch is closed and the first control switch is open (i.e., CT = 0), the voltage is stored by the 2... n-1 The outputs of the comparators constitute an even number of bits, and the 2... n-1 The outputs of the latches form an odd-number combination of 2. n Bit output.

[0057] In one embodiment, the integrator samples in the first phase and establishes in the second phase. The comparison time required for the comparator array to complete one comparison is t1. At least 2*t1 before the end of the second phase, the first control switch is closed and the second control switch is opened. After the comparator array completes one comparison, the second control switch is closed and the first control switch is opened.

[0058] It should be noted that Figure 2 and Figure 5 The single-ended signal corresponding to the sub-analog-to-digital converter structure shown. Figure 6 This is a schematic diagram of a sub-analog-to-digital converter structure in another embodiment of this application, corresponding to a differential signal. The sub-analog-to-digital converter structure includes: a comparator array 601, a first resistor network 602, and a second resistor network 605.

[0059] The comparator array 601 includes 2 n-1 Each comparator 603 has a first input terminal (e.g., a positive input terminal) connected to a first input voltage V. INP Each comparator 603 has its second input terminal (e.g., negative or positive input terminal) connected to a second input voltage V. INN The output of each comparator 603 is connected to the decoder 604.

[0060] The first resistor network 602 includes 2 resistors connected in series. n-2 -1 2R resistor, one R resistor, and two 0.5R resistors located at both ends, the 2 n-2 One end of the i-th 2R resistor in the -1 2R resistor is connected to the positive reference voltage V of each of the 2i comparators. RP and the negative reference voltage V of the 2i-1 comparators RN The first control switch is connected in parallel across the R resistor. One end of the second 0.5R resistor is connected to the first reference voltage V through an R resistor, the first control switch, and the second control switch. REFN .

[0061] The second resistor network 605 includes 2 resistors connected in series. n-2 -1 2R resistor, one R resistor, and two 0.5R resistors located at both ends, the 2 n-2 One end of the i-th 2R resistor in the -1 2R resistor is connected to the negative reference voltage V of each of the 2i comparators. RN and the positive reference voltage V of the 2i-1 comparators RP The first control switch is connected in parallel across the R resistor. One end of the first 0.5R resistor is connected to one end of the first 0.5R resistor in the first resistor network. One end of the second 0.5R resistor is connected to the second reference voltage V through an R resistor, the first control switch, and the second control switch. REFP .

[0062] The first control switch refers to the switch that closes when the control signal CT is high (e.g., "1"), and the second control switch refers to the switch that closes when the control signal CT is low (e.g., "0"). Furthermore, in other embodiments of this application, one R resistor connected to the first 2R resistor in the first resistor network 602 can also be connected in series with a second control switch and then in parallel with a first control switch. The second 0.5R resistor in the first resistor network 602 can also be connected to a second reference voltage V through another R resistor. REFP Furthermore, a second control switch is connected in parallel with resistor R. In other embodiments of this application, one resistor R in the second resistor network 605 connected to the first 2R resistor can also be connected in series with a second control switch and then in parallel with a first control switch. The second resistor network 605, connected to the second 0.5R resistor, can also be connected to a second reference voltage V through another resistor R. REFP Furthermore, a second control switch is connected in parallel with resistor R.

[0063] In one embodiment, the decoder 604 includes 2 n-1Each comparator has a latch, and the output of each comparator is connected to the data terminal of a latch. The structure of the decoder 604 can be the same as that of the decoder 204, and will not be described in detail here.

[0064] In one embodiment, when the first control switch is closed and the second control switch is open (i.e., CT = 1), the 2 n-1 The output voltage of each comparator is stored by a corresponding latch. When the second control switch is closed and the first control switch is open (i.e., CT = 0), the voltage is stored by the 2... n-1 The outputs of the comparators constitute the odd-numbered bits, and the 2... n-1 The outputs of the latches form an even-number combination of 2 bits. n Bit output.

[0065] In one embodiment, the integrator samples in the first phase and establishes in the second phase. The comparison time required for the comparator array to complete one comparison is t1. At least 2*t1 before the end of the second phase, the first control switch is closed and the second control switch is opened. After the comparator array completes one comparison, the second control switch is closed and the first control switch is opened.

[0066] In summary, this application proposes a two-step time-division multiplexing comparator array structure, which can complete two comparisons before the falling edge of the ph2 stage of the integrator setup, and combine the results of the two comparisons to obtain the final comparison result. Compared with the traditional 2 n This application requires only 2 comparators. n-1 The number of comparators is reduced by half, which significantly reduces the power consumption and area of ​​the sub-ADC, allowing for further reduction in the overall power consumption and area of ​​the sigma-delta ADC.

[0067] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0068] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.

[0069] This specification includes combinations of various embodiments described herein. Individual references to embodiments (e.g., “one embodiment”, “some embodiments”, or “preferred embodiments”) do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word “or” is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.

[0070] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. An analog-to-digital converter, characterized in that, include: Integrator; The sub-analog-to-digital converter structure coupled to the integrator includes: Comparator array, the comparator array comprising 2 n-1 There are 3 comparators, wherein the first input terminal of each comparator is connected to an input voltage, and the output terminal of each comparator is connected to a decoder, the decoder comprising 2... n-1 One latch, the 2 n-1 The output of each comparator is connected to the data terminal of a latch. as well as A resistor network, the resistor network comprising 2 resistors connected in series n-1 -1 2R resistor, the 2 n-1 -1 2R resistors, each of which is connected sequentially to the 2 n-1 Between the second input terminals of adjacent comparators in the comparator array, one end of the first 2R resistor is connected to the first reference voltage via a first control switch, an R resistor, and a second control switch. One end of the last 2R resistor is connected to the second reference voltage via a 2R resistor, a first control switch, an R resistor, and a second control switch. When the first control switch is closed and the second control switch is open, the 2... n-1 Each comparator in the comparator performs an initial comparison, and the output voltage is stored as an odd-numbered bit result by the corresponding latch. When the second control switch is closed and the first control switch is open, the 2 n-1 Each comparator in the comparator performs a second comparison, and the output voltage is used as the even-numbered result to compare with the 2... n-1 The combination of odd-numbered bits stored in each latch is 2. n Bit output.

2. The analog-to-digital converter according to claim 1, characterized in that, The integrator samples in the first phase and establishes in the second phase. The comparator array requires a comparison time of t1 to complete one comparison, which is at least 2 seconds before the end of the second phase. At time t1, the first control switch is closed and the second control switch is open. After the comparator array completes one comparison, the second control switch is closed and the first control switch is open.

3. An analog-to-digital converter, characterized in that, include: Integrator; The sub-analog-to-digital converter structure coupled to the integrator includes: Comparator array, the comparator array comprising 2 n-1 There are 3 comparators, wherein the first input terminal of each comparator is connected to an input voltage, and the output terminal of each comparator is connected to a decoder, the decoder comprising 2... n-1 One latch, the 2 n-1 The output of each comparator is connected to the data terminal of a latch. as well as A resistor network, the resistor network comprising 2 resistors connected in series n-1 -1 2R resistor and two 0.5R resistors located at both ends, the 2 n-1 -1 2R resistors, each of which is connected sequentially to the 2 n-1 Between the second input terminals of adjacent comparators in the comparators, one end of the first 0.5R resistor is connected to the first reference voltage via a first control switch, an R resistor, and a second control switch. One end of the second 0.5R resistor is connected to the second reference voltage via an R resistor, a first control switch, and a second control switch. When the first control switch is closed and the second control switch is open, the 2... n-1 Each comparator in the comparator performs an initial comparison, and the output voltage is stored as an odd-numbered bit result by the corresponding latch. When the second control switch is closed and the first control switch is open, the 2 n-1 Each comparator in the comparator performs a second comparison, and the output voltage is used as the even-numbered result to compare with the 2... n-1 The combination of odd-numbered bits stored in each latch is 2. n Bit output.

4. The analog-to-digital converter according to claim 3, characterized in that, The integrator samples in the first phase and establishes in the second phase. The comparator array requires a comparison time of t1 to complete one comparison, which is at least 2 seconds before the end of the second phase. At time t1, the first control switch is closed and the second control switch is open. After the comparator array completes one comparison, the second control switch is closed and the first control switch is open.

5. An analog-to-digital converter, characterized in that, include: Integrator; The sub-analog-to-digital converter structure coupled to the integrator includes: Comparator array, the comparator array comprising 2 n-1 Each comparator has a first input terminal connected to a first input voltage, a second input terminal connected to a second input voltage, and an output terminal connected to a decoder, wherein the decoder comprises 2... n-1 Each comparator has a latch, and the output of each comparator is connected to the data terminal of a latch. A first resistor network, the first resistor network comprising 2 resistors connected in series n-2 -1 2R resistor, one R resistor, and two 0.5R resistors located at both ends, the 2 n-2 One end of the i-th 2R resistor in the -1 2R resistor is connected to 2 i The positive reference voltage of the comparator and 2 i -1 is the negative reference voltage of the comparator. The first control switch is connected in parallel across the R resistor. One end of the second 0.5R resistor is connected to the first reference voltage through an R resistor, the first control switch, and the second control switch. as well as The second resistor network, the second resistor network comprising 2 resistors connected in series n-2 -1 2R resistor, one R resistor, and two 0.5R resistors located at both ends, the 2 n-2 One end of the i-th 2R resistor in the -1 2R resistor is connected to 2 i The negative reference voltage of the comparator and 2 i -1 is the positive reference voltage of the comparator. A first control switch is connected in parallel across the R resistor. One end of the first 0.5R resistor is connected to one end of the first 0.5R resistor in the first resistor network. One end of the second 0.5R resistor is connected to the second reference voltage via an R resistor, the first control switch, and the second control switch. When the first control switch is closed and the second control switch is open, the 2... n-1 Each comparator in the comparator performs an initial comparison, and the output voltage is stored as an odd-numbered bit result by the corresponding latch. When the second control switch is closed and the first control switch is open, the 2 n-1 Each comparator in the comparator performs a second comparison, and the output voltage is used as the even-numbered result to compare with the 2... n-1 The combination of odd-numbered bits stored in each latch is 2. n Bit output.

6. The analog-to-digital converter according to claim 5, characterized in that, The integrator samples in the first phase and establishes in the second phase. The comparator array requires a comparison time of t1 to complete one comparison, which is at least 2 seconds before the end of the second phase. At time t1, the first control switch is closed and the second control switch is open. After the comparator array completes one comparison, the second control switch is closed and the first control switch is open.

Images