A method, system, device, and storage medium for verifying an APB UART architecture

Abstract

The present invention provides a method, system, device and storage medium for verifying an APB UART architecture. The method includes: setting an APB bus model as an APB client and setting a UART transceiver model as a UART client; defining a data comparison function in a top-level basic test sequence; sending and receiving data packets in the APB client and the UART client through a virtual sequence; and performing real-time comparison on the data sent and received by the APB client and the UART client through the data comparison function. The present invention is built based on UVM and completes the verification function with fewer components. Through the response mechanism, it is very convenient to obtain the received data in real time in the test sequence and compare it with the sent data. In this way, the sending of data, the receiving of data, and the data comparison are all realized in the same sequence, improving the readability of test cases, reducing the complexity of environment setup, and improving efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and more specifically, particularly to a method, system, device, and storage medium for verifying an APB UART architecture. Background Art

[0002] Since the UART (Universal Asynchronous Receiver / Transmitter) protocol is widely used, almost most general-purpose SOCs (System on Chip) have a uart module, and its verification schemes are diverse. Generally speaking, there are the following several types:

[0003] 1. Verilog testbench, the environment setup is simple and fast. Usually, designers use it for basic verification before releasing the code. However, for a large number of test cases, it is not convenient to maintain and reuse.

[0004] 2. System verification based on c code, usually combined with other relevant modules for subsystem-level or system-level verification. However, this verification method requires a cpu model and is often used after the completion of the later system integration.

[0005] 3. In the module verification stage, professional verification personnel generally build a uvm environment to perform detailed functional and timing verification on the uart module.

[0006] The environment env built by UVM (Universal Verification Methodology) generally includes a bus model and a uart model. As a sub-environment (env) or as an agent component, it internally includes a driver, a monitor, and a sequencer. The Scoreboard, as a scoreboard, receives and compares the data transmitted and received monitored by the monitor in the apb and uart models to obtain the result. However, the result obtained by this method is not very easy to read. Summary of the Invention

[0007] In view of this, an object of an embodiment of the present invention is to provide a method, a system, a computer device, and a computer-readable storage medium for verifying an APB UART architecture. The present invention is built based on UVM, and the verification function is completed with fewer components. The monitor detectors in the APB (Advanced Peripheral Bus) and UART models are virtualized, and the scoreboard is deprecated. Through the response mechanism, the received data can be obtained in real time in the test sequence very conveniently and compared with the transmitted data. In this way, the transmitted data, the received data, and the data comparison are all realized in the same sequence, improving the readability of the test cases, reducing the complexity of the environment setup at the same time, and improving the efficiency.

[0008] Based on the above object, an aspect of an embodiment of the present invention provides a method for verifying an APB UART architecture, including the following steps: setting the APB bus model as an APB client and setting the UART transceiver model as a UART client; defining a data comparison function in the top-level basic test sequence; sending and receiving data packets in the APB client and the UART client through a virtual sequence; and comparing the data sent and received by the APB client and the UART client in real time through the data comparison function.

[0009] In some embodiments, the sending and receiving the data packets in the APB client and the UART client through a virtual sequence includes: sending the data in the APB client to the APB sequence through a virtual sequence and receiving the data sent by the APB sequence; and sending the data in the UART client to the UART sequence through a virtual sequence and receiving the data sent by the UART sequence.

[0010] In some embodiments, the comparing the data sent and received by the APB client and the UART client in real time through the data comparison function includes: inputting the data of the APB sequence and the UART sequence into the comparison function for comparison.

[0011] In some embodiments, the method further includes: performing data interaction with the device under test through the drivers inside the APB client and the UART client respectively, and performing data interaction with the APB sequence and the UART sequence through the transmitters inside the APB client and the UART client respectively.

[0012] On the other hand, an embodiment of the present invention provides a system for verifying an APB UART architecture, including: a setting module configured to set an APB bus model as an APB client and set a UART transceiver model as a UART client; a defining module configured to define a data comparison function in a top-level basic test sequence; an execution module configured to send and receive data packets in the APB client and the UART client through a virtual sequence; and a comparison module configured to perform real-time comparison on the data sent and received by the APB client and the UART client through the data comparison function.

[0013] In some embodiments, the execution module is configured to: send the data in the APB client to an APB sequence through a virtual sequence and receive the data sent by the APB sequence; and send the data in the UART client to a UART sequence through a virtual sequence and receive the data sent by the UART sequence.

[0014] In some embodiments, the comparison module is configured to: input the data of the APB sequence and the UART sequence into the comparison function for comparison.

[0015] In some embodiments, the system further includes an interaction module configured to: perform data interaction with a device under test through drivers inside the APB client and the UART client respectively, and perform data interaction with the APB sequence and the UART sequence through transmitters inside the APB client and the UART client respectively.

[0016] In yet another aspect of an embodiment of the present invention, a computer device is further provided, including: at least one processor; and a memory storing computer instructions executable on the processor, and when the instructions are executed by the processor, the steps of the above method are implemented.

[0017] In still another aspect of an embodiment of the present invention, a computer-readable storage medium is further provided, and the computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the above method.

[0018] The present invention has the following beneficial technical effects: Based on UVM, it completes the verification function with fewer components, virtualizes the monitor detectors in the APB and UART models, abandons the scoreboard, and can conveniently obtain the received data in real time in the test sequence through the response mechanism and compare it with the transmitted data. In this way, the transmitted data, received data, and data comparison are all realized in the same sequence, improving the readability of test cases, reducing the complexity of environment setup, and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings.

[0020] Figure 1 Schematic diagram of an embodiment of the method for verifying the APB UART architecture provided by the present invention;

[0021] Figure 2 Schematic diagram of the verification environment components for verifying the APB UART architecture provided by the present invention;

[0022] Figure 3 Schematic diagram of an embodiment of the system for verifying the APB UART architecture provided by the present invention;

[0023] Figure 4 Schematic diagram of the hardware structure of an embodiment of the computer device for verifying the APB UART architecture provided by the present invention;

[0024] Figure 5 Schematic diagram of an embodiment of the computer storage medium for verifying the APB UART architecture provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0026] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities or parameters with the same name but different, and it can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be elaborated one by one in the subsequent embodiments.

[0027] In the first aspect of the embodiments of the present invention, an embodiment of a method for verifying an APB UART architecture is proposed. Figure 1 The figure shows a schematic diagram of an embodiment of the method for verifying an APB UART architecture provided by the present invention. As Figure 1 shown, the embodiments of the present invention include the following steps:

[0028] S1. Set the APB bus model as an APB client and set the UART transceiver model as a UART client;

[0029] S2. Define a data comparison function in the top-level basic test sequence;

[0030] S3. Send and receive data packets in the APB client and the UART client through a virtual sequence; and

[0031] S4. Compare the data sent and received by the APB client and the UART client in real time through the data comparison function.

[0032] UART (Universal Asynchronous Receiver / Transmitter) is a commonly used serial communication protocol, which is widely used in SOC chips. The UART protocol has two communication signals, rx (receive signal) and tx (transmit signal), and does not require a clk clock signal. The two communicating parties transmit data by agreeing on the same baud rate. The UART character frame structure includes a start bit, 5 to 8 data bits, an optional parity bit, and 1 to 2 stop bits.

[0033] UVM (Universal Verification Methodology) is a commonly used methodology for IC verification at present. Based on its huge infrastructure, different test environments can be built for the same DUT (Device Under Test) verification object, and various test cases can be designed. Verification engineers can select and build an environment with appropriate complexity according to the characteristics of the verification object, and make the environment as simple and effective as possible while ensuring coverage, with high reusability, saving development time and improving efficiency.

[0034] Figure 2 This is a schematic diagram of the verification environment components for verifying the APB UART architecture provided by the present invention. In combination with Figure 2 This will illustrate the embodiments of the present invention. UVM is a set of verification platform development frameworks built based on the SystemVerilog language. Verification engineers can use its class structure components and phase mechanism to build a verification environment that is easy to reuse. As Figure 2As shown, this verification environment includes an APB bus model as the apb_agent, a UART transceiver model as the uart_agent, which internally includes a sequencer (transmitter) and a driver (driver) respectively to drive the sequence (test sequence); the monitor is not used in practice as a monitor, but the response mechanism is used to receive the returned data.

[0035] In some embodiments, the sending and receiving of data packets in the APB client and the UART client through the virtual sequence includes: sending the data in the APB client to the APB sequence through the virtual sequence and receiving the data sent by the APB sequence; and sending the data in the UART client to the UART sequence through the virtual sequence and receiving the data sent by the UART sequence.

[0036] In some embodiments, the real-time comparison of the data sent and received by the APB client and the UART client through the data comparison function includes: inputting the data of the APB sequence and the UART sequence into the comparison function for comparison.

[0037] In the top_test virtual sequence, the APB and UART data packets are sent and received through the virtual sequencer via the apb_seqr and uart_seqr respectively. The sent and received data is compared in real time through the data comparison function compare_data(data1, data2) defined by the top-level base test sequence.

[0038] In some embodiments, the method further includes: respectively performing data interaction with the device under test through the drivers inside the APB client and the UART client, and respectively performing data interaction with the APB sequence and the UART sequence through the transmitters inside the APB client and the UART client.

[0039] This method is built based on UVM and completes the verification function with fewer components. Through the response mechanism, it is very convenient to obtain the received data in real time in the test sequence and compare it with the sent data. In this way, sending data, receiving data, and data comparison are all implemented in the same sequence, improving the readability of the test cases. At the same time, it reduces the complexity of environment setup and improves efficiency.

[0040] It should be specifically noted that each step in each of the above-described embodiments of the method for verifying the APB UART architecture can be cross-checked, replaced, added, or deleted with each other. Therefore, these reasonable permutation and combination transformations for the method of verifying the APB UART architecture should also fall within the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.

[0041] Based on the above objectives, the second aspect of the embodiments of the present invention proposes a system for verifying the APB UART architecture. As Figure 3 shown, the system 200 includes the following modules: a setting module configured to set the apb bus model as an apb client and the uart transceiver model as a uart client; a definition module configured to define a data comparison function in the top-level basic test sequence; an execution module configured to send and receive data packets in the apb client and the uart client through a virtual sequence; and a comparison module configured to perform real-time comparison of the data sent and received by the apb client and the uart client through the data comparison function.

[0042] In some embodiments, the execution module is configured to: send the data in the apb client to the apb sequence through a virtual sequence and receive the data sent by the apb sequence; and send the data in the uart client to the uart sequence through a virtual sequence and receive the data sent by the uart sequence.

[0043] In some embodiments, the comparison module is configured to: input the data of the apb sequence and the uart sequence into the comparison function for comparison.

[0044] In some embodiments, the system further includes an interaction module configured to: perform data interaction with the device under test through the drivers inside the apb client and the uart client respectively, and perform data interaction with the apb sequence and the uart sequence through the transmitters inside the apb client and the uart client respectively.

[0045] For the above purposes, in the third aspect of the embodiments of the present invention, a computer device is proposed, including: at least one processor; and a memory storing computer instructions that can run on the processor, and the instructions are executed by the processor to implement the following steps: S1. Set the APB bus model as an APB client and set the UART transceiver model as a UART client; S2. Define a data comparison function in the top-level basic test sequence; S3. Send and receive data packets in the APB client and the UART client through a virtual sequence; and S4. Compare the data sent and received by the APB client and the UART client in real time through the data comparison function.

[0046] In some embodiments, the sending and receiving of data packets in the APB client and the UART client through the virtual sequence includes: sending the data in the APB client to the APB sequence through the virtual sequence and receiving the data sent by the APB sequence; and sending the data in the UART client to the UART sequence through the virtual sequence and receiving the data sent by the UART sequence.

[0047] In some embodiments, the real-time comparison of the data sent and received by the APB client and the UART client through the data comparison function includes: inputting the data of the APB sequence and the UART sequence into the comparison function for comparison.

[0048] In some embodiments, the steps further include: respectively performing data interaction with the device under test through the drivers inside the APB client and the UART client, and respectively performing data interaction with the APB sequence and the UART sequence through the transmitters inside the APB client and the UART client.

[0049] As Figure 4 shown, it is a schematic diagram of the hardware structure of an embodiment of the computer device for verifying the APB UART architecture provided by the present invention.

[0050] Taking the device as Figure 4 shown as an example, in this device, there is a processor 301 and a memory 302.

[0051] The processor 301 and the memory 302 can be connected through a bus or other means, Figure 4 and taking the connection through the bus as an example.

[0052] The memory 302, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the method for verifying the APB UART architecture in the embodiments of the present application. The processor 301 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 302, that is, implements the method for verifying the APB UART architecture.

[0053] The memory 302 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the method for verifying the APB UART architecture, etc. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 302 may optionally include a memory remotely disposed relative to the processor 301, and these remote memories can be connected to the local module through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0054] One or more computer instructions 303 corresponding to the method for verifying the APB UART architecture are stored in the memory 302, and when executed by the processor 301, execute the method for verifying the APB UART architecture in any of the above method embodiments.

[0055] Any embodiment of the computer device executing the above method for verifying the APB UART architecture can achieve the same or similar effects as any of the foregoing method embodiments corresponding thereto.

[0056] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, executes the method for verifying the APB UART architecture.

[0057] As Figure 5 shown, it is a schematic diagram of an embodiment of the above computer storage medium for verifying the APB UART architecture provided by the present invention. Taking the computer storage medium as shown in Figure 5 shown as an example, the computer-readable storage medium 401 stores a computer program 402 that, when executed by a processor, executes the above method.

[0058] Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the above-described method embodiments can be implemented by instructing relevant hardware through a computer program. The program for verifying the APB UART architecture can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above-described method embodiments. Among them, the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc. The embodiments of the above computer program can achieve the same or similar effects as the corresponding foregoing method embodiments.

[0059] The above are exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any particular order. In addition, although the elements disclosed by the embodiments of the present invention can be described or claimed in individual form, they can also be understood as plural unless explicitly limited to the singular.

[0060] It should be understood that, as used herein, unless the context clearly supports exceptions, the singular form "a" is also intended to include the plural form. It should also be understood that the "and / or" used herein refers to any and all possible combinations of one or more of the associated listed items.

[0061] The serial numbers of the disclosed embodiments of the present invention above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0062] Those of ordinary skill in the art can understand that all or part of the steps of the above-described embodiments can be completed by hardware or can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk, or an optical disk, etc.

[0063] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the embodiments disclosed by the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features between the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included within the protection scope of the embodiments of the present invention.

Claims

1. A method for verifying an APB UART architecture, characterized in that, It includes the following steps: Set the APB bus model as an APB client and set the UART transceiver model as a UART client; Define a data comparison function in the top-level basic test sequence; Send and receive data packets in the APB client and the UART client through a virtual sequence; And Real-time compare the data sent and received by the APB client and the data sent and received by the UART client respectively through the data comparison function.

2. The method according to claim 1, wherein The sending and receiving of data packets in the APB client and the UART client through the virtual sequence includes: Send the data in the APB client to the APB sequence through the virtual sequence and receive the data sent by the APB sequence; and Send the data in the UART client to the UART sequence through the virtual sequence and receive the data sent by the UART sequence.

3. The method according to claim 2, wherein The real-time comparison of the data sent and received by the APB client and the UART client through the data comparison function includes: Input the data of the APB sequence and the UART sequence into the comparison function for comparison.

4. The method according to claim 1, characterized in that, The method further includes: Perform data interaction with the device under test through the drivers inside the APB client and the UART client respectively, and perform data interaction with the APB sequence and the UART sequence through the transmitters inside the APB client and the UART client respectively.

5. A system for verifying an APB UART architecture, characterized in that, It includes: A setting module configured to set the APB bus model as an APB client and set the UART transceiver model as a UART client; A definition module configured to define a data comparison function in the top-level basic test sequence; An execution module configured to send and receive data packets in the APB client and the UART client through a virtual sequence; And A comparison module configured to real-time compare the data sent and received by the APB client and the data sent and received by the UART client respectively through the data comparison function.

6. The system according to claim 5, characterized in that, The execution module is configured to: Send the data in the APB client to the APB sequence through the virtual sequence and receive the data sent by the APB sequence; And Send the data in the UART client to the UART sequence through the virtual sequence and receive the data sent by the UART sequence.

7. The system according to claim 6, wherein The comparison module is configured to: Input the data of the APB sequence and the UART sequence into the comparison function for comparison.

8. The system according to claim 5, wherein The system further includes an interaction module configured to: Perform data interaction with the device under test through the drivers inside the APB client and the UART client respectively, and perform data interaction with the APB sequence and the UART sequence through the transmitters inside the APB client and the UART client respectively.

9. A computer device, characterized in that, It includes: At least one processor; And A memory, where the memory stores computer instructions that can run on the processor, and when the instructions are executed by the processor, the steps of the method according to any one of claims 1-4 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-4.

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