An FFT / DFT processing method and device applied to a 5G multi-stream data link

Abstract

The application provides an FFT / DFT processing method applied to a 5G multi-flow data link, including: obtaining FFT / DFT data in a communication link; performing preprocessing or WOLA_RX operation on the FFT / DFT data according to configuration information and then writing the FFT / DFT data into a ping-pong memory; performing a butterfly operation on the FFT / DFT data after the preprocessing or WOLA_RX operation between the ping-pong memories; performing WOLA_TX operation or post-processing on the FFT / DFT data after the butterfly operation and then outputting the FFT / DFT data to an output data memory; and outputting the FFT / DFT data after the WOLA_TX operation or the post-processing through the output data memory. Through the method, the FFT / DFT operation with extremely high throughput can be realized without increasing too much hardware, meanwhile, the data calling and calculation process before and after the FFT operation can be greatly simplified, and the operation efficiency is further improved.

Description

Technical Field

[0001] This invention belongs to the field of communication technology. Background Technology

[0002] The Fast Fourier Transform (FFT) plays an indispensable role in digital signal processing due to its efficient data conversion between the frequency and time domains. FFT processors have also become a key component of baseband SoC chips in Orthogonal Frequency Division Multiplexing (OFDM) communication systems (such as 4G LTE and the booming 5G NR), which deploy power-of-two FFTs and non-power-of-two Discrete Fourier Transforms (DFTs) to perform modulation. Therefore, high-throughput FFT processors supporting various FFT operations are essential to meeting the real-time requirements of evolving communication standards. Memory-based FFT is a commonly used FFT processor architecture. It can support multi-point FFTs with only a single set of butterfly PEs and a single-stage loop processing scheme, and can achieve conflict-free data allocation simply by changing the memory write / read address scheme. Therefore, memory-based FFT processor architectures are always the preferred solution in scenarios with limited area and multi-mode requirements, such as base station communication applications.

[0003] The existing memory-based FFT processing system architecture is roughly as follows: Figure 2 As shown, the data in the system simply completes the process of input → butterfly operation → output. The butterfly operation module can support various small-point butterfly operations, such as radix-2, radix-3, and radix-4, depending on the selected algorithm. The twiddle factor module can use a lookup table structure or a structure generated using a fast algorithm.

[0004] Most existing FFT / DFT processing systems simply perform FFT / DFT operations and do not support various data preprocessing and post-processing requirements in communication, such as CP addition / removal, frequency offset processing, and WOLA. To accomplish these functions in applications, the CPU / DSP needs to perform corresponding calculations, which is not only slow but also increases the complexity of the system scheduling algorithm. On the other hand, for systems supporting multiple point counts, some current solutions can only process one set of FFT data at a time, regardless of the FFT data length. Furthermore, due to the existence of hardware pipeline bubbles, there is a significant difference in throughput between small-point and large-point FFT operations, making it impossible to balance the throughput. Summary of the Invention

[0005] The present invention aims to at least partially solve one of the technical problems in the related art.

[0006] Therefore, the purpose of this invention is to propose an FFT / DFT processing method for use in 5G multi-stream data links, which can achieve extremely high throughput FFT / DFT operations without adding too much hardware, while simplifying the data calling and calculation process before and after FFT operations.

[0007] To achieve the above objectives, a first aspect of the present invention provides an FFT / DFT processing method applied in a 5G multi-stream data link, comprising:

[0008] Acquire FFT / DFT data in the communication link;

[0009] The FFT / DFT data is preprocessed or WOLA_RX calculated according to the configuration information and then written into the ping-pong memory.

[0010] The preprocessed or WOLA_RX FFT / DFT data is butterfly-operated between ping-pong memory, and the butterfly-operated FFT / DFT data is output to the output data memory after WOLA_TX operation or post-processing.

[0011] The FFT / DFT data after WOLA_TX operation or post-processing is output through the output data memory.

[0012] In addition, an FFT / DFT processing method applied in a 5G multi-stream data link according to the above embodiments of the present invention may also have the following additional technical features:

[0013] Furthermore, in one embodiment of the present invention, the step of preprocessing the FFT / DFT data or performing a WOLA_RX operation on the data according to the configuration information and then writing it into the ping-pong memory includes:

[0014] The data type of the FFT / DFT data is obtained, and the FFT / DFT data is stored in the corresponding memory according to the data type; wherein, the memory includes an input data memory, a WOLA_RX memory, and a pre-operation data memory;

[0015] Perform WOLA_RX operations or pre-addition, pre-subtraction, and pre-multiplication operations on the FFT / DFT data according to the configuration information.

[0016] Furthermore, in one embodiment of the present invention, the step of performing butterfly operations on the preprocessed or WOLA_RX-operated FFT / DFT data between ping-pong memories further includes:

[0017] Depending on the number of points in the FFT / DFT, multiple rounds of butterfly operations are performed between ping-pong memory.

[0018] Further, in an embodiment of the present invention, the process of outputting the FFT / DFT data after completing the butterfly operation to the output data memory through the WOLA_TX operation or post-processing includes:

[0019] Performing the corresponding WOLA_TX operation and the operations of post-addition, post-subtraction, and post-multiplication on the FFT / DFT data after completing the butterfly operation.

[0020] Further, in an embodiment of the present invention, it further includes:

[0021] Dividing the storage spaces of the input data memory, the pre-operand memory, the output data memory, and the ping-pong memory into t logical blocks of the same size, where the parallel storage blocks are segmented at intervals of the set parallel offset, so as to implement the operation of t small-point FFT / DFT data of the same length.

[0022] Further, in an embodiment of the present invention, the implementation of the operation of t small-point FFT / DFT data of the same length includes:

[0023] Configuring parameters, defining k as the number of levels of the butterfly operation, t as the number of parallels, and N as the number of points of the current FFT / DFT data;

[0024] Inputting t N-point FFT / DFT data into the ping-pong storage; the algorithm is as follows:

[0025] For(i = 0, i < k, i = i + 1) / / Inter-level iteration of the butterfly operation;

[0026] For(j = 0, j < t, j = j + 1) / / The ping-pong storage sequentially retrieves data from different FFT blocks;

[0027] Intra-level butterfly operation of the FFT data;

[0028] Outputting the operation results of t N-point FFT / DFT data.

[0029] To achieve the above object, an embodiment of the second aspect of the present invention proposes an FFT / DFT processing device applied to a 5G multi-stream data link, including the following modules:

[0030] An acquisition module, configured to acquire FFT / DFT data in the communication link;

[0031] A pre-operation module, configured to perform pre-processing on the FFT / DFT data or perform the WOLA_RX operation according to the configuration information and then write it into the ping-pong memory;

[0032] The butterfly operation module is used to perform butterfly operations on the pre-processed or WOLA_RX FFT / DFT data between ping-pong memory, and output the completed butterfly FFT / DFT data to the output data memory after WOLA_TX operation or post-processing.

[0033] The output module is used to output the FFT / DFT data after WOLA_TX operation or post-processing through the output data memory.

[0034] To achieve the above objectives, a third aspect of the present invention provides a computer hardware device, characterized in that it includes a memory, a processing module, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements an FFT / DFT processing method applied in a 5G multi-stream data link as described above.

[0035] To achieve the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements an FFT / DFT processing method applied in a 5G multi-stream data link as described above.

[0036] The FFT / DFT processing method proposed in this invention for use in 5G multi-stream data links can achieve extremely high throughput FFT / DFT operations without adding too much hardware. It supports multi-point FFT / DFT operations and employs a parallel execution mode that allows multiple FFT / DFT operations with the same number of points to share storage space and execute in parallel. Furthermore, the system integrates WOLA and post-processing functions, greatly simplifying data retrieval and computation processes before and after FFT operations, further improving computational efficiency. Attached Figure Description

[0037] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0038] Figure 1 This is a flowchart illustrating an FFT / DFT processing method applied in a 5G multi-stream data link, as provided in an embodiment of the present invention.

[0039] Figure 2 This is a schematic diagram of a conventional FFT processing system provided in an embodiment of the present invention.

[0040] Figure 3 This is a block diagram of a high-throughput FFT / DFT processing system with parallel mechanism and WOLA processing provided in an embodiment of the present invention.

[0041] Figure 4 This is a schematic diagram of a parallel-mode storage planning method provided in an embodiment of the present invention.

[0042] Figure 5 This is a schematic diagram of the execution flow of a PARA mode provided in an embodiment of the present invention.

[0043] Figure 6 This is a schematic diagram of a WOLA RX processing flow provided in an embodiment of the present invention.

[0044] Figure 7 This is a schematic diagram illustrating the principle of WOLA_TX windowing provided in an embodiment of the present invention.

[0045] Figure 8 This is a hardware structure block diagram of WOLA_TX provided in an embodiment of the present invention.

[0046] Figure 9 This is a schematic diagram of the workflow of an FFT / DFT processing system applied in a 5G multi-stream data link, provided by an embodiment of the present invention.

[0047] Figure 10 This is a flowchart illustrating an FFT / DFT processing device applied in a 5G multi-stream data link, provided as an embodiment of the present invention. Detailed Implementation

[0048] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0049] The following describes an embodiment of the FFT / DFT processing method applied in a 5G multi-stream data link with reference to the accompanying drawings.

[0050] Figure 1 This is a flowchart illustrating an FFT / DFT processing method applied in a 5G multi-stream data link, as provided in an embodiment of the present invention.

[0051] like Figure 1 As shown, this FFT / DFT processing method applied in 5G multi-stream data links includes the following steps:

[0052] S101: Acquire FFT / DFT data in the communication link;

[0053] S102: Based on the configuration information, preprocess the FFT / DFT data or perform WOLA_RX operation and then write it into the ping-pong memory;

[0054] S103: Perform butterfly operation on the pre-processed or WOLA_RX FFT / DFT data between ping-pong memories, and output the completed butterfly FFT / DFT data to the output data memory after WOLA_TX operation or post-processing.

[0055] S104: Output the FFT / DFT data after WOLA_TX operation or post-processing through the output data memory.

[0056] like Figure 3 The diagram shows a high-throughput FFT / DFT processing system with parallel mechanism and WOLA processing proposed in this invention. The computation data and corresponding configuration parameters are transmitted via a DMA interface. The control channel controls the overall FFT / DFT operation flow based on the received configuration parameters. FFT / DFT computation data is stored in the input data memory, WOLA_RX memory, and pre-operation data memory according to different data types. Then, WOLA_RX operations or pre-addition, pre-subtraction, and pre-multiplication operations are performed according to the configuration information. After pre-operation, the data is stored in the ping-pong memory, and then read from the ping-pong memory according to the executed FFT / DFT operation mode and sent to the butterfly operation unit for computation. The twiddle factor module reads the corresponding twiddle factor according to the configuration information to participate in the computation. During the butterfly operation, the block floating-point processing module is responsible for the block floating-point operations of the data. After completing all butterfly operations, the data is written back to the ping-pong memory through the data selector selection logic. The butterfly operation will be executed several times depending on the number of points in the FFT / DFT, and the data will be read and written back and forth between two ping-pong memories.

[0057] Furthermore, in one embodiment of the present invention, the step of preprocessing the FFT / DFT data or performing a WOLA_RX operation on the data according to the configuration information and then writing it into the ping-pong memory includes:

[0058] The data type of the FFT / DFT data is obtained, and the FFT / DFT data is stored in the corresponding memory according to the data type; wherein, the memory includes an input data memory, a WOLA_RX memory, and a pre-operation data memory;

[0059] Perform WOLA_RX operations or pre-addition, pre-subtraction, and pre-multiplication operations on the FFT / DFT data according to the configuration information.

[0060] Furthermore, in one embodiment of the present invention, the step of preprocessing the FFT / DFT data or performing a WOLA_RX operation on the data according to the configuration information and then writing it into the ping-pong memory includes:

[0061] The data type of the FFT / DFT data is obtained, and the FFT / DFT data is stored in the corresponding memory according to the data type; wherein, the memory includes an input data memory, a WOLA_RX memory, and a pre-operation data memory;

[0062] Perform WOLA_RX operations or pre-addition, pre-subtraction, and pre-multiplication operations on the FFT / DFT data according to the configuration information.

[0063] Furthermore, in one embodiment of the present invention, the step of performing butterfly operations on the preprocessed or WOLA_RX-operated FFT / DFT data between ping-pong memories further includes:

[0064] Depending on the number of points in the FFT / DFT, multiple rounds of butterfly operations are performed between ping-pong memory.

[0065] Specifically, after all butterfly operations are completed, the data is read from the ping-pong memory and, according to the configuration information, enters the post-operation module or the WOLA_TX operation module. This module performs the corresponding WOLA_TX operations, as well as post-addition, post-subtraction, and post-multiplication operations, and writes the results to the output data memory and the WOLA_TX memory respectively. Finally, the data is output via the DMA channel.

[0066] Furthermore, in one embodiment of the present invention, the step of outputting the FFT / DFT data after butterfly operation to the output data memory after WOLA_TX operation or post-processing includes:

[0067] Perform the corresponding WOLA_TX operation, as well as subsequent addition, subtraction, and multiplication operations on the FFT / DFT data after the butterfly operation is completed.

[0068] This invention also proposes a parallel memory allocation method that employs a hybrid parallel approach using multiple FFT data blocks to improve the utilization efficiency of the FFT processor. This mode is referred to as the parallel mode. Figure 4For the parallel storage planning method, the depth of each of the input data memory, preoperand memory, output data memory, postoperand memory, and ping-pong memory in this system is the same as the maximum number of FFT / DFT points supported by the FFT / DFT processing system. To fully utilize storage space and improve efficiency when processing small-point FFT / DFTs, the storage space of each of these memories is divided into t logical blocks of the same size. The parallel storage blocks are divided at intervals set by a parallel offset, thus supporting t small-point FFT operations of the same length. Taking a maximum 4096-point FFT operation as an example, the maximum storage depth is 4096. To support 128-point FFT operations simultaneously, the parallelism t can be set to a maximum of 32. In this case, the parallel offset is 128, and t is 32, meaning that 32 128-point FFT operations can be performed in parallel within the same storage space. Figure 5 To complete a full FFT operation, the execution flow of the PARA mode requires multiple levels of butterfly operations. After storing multiple FFT data blocks with the same number of points into the ping-pong memory, each level of butterfly operation reads data from each parallel memory block in sequence. Taking 32 FFTs with 128 points as an example, after the first level of butterfly operation completes the butterfly operation on 32 memory blocks, the system jumps to the second level of butterfly operation, and so on.

[0069] The weighted overlap-add (WOLA) structure is a highly efficient and flexible filter bank that has been widely used in subband coding, OFDM, and speech signal processing in recent years. Traditional methods treat WOLA independently of the FFT / IFFT operation, performing additional computation on the CPU or DSP. This invention's FFT / DFT processing system specifically supports configurable WOLA RX and WOLA TX operations. Before the WOLA RX operation is applied to the FFT / DFT calculation, its overall structure is as follows... Figure 6 As shown.

[0070] The WOLA_TX function can improve the Adjacent Channel Leakage Ratio (ACLR). The windowing function makes the transition between adjacent OFDM symbols smoother, thus improving the spectral leakage effect caused by OFDM symbol discontinuities. The principle of WOLA_TX windowing is as follows: Figure 7 As shown, the hardware structure block diagram of WOLA_TX is as follows: Figure 8 As shown.

[0071] Furthermore, in one embodiment of the present invention, it further includes:

[0072] Divide the storage spaces of the input data memory, the pre-operand memory, the output data memory, and the ping-pong memory into t logical blocks of the same size. The parallel storage blocks are segmented at intervals of a set parallel offset, so as to implement small-point FFT / DFT data operations of t same lengths.

[0073] Further, in an embodiment of the present invention, the implementation of small-point FFT / DFT data operations of t same lengths includes:

[0074] Configure parameters, define k to represent the number of stages of butterfly operations, t to represent the number of parallels, and N to represent the current number of FFT / DFT data points;

[0075] Input t N-point FFT / DFT data into the ping-pong storage; the algorithm is as follows:

[0076] For(i = 0, i < k, i = i + 1) / / Iteration between stages of butterfly operations;

[0077] For(j = 0, j < t, j = j + 1) / / The ping-pong storage sequentially retrieves data from different FFT blocks;

[0078] Intra-stage butterfly operations of FFT data;

[0079] Output the processed t N-point FFT / DFT data.

[0080] The above is the complete FFT / DFT processing method flow applied to the 5G multi-stream data link, Figure 9 which is the schematic diagram of the technical route of the present invention.

[0081] As Figure 9 shown, the acquired data is first stored in the input data memory, the preprocessed data memory, the WOLA_RX memory, etc., and then written into the ping-pong memory after preprocessing or WOLA_RX operations according to the configuration information, waiting for butterfly operations. The corresponding configuration information is stored in the butterfly stage register. At this time, the input memory can receive new configurations and data. Subsequently, the data repeatedly performs butterfly operations between the ping-pong memories. After the operations are completed, the data is output to the output memory through WOLA_TX operations or post-processing. At the same time, the corresponding configuration is written into the output configuration register, and the butterfly operation stage can perform FFT / DFT operations for the next configuration. In the data output stage, the data output memory outputs the data to the DMA interface. Throughout the process, whether processing one FFT data or enabling the parallel mode to process multiple FFT operations at once, the entire process is unified. The only difference is that the operations are completed block by block according to the address offset during the data reading process in each memory.

[0082] At maximum parallelism, the data input, butterfly operation, and data output stages can simultaneously perform three different configurations and lengths of FFT / DFT operations, realizing a fully pipelined structure for input, operation, and output, thereby improving throughput.

[0083] The FFT / DFT processing method proposed in this invention for use in 5G multi-stream data links can achieve extremely high throughput FFT / DFT operations without adding excessive hardware. It supports multi-point FFT / DFT operations and employs a parallel execution mode that allows multiple FFT / DFT operations with the same number of points to share storage space and execute in parallel. Furthermore, the system integrates WOLA and post-processing functions, greatly simplifying data retrieval and computation processes before and after FFT operations, further improving computational efficiency. Compared to existing technologies, this invention offers the following advantages:

[0084] 1) When it is necessary to support FFT (Fast Fourier Transform) / DFT (Discrete Fourier Transform) processing of many lengths simultaneously, in order to be compatible with large data lengths, the system storage space needs to be allocated according to the longest number of data points. Therefore, for FFT / DFT operations with small number of points, if each FFT / DFT operation is still performed as one, most of the storage space will be idle and cannot be fully utilized, which is a waste. This invention proposes a parallel mechanism. Based on this mechanism, multiple small-point FFT / DFTs can share the same memory to expand and execute FFT / DFT, thereby improving storage utilization and effectively improving and balancing the throughput of FFT / DFT.

[0085] 2) This invention integrates WOLA (weighted overlap-add) processing function, which supports parallel operation, into the FFT / DFT processing system. Compared with the current separate operation mode, it simplifies the data processing complexity in the communication link process and improves efficiency.

[0086] 3) The FFT / DFT processing system of this invention integrates multiple preprocessing and postprocessing modules that support parallel mode. Compared with the traditional process of first performing data preprocessing / postprocessing through CPU / DSP and then using DMA to transfer data to complete the FFT operation, this system can provide a flexible operating mode and achieve efficient data processing.

[0087] To achieve the above embodiments, the present invention also proposes an FFT / DFT processing device for use in 5G multi-stream data links.

[0088] Figure 10 This is a schematic diagram of the structure of an FFT / DFT processing device applied in a 5G multi-stream data link, provided as an embodiment of the present invention.

[0089] like Figure 10 As shown, the FFT / DFT processing device applied in a 5G multi-stream data link includes: an acquisition module 100, a pre-operation module 200, a butterfly operation module 300, and an output module 400, wherein...

[0090] The acquisition module is used to acquire FFT / DFT data in the communication link;

[0091] The pre-operation module is used to preprocess the FFT / DFT data or perform WOLA_RX operations on the data according to the configuration information and then write it into the ping-pong memory.

[0092] The butterfly operation module is used to perform butterfly operations on the pre-processed or WOLA_RX FFT / DFT data between ping-pong memory, and output the completed butterfly FFT / DFT data to the output data memory after WOLA_TX operation or post-processing.

[0093] The output module is used to output the FFT / DFT data after WOLA_TX operation or post-processing through the output data memory.

[0094] To achieve the above objectives, a third aspect of the present invention provides a computer device, characterized in that it includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the FFT / DFT processing method applied to a 5G multi-stream data link as described above.

[0095] To achieve the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the FFT / DFT processing method described above for use in 5G multi-stream data links.

[0096] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0097] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0098] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for FFT / DFT processing applied in 5G multi-stream data links, characterized in that, Includes the following steps: Acquire FFT / DFT data in the communication link; According to the configuration information, the FFT / DFT data is preprocessed or WOLA_RX is performed, and the FFT / DFT data after preprocessing or WOLA_RX is written into the ping-pong memory to wait for butterfly operation. The corresponding configuration information is stored in the butterfly stage register. The preprocessed or WOLA_RX FFT / DFT data is processed in a butterfly operation between ping-pong memories. The WOLA_TX operation or post-processing is performed on the FFT / DFT data after the butterfly operation. The FFT / DFT data after the WOLA_TX operation or post-processing is then output to the output data memory, and the corresponding configuration information is written to the output configuration register. The FFT / DFT data after WOLA_TX operation or post-processing is output through the output data memory; The preprocessing or WOLA_RX operation of the FFT / DFT data based on the configuration information includes: The data type of the FFT / DFT data is obtained, and the FFT / DFT data is stored in the corresponding memory according to the data type; wherein, the memory includes an input data memory, a WOLA_RX memory, and a pre-operation data memory, and the depth of each memory is the same as the maximum number of FFT / DFT points supported by the FFT / DFT processing system; Perform WOLA_RX operations or pre-addition, pre-subtraction, and pre-multiplication operations on the FFT / DFT data according to the configuration information; The method further includes: The storage space of the input data memory, the pre-operation data memory, the output data memory, and the ping-pong memory are all divided into t logical blocks of the same size, wherein the parallel storage blocks are divided at intervals with a set parallel offset, thereby realizing the operation of t small-point FFT / DFT data of the same length. The implementation of FFT / DFT data operations on t small points of the same length includes: Configure parameters, defining k as the number of butterfly operations, t as the number of parallel operations, and N as the current number of FFT / DFT data points; Input t N-point FFT / DFT data points into ping-pong storage; the algorithm is as follows: For (i=0, i <k,i=i+1); For(j=0,j <t,j=j+1); Intra-level butterfly operations on FFT data; Output the results after processing t N-point FFT / DFT data.

2. The method according to claim 1, characterized in that, The step of performing butterfly operations on the preprocessed or WOLA_RX-operated FFT / DFT data between ping-pong memories also includes: Depending on the number of points in the FFT / DFT, multiple rounds of butterfly operations are performed between ping-pong memory locations.

3. The method according to claim 1, characterized in that, The step of outputting the FFT / DFT data after butterfly operation to the output data memory after WOLA_TX operation or post-processing includes: Perform the corresponding WOLA_TX operation, as well as subsequent addition, subtraction, and multiplication operations on the FFT / DFT data after the butterfly operation is completed.

4. An FFT / DFT processing device for use in 5G multi-stream data links, characterized in that, Includes the following modules: The acquisition module is used to acquire FFT / DFT data in the communication link; The pre-operation module is used to preprocess or perform WOLA_RX operation on the FFT / DFT data according to the configuration information, and write the FFT / DFT data after preprocessing or WOLA_RX operation into the ping-pong memory to wait for butterfly operation, and store the corresponding configuration information into the butterfly stage register. The butterfly operation module is used to perform butterfly operations on the pre-processed or WOLA_RX FFT / DFT data between ping-pong memories, perform WOLA_TX operations or post-processing on the FFT / DFT data after butterfly operations, and output the FFT / DFT data after WOLA_TX operations or post-processing to the output data memory, and write the corresponding configuration information to the output configuration register. The output module is used to output the FFT / DFT data after WOLA_TX operation or post-processing through the output data memory; The preprocessing or WOLA_RX operation of the FFT / DFT data based on the configuration information includes: The data type of the FFT / DFT data is obtained, and the FFT / DFT data is stored in the corresponding memory according to the data type; wherein, the memory includes an input data memory, a WOLA_RX memory, and a pre-operation data memory, and the depth of each memory is the same as the maximum number of FFT / DFT points supported by the FFT / DFT processing system; Perform WOLA_RX operations or pre-addition, pre-subtraction, and pre-multiplication operations on the FFT / DFT data according to the configuration information; The storage space of the input data memory, the pre-operation data memory, the output data memory, and the ping-pong memory is divided into t logical blocks of the same size. The parallel storage blocks are divided at intervals with a set parallel offset, thereby realizing the operation of t small-point FFT / DFT data of the same length. The implementation of FFT / DFT data operations on t small points of the same length includes: Configure parameters, defining k as the number of butterfly operations, t as the number of parallel operations, and N as the current number of FFT / DFT data points; Input t N-point FFT / DFT data points into ping-pong storage; the algorithm is as follows: For (i=0, i <k,i=i+1); For(j=0,j <t,j=j+1); Intra-level butterfly operations on FFT data; Output the results after processing t N-point FFT / DFT data.

5. A computer hardware device, characterized in that, The device includes a memory, a processor, and a computer program stored in the memory and executable on the hardware device. When the processor executes the computer program, it implements the FFT / DFT processing method for 5G multi-stream data links as described in any one of claims 1-3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the FFT / DFT processing method for 5G multi-stream data links as described in any one of claims 1-3.

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