Circuit board and method for manufacturing the same

Abstract

A circuit substrate includes a first insulating layer having a first opening, a second insulating layer having a second opening, a high-frequency circuit layer, a first circuit layer, a second circuit layer, and a plurality of conductive pillars. The high-frequency circuit layer is sandwiched between the first insulating layer and the second insulating layer, and includes a high-frequency trace. The first opening and the second opening respectively expose two sides of the high-frequency trace. The high-frequency trace has a smooth surface that is not covered by the first insulating layer and the second insulating layer, and has a roughness of 0.1-2 microns. The first insulating layer and the second insulating layer are both located between the first circuit layer and the second circuit layer. The conductive pillars are arranged in the second insulating layer, and are connected to the high-frequency trace. The high-frequency trace is located in a hollow cavity formed by the first opening and the second opening, so as to reduce dielectric loss and improve signal transmission quality.

Description

TECHNICAL FIELD

[0001] The present application relates to a circuit board and a manufacturing method thereof, and particularly relates to a circuit board suitable for transmitting high frequency signals and a manufacturing method thereof. BACKGROUND

[0002] Nowadays, the frequency used by communication devices, such as smart phones and tablet computers, is getting higher and higher, so that the high frequency signals transmitted by the communication devices are easily affected by the medium loss and thus significantly attenuated. In order to reduce the influence of the medium loss, the circuit board in the communication device usually adopts a low relative permittivity material to make the insulating layer, wherein the low relative permittivity material is usually liquid crystal polymer (LCP) or teflon. However, the relative permittivity of both the liquid crystal polymer and the teflon is still difficult to meet the high frequency requirement of the current communication device. SUMMARY

[0003] At least one embodiment of the present application provides a circuit board, which includes high frequency traces suitable for transmitting high frequency signals.

[0004] At least one embodiment of the present application provides a manufacturing method of a circuit board, so as to manufacture the above-mentioned circuit board.

[0005] The circuit substrate includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a high-frequency circuit layer, a first circuit layer, a second circuit layer, and a plurality of conductive pillars. The first insulating layer has a first opening. The first conductive layer is formed on a hole wall of the first opening. The second insulating layer has a second opening. The second conductive layer is formed on a hole wall of the second opening. The high-frequency circuit layer is sandwiched between the first insulating layer and the second insulating layer, wherein the high-frequency circuit layer includes a high-frequency trace. The high-frequency trace has a first surface and a second surface opposite to the first surface. The first opening exposes the first surface, and the second opening exposes the second surface. The first surface has a first smooth surface not covered by the first insulating layer, and the second surface has a second smooth surface not covered by the second insulating layer, wherein the first smooth surface and the second smooth surface are between 0.1 microns and 2 microns. The first circuit layer includes a first return layer, and the second circuit layer includes a second return layer and a signal circuit layer. The signal circuit layer is located around the second return layer, wherein the first insulating layer and the second insulating layer are both located between the first circuit layer and the second circuit layer. The first opening and the second opening are located between the first return layer and the second return layer, and form a hollow cavity. The high-frequency trace is located in the hollow cavity, and the high-frequency trace, the first return layer, and the second return layer overlap each other and do not contact. The conductive pillars are arranged in the second insulating layer, wherein the conductive pillars connect the high-frequency trace and the signal circuit layer, and do not electrically connect the second return layer.

[0006] In at least one embodiment of the present application, the first return layer has a first glossy surface facing the first smooth surface, and the second return layer has a second glossy surface facing the second smooth surface, wherein the first glossy surface and the second glossy surface both have a roughness between 0.5 microns and 2 microns.

[0007] In at least one embodiment of the present application, the circuit substrate further includes a third insulating layer, a fourth insulating layer, a third circuit layer, and a fourth circuit layer. The third insulating layer covers the first circuit layer. The fourth insulating layer covers the second circuit layer, wherein the first circuit layer and the second circuit layer are both located between the third insulating layer and the fourth insulating layer. The third insulating layer and the fourth insulating layer are both located between the third circuit layer and the fourth circuit layer.

[0008] In at least one embodiment of the present application, the first return layer has a first glossy surface and a first matte surface. The first glossy surface faces the first smooth surface. The first matte surface is opposite to the first glossy surface and directly contacts the third insulating layer. The second return layer has a second glossy surface and a second matte surface. The second glossy surface faces the second smooth surface. The second matte surface is opposite to the second glossy surface and directly contacts the fourth insulating layer.

[0009] In at least one embodiment of the present invention, the circuit substrate further comprises a plurality of shielded conductive pillars. The shielded conductive pillars penetrate the first insulating layer and the second insulating layer, and connect the first circuit layer and the second circuit layer, wherein the shielded conductive pillars are positioned around the first opening and the second opening, and are not electrically connected to the high-frequency trace.

[0010] In at least one embodiment of the present invention, the first insulating layer comprises a plurality of first support pillars and a first peripheral layer. The first support pillars are disposed on the first surface and positioned within the first opening, wherein the first support pillars are positioned between the high-frequency trace and the first return layer. The first peripheral layer is disposed on the high-frequency circuit layer and surrounds the first support pillars, wherein the first peripheral layer and the first support pillars are separated from each other, and the first peripheral layer does not cover the high-frequency trace.

[0011] In at least one embodiment of the present invention, the material of the first support pillars is different from the material of the first peripheral layer.

[0012] In at least one embodiment of the present invention, the pitch between the first support pillars is equal to each other.

[0013] In at least one embodiment of the present invention, the second insulating layer comprises a plurality of second support pillars and a second peripheral layer. The second support pillars are disposed on the second surface and positioned within the second opening, wherein the second support pillars are positioned between the high-frequency trace and the second return layer, and the conductive pillars are respectively positioned in at least two second support pillars. The second peripheral layer is disposed on the high-frequency circuit layer and surrounds the second support pillars. The second peripheral layer and the second support pillars are separated from each other, and the second peripheral layer does not cover the high-frequency trace, wherein the high-frequency circuit layer is positioned between the first peripheral layer and the second peripheral layer.

[0014] In at least one embodiment of the present invention, the material of the second support pillars is different from the material of the second peripheral layer.

[0015] In at least one embodiment of the present invention, the first support pillars respectively overlap the second support pillars.

[0016] In at least one embodiment of the present invention, the pitch between the second support pillars is equal to each other.

[0017] In at least one embodiment of the present invention, the materials of the first conductive layer and the second conductive layer are different from the materials of the first circuit layer and the second circuit layer.

[0018] In at least one embodiment of the present invention, the high-frequency circuit layer further comprises a peripheral metal layer. The peripheral metal layer surrounds the high-frequency trace, wherein the high-frequency trace is not electrically connected to the peripheral metal layer.

[0019] In at least one embodiment of the present application, the perimeter metal layer includes two metal lines. The high frequency trace is positioned between the metal lines, and the high frequency trace is parallel to the metal lines.

[0020] In at least one embodiment of the present application, the method of manufacturing a circuit substrate includes the following steps. A high frequency trace layer is formed, which includes a high frequency trace having a first surface and a second surface opposite to the first surface. A first insulating layer having a first opening and a second insulating layer having a second opening are formed. A first conductive layer is formed on the hole wall of the first opening, and a second conductive layer is formed on the hole wall of the second opening. The first insulating layer is disposed on the high frequency trace layer, wherein the first opening exposes the first surface. The first surface has a first smooth surface which is not covered by the first insulating layer, and the roughness of the first smooth surface is between 0.1 microns and 2 microns. The second insulating layer is disposed on the high frequency trace layer, wherein the second opening exposes the second surface. The second surface has a second smooth surface which is not covered by the second insulating layer, and the roughness of the second smooth surface is between 0.1 microns and 2 microns. Then, a first circuit layer including a first return layer is formed on the first insulating layer. A second circuit layer including a second return layer is formed on the second insulating layer. The first opening and the second opening are positioned between the first return layer and the second return layer, and form a hollow cavity, wherein the high frequency trace is positioned in the hollow cavity, and the high frequency trace, the first return layer and the second return layer overlap each other and do not contact.

[0021] In at least one embodiment of the present application, the step of forming the high frequency trace layer includes providing a metal composite substrate including a metal layer, a support plate and a release layer between the metal layer and the support plate. Then, the metal layer is patterned.

[0022] In at least one embodiment of the present application, the step of forming at least one of the first insulating layer and the second insulating layer includes providing an insulating composite substrate including an insulating layer, a support plate and a release layer between the insulating layer and the support plate. Then, the insulating layer is patterned.

[0023] In at least one embodiment of the present application, the method of forming the first conductive layer and the second conductive layer includes electroless plating.

[0024] In at least one embodiment of the present application, the step of forming the first insulating layer includes providing an insulating layer stack substrate including a plurality of insulating layers and a plurality of release layers, wherein the insulating layers and the release layers are alternately stacked with each other, and two release layers are positioned between the insulating layers. Then, a slot is formed in the insulating layer stack substrate, wherein the slot is formed through the insulating layers and the release layers. After forming the slot, the release layers and part of the insulating layers are removed, and one of the insulating layers is retained to form a first perimeter layer, wherein the first perimeter layer has a first opening. Then, the first opening is filled with a first dielectric material. Then, the first dielectric material is patterned.

[0025] In at least one embodiment of the present application, a high frequency line layer is formed on the first dielectric material before patterning the dielectric material.

[0026] In at least one embodiment of the present application, the step of forming the second insulating layer includes forming a second perimeter layer on the high frequency line layer, wherein the second perimeter layer has a second opening. Thereafter, the second dielectric material is filled in the second opening. Thereafter, the second dielectric material is patterned.

[0027] In at least one embodiment of the present application, the step of forming the first conductive layer includes forming a metal layer on the slotted groove walls. After forming the metal layer, portions of the metal layer are removed.

[0028] In at least one embodiment of the present application, the step of removing portions of the metal layer, the release layers, and portions of the insulating layers, and retaining one of the insulating layers includes, after forming the metal layer, removing the outermost two release layers and retaining the insulating layers and at least one release layer, wherein the release layer is between the two insulating layers. After removing the outermost two release layers, the insulating layers and at least one release layer are disposed on an additional circuit board. After the insulating layers and at least one release layer are disposed on the additional circuit board, at least one of the insulating layers and the release layer is removed and one of the insulating layers is retained.

[0029] Based on the above, since the high frequency line is located in the hollow cavity, and air can be present in the hollow cavity, the relative dielectric constant of air (about 1) is lower than that of liquid crystal polymer (LCP) and ferrofluorine dragon, so that the dielectric loss can be reduced, the high frequency signal attenuation caused by the dielectric loss is reduced, and the signal transmission quality of the line substrate is improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] FIG. 1A is a top view of a line substrate of at least one embodiment of the present application.

[0031] FIG. 1B is a cross-sectional view of the line substrate of FIG. 1A along line IB-IB.

[0032] FIG. 1C is a cross-sectional view of the line substrate of FIG. 1A along line 1C-1C.

[0033] FIG. 2A to FIG. 2J is a manufacturing method of the line substrate of FIG. 1A .

[0034] FIG. 3A to FIG. 3I is a manufacturing method of the line substrate of another embodiment of the present application. DETAILED DESCRIPTION

[0035] In the following description, for purposes of clarity, the sizes of elements such as layers, films, panels, and regions that are depicted in the drawings are not necessarily shown to scale and the dimensions of various features can have been exaggerated relative to others to illustrate details and current embodiments. Therefore, the following description of embodiments and examples should not be considered to be limited by the particular shapes of the elements as depicted in the drawings and the description provided herein. For example, the regions illustrated in the various figures can not be drawn to scale and can be arbitrarily positioned for clarity. Similarly, but not identically, the various regions and / or elements can be arbitrarily spaced for clarity. Thus, the following description should be understood to encompass all possible shapes and relative positions of the elements depicted in the figures. For example, in actual practice, a flat surface illustrated in the figures can have rough and / or nonlinear features, and a sharp angle illustrated in the figures can be rounded. Therefore, the elements illustrated in the figures are intended to be illustrative, and not intended to limit the scope of the claims to the precise arrangements and relative sizes illustrated in the figures.

[0036] Second, the use of "about," "approximately," or "substantially" anywhere in the specification and claims is intended to allow for a range of equivalents based on the legal principles of equivalents for litigated patent claims. Such equivalents can include, but are not limited to, substituting equivalent technical features for technical features disclosed in the specification and claims, or substituting equivalent legal technical terms for legal technical terms disclosed in the specification and claims. For example, the use of "about" or "approximately" can indicate that a value + / - 30% of the stated value is intended. Similarly, the use of "substantially" can indicate that a value + / - 20% of the stated value is intended. Similarly, the use of "substantially" can indicate that a value + / - 10% of the stated value is intended. Similarly, the use of "substantially" can indicate that a value + / - 5% of the stated value is intended. The use of "about," "approximately," or "substantially" in the specification and claims is not intended to limit the scope of the claims to only a single alternative indicated by the use of "about," "approximately," or "substantially."

[0037] FIG. 1A is a top view schematic diagram of a wiring board according to at least one embodiment of the present invention, FIG. 1B is a cross-sectional view schematic diagram of the wiring board 100 taken along the line 1B-1B in FIG. 1A is a cross-sectional view schematic diagram of the wiring board 100 taken along the line 1C-1C in FIG. 1C is a cross-sectional view schematic diagram of the wiring board 100 taken along the line 1C-1C in FIG. 1A is a cross-sectional view schematic diagram of the wiring board 100 taken along the line 1C-1C in FIG. 1A to FIG. 1C The wiring board 100 can be a rigid wiring board or a flexible wiring board, and includes a first insulating layer 111, a second insulating layer 112, a high-frequency wiring layer 129, a first wiring layer 121, and a second wiring layer 122.

[0038] A high-frequency circuit layer 129 is sandwiched between a first insulating layer 111 and a second insulating layer 112, and can directly contact the first insulating layer 111 and the second insulating layer 112. Both the first insulating layer 111 and the second insulating layer 112 are located between the first circuit layer 121 and the second circuit layer 122, wherein the first circuit layer 121 is disposed on the lower surface of the first insulating layer 111, and the second circuit layer 122 is disposed on the upper surface of the second insulating layer 112. FIG. 1B and FIG. 1C As shown.

[0039] In this embodiment, the circuit board 100 may further include a third insulating layer 113, a fourth insulating layer 114, a third circuit layer 123, and a fourth circuit layer 124. The fourth insulating layer 114 covers the second circuit layer 122, while the third insulating layer 113 covers the first circuit layer 121. FIG. 1B and FIG. 1C For example, the fourth insulating layer 114 covers the upper surface of the second circuit layer 122, while the third insulating layer 113 covers the lower surface of the first circuit layer 121, such that both the first circuit layer 121 and the second circuit layer 122 are located between the third insulating layer 113 and the fourth insulating layer 114. The third insulating layer 113 and the fourth insulating layer 114 are both located between the third circuit layer 123 and the fourth circuit layer 124, wherein the third circuit layer 123 is disposed on the lower surface of the third insulating layer 113, and the fourth circuit layer 124 is disposed on the upper surface of the fourth insulating layer 114.

[0040] The circuit board 100 may also include two insulating protective layers 119, wherein these insulating protective layers 119 may be solder resist layers. A third circuit layer 123 and a fourth circuit layer 124 are both located between these insulating protective layers 119, and these insulating protective layers 119 partially cover the third circuit layer 123 and the fourth circuit layer 124, respectively. Each of the third circuit layer 123 and the fourth circuit layer 124 may include at least one pad (not shown), and the insulating protective layers 119 may not completely cover or cover the pads of the third circuit layer 123 and the fourth circuit layer 124, so that the pads of the third circuit layer 123 and the fourth circuit layer 124 are exposed and electrically connected to electronic components, such as discrete components or integrated circuits (ICs).

[0041] In this embodiment, the circuit board 100 includes a high-frequency circuit layer 129, a first circuit layer 121, a second circuit layer 122, a third circuit layer 123, and a fourth circuit layer 124, thus the circuit board 100 has five circuit layers. However, in other embodiments, the circuit board 100 may have three circuit layers: a high-frequency circuit layer 129, a first circuit layer 121, and a second circuit layer 122, excluding the third circuit layer 123 and the fourth circuit layer 124, i.e.FIG. 1B With FIG. 1C The third and fourth circuit layers 123 and 124 shown in FIG. 1 can be omitted.

[0042] In other embodiments, the circuit substrate 100 can have more than five circuit layers. For example, the circuit substrate 100 can further include a fifth and a sixth circuit layers (both not shown), where the first, second, third and fourth circuit layers 121, 122, 123 and 124 are all between the fifth and sixth circuit layers. In addition, it must be noted that, FIG. 1A The circuit substrate 100 shown in FIG. 2 is drawn by omitting the second circuit layer 122, the fourth insulating layer 114, the fourth circuit layer 124 and the insulating protective layer 119 covering the fourth circuit layer 124, to show the structure of the second insulating layer 112.

[0043] The first insulating layer 111 has a first opening 111h, and the second insulating layer 112 has a second opening 112h, where the first opening 111h is aligning with the second opening 112h. For example, both the first and second openings 111h and 112h can have substantially the same size and shape, so that the hole wall 111w of the first opening 111h and the hole wall 112w of the second opening 112h can be substantially flush with each other. Therefore, the first and second openings 111h and 112h can be in communication with each other, so that the first and second openings 111h and 112h can form a hollow cavity C11, where air can be contained in the hollow cavity C11.

[0044] The circuit substrate 100 further includes a first conductive layer 131 and a second conductive layer 132, where the first conductive layer 131 is formed on the hole wall 111w of the first opening 111h, and the second conductive layer 132 is formed on the hole wall 112w of the second opening 112h. Both the first and second conductive layers 131 and 132 are annular in shape, and can respectively fully cover the hole walls 111w and 112w, as shown in FIG. 1A the second conductive layer 132 shown in FIG. 2.

[0045] The second insulating layer 112 includes a second peripheral layer 112a and a plurality of second support columns 112c, where the second peripheral layer 112a has the second opening 112h, and the second support columns 112c are within the second opening 112h. Therefore, the second peripheral layer 112a surrounds the second support columns 112c. In addition, the second peripheral layer 112a and the second support columns 112c are separated from each other. In other words, each of the second support columns 112c does not directly contact or connect the second peripheral layer 112a, as shown in FIG. 1A

[0046] ​The first insulating layer 111 includes a first peripheral layer 111a having a first opening 111h and a plurality of first support columns 111c located within the first opening 111h. Thus, the first peripheral layer 111a surrounds the first support columns 111c. In addition, the first support columns 111c can respectively overlap the second support columns 112c, and thus FIG. 1A The locations of the second support columns 112c are equal to the locations of the first support columns 111c, wherein the first peripheral layer 111a and the first support columns 111c are separated from each other.

[0047] In addition, the distances between the first support columns 111c can be equal to each other, and the distances between the second support columns 112c can be equal to each other, such that the distance between adjacent ones of the first support columns 111c is substantially constant, and the distance between adjacent ones of the second support columns 112c is also substantially constant. In other words, both the first support columns 111c and the second support columns 112c can be evenly distributed on the high-frequency trace 129t.

[0048] The high-frequency trace layer 129 is located between the first peripheral layer 111a and the second peripheral layer 112a, such that the first peripheral layer 111a and the second peripheral layer 112a are disposed on the high-frequency trace layer 129, and the first peripheral layer 111a and the second peripheral layer 112a are respectively located on opposite sides of the high-frequency trace layer 129. The high-frequency trace layer 129 includes at least one high-frequency trace 129t having a first surface 129a and a second surface 129b opposite the first surface 129a.

[0049] The high-frequency trace 129t is located within the hollow cavity C11, wherein the first opening 111h exposes the first surface 129a, and the second opening 112h exposes the second surface 129b. Since the high-frequency trace 129t is located within the hollow cavity C11, neither the first peripheral layer 111a nor the second peripheral layer 112a covers the high-frequency trace 129t. The first support columns 111c are disposed on the first surface 129a, and the second support columns 112c are disposed on the second surface 129b, such that the high-frequency trace 129t is located between the first support columns 111c and the second support columns 112c, wherein the first surface 129a is partially covered by the first insulating layer 111, and the second surface 129b is partially covered by the second insulating layer 112.

[0050] The first surface 129a has a first smooth surface (not labeled) that is not covered by the first insulating layer 111, and the second surface 129b has a second smooth surface (not labeled) that is not covered by the second insulating layer 112, wherein the roughness of both the first and second smooth surfaces is between 0.1 microns and 2 microns. Thus, the surface of the high-frequency trace 129t that is not covered by the first and second insulating layers 111 and 112 can be smooth and have a roughness between 0.1 microns and 2 microns to effectively reduce the adverse effects of skin effect on the high-frequency trace 129t and reduce the attenuation of high-frequency signals within the high-frequency trace 129t.

[0051] Second, since the high-frequency trace 129t is located within the hollow cavity C11, and the hollow cavity C11 can contain air, most of the high-frequency trace 129t can be covered by air. Since air has a lower relative dielectric constant (the relative dielectric constant of air is about 1) than liquid crystal polymer (LCP) and ferrofluorine dragon, it can reduce dielectric loss, thereby effectively reducing the attenuation of high-frequency signals transmitted within the high-frequency trace 129t due to dielectric loss, to improve the signal transmission quality of the circuit substrate 100.

[0052] In addition, the first support columns 111c and the second support columns 112c can support the high-frequency trace 129t so that the high-frequency trace 129t can be suspended within the hollow cavity C11. When the circuit substrate 100 is a hard circuit board, the high-frequency trace 129t supported by the first support columns 111c and the second support columns 112c can remain flat to avoid impedance mismatch caused by bending of the high-frequency trace 129t, thereby reducing attenuation of high-frequency signals.

[0053] When the circuit substrate 100 is a soft circuit board and is bent, the high-frequency trace 129t can bend with the bending of the circuit substrate 100, and the first support columns 111c and the second support columns 112c can support the bent high-frequency trace 129t so that the high-frequency trace 129t, the first return signal layer 121b, and the second return signal layer 122b can remain in a state of being separated from each other and maintain the distance between the first return signal layer 121b and the second return signal layer 122b and the high-frequency trace 129t so that the distance does not change drastically to affect the signal transmission quality of the high-frequency trace 129t.

[0054] It is worth mentioning that, although the first support pillars 111c and the second support pillars 112c are disposed on the high-frequency trace 129t, the size of each first support pillar 111c and each second support pillar 112c is relatively small, and the first support pillars 111c and the second support pillars 112c are not continuously distributed on the high-frequency trace 129t. Therefore, the signal reflection or standing wave caused by the first support pillars 111c and the second support pillars 112c has little effect on the high-frequency signal. In other words, the first support pillars 111c and the second support pillars 112c disposed on the high-frequency trace 129t have little effect on the high-frequency signal and can be ignored.

[0055] Since the first conductive layer 131 is formed on the hole wall 111w of the first opening 111h, and the second conductive layer 132 is formed on the hole wall 112w of the second opening 112h, the high-frequency trace 129t located in the hollow cavity C11 can be surrounded by the first conductive layer 131 and the second conductive layer 132, so that the first conductive layer 131 and the second conductive layer 132 have the function of electromagnetic shielding, and can shield the interference of external electromagnetic waves on the high-frequency trace 129t. In addition, the first conductive layer 131 and the second conductive layer 132 can also reduce the dielectric loss caused by the first peripheral layer 111a and the second peripheral layer 112a, so as to reduce the attenuation of the high-frequency signal in the high-frequency trace 129t.

[0056] It is worth mentioning that, when the circuit substrate 100 is a soft circuit board, the thickness of each of the first conductive layer 131 and the second conductive layer 132 can be between 5 microns and 10 microns, so that the circuit substrate 100 is easy to be bent. When the circuit substrate 100 is a hard circuit board, the thickness of each of the first conductive layer 131 and the second conductive layer 132 can be more than 10 microns. In this way, not only the ability of the first conductive layer 131 and the second conductive layer 132 to shield external electromagnetic waves can be improved, but also the dielectric loss caused by the first peripheral layer 111a and the second peripheral layer 112a can be greatly reduced, effectively reducing the attenuation of the high-frequency signal.

[0057] The high-frequency circuit layer 129 can further include a peripheral metal layer 129p surrounding the high-frequency trace 129t, wherein the high-frequency trace 129t is not electrically connected to the peripheral metal layer 129p, so the high-frequency trace 129t does not directly contact the peripheral metal layer 129p. In addition, the peripheral metal layer 129p can be sandwiched between the first peripheral layer 111a and the second peripheral layer 112a, and surround the hollow cavity C11. In other words, the peripheral metal layer 129p can have an opening (not labeled) that communicates the first opening 111h and the second opening 112h, and the high-frequency trace 129t is located in the above-mentioned opening. FIG. 1A to FIG. 1C

[0058] ​The first circuit layer 121 includes a first return signal layer 121b, and the second circuit layer 122 includes a second return signal layer 122b, wherein the first opening 111h and the second opening 112h are located between the first return signal layer 121b and the second return signal layer 122b. Therefore, the hollow cavity C11 can be distributed between the first return signal layer 121b and the second return signal layer 122b. The high-frequency trace 129t, the first return signal layer 121b and the second return signal layer 122b are overlapped with each other, wherein the first support columns 111c are located between the high-frequency trace 129t and the first return signal layer 121b, and the second support columns 112c are located between the high-frequency trace 129t and the second return signal layer 122b, as shown in FIG. 1B As shown in FIG. 1C .

[0059] The high-frequency trace 129t, the first return signal layer 121b and the second return signal layer 122b are not in contact with each other, so that the high-frequency trace 129t is not electrically connected to the first return signal layer 121b and the second return signal layer 122b. In other words, the high-frequency trace 129t, the first return signal layer 121b and the second return signal layer 122b are separated from each other, so that the high-frequency trace 129t is electrically insulated from the first return signal layer 121b and the second return signal layer 122b, and the high-frequency signal transmitted by the high-frequency trace 129t cannot be directly transmitted to the first return signal layer 121b and the second return signal layer 122b through a conductor.

[0060] As shown in FIG. 1C , the first return signal layer 121b has a first glossy surface G21 and a first matte surface M21, wherein the first matte surface M21 is opposite to the first glossy surface G21. The first glossy surface G21 faces the first surface 129a and its first smooth surface, and the first matte surface M21 directly contacts the third insulating layer 113. The first matte surface M21 is a rough surface, so that a sufficient bonding force can be generated between the first matte surface M21 and the third insulating layer 113, so that the first return signal layer 121b can be firmly combined with the third insulating layer 113, thereby making it difficult for the first return signal layer 121b to be separated from the third insulating layer 113.

[0061] The second return signal layer 122b has a second glossy surface G22 and a second matte surface M22, wherein the second matte surface M22 is opposite to the second glossy surface G22. The second glossy surface G22 faces the second surface 129b and its second smooth surface, and the second matte surface M22 directly contacts the fourth insulating layer 114. Similarly to the first matte surface M21, the second matte surface M22 is also a rough surface, so that a sufficient bonding force can be generated between the second matte surface M22 and the fourth insulating layer 114, so that the second return signal layer 122b can also be firmly combined with the fourth insulating layer 114, thereby making it difficult for the second return signal layer 122b to be separated from the fourth insulating layer 114.

[0062] The first bright surface G21 and the second bright surface G22 have a roughness between 0.5 microns and 2 microns. During transmission of the high-frequency signal by the high-frequency trace 129t, the first bright surface G21 of the first return signal layer 121b and the second bright surface G22 of the second return signal layer 122b induce return signal signals transmitted along the return path. Since the first bright surface G21 and the second bright surface G22 have a roughness between 0.5 microns and 2 microns, the return signal signals in the first bright surface G21 and the second bright surface G22 can be effectively reduced, thereby improving the signal transmission quality of the circuit substrate 100.

[0063] Referring to FIG. 1A and FIG. 1C The second circuit layer 122 further includes a signal circuit layer 122a, wherein the signal circuit layer 122a is disposed around the second return signal layer 122b and is not electrically connected to the second return signal layer 122b. The circuit substrate 100 further includes a plurality of conductive pillars 142, wherein the conductive pillars 142 are disposed in the second insulating layer 112 and are connected to the high-frequency trace 129t and the signal circuit layer 122a, so that the high-frequency trace 129t can be electrically connected to the signal circuit layer 122a through the conductive pillars 142.

[0064] Each of the conductive pillars 142 is not electrically connected to the second return signal layer 122b, so the conductive pillars 142 do not contact the second return signal layer 122b, and the return signal signals in the second return signal layer 122b cannot pass through the conductive pillars 142. In addition, the conductive pillars 142 are respectively located in at least two second support pillars 112c. For example, FIG. 1A and FIG. 1C For example, the conductive pillars 142 can be respectively located in the two second support pillars 112c at the leftmost and rightmost sides, so that the conductive pillars 142 can be connected to opposite ends of the high-frequency trace 129t.

[0065] The circuit substrate 100 can further include a plurality of shielding conductive pillars 141. The shielding conductive pillars 141 pass through the first insulating layer 111 and the second insulating layer 112 and are disposed around the first opening 111h and the second opening 112h. The shielding conductive pillars 141 can be connected to the first circuit layer 121 and the second circuit layer 122, but are not electrically connected to the high-frequency trace 129t, wherein the shielding conductive pillars 141 can all be electrically insulated from the high-frequency trace 129t, so that the high-frequency signals in the high-frequency trace 129t cannot be directly transmitted to any of the shielding conductive pillars 141 through a conductor. In addition, the shielding conductive pillars 141 also have the function of electromagnetic shielding to shield external electromagnetic waves from interfering with the high-frequency trace 129t.

[0066] FIG. 2A to FIG. 2J are FIG. 1AFIG. 1 is a schematic diagram of a manufacturing method of a circuit substrate in the present disclosure. In the manufacturing method of the circuit substrate 100, at least one of the first insulating layer 111, the second insulating layer 112, and the high-frequency circuit layer 129 can be formed first. FIG. 2A to FIG. 2B The step of forming at least one of the first insulating layer 111 and the second insulating layer 112 is disclosed. FIG. 2C to FIG. 2F The step of forming the high-frequency circuit layer 129 is disclosed. The present embodiment first describes the step of forming at least one of the first insulating layer 111 and the second insulating layer 112, but in other embodiments, the high-frequency circuit layer 129 can be formed first. Therefore, the formation sequence of the first insulating layer 111, the second insulating layer 112, and the high-frequency circuit layer 129 is not limited by the present embodiment.

[0067] Referring to FIG. 1, the step of forming at least one of the first insulating layer 111 and the second insulating layer 112 is disclosed. FIG. 2A In the step of forming at least one of the first insulating layer 111 and the second insulating layer 112, an insulating composite substrate 210 can be provided, wherein the insulating composite substrate 210 includes the insulating layer 110i, the support plate 20, and the release layer 21 between the insulating layer 110i and the support plate 20. For example, FIG. 2A For example, the insulating composite substrate 210 can include two insulating layers 110i, one support plate 20, and two release layers 21, wherein each release layer 21 is sandwiched between the support plate 20 and one of the insulating layers 110i. Each of the insulating layers 110i contacts and temporarily adheres to the release layer 21, so each of the insulating layers 110i can be separated from the support plate 20 by the release layer 21.

[0068] Referring to FIG. 1, the step of forming at least one of the first insulating layer 111 and the second insulating layer 112 is disclosed. FIG. 2B After that, the insulating layers 110i are patterned to form the multilayer insulating layer 110, wherein the insulating layers 110i can be photosensitive and, for example, photoimageable dielectric (PID). Therefore, the method of patterning the insulating layers 110i can be exposure and development. In addition, in other embodiments, the method of patterning the insulating layers 110i can also be laser ablation, so it is not limited to exposure and development.

[0069] Each of the insulating layers 110 can be the first insulating layer 111 or the second insulating layer 112. Specifically, each of the insulating layers 110 can have an opening 110h, wherein each of the openings 110h can be the first opening 111h or the second opening 112h. Secondly, each of the insulating layers 110 can include a plurality of peripheral layers 110a and a plurality of support columns 110c, wherein the peripheral layers 110a can be the first peripheral layer 111a or the second peripheral layer 112a, and the support columns 110c can be the first support column 111c or the second support column 112c.

[0070] Therefore, each insulating layer 110i can form the first insulating layer 111 or the second insulating layer 112. Thus, one insulating composite substrate 210 can form two layers of the first insulating layer 111, two layers of the second insulating layer 112, or one layer of the first insulating layer 111 and one layer of the second insulating layer 112. In addition, in other embodiments, the insulating composite substrate 210 can include only one insulating layer 110i, one support plate 20, and one release layer 21. Therefore FIG. 2A The release layer 21 and the insulating layer 110i on the same side of the support plate 20 can be omitted.

[0071] Subsequently, a plurality of conductive layers 130 are formed on the hole walls of the openings 110h, respectively, wherein each conductive layer 130 can be the first conductive layer 131 or the second conductive layer 132, and the method of forming the conductive layers 130 can be electroless plating or include electroless plating and electroplating. After the conductive layers 130 are formed, the insulating layers 110 are patterned to form a plurality of holes 110v, wherein the method of patterning the insulating layers 110 can be exposure and development or laser ablation.

[0072] Referring to FIG. 2C In the process of forming the high-frequency circuit layer 129, a metal composite substrate 220 can be provided, wherein the metal composite substrate 220 includes metal layers 120i, a support plate 20, and release layers 21 between the metal layers 120i and the support plate 20. For example, FIG. 2C For example, the metal composite substrate 220 can include two metal layers 120i, one support plate 20, and two release layers 21, wherein each release layer 21 is interposed between the support plate 20 and one of the metal layers 120i.

[0073] The metal layers 120i are respectively in contact with and temporarily bonded to the release layers 21, so that each metal layer 120i can be separated from the support plate 20 by the release layer 21. In addition, each metal layer 120i has a matte surface M12 and a glossy surface G12 opposite to the matte surface M12, wherein the glossy surfaces G12 can be directly in contact with the release layers 21, respectively, to expose the matte surfaces M12.

[0074] Referring to FIG. 2D and FIG. 2E wherein FIG. 2D is FIG. 2E is drawn along the line 2D-2D. Subsequently, the metal layers 120i are patterned to form at least one high-frequency circuit layer 129, wherein the method of patterning the metal layers 120i can be photolithography and etching. In this embodiment, each metal layer 120i can form the high-frequency circuit layer 129 after being patterned, so that the metal layers 120i can form a plurality of high-frequency circuit layers 129. In addition, in other embodiments, FIG. 2DIn the present embodiment, each high-frequency circuit layer 129 can include a high-frequency trace 129t and a peripheral metal layer 129p, wherein the peripheral metal layer 129p has a plurality of through-holes 129v for forming the shield conductive pillars 141, and FIG. 2E These through-holes 129v are omitted from illustration.

[0075] Referring to FIG. 2F , another embodiment of a high-frequency circuit layer 229 is illustrated, wherein the high-frequency circuit layer 229 also includes a high-frequency trace 129t and a peripheral metal layer 229p. Unlike the high-frequency circuit layer 129 in FIG. 2E , the peripheral metal layer 229p includes two metal lines M29, wherein the high-frequency trace 129t is located between the metal lines M29, and the high-frequency trace 129t and the metal lines M29 are parallel to each other. The metal lines M29 can also have the function of electromagnetic shielding to help shield external electromagnetic waves. In addition, in the high-frequency circuit layer 229, the peripheral metal layer 229p can have a pair of grooves 229h, wherein the metal lines M29 are located between the grooves 229h, and each groove 229h can extend along the metal lines M29.

[0076] Referring to FIG. 2D and FIG. 2G , the high-frequency circuit layers 129 are then separated from the support plate 20, and the high-frequency circuit layers 129 separated from the support plate 20 are laminated to the insulating layers 110. Before laminating the high-frequency circuit layers 129 to the insulating layers 110, the insulating layers 110 can be roughened to have a rough surface to facilitate bonding of the high-frequency circuit layers 129 to the insulating layers 110. There are various methods for roughening the insulating layers 110, and in the present embodiment, the surface of the insulating layers 110 can be roughened by laser. Alternatively, the surface of the insulating layers 110 can also be roughened by chemical methods.

[0077] Referring to FIG. 2G and FIG. 2H , other insulating layers 110 are then laminated to the high-frequency circuit layers 129, and the insulating layers 110 in FIG. 2G are separated from the support plate 20 to dispose the first insulating layers 111 and the second insulating layers 112 on the high-frequency circuit layers 129. The other insulating layers 110 laminated to the high-frequency circuit layers 129 can be made of another insulating composite substrate 210. Alternatively, in FIG. 2G , the upper insulating layers 110 can serve as the first insulating layers 111, and the lower insulating layers 110 can serve as the second insulating layers 112, wherein the lower insulating layers 110 can not be laminated with the high-frequency circuit layers 129 first, i.e. FIG. 2GThe high-frequency circuit layer 129 in the middle and lower part can be removed, and the lower insulating layer 110 separated from the support plate 20 can be directly laminated to the upper insulating layer 110 and the high-frequency circuit layer 129 to form the first insulating layer 111 and the second insulating layer 112.

[0078] After the first insulating layer 111 and the second insulating layer 112 are disposed on the high-frequency circuit layer 129, the surface of the high-frequency circuit layer 129 not covered by the first insulating layer 111 and the second insulating layer 112 can be subjected to surface treatment to make the high-frequency circuit layer 129 have a first smooth surface not covered by the first insulating layer 111 and a second smooth surface not covered by the second insulating layer 112, wherein the surface treatment can be performed using a laser.

[0079] Please refer to FIG. 2I and FIG. 2J wherein FIG. 2J is basically drawn along the line 1C-1C in FIG. 1A . Then, the first circuit layer 121 is formed on the first insulating layer 111, the second circuit layer 122 is formed on the second insulating layer 112, and the shielding conductive column 141 is formed in the hole 110v and the through-hole 129v, wherein the method for forming the shielding conductive column 141 can include through-hole plating, and the first circuit layer 121 and the second circuit layer 122 can be formed by a semi-additive method and micro-etching of a metal foil.

[0080] The surfaces of the first circuit layer 121 and the second circuit layer 122 in contact with the first insulating layer 111 and the second insulating layer 112 can be roughened to facilitate bonding of the first circuit layer 121 and the first insulating layer 111 and bonding of the second circuit layer 122 and the second insulating layer 112. Then, the third insulating layer 113, the fourth insulating layer 114, the third circuit layer 123, the fourth circuit layer 124, and the insulating protective layer 119 are formed as shown in FIG. 1A to FIG. 1C . At this point, the circuit substrate 100 has basically been completed.

[0081] FIG. 3A to FIG. 3I is a cross-sectional schematic view of a manufacturing method of a circuit substrate according to another embodiment of the present application. Please refer to FIG. 3A , first, an insulating layer stack substrate 310 is provided, which includes a plurality of insulating layers 310i and a plurality of release layers 21, wherein the insulating layers 310i and the release layers 21 are alternately stacked with each other, and the insulating layers 310i are located between two release layers 21. Unlike the insulating layer 110i, the insulating layer 310i can be a prepreg or a resin, and can not have photosensitivity.

[0082] Please refer to FIG. 3BAfter that, grooves 330h are formed in the insulating layer stack substrate 310 to form a plurality of insulating layers 310i, wherein the grooves 330h are formed through the insulating layers 310i and the release layers 21, and the grooves 330h can be formed by punching or routing. After that, metal layers 330i are formed on the groove walls of the grooves 330h and on the outermost two release layers 21, wherein the metal layers 330i can be formed by electroless plating, and the metal layers 330i can be nickel layers, gold layers or silver layers.

[0083] Referring to FIG. 3B and FIG. 3C After the metal layers 330i are formed, the outermost two release layers 21 are removed, and the insulating layers 310 and at least one release layer 21 are retained, wherein the retained release layer 21 can be located between two insulating layers 310. In addition, after the outermost two release layers 21 are removed, part of the metal layers 330i are also removed to form metal layers 330 that only cover the groove walls of the grooves 330h.

[0084] After that, the insulating layers 310 and the release layers 21 are arranged on the additional circuit board 30. In FIG. 3C an embodiment, two additional circuit boards 30 can be provided, and the insulating layers 310 and the release layers 21 are sandwiched between the two additional circuit boards 30. At this time, the grooves 330h are sealed between the two additional circuit boards 30. The two additional circuit boards 30 can be connected to the insulating layers 310 by two release layers 31, as shown in FIG. 3C .

[0085] Referring to FIG. 3C and FIG. 3D After the insulating layers 310 and the release layers 21 are arranged on the additional circuit board 30, at least one insulating layer 310, release layer 21 and part of the metal layer 330 are removed, and one insulating layer 310 is retained to form a first peripheral layer 311a and a first conductive layer 331. The first peripheral layer 311a is arranged on the release layer 31 and the additional circuit board 30, and has a first opening 311h. After that, the first opening 311h is filled with a first dielectric material 311f, wherein the first dielectric material 311f can be photosensitive, and different from the material of the first peripheral layer 311a.

[0086] Afterwards, a high frequency line layer 329 is formed on the first dielectric material 311f, wherein the high frequency line layer 329 includes high frequency traces 329t and a perimeter metal layer 329p. The high frequency line layer 329 can be formed by first laminating a metal foil (e.g. copper foil) with a low surface roughness on the first dielectric material 311f and the first perimeter layer 311a, so that the high frequency traces 329t can have a smooth surface to reduce the adverse effects caused by skin effect. Afterwards, the metal foil is patterned, wherein the metal foil can be patterned by photolithography and etching. Alternatively, the high frequency line layer 329 can also be formed by using a half-additive process and micro-etching.

[0087] Referring to FIG. 3E , afterwards, a second perimeter layer 312a is formed on the high frequency line layer 329, wherein the second perimeter layer 312a has a second opening 312h. The second perimeter layer 312a can be formed by the same method and material as the first perimeter layer 311a, and the second perimeter layer 312a can be first disposed on the release layer 31 and the additional circuit board 30. Afterwards, the second perimeter layer 312a is laminated with the release layer 31 and the additional circuit board 30 on the high frequency line layer 329, as shown in FIG. 3E .

[0088] Before the second perimeter layer 312a is laminated on the high frequency line layer 329, the second opening 312h can be first filled with a second dielectric material 312f, wherein the first dielectric material 311f and the second dielectric material 312f can have the same composition. After the second dielectric material 312f is filled, the second perimeter layer 312a is laminated on the high frequency line layer 329. Afterwards, drilling can be performed on the additional circuit board 30 above to form a plurality of holes V3 extending from the additional circuit board 30 through the second perimeter layer 312a to the high frequency line layer 329, wherein the holes V3 can be formed by mechanical drilling or laser drilling.

[0089] Referring to FIG. 3F , afterwards, the release layer 31 and the additional circuit board 30 adjacent to the second perimeter layer 312a and the second dielectric material 312f are removed to expose the second dielectric material 312f and the second perimeter layer 312a. Afterwards, the second dielectric material 312f is patterned to form a plurality of second support columns 312c, wherein at least two of the second support columns 312c can have a via 312v respectively. The second dielectric material 312f can be photosensitive, and the second dielectric material 312f can be patterned by exposure and development, or laser ablation. After the second support columns 312c are formed, a second insulating layer 312 including the second perimeter layer 312a and the second support columns 312c is also formed.

[0090] Referring to FIG. 3GAfterwards, a second circuit layer 322 is formed on the second insulating layer 312, and a plurality of conductive pillars 342 are formed in the through holes 312v, wherein the second circuit layer 322 includes a signal circuit layer 322a and a second return layer 322b, and the second circuit layer 322 can be formed by a metal foil through photolithography and etching, and the conductive pillars 342 can be formed by through-hole plating. The materials of the first conductive layer 331 and the second conductive layer 332 can be different from the material of the second circuit layer 322, so that in the process of forming the second circuit layer 322, a suitable etching solution can be selected for etching to avoid damage to the first conductive layer 331 and the second conductive layer 332 by the etching solution. Afterwards, a fourth insulating layer 314 and a fourth circuit layer 324 can be sequentially formed.

[0091] Referring to FIG. 3H Afterwards, the underlying additional circuit board 30 and the release layer 31 are removed to expose the first dielectric material 311f. Then, the first dielectric material 311f is patterned to form a plurality of first support pillars 311c, wherein the method of patterning the first dielectric material 311f can be exposure and development, and the first insulating layer 311 including the first peripheral layer 311a and the first support pillars 311c is formed.

[0092] Since the first dielectric material 311f and the second dielectric material 312f can have the same composition, the materials of the first peripheral layer 311a and the second peripheral layer 312a can be the same, and the first dielectric material 311f is different from the material of the first peripheral layer 311a. Therefore, the materials of the first support pillars 311c are different from the material of the first peripheral layer 311a, and the materials of the second support pillars 312c are also different from the material of the second peripheral layer 312a.

[0093] Referring to FIG. 3I Afterwards, a first circuit layer 321 is formed on the first insulating layer 311, wherein the first circuit layer 321 and the second circuit layer 322 can be formed by the same method, and the first circuit layer 321 includes a first return layer (not labeled). After the first circuit layer 321 is formed, a third insulating layer 313, a fourth insulating layer 314, a third circuit layer 323, and a fourth circuit layer 324 can be formed. At this point, the circuit substrate 300 has been basically completed.

[0094] It is worth mentioning that in the process of forming the first circuit layer 321 and the second circuit layer 322, the adhesive tape can be used to cover the bright surface of the metal foil to be formed into the first return layer and the second return layer 322b, so as to protect the bright surface of the metal foil from being roughened, maintain the roughness of the bright surface, and thus improve the signal transmission quality of the circuit substrate 300.

[0095] Although the present application has been disclosed with reference to the embodiments above, it is not intended to limit the present application and one skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, and the scope of protection of the present application is defined by the appended claims.

[0096] SYMBOL DESCRIPTION

[0097] 20: support plate

[0098] 21, 31: release layer

[0099] 30: additional circuit board

[0100] 100, 300: circuit substrate

[0101] 110, 110i, 310, 310i: insulating layer

[0102] 110a: peripheral layer

[0103] 110c: support column

[0104] 110h: opening

[0105] 110v, V3: hole

[0106] 111, 311: first insulating layer

[0107] 111a, 311a: first peripheral layer

[0108] 111c, 311c: first support column

[0109] 111h, 311h: first opening

[0110] 111w, 112w: hole wall

[0111] 112, 312: second insulating layer

[0112] 112a, 312a: second peripheral layer

[0113] 112c, 312c: second support column

[0114] 112h, 312h: second opening

[0115] 113, 313: third insulating layer

[0116] 114, 314: fourth insulating layer

[0117] 119: insulating protective layer

[0118] 120i, 330, 330i: metal layer

[0119] 121, 321: first circuit layer

[0120] 121b: first return layer

[0121] 122, 322: second line layer

[0122] 122a, 322a: signal line layer

[0123] 122b, 322b: second return layer

[0124] 123, 323: third line layer

[0125] 124, 324: fourth line layer

[0126] 129, 229, 329: high frequency line layer

[0127] 129a: first surface

[0128] 129b: second surface

[0129] 129p, 229p, 329p: perimeter metal layer

[0130] 129t, 329t: high frequency trace

[0131] 129v, 312v: via

[0132] 130: conductive layer

[0133] 131, 331: first conductive layer

[0134] 132, 332: second conductive layer

[0135] 141: shielded conductive post

[0136] 142, 342: conductive post

[0137] 210: insulating composite substrate

[0138] 220: metal composite substrate

[0139] 229h: trench

[0140] 310: insulating layer stack substrate

[0141] 311f: first dielectric material

[0142] 312f: second dielectric material

[0143] 330h: slot

[0144] C11: hollow cavity

[0145] M12: matte finish

[0146] M21 : first matte surface

[0147] M22: second matte surface

[0148] M29: metal wire

[0149] G12: glossy surface

[0150] G21 : first glossy surface

[0151] G22: second glossy surface

Claims

1. A circuit substrate, characterized by comprising: The first insulating layer has a first opening. The first conductive layer is formed on a hole wall of the first opening. The second insulating layer has a second opening. The second conductive layer is formed on a hole wall of the second opening. The high-frequency line layer is sandwiched between the first insulating layer and the second insulating layer, wherein the high-frequency line layer comprises: The high-frequency trace has a first surface and a second surface opposite to the first surface, the first opening exposes the first surface, and the second opening exposes the second surface; the first surface has a first smooth surface not covered by the first insulating layer, and the second surface has a second smooth surface not covered by the second insulating layer, wherein the roughness of both the first smooth surface and the second smooth surface is between 0.1 microns and 2 microns. The first line layer comprises a first return layer. The second line layer comprises a second return layer and a signal line layer, the signal line layer is arranged around the second return layer, wherein the first insulating layer and the second insulating layer are both arranged between the first line layer and the second line layer, the first opening and the second opening are arranged between the first return layer and the second return layer, and form a hollow cavity, the high-frequency trace is arranged in the hollow cavity, and the high-frequency trace, the first return layer and the second return layer overlap each other and do not contact. And A plurality of conductive columns are arranged in the second insulating layer, wherein the conductive columns connect the high-frequency trace and the signal line layer, and are not electrically connected to the second return layer. The first return layer has a first bright surface facing the first smooth surface, and the second return layer has a second bright surface facing the second smooth surface, the roughness of both the first bright surface and the second bright surface is between 0.5 microns and 2 microns.

2. The circuit substrate according to claim 1, wherein Further comprising:

3. The circuit substrate according to claim 1, wherein The third insulating layer covers the first line layer. The fourth insulating layer covers the second line layer, wherein the first line layer and the second line layer are both arranged between the third insulating layer and the fourth insulating layer. The third line layer; and The fourth line layer, wherein the third insulating layer and the fourth insulating layer are both arranged between the third line layer and the fourth line layer. The first return layer has: The first bright surface faces the first smooth surface; and 4. The circuit substrate according to claim 3, wherein The first rough surface is opposite to the first bright surface and directly contacts the third insulating layer; the second return layer has: The second bright surface faces the second smooth surface; and The second rough surface is opposite to the second bright surface and directly contacts the fourth insulating layer. Further comprising: A plurality of shielding conductive columns penetrate the first insulating layer and the second insulating layer, and connect the first line layer and the second line layer, wherein the shielding conductive columns are arranged around the first opening and the second opening, and are not electrically connected to the high-frequency trace. The first insulating layer comprises:

5. The circuit substrate according to claim 1, wherein A plurality of first support columns arranged on the first surface and arranged in the first opening, wherein the first support columns are arranged between the high-frequency trace and the first return layer; and The first peripheral layer is arranged on the high-frequency line layer and surrounds the first support columns, wherein the first peripheral layer and the first support columns are separated from each other, and the first peripheral layer does not cover the high-frequency trace.

6. The circuit substrate according to claim 1, wherein The material of the first support columns is different from the material of the first peripheral layer. ​ ​ 7. The circuit substrate according to claim 6, wherein ​ 8. The circuit substrate according to claim 6, wherein The intervals between the first support columns are equal to each other.

9. The circuit substrate according to claim 6, wherein The second insulating layer comprises: a plurality of second support columns disposed on the second surface and located in the second openings, wherein the second support columns are located between the high-frequency trace and the second return layer, and the conductive columns are respectively located in at least two of the second support columns; and a second perimeter layer disposed on the high-frequency line layer and surrounding the second support columns, wherein the second perimeter layer and the second support columns are separated from each other, and the second perimeter layer does not cover the high-frequency trace, wherein the high-frequency line layer is located between the first perimeter layer and the second perimeter layer.

10. The circuit substrate according to claim 9, wherein The materials of the second support columns are different from the material of the second perimeter layer.

11. The circuit substrate according to claim 9, wherein The first support columns respectively overlap the second support columns.

12. The circuit substrate according to claim 9, wherein The intervals between the second support columns are equal to each other.

13. The circuit substrate according to claim 1, wherein The materials of the first conductive layer and the second conductive layer are different from the materials of the first line layer and the second line layer.

14. The circuit substrate according to claim 1, wherein The high-frequency line layer further comprises: a perimeter metal layer surrounding the high-frequency trace, wherein the high-frequency trace is not electrically connected to the perimeter metal layer.

15. The circuit substrate according to claim 14, wherein The perimeter metal layer comprises: two metal lines, wherein the high-frequency trace is located between the metal lines, and the high-frequency trace and the metal lines are parallel to each other.

16. A method for manufacturing a circuit substrate, characterized by Comprising: forming a high-frequency line layer comprising a high-frequency trace, wherein the high-frequency trace has a first surface and a second surface opposite to the first surface; forming a first insulating layer having a first opening; forming a first conductive layer on the hole wall of the first opening; forming a second insulating layer having a second opening; forming a second conductive layer on the hole wall of the second opening; disposing the first insulating layer on the high-frequency line layer, wherein the first opening exposes the first surface, and the first surface has a first smooth surface not covered by the first insulating layer, wherein the roughness of the first smooth surface is between 0.1 microns and 2 microns; disposing the second insulating layer on the high-frequency line layer, wherein the second opening exposes the second surface, and the second surface has a second smooth surface not covered by the second insulating layer, wherein the roughness of the second smooth surface is between 0.1 microns and 2 microns; forming a first line layer comprising a first return layer on the first insulating layer; and forming a second line layer comprising a second return layer on the second insulating layer, wherein the first opening and the second opening are located between the first return layer and the second return layer, and form a hollow cavity, the high-frequency trace is located in the hollow cavity, and the high-frequency trace, the first return layer, and the second return layer overlap each other and do not contact.

17. The method of manufacturing a circuit substrate according to claim 16, wherein The step of forming the high-frequency line layer comprises: providing a metal composite substrate comprising a metal layer, a support plate, and a release layer located between the metal layer and the support plate; and patterning the metal layer.

18. The method of manufacturing a circuit substrate according to claim 16, wherein The step of forming at least one of the first insulating layer and the second insulating layer comprises: providing an insulating composite substrate comprising an insulating layer, a support plate, and a release layer located between the insulating layer and the support plate; and patterning the insulating layer.

19. The method of manufacturing a circuit substrate according to claim 16, wherein The method of forming the first conductive layer and the second conductive layer comprises electroless plating.

20. The method of manufacturing a circuit substrate according to claim 16, wherein The step of forming the first insulating layer comprises: An insulating layer stack substrate is provided, which includes a plurality of insulating layers and a plurality of release layers, wherein the insulating layers and the release layers are alternately stacked with each other, and the insulating layers are located between two of the release layers; A slot is formed in the insulating layer stack substrate, wherein the slot is formed through the insulating layers and the release layers; After the slot is formed, the release layers and part of the insulating layers are removed, and one of the insulating layers is retained, to form a first perimeter layer, wherein the first perimeter layer has the first opening; The first opening is filled with a first dielectric material; and The first dielectric material is patterned.

21. The method of manufacturing a circuit substrate according to claim 20, wherein The high-frequency circuit layer is formed on the first dielectric material before the first dielectric material is patterned.

22. The method of manufacturing a circuit substrate according to claim 21, wherein The step of forming the second insulating layer includes: A second perimeter layer is formed on the high-frequency circuit layer, wherein the second perimeter layer has the second opening; The second opening is filled with a second dielectric material; and The second dielectric material is patterned.

23. The method of manufacturing a circuit substrate according to claim 20, wherein The step of forming the first conductive layer includes: A metal layer is formed on the slot wall of the slot; and Part of the metal layer is removed after the metal layer is formed.

24. The method of manufacturing a circuit substrate according to claim 23, wherein The step of removing part of the metal layer, the release layers and part of the insulating layers, and retaining one of the insulating layers includes: After the metal layer is formed, the outermost two layers of the release layers are removed, and the insulating layers and at least one layer of the release layers are retained, wherein at least one layer of the release layers is located between two of the insulating layers; After the outermost two layers of the release layers are removed, the insulating layers and at least one layer of the release layers are arranged on an additional circuit board; and After the insulating layers and at least one of the release layers are arranged on the additional circuit board, at least one of the insulating layers and the release layers is removed, and one of the insulating layers is retained.

Images