Semiconductor structure and manufacturing method

Abstract

This application discloses a semiconductor structure and its manufacturing method. The semiconductor structure manufacturing method includes: forming a contact hole on a substrate; forming a first doped layer on the surface of the contact hole and annealing the first doped layer; forming at least one second doped layer on the first doped layer and annealing each second doped layer; forming a third doped layer on the second doped layer to fill the contact hole; wherein the thickness of the second doped layer is greater than the thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. The annealing process can not only repair the lattice mismatch and lattice defects inside the first / second doped layer, but also improve the surface roughness of the first / second doped layer, making the grain growth of the first / second doped layer more uniform, thereby improving the sealing problem that occurs after the formation of the first / second doped layer and forming a good filling effect.

Description

Technical Field

[0001] This application relates to the field of semiconductor structure and manufacturing technology, and more specifically, to a semiconductor structure and its manufacturing method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a widely used semiconductor memory in multi-computer systems. As the feature size of semiconductor integrated circuit devices continues to shrink, the critical dimensions of DRAM are also becoming smaller, and the aspect ratio of contact holes is increasing. However, methods for filling contact holes in related technologies can easily lead to voids within the contact holes, thus affecting device yield. Summary of the Invention

[0003] This application provides a semiconductor structure and its manufacturing method to solve the problem of pores easily appearing in contact holes in related technologies.

[0004] The method for manufacturing a semiconductor structure according to an embodiment of this application includes:

[0005] Forming contact holes on a substrate;

[0006] A first doped layer is formed on the surface of the contact hole, and the first doped layer is annealed.

[0007] At least one second doped layer is formed on the first doped layer, and each second doped layer is annealed.

[0008] A third doped layer is formed on the second doped layer to fill the contact hole;

[0009] Wherein, the thickness of the second doped layer is greater than the thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer.

[0010] In some embodiments of this application, the ratio of the thickness of the first doped layer to the original porosity of the contact hole is between 5% and 12.5%, the ratio of the thickness of each second doped layer to the original porosity of the contact hole is between 20% and 30%, and the ratio of the thickness of the third doped layer to the original porosity of the contact hole is between 20% and 35%.

[0011] In some embodiments of this application, the doping concentration of the first doped layer is greater than the doping concentration of the third doped layer, and the doping concentration of the third doped layer is greater than the doping concentration of the second doped layer.

[0012] In some embodiments of this application, the doping concentration of the first doped layer is 8*10. 20~30*10 20 cm -2 The doping concentration of the second doped layer is 1*10. 20 ~4*10 20 cm -2 The doping concentration of the third doped layer is 4*10. 20 ~10*10 20 cm -2 .

[0013] In some embodiments of this application, a first doped layer is formed on the surface of the contact hole, and the first doped layer is annealed, including:

[0014] The substrate is placed inside the furnace body;

[0015] A reactive gas is introduced into the furnace body to form the first doped layer;

[0016] After the first doped layer is formed, nitrogen gas is introduced into the furnace to anneal the first doped layer.

[0017] In some embodiments of this application, the first doped layer is annealed, including:

[0018] The annealing temperature of the first doped layer is between 500 and 700°C, and the annealing time is between 0.5 and 3 hours.

[0019] In some embodiments of this application, at least one second doped layer is formed on the first doped layer, and each second doped layer is subjected to annealing, including:

[0020] The annealed substrate is placed in the furnace body;

[0021] A reaction gas is introduced into the furnace body to form at least one second doped layer;

[0022] After each second doped layer is formed and before the next second doped layer is formed, nitrogen gas is introduced into the furnace to anneal each second doped layer.

[0023] In some embodiments of this application, each of the second doped layers is annealed, including:

[0024] The annealing temperature of the second doped layer is between 500 and 700°C, and the annealing time is between 0.5 and 3 hours.

[0025] The method for manufacturing a semiconductor structure according to an embodiment of this application includes:

[0026] Forming contact holes on a substrate;

[0027] A first doped layer is formed on the surface of the contact hole, and the first doped layer is annealed and etched so that the thickness of the first doped layer located at the upper part of the contact hole after etching is less than the thickness of the first doped layer located at the lower part of the contact hole.

[0028] At least one second doped layer is formed on the surface of the first doped layer, and after forming each second doped layer, the second doped layer is annealed and etched so that the thickness of the second doped layer located above the contact hole after etching is less than the thickness of the second doped layer located below the contact hole; and

[0029] A third doped layer is formed on the second doped layer to fill the contact hole;

[0030] Wherein, the thickness of the second doped layer is greater than the thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer.

[0031] In some embodiments of this application, before the first doped layer is annealed and etched, the ratio of the thickness of the first doped layer to the original porosity of the contact hole is between 5% and 12.5%.

[0032] Before annealing and etching the second doped layer, the ratio of the thickness of each second doped layer to the original porosity of the contact hole is between 20% and 30%.

[0033] The ratio of the thickness of the third doped layer to the original porosity of the contact hole is between 20% and 35%.

[0034] In some embodiments of this application, the ratio of the thickness of the first doped layer located above the contact hole to the original thickness of the first doped layer is between 10% and 50%.

[0035] The ratio of the thickness of the first doped layer located below the contact hole to the original thickness of the first doped layer is between 70% and 90%.

[0036] In some embodiments of this application, the ratio of the thickness of the second doped layer located above the contact hole to the original thickness of the second doped layer is between 10% and 50%.

[0037] The ratio of the thickness of the second doped layer located below the contact hole to the original thickness of the second doped layer is between 70% and 90%.

[0038] In some embodiments of this application, the doping concentration of the first doped layer is greater than the doping concentration of the third doped layer, and the doping concentration of the third doped layer is greater than the doping concentration of the second doped layer.

[0039] In some embodiments of this application, the doping concentration of the first doped layer is 8*10. 20 ~30*10 20 cm -2 The doping concentration of the second doped layer is 1*10. 20 ~4*10 20 cm -2 The doping concentration of the third doped layer is 4*10. 20 ~10*10 20 cm -2 .

[0040] The semiconductor structure of this application embodiment includes:

[0041] The substrate, including contact holes;

[0042] A first doped layer is disposed on the surface of the contact hole, wherein the thickness of the first doped layer located above the contact hole is less than the thickness of the first doped layer located below the contact hole;

[0043] At least one second doped layer is disposed on the surface of the first doped layer, wherein the thickness of the second doped layer above the contact hole is less than the thickness of the second doped layer below the contact hole; and

[0044] A third doped layer is disposed on the surface of the second doped layer and fills the contact hole. The thickness of the third doped layer located above the contact hole is greater than the thickness of the third doped layer located below the contact hole.

[0045] Wherein, the thickness of the second doped layer is greater than the thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer.

[0046] In some embodiments of this application, the thickness of the first doped layer formed on the sidewall of the contact hole gradually increases from top to bottom;

[0047] The thickness of the second doped layer formed on the sidewall of the contact hole gradually increases from top to bottom;

[0048] The thickness of the third doped layer filling the contact hole gradually decreases from top to bottom.

[0049] In some embodiments of this application, the doping concentration of the first doped layer is greater than the doping concentration of the third doped layer, and the doping concentration of the third doped layer is greater than the doping concentration of the second doped layer.

[0050] In some embodiments of this application, the doping concentration of the first doped layer is 8*10.20 ~30*10 20 cm -2 The doping concentration of the second doped layer is 1*10. 20 ~4*10 20 cm -2 The doping concentration of the third doped layer is 4*10. 20 ~10*10 20 cm -2 .

[0051] The semiconductor structure manufacturing method of this application embodiment forms a first doped layer, at least one second doped layer, and a third doped layer within a contact hole, and performs annealing after forming the first and second doped layers. This method can, on the one hand, repair lattice mismatch and lattice defects within the first / second doped layers, and on the other hand, improve the surface roughness of the first / second doped layers, resulting in more uniform grain growth. This improves the sealing problem that occurs after forming the first / second doped layers, preventing the formation of voids within the contact hole and achieving a good filling effect, thereby improving the device yield and performance. Furthermore, because the surface roughness of the first doped layer is relatively poor, the thickness of the second doped layer can be greater than that of the first doped layer, thus improving the performance of the semiconductor device.

[0052] In addition, by etching the first doped layer after its formation and etching the second doped layer after each formation of the second doped layer, the etched first and second doped layers exhibit a structure that is thinner at the top and thicker at the bottom within the contact hole. This results in a widened structure for the contact hole, which helps to reduce the aspect ratio of the contact hole and further prevents the formation of voids after the contact hole is filled. Attached Figure Description

[0053] Figure 1 The diagram shows a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of this application.

[0054] Figures 2 to 7 The diagram shown is a schematic diagram of each step of a semiconductor structure manufacturing method according to an embodiment of this application.

[0055] Figure 8 The diagram shows a flowchart of a method for manufacturing a semiconductor structure according to another embodiment of this application.

[0056] Figures 9 to 13 The diagram shown is a schematic diagram of the steps of a method for manufacturing a semiconductor structure according to another embodiment of this application.

[0057] The reference numerals in the attached figures are explained as follows:

[0058] 100, substrate 110, contact hole

[0059] 120, bit line 130, first spacer layer

[0060] 140, second spacer layer, 150, third spacer layer

[0061] 160, Fourth Interval Layer, 170, Fifth Interval Layer

[0062] 200, First doped layer, 300, Second doped layer

[0063] 400, Third doped layer Detailed Implementation

[0064] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0065] like Figure 1 As shown, Figure 1 The diagram shows a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of this application. The method for manufacturing a semiconductor structure according to an embodiment of this application includes the following steps:

[0066] Step S110: Form a contact hole on a substrate;

[0067] Step S130: A first doped layer is formed on the surface of the contact hole, and the first doped layer is annealed.

[0068] Step S150: At least one second doped layer is formed on the first doped layer, and each second doped layer is annealed.

[0069] Step S170: A third doped layer is formed on the second doped layer to fill the contact holes;

[0070] The thickness of the second doped layer is greater than that of the third doped layer, and the thickness of the third doped layer is greater than that of the first doped layer.

[0071] The semiconductor structure manufacturing method of this application embodiment forms a first doped layer, at least one second doped layer, and a third doped layer in the contact hole, and performs annealing treatment after forming the first and second doped layers. On the one hand, it can repair the lattice mismatch and lattice defects inside the first / second doped layer, and on the other hand, it can improve the surface roughness of the first / second doped layer, making the grain growth of the first / second doped layer more uniform. This improves the sealing problem that occurs after the formation of the first / second doped layer, prevents the formation of pores in the contact hole, forms a good filling effect, and improves the yield and performance of the device.

[0072] like Figure 2 As shown, contact holes 110 are formed on substrate 100. It is understood that substrate 100 can be a semiconductor substrate; for example, substrate 100 can include silicon substrates, germanium substrates, germanium-silicon substrates, and silicon carbide substrates. If applied to dynamic random access memory, substrate 100 may also include word lines and bit lines 120. Contact holes 110 are formed in the region between adjacent bit lines 120. A first spacer layer 130 is provided on both sides of the bit line 120, a second spacer layer 140 is formed on the sidewalls of the first spacer layer 130, and a third spacer layer 150 is formed on the sidewalls of the second spacer layer 140.

[0073] In one embodiment, the first spacer layer 130 and the third spacer layer 150 may be made of the same material, but different from the material of the second spacer layer 140. For example, the first spacer layer 130 and the third spacer layer 150 may be made of silicon nitride, and the second spacer layer 140 may be made of silicon oxide, such that the first spacer layer 130, the second spacer layer 140, and the third spacer layer 150 form a non-non-isolated structure (silicon nitride-silicon oxide-silicon nitride isolation structure). The first spacer layer 130, the second spacer layer 140, and the third spacer layer 150 can be used to protect the bit line 120, and also serve to isolate the bit line 120 from the subsequent polysilicon layer.

[0074] Of course, in another embodiment, the isolation structure on both sides of the bit line 120 may also include two isolation layers, such as an ON isolation structure (silicon oxide-silicon nitride isolation structure), for example, the material of the first spacer layer 130 includes silicon nitride, and the material of the second spacer layer 140 includes silicon oxide.

[0075] It should be noted that shallow trench isolation structures, doped regions, or other semiconductor structures can also be formed in the substrate 100, and this application does not impose any particular limitations on this. Additionally, in Figures 2 to 7 The related structures not marked in the text can be existing semiconductor structures (such as the related structures required to form contact hole 110), and this application does not impose any special limitations.

[0076] Please continue reading. Figure 3 Bit lines 120 are provided on both sides of the contact hole 110. The bottom of one bit line 120 extends into the substrate 100, and the bottom surface of the bit line 120 is deeper than the bottom surface of the contact hole 110. Since the bit line 120 extends into the substrate 100, the contact hole 110 also extends into the substrate 100, and the contact hole 110 can contact the active region within the substrate 100. The bottom of the other bit line 120 is further provided with a third spacer layer 150 and a second spacer layer 140 to isolate the bit line 120 from the substrate 100.

[0077] like Figure 3 and Figure 4 As shown, a first doped layer 200 is formed on the surface of the contact hole 110, and the first doped layer 200 is annealed. By annealing the first doped layer 200, on the one hand, the lattice mismatch and lattice defects inside the first doped layer 200 can be repaired, and on the other hand, the surface roughness of the first doped layer 200 can be improved, making the grain growth of the first doped layer 200 more uniform. This avoids the sealing problem in the contact hole 110 after the formation of the first doped layer 200, and therefore no more pores will be formed in the contact hole 110.

[0078] In one embodiment, the material of the first doped layer 200 may include polycrystalline silicon.

[0079] For example, the step of forming the first doped layer 200 may include: placing a substrate 100 including a contact hole 110 in a furnace, then introducing silane into the furnace to form a polycrystalline silicon layer on the surface of the contact hole 110, while simultaneously introducing a doping gas into the furnace to finally form the first doped layer 200.

[0080] In one embodiment, the polysilicon layer can be ion-doped using ion implantation or diffusion processes to form a first doped layer 200.

[0081] In one embodiment, the doping concentration of the first doped layer 200 can be 8*10⁻⁶. 20 cm -2 ~30*10 20 cm -2 At this doping concentration, the contact resistance at the interface between the first doped layer 200 and the active region within the substrate 100 can be reduced, thereby lowering the device resistance and improving device performance.

[0082] In one embodiment, the first doped layer 200 may include a P-type or N-type doped material.

[0083] After the first doped layer 200 is formed, nitrogen gas can be introduced into the furnace to anneal the first doped layer 200. It should be noted that in this embodiment, the formation of the first doped layer 200 and the annealing of the first doped layer 200 are completed in the same furnace. This improves work efficiency, and the introduction of nitrogen gas ensures that the first doped layer 200 is not oxidized, thus maintaining its conductivity and improving device performance. In one embodiment, the annealing temperature of the first doped layer 200 is between 500 and 700°C, for example, 550-650°C, and the annealing time is between 0.5 and 3 hours, for example, 1-2 hours. The temperature for forming the first doped layer 200 and the annealing temperature can be essentially the same, allowing the formation and annealing of the first doped layer 200 to be completed within the same temperature range, saving operational steps.

[0084] Please continue reading. Figure 3 and Figure 4 Before the first doped layer 200 is formed on the surface of the contact hole 110, the original porosity of the contact hole 110 is W (i.e., the width of the contact hole 110 is W). The thickness of the formed first doped layer 200 is t1. The ratio of the thickness of the first doped layer 200 to the original porosity of the contact hole 110 is between 5% and 12.5%, i.e., t1 / W = 5% to 12.5%, for example, t1 / W = 10%. Since the doping concentration of the first doped layer 200 is 8*10... 20 ~30*10 20 cm -2 When the doping concentration is high, the surface roughness of the first doped layer 200 is poor. Therefore, the ratio of the thickness of the first doped layer 200 to the original porosity of the contact hole 110 is designed to be 5% to 12.5%.

[0085] like Figure 5 and Figure 6 As shown, at least one second doped layer 300 is formed on the first doped layer 200, and each second doped layer 300 is annealed. Figure 5 Only one second doped layer 300 is shown, but it is not limited to this. By annealing the second doped layer 300, on the one hand, the lattice mismatch and lattice defects inside the second doped layer 300 can be repaired, and on the other hand, the surface roughness of the second doped layer 300 can be improved, making the grain growth of the second doped layer 300 more uniform. This avoids the sealing problem of the contact hole 110 after the formation of the second doped layer 300, and therefore no more pores will be formed in the contact hole 110.

[0086] In one embodiment, the material of the second doped layer 300 may include polycrystalline silicon.

[0087] For example, the steps of forming the second doped layer 300 may include: placing the substrate 100, on which the first doped layer 200 has been formed, in a furnace, and then introducing silane into the furnace to form a polycrystalline silicon layer on the surface of the first doped layer 200, while simultaneously introducing doping gas into the furnace to finally form the second doped layer 300.

[0088] In one embodiment, the polysilicon layer can be ion-doped using ion implantation or diffusion processes to form a second doped layer 300.

[0089] In one embodiment, the doping concentration of the second doped layer 300 can be 1*10⁻⁶. 20 ~4*10 20 cm -2 At this doping concentration, the poor surface roughness of the second doped layer 300 caused by polycrystalline silicon lattice mismatch and uneven growth rate due to doping can be improved as much as possible.

[0090] In one embodiment, the first doped layer 200 may include a P-type or N-type doped material.

[0091] After the formation of the second doped layer 300 and before the formation of the next second doped layer 300, nitrogen gas is introduced into the furnace to anneal the second doped layer 300. It should be noted that in this embodiment, the formation of the second doped layer 300 and the annealing of the second doped layer 300 are completed in the same furnace. This improves work efficiency, and the introduction of nitrogen gas ensures that the second doped layer 300 is not oxidized, thus maintaining its conductivity and improving device performance.

[0092] In one embodiment, the annealing temperature of the second doped layer 300 is between 500 and 700°C, for example, 550-650°C, and the annealing time is between 0.5 and 3 hours, for example, 1-2 hours. The temperature at which the second doped layer 300 is formed and the annealing temperature of the second doped layer 300 can be substantially the same. In this way, the formation and annealing of the second doped layer 300 can be completed within the same temperature range, saving operation steps.

[0093] Please continue reading. Figure 5 and Figure 6 The thickness of the second doped layer 300 in each layer is t2, wherein the ratio of the thickness of each second doped layer 300 to the original porosity of the contact hole 110 is between 20% and 30%, i.e., t2 / W = 20% to 30%, for example, t2 / W = 25%.

[0094] The doping concentration of the first doped layer 200 is greater than that of the second doped layer 300, and the thickness of the second doped layer 300 is greater than that of the first doped layer 200. Thus, because the first doped layer 200 has a higher doping concentration, the contact resistance between the first doped layer 200 and the active region can be reduced. The second doped layer 300 has a lower doping concentration, which improves the lattice mismatch of the polysilicon layer and the growth rate of the polysilicon. Simultaneously, because the first doped layer 200 has a higher doping concentration, its surface roughness is poorer, resulting in a thinner first doped layer than the second doped layer 300. This leads to a better overall surface roughness of the doped layer and reduces the overall lattice mismatch, ultimately resulting in a good polysilicon filling effect and preventing the formation of voids in the filled contact holes 110.

[0095] Understandably, the number of layers forming the second doped layer 300 can be adjusted according to the aspect ratio of the contact hole 110. For example, when the aspect ratio of the contact hole 110 is less than 15, the number of layers of the second doped layer 300 can be selected from 1 to 3.

[0096] like Figure 7 As shown, a third doped layer 400 is formed on the second doped layer 300 to fill the contact hole 110.

[0097] In one embodiment, the material of the third doped layer 400 may include polycrystalline silicon.

[0098] For example, the steps of forming the third doped layer 400 may include: placing the substrate 100 on which the second doped layer 300 is formed in a furnace, then introducing silane into the furnace to form a polycrystalline silicon layer on the surface of the second doped layer 300, while introducing doping gas into the furnace to finally form the third doped layer 400.

[0099] In one embodiment, the polysilicon layer can be particle-doped using ion implantation or diffusion processes to form a third doped layer 400.

[0100] In one embodiment, the doping concentration of the third doped layer 400 can be 4*10⁻⁶. 20 ~10*10 20 cm -2 It should be noted that the conductivity of doped polysilicon is positively correlated with the doping concentration; that is, the higher the doping concentration, the higher the conductivity. However, a higher doping concentration results in a poorer surface roughness of the doped layer. Therefore, at a moderate doping concentration, both the conductivity of polysilicon and the surface roughness of the doped layer can be balanced.

[0101] In one embodiment, the third doped layer 400 may include a P-type or N-type doped material.

[0102] Please continue reading. Figure 7 The thickness of the third doped layer 400 is t3, and the ratio of the thickness of the third doped layer 400 to the original porosity of the contact hole 110 is between 20% and 35%, i.e., t3 / W = 20% to 35%, for example, t3 / W = 30%. In other words, after forming one or more second doped layers 300, the size of the remaining pores in the contact hole 110 is at least 20% larger than the original size. This prevents the formation of pores with large aspect ratios after the formation of the second doped layer 300, which is beneficial for achieving a good filling effect. It should be noted that after forming the third doped layer 400, annealing can be performed to improve the stress between the first doped layer 200, the second doped layer 300, and the third doped layer 400.

[0103] like Figure 8 As shown, Figure 8 The diagram shows a flowchart of a method for manufacturing a semiconductor structure according to another embodiment of this application. The method for manufacturing a semiconductor structure according to this embodiment includes the following steps:

[0104] Step S210: Form a contact hole on a substrate;

[0105] Step S230: A first doped layer is formed on the surface of the contact hole, and the first doped layer is annealed and etched so that the thickness of the first doped layer located on the upper part of the contact hole after etching is less than the thickness of the first doped layer located on the lower part of the contact hole.

[0106] Step S250: At least one second doped layer is formed on the surface of the first doped layer, and after each second doped layer is formed, the second doped layer is annealed and etched so that the thickness of the second doped layer located above the contact hole after etching is less than the thickness of the second doped layer located below the contact hole.

[0107] Step S270: A third doped layer is formed on the second doped layer to fill the contact holes;

[0108] The thickness of the second doped layer is greater than that of the third doped layer, and the thickness of the third doped layer is greater than that of the first doped layer.

[0109] The semiconductor structure manufacturing method of this application embodiment, based on controlling the thickness relationship between the first doped layer 200, the second doped layer 300 and the third doped layer 400, etches the first doped layer 200 after its formation and etches the second doped layer 300 after each formation. This results in the etched first doped layer 200 and second doped layer 300 having a structure that is thinner at the top and thicker at the bottom. Consequently, the contact hole 110 has an enlarged structure, which helps to reduce the aspect ratio of the contact hole 110 and ultimately achieves a good filling effect, avoiding the formation of filling gaps.

[0110] It should be noted that the specific details of forming the first doped layer 200, the second doped layer 300, and the third doped layer 400 in the semiconductor structure manufacturing method of this application embodiment are basically the same as those in the above embodiments, and will not be repeated here. The difference between the manufacturing method of this embodiment and the above embodiments is that after annealing the first doped layer 200 and the second doped layer 300, etching processes are performed on the first doped layer 200 and the second doped layer 300, respectively.

[0111] like Figure 9 As shown, after annealing the first doped layer 200, the first doped layer 200 is etched. After etching, the thickness of the first doped layer 200 located above the contact hole 110 is t1', t1' / t1 = 10%~50%; the thickness of the first doped layer 200 located below the contact hole 110 is t1”, t1” / t = 70%~90%.

[0112] By controlling the etching rate, the etching rate of the upper part of the contact hole 110 is greater than that of the lower part, thereby making the thickness of the upper part of the first doped layer 200 less than that of the lower part, ultimately forming an flared structure, reducing the aspect ratio of the contact hole 110, which helps with the filling of polysilicon.

[0113] In one embodiment, the first doped layer 200 is etched using at least one of CF4, HBr, Cl2, and Ar2 to etch the polysilicon. In this embodiment, Cl2 is used to etch the first doped layer 200 at a temperature between 280 and 380°C and a pressure between 3 and 20 torr.

[0114] like Figures 10 to 12 As shown, at least one second doped layer 300 is formed on the surface of the first doped layer 200 after etching, and after each second doped layer 300 is formed, the second doped layer 300 is subjected to annealing and etching.

[0115] It should be noted that the process steps for forming the second doped layer 300 and annealing the second doped layer 300 are basically the same as those in the above embodiments. Therefore, the manufacturing method of this embodiment has all the advantages and beneficial effects of the above embodiments, and will not be repeated here.

[0116] like Figure 12 As shown, after forming a second doped layer 300 and annealing it, and before forming the next second doped layer 300, the second doped layer 300 is etched. After etching, the thickness of the second doped layer 300 above the contact hole 110 is t2', t2' / t2 = 10%~50%; the thickness of the second doped layer 300 below the contact hole 110 is t2”, t2” / t2 = 70%~90%.

[0117] By controlling the etching rate, the etching rate of the upper part of the contact hole 110 is greater than that of the lower part, which in turn makes the thickness of the upper part of the second doped layer 300 less than that of the lower part, ultimately forming an flared structure, reducing the aspect ratio of the contact hole 110, and facilitating the filling of polysilicon.

[0118] In one embodiment, the second doped layer 300 is etched using at least one of CF4, HBr, Cl2, and Ar2 to etch the polysilicon. In this embodiment, Cl2 is used to etch the second doped layer 300 at a temperature between 280 and 380°C and a pressure between 3 and 20 torr. It should be noted that after annealing the first doped layer 200 or the second doped layer 300, an etching gas is introduced into the furnace to etch the first doped layer 200 or the second doped layer 300. This means that the annealing and etching steps of the first doped layer 200 or the second doped layer 300 are performed in the same furnace, which simplifies the operation and prevents oxidation of the first doped layer 200 or the second doped layer 300.

[0119] like Figure 13 As shown, a third doped layer 400 is formed on the second doped layer 300 to fill the contact hole 110. The method for forming the third doped layer 400 is basically the same as in the above embodiment, and will not be described again here. It should be noted that after forming the third doped layer 400, an annealing process can be performed to improve the stress between the first doped layer 200, the second doped layer 300, and the third doped layer 400.

[0120] like Figure 13As shown in the embodiments of this application, a semiconductor structure is also provided, including a substrate 100, a first doped layer 200, at least one second doped layer 300 and a third doped layer 400. The substrate 100 includes a contact hole 110; a first doped layer 200 is disposed on the surface of the contact hole 110, the thickness of the first doped layer 200 located above the contact hole 110 is less than the thickness of the first doped layer 200 located below the contact hole 110; at least one second doped layer 300 is disposed on the surface of the first doped layer 200, the thickness of the second doped layer 300 located above the contact hole 110 is less than the thickness of the second doped layer 300 located below the contact hole 110; a third doped layer 400 is disposed on the surface of the second doped layer 300 and fills the contact hole 110, the thickness of the third doped layer 400 located above the contact hole 110 is greater than the thickness of the third doped layer 400 located below the contact hole 110; wherein, the thickness of the second doped layer 300 is greater than the thickness of the third doped layer 400, and the thickness of the third doped layer 400 is greater than the thickness of the first doped layer 200.

[0121] In one embodiment, the thickness of the first doped layer 200 formed on the sidewall of the contact hole 110 gradually increases from top to bottom; the thickness of the second doped layer 300 formed on the sidewall of the contact hole 110 gradually increases from top to bottom; and the thickness of the third doped layer 400 filling the contact hole 110 gradually decreases from top to bottom.

[0122] In the embodiments of this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0123] In the description of the embodiments of the application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the application.

[0124] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the claims. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0125] The above are merely preferred embodiments of the application examples and are not intended to limit the application examples. For those skilled in the art, the application examples can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the application examples should be included within the protection scope of the application examples.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Forming contact holes on a substrate; A first doped layer is formed on the surface of the contact hole, and the first doped layer is annealed. At least one second doped layer is formed on the first doped layer, and each second doped layer is annealed. A third doped layer is formed on the second doped layer to fill the contact hole; Wherein, the thickness of the second doped layer is greater than the thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The ratio of the thickness of the first doped layer to the original porosity of the contact hole is between 5% and 12.5%, the ratio of the thickness of each second doped layer to the original porosity of the contact hole is between 20% and 30%, and the ratio of the thickness of the third doped layer to the original porosity of the contact hole is between 20% and 35%.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The doping concentration of the first doped layer is greater than that of the third doped layer, and the doping concentration of the third doped layer is greater than that of the second doped layer.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, The doping concentration of the first doped layer is 8*10 20 ~30*10 20 cm -2 The doping concentration of the second doped layer is 1*10. 20 ~4*10 20 cm -2 The doping concentration of the third doped layer is 4*10. 20 ~10*10 20 cm -2 .

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, A first doped layer is formed on the surface of the contact hole, and the first doped layer is annealed, including: The substrate is placed inside the furnace body; A reactive gas is introduced into the furnace body to form the first doped layer; After the first doped layer is formed, nitrogen gas is introduced into the furnace to anneal the first doped layer.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, Annealing the first doped layer includes: The annealing temperature of the first doped layer is between 500 and 700°C, and the annealing time is between 0.5 and 3 hours.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, At least one second doped layer is formed on the first doped layer, and each second doped layer is annealed, including: The annealed substrate is placed in the furnace body; A reaction gas is introduced into the furnace body to form at least one second doped layer; After each second doped layer is formed and before the next second doped layer is formed, nitrogen gas is introduced into the furnace to anneal each second doped layer.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, Annealing is performed on each of the second doped layers, including: The annealing temperature of the second doped layer is between 500 and 700°C, and the annealing time is between 0.5 and 3 hours.

9. A method for manufacturing a semiconductor structure, characterized in that, include: Forming contact holes on a substrate; A first doped layer is formed on the surface of the contact hole, and the first doped layer is annealed and etched so that the thickness of the first doped layer located at the upper part of the contact hole after etching is less than the thickness of the first doped layer located at the lower part of the contact hole. At least one second doped layer is formed on the surface of the first doped layer, and after each second doped layer is formed, the second doped layer is annealed and etched so that the thickness of the second doped layer located above the contact hole after etching is less than the thickness of the second doped layer located below the contact hole. as well as A third doped layer is formed on the second doped layer to fill the contact hole; Wherein, the thickness of the second doped layer is greater than the thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, Before annealing and etching the first doped layer, the ratio of the thickness of the first doped layer to the original porosity of the contact hole is between 5% and 12.5%. Before annealing and etching the second doped layer, the ratio of the thickness of each second doped layer to the original porosity of the contact hole is between 20% and 30%. The ratio of the thickness of the third doped layer to the original porosity of the contact hole is between 20% and 35%.

11. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, The ratio of the thickness of the first doped layer located above the contact hole to the original thickness of the first doped layer is between 10% and 50%. The ratio of the thickness of the first doped layer located below the contact hole to the original thickness of the first doped layer is between 70% and 90%.

12. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, The ratio of the thickness of the second doped layer located above the contact hole to the original thickness of the second doped layer is between 10% and 50%. The ratio of the thickness of the second doped layer located below the contact hole to the original thickness of the second doped layer is between 70% and 90%.

13. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, The doping concentration of the first doped layer is greater than that of the third doped layer, and the doping concentration of the third doped layer is greater than that of the second doped layer.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, The doping concentration of the first doped layer is 8*10 20 ~30*10 20 cm -2 The doping concentration of the second doped layer is 1*10. 20 ~4*10 20 cm -2 The doping concentration of the third doped layer is 4*10. 20 ~10*10 20 cm -2 .

15. A semiconductor structure, characterized in that, include: The substrate, including contact holes; A first doped layer is disposed on the surface of the contact hole, wherein the thickness of the first doped layer located above the contact hole is less than the thickness of the first doped layer located below the contact hole; At least one second doped layer is disposed on the surface of the first doped layer, and the thickness of the second doped layer located above the contact hole is less than the thickness of the second doped layer located below the contact hole; as well as A third doped layer is disposed on the surface of the second doped layer and fills the contact hole. The thickness of the third doped layer located above the contact hole is greater than the thickness of the third doped layer located below the contact hole. Before forming the third doped layer, the first doped layer and the second doped layer are annealed; the thickness of the second doped layer is greater than the thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer.

16. The semiconductor structure according to claim 15, characterized in that, The thickness of the first doped layer formed on the sidewall of the contact hole gradually increases from top to bottom; The thickness of the second doped layer formed on the sidewall of the contact hole gradually increases from top to bottom; The thickness of the third doped layer filling the contact hole gradually decreases from top to bottom.

17. The semiconductor structure according to claim 15, characterized in that, The doping concentration of the first doped layer is greater than that of the third doped layer, and the doping concentration of the third doped layer is greater than that of the second doped layer.

18. The semiconductor structure according to claim 17, characterized in that, The doping concentration of the first doped layer is 8*10 20 ~30*10 20 cm -2 The doping concentration of the second doped layer is 1*10. 20 ~4*10 20 cm -2 The doping concentration of the third doped layer is 4*10. 20 ~10*10 20 cm -2 .

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