Display panel, display device and driving method thereof

Abstract

The embodiment of the present disclosure provides a display panel, a display device and a driving method thereof. The display panel includes: a first substrate; a plurality of scan lines; a plurality of data lines; a plurality of sub-pixels, respectively located in the areas divided by the plurality of scan lines and the plurality of data lines; at least two sub-pixels adjacent along the first direction and the second direction constitute a pixel island; a plurality of sub-pixels constitute a plurality of pixel islands; each pixel island includes n rows of sub-pixel rows in the second direction; a plurality of scan signal input lines, corresponding to the scan lines one by one; a plurality of control signal lines; a plurality of fixed potential lines; a plurality of control circuits, located between adjacent sub-pixels; a pixel island is connected to at least n control circuits; a control circuit corresponds to a row of sub-pixels in the pixel island; the control circuit is configured to: under the control of the control signal line, transmit the signal provided by the scan signal input line or the signal provided by the fixed potential line to the scan line.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a display device and a driving method thereof. Background Art

[0002] With the continuous development of display technology, ultra-high resolution display has become a possibility. At present, the display with a pixel density of up to 3000 (PPI) is no longer a fantasy. However, due to factors such as system capacity and graphics card processing speed, ultra-high resolution display cannot be popularized. Therefore, a partition-driven intelligent display mode is proposed, which displays the areas that the human eye focuses on normally, and reduces the resolution and refresh rate of the remaining areas, which can not only deal with the problem of insufficient system resources, but also meet the demand for low power consumption. However, the display products in the prior art can only realize the function of horizontal partition driving, and cannot realize vertical partition. Summary of the invention

[0003] An embodiment of the present disclosure provides a display panel, the display panel comprising:

[0004] a first substrate base plate;

[0005] A plurality of scanning lines are located on one side of the first substrate, the plurality of scanning lines extend along a first direction and are arranged along a second direction; the first direction intersects the second direction;

[0006] A plurality of data lines are located on the same side of the first substrate as the scanning lines, and the plurality of data lines extend along the second direction and are arranged along the first direction;

[0007] A plurality of sub-pixels are respectively located in areas divided by a plurality of scan lines and a plurality of data lines; at least two sub-pixels adjacent to each other along a first direction and a second direction constitute a pixel island; a plurality of sub-pixels constitute a plurality of pixel islands; each pixel island includes n rows of sub-pixel rows in the second direction;

[0008] A plurality of scan signal input lines, corresponding one to one with the scan lines, extending along the first direction and arranged along the second direction;

[0009] A plurality of control signal lines extending along the second direction and arranged along the first direction;

[0010] Multiple fixed potential lines;

[0011] A plurality of control circuits are located between adjacent sub-pixels; one pixel island is connected to at least n control circuits; one control circuit corresponds to a row of sub-pixels in the pixel island;

[0012] The control circuit is configured to transfer a signal provided by the scanning signal input line or a signal provided by the fixed potential line to the scanning line under the control of the control signal line.

[0013] In some embodiments, the control circuit includes: a first transistor and a second transistor;

[0014] A control electrode of the first transistor is electrically connected to a control signal line, a first electrode of the first transistor is electrically connected to a scan signal input line, and a second electrode of the first transistor is electrically connected to the scan line;

[0015] The control electrode of the second transistor is electrically connected to a control signal line, the first electrode of the second transistor is electrically connected to the fixed potential line, and the second electrode of the second transistor is electrically connected to the scanning line.

[0016] In some embodiments, the control circuit is located between two adjacent sub-pixels in the first direction;

[0017] A plurality of fixed potential lines extend along the first direction and are arranged along the second direction.

[0018] In some embodiments, the display panel specifically includes:

[0019] The first conductive layer includes a scan line, a scan signal input line, a fixed potential line, a control electrode of the first transistor, and a control electrode of the second transistor;

[0020] A second conductive layer, located on a side of the first conductive layer away from the first substrate, comprising a data line and a control signal line;

[0021] The third conductive layer is located on a side of the second conductive layer away from the first conductive layer, and includes a first electrode and a second electrode of the first transistor and a first electrode and a second electrode of the second transistor.

[0022] In some embodiments, the sub-pixel includes a driving transistor; the first conductive layer further includes: a control stage of the driving transistor electrically connected to the scan line;

[0023] The second conductive layer also includes: a first electrode of the driving transistor;

[0024] The third conductive layer also includes: a second electrode of the driving transistor.

[0025] In some embodiments, in each control circuit, the first transistors and the second transistors are arranged in two rows along a first direction.

[0026] In some embodiments, in each control circuit, an orthographic projection of a control electrode of the first transistor on a plane perpendicular to the first direction and an orthographic projection of a control electrode of the second transistor on a plane perpendicular to the first direction do not overlap each other.

[0027] In some embodiments, the first electrode and the second electrode of the first transistor are arranged along the second direction;

[0028] The first electrode and the second electrode of the second transistor are arranged along the second direction.

[0029] In some embodiments, the third conductive layer further includes: a first input lead, a second input lead, a first output lead, and a second output lead;

[0030] The first input lead is electrically connected to the first electrode of the first transistor and to the scan signal input line;

[0031] The second input lead is electrically connected to the first electrode of the second transistor and to the fixed potential line;

[0032] The first output lead is electrically connected to the second electrode of the first transistor and to the scan line;

[0033] The second output lead is electrically connected to the second electrode of the second transistor and to the scan line;

[0034] The first input lead, the second input lead, the first output lead and the second output lead all extend along the second direction.

[0035] In some embodiments, the control circuit is located between two adjacent sub-pixels in the second direction;

[0036] The plurality of fixed potential lines extend along the second direction and are arranged along the first direction.

[0037] In some embodiments, the display panel specifically includes:

[0038] A first conductive layer includes a scan line, a control electrode of a first transistor, and a control electrode of a second transistor;

[0039] A second conductive layer, located on a side of the first conductive layer away from the first substrate, comprising a scan signal input line;

[0040] A third conductive layer, located on a side of the second conductive layer away from the first conductive layer, comprising a data line;

[0041] The fourth conductive layer is located on the side of the third conductive layer away from the second conductive layer, and includes a control signal line, a fixed potential line, a first electrode and a second electrode of the first transistor, and a first electrode and a second electrode of the second transistor; the orthographic projection of the control signal line and the fixed potential line on the first substrate overlaps with a partial area of ​​the orthographic projection of the data line on the first substrate.

[0042] In some embodiments, the fourth conductive layer further includes: a plurality of first output leads and a plurality of second output leads extending along the second direction;

[0043] The second electrode of the first transistor is electrically connected to the scan line through the first output lead;

[0044] The second electrode of the second transistor is electrically connected to the scan line through the second output lead;

[0045] The orthographic projections of the first output lead and the second output lead on the first base substrate overlap a portion of the orthographic projection of the data line on the first base substrate.

[0046] In some embodiments, the subpixel includes a drive transistor;

[0047] The first conductive layer also includes: a control stage of a drive transistor electrically connected to the scan line;

[0048] The second conductive layer also includes: a first electrode of the driving transistor;

[0049] The display panel also includes:

[0050] The fifth conductive layer is located on a side of the fourth conductive layer away from the third conductive layer and includes a second electrode of the driving transistor.

[0051] In some embodiments, the control circuits corresponding to each pixel island are arranged in a row in the first direction.

[0052] In some embodiments, in each first transistor, the first electrode of the first transistor, the control stage of the first transistor, and the second electrode of the first transistor are arranged along a first direction;

[0053] In each second transistor, a first electrode of the second transistor, a control stage of the second transistor and a second electrode of the second transistor are arranged along a first direction.

[0054] In some embodiments, the display panel further includes: an active layer located between the first conductive layer and the first base substrate; the active layer includes an active layer of the first transistor and an active layer of the second transistor;

[0055] The active layer of the first transistor includes a portion extending along a first direction;

[0056] The active layer of the second transistor includes a portion extending along the first direction.

[0057] In some embodiments, the fourth conductive layer further includes: a plurality of first output leads and a plurality of second output leads extending along the second direction;

[0058] The second electrode of the first transistor is electrically connected to the scan line through the first output lead;

[0059] The second electrode of the second transistor is electrically connected to the scan line through the second output lead;

[0060] The orthographic projections of the first output lead and the second output lead on the first base substrate overlap a portion of the orthographic projection of the data line on the first base substrate.

[0061] In some embodiments, the display panel further includes: a first gate insulating layer between the first conductive layer and the active layer, a second gate insulating layer between the first conductive layer and the second conductive layer, a first interlayer insulating layer between the second conductive layer and the third conductive layer, a second interlayer insulating layer between the third conductive layer and the fourth conductive layer, and a third interlayer insulating layer between the fourth conductive layer and the fifth conductive layer;

[0062] The fourth conductive layer further includes: a plurality of first connection pads, a plurality of second connection pads, a plurality of third connection pads, a plurality of fourth connection pads, and a plurality of fifth connection pads;

[0063] The second electrode of the driving transistor is electrically connected to the active layer through a via hole penetrating the third interlayer insulating layer, the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer;

[0064] The first input lead is electrically connected to the first connection pad, and the first connection pad is electrically connected to the scan signal input line through a via hole penetrating the second interlayer insulating layer and the first interlayer insulating layer;

[0065] The first output lead is electrically connected to the second connection pad, and the second connection pad is electrically connected to the scan line through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer;

[0066] The first control signal line is electrically connected to the third connection pad, and the third connection pad is electrically connected to the control stage of the first transistor through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer;

[0067] The second control signal line is electrically connected to the fourth connection pad, and the fourth connection pad is electrically connected to the control stage of the second transistor through a via hole penetrating the second interlayer insulation layer, the first interlayer insulation layer, and the second gate insulation layer;

[0068] The second output lead is electrically connected to the fifth connection pad, and the fifth connection pad is electrically connected to the scan line through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer;

[0069] In which, in the area where the second electrode of the driving transistor is electrically connected to the active layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer have a first via hole; in the area where the second connection pad is electrically connected to the scan line, the first interlayer insulating layer and the second gate insulating layer have a second via hole; in the area where the second electrode of the driving transistor is electrically connected to the active layer and in the area where the second connection pad is electrically connected to the scan line, the second interlayer insulating layer has a third via hole exposing the first via hole and the second via hole.

[0070] In some embodiments, the display panel further comprises:

[0071] The pixel electrode layer is located on the side of the fifth conductive layer away from the fourth conductive layer, and includes a plurality of pixel electrodes corresponding to the sub-pixels one by one; the pixel electrodes are electrically connected to the second electrode of the driving transistor;

[0072] a common electrode layer, located at a side of the pixel electrode layer away from the fifth conductive layer;

[0073] A plurality of support parts are located on a side of the common electrode layer away from the pixel electrode layer, the orthographic projections of the support parts on the first substrate are located between adjacent sub-pixel rows, and the control circuit is located between the sub-pixel rows provided with the support parts;

[0074] The opposing substrate is located on the side of the supporting part away from the common electrode layer, and includes a plurality of shading parts extending along the first direction and arranged along the second direction; the orthographic projection of the shading part on the first base substrate covers the orthographic projection of the supporting part on the first base substrate and the orthographic projection of the control circuit on the first base substrate.

[0075] In some embodiments, each pixel island includes: a first sub-pixel row, a second sub-pixel row, and a third sub-pixel row;

[0076] The first sub-pixel row includes a plurality of first color sub-pixels arranged along a first direction;

[0077] The second sub-pixel row includes a plurality of second color sub-pixels arranged along the first direction;

[0078] The third sub-pixel row includes a plurality of third color sub-pixels arranged along the first direction;

[0079] The orthographic projection of the support portion on the base substrate is located between the first sub-pixel row and the third sub-pixel row.

[0080] In some embodiments, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

[0081] In some embodiments, the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to the same control signal line;

[0082] The first transistor is an N-type transistor, and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0083] In some embodiments, the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines.

[0084] In some embodiments, colors of sub-pixels in a row arranged in the first direction are all the same.

[0085] In some embodiments, the plurality of pixel islands are divided into a plurality of control regions, each control region including at least one pixel island;

[0086] Each scan line includes: a plurality of sub-scan lines arranged in a first direction and disconnected from each other; in each scan line, the number of sub-scan lines is the same as the number of a row of control areas arranged in the first direction, and each sub-scan line corresponds to a row of sub-pixels in a control area.

[0087] In some embodiments, in each control region, a row of pixel islands arranged in the first direction is connected to corresponding n control circuits.

[0088] A display device provided by an embodiment of the present disclosure includes:

[0089] The display panel provided by the embodiment of the present disclosure;

[0090] A cylindrical lens structure is located at the light-emitting side of the display panel; the cylindrical lens structure includes a plurality of cylindrical lenses arranged in an array;

[0091] The controller is connected to the display panel and is configured to provide a driving signal to the display panel.

[0092] An embodiment of the present disclosure provides a method for driving a display device, comprising:

[0093] Determine in real time the gaze area and non-gaze area of ​​the user on the display device;

[0094] The attention area is driven to display images at a first refresh rate, and the non-attention area is driven to display images at a second refresh rate; wherein the first refresh rate is higher than the second refresh rate.

[0095] In some embodiments, driving the attention area to display an image at a first refresh rate, and driving the non-attention area to display an image at a second refresh rate specifically includes:

[0096] Drive each sub-pixel in the focus area to refresh A times;

[0097] Driving each sub-pixel in the non-attention area to refresh B times;

[0098] Among them, A and B are positive integers, and A is greater than B.

[0099] In some embodiments, driving each sub-pixel in the focus area to refresh specifically includes:

[0100] Driving each scanning signal input line corresponding to the attention area to transmit effective level signals in sequence;

[0101] Control each control signal line to transmit a control signal, transmit the signal provided by the scan signal input line to the scan line corresponding to the attention area, and transmit the signal provided by the fixed potential line to the scan line corresponding to the non-attention area;

[0102] Driving each sub-pixel in the non-attention area to refresh, including:

[0103] Driving each scanning signal input line in the display panel to transmit effective level signals in sequence;

[0104] When scanning the sub-pixel rows corresponding to the attention area, control the control signal lines to transmit control signals, transmit the signals provided by the fixed potential lines to the scanning lines corresponding to the attention area, and transmit the signals provided by the scanning signal input lines to the scanning lines corresponding to the non-attention area. BRIEF DESCRIPTION OF THE DRAWINGS

[0105] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0106] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0107] Figure 2 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0108] Figure 3 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0109] Figure 4 A schematic diagram of sub-pixel arrangement in a display panel provided by an embodiment of the present disclosure;

[0110] Figure 5 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0111] Figure 6 A schematic diagram of the structure of a second light shielding layer in a display panel provided by an embodiment of the present disclosure;

[0112] Figure 7 A schematic diagram of the structure of an active layer in a display panel provided by an embodiment of the present disclosure;

[0113] Figure 8 A schematic diagram of the structure of a first conductive layer in a display panel provided by an embodiment of the present disclosure;

[0114] Fig. 9A schematic diagram of the structure of a first interlayer insulating layer in a display panel provided by an embodiment of the present disclosure;

[0115] Fig.10 A schematic diagram of the structure of a second conductive layer in a display panel provided by an embodiment of the present disclosure;

[0116] Fig.11 A schematic diagram of the structure of a second interlayer insulating layer in a display panel provided by an embodiment of the present disclosure;

[0117] Fig.12 A schematic diagram of the structure of a third conductive layer in a display panel provided by an embodiment of the present disclosure;

[0118] Fig.13 A schematic structural diagram of a first planarization layer in a display panel provided in an embodiment of the present disclosure;

[0119] Fig.14 A schematic diagram of the structure of a pixel electrode layer in a display panel provided by an embodiment of the present disclosure;

[0120] Fig.15 A schematic diagram of the structure of a common electrode layer in a display panel provided by an embodiment of the present disclosure;

[0121] Fig.16 A schematic structural diagram of a first light shielding layer in a display panel provided in an embodiment of the present disclosure;

[0122] Fig.17 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0123] Fig.18 A schematic diagram of the structure of a second light shielding layer in another display panel provided by an embodiment of the present disclosure;

[0124] Fig.19 A schematic structural diagram of an active layer in another display panel provided by an embodiment of the present disclosure;

[0125] Fig. 20 A schematic structural diagram of a first conductive layer in another display panel provided by an embodiment of the present disclosure;

[0126] Fig.21 A schematic structural diagram of a second conductive layer in another display panel provided by an embodiment of the present disclosure;

[0127] Fig. 22 A schematic structural diagram of a first interlayer insulating layer in another display panel provided by an embodiment of the present disclosure;

[0128] Fig.23 A schematic structural diagram of a third conductive layer in another display panel provided by an embodiment of the present disclosure;

[0129] Fig.24 A schematic diagram of the structure of a second interlayer insulating layer in another display panel provided by an embodiment of the present disclosure;

[0130] Fig.25 A schematic diagram of the structure of a second interlayer insulating layer in another display panel provided by an embodiment of the present disclosure;

[0131] Fig.26 A schematic structural diagram of a fourth conductive layer in a display panel provided by an embodiment of the present disclosure;

[0132] Fig. 27 A schematic diagram of the structure of a third interlayer insulating layer in a display panel provided by an embodiment of the present disclosure;

[0133] Fig.28 A schematic diagram of the structure of a fifth conductive layer in a display panel provided by an embodiment of the present disclosure;

[0134] Fig.29 A schematic structural diagram of a first passivation layer in another display panel provided in an embodiment of the present disclosure;

[0135] Fig.30 A schematic diagram of the structure of a pixel electrode layer in another display panel provided by an embodiment of the present disclosure;

[0136] Fig.31 A schematic diagram of the structure of a common electrode layer in another display panel provided by an embodiment of the present disclosure;

[0137] Fig.32 The embodiment of the present disclosure provides Fig.17 Cross-sectional view of AA';

[0138] Fig.33 The embodiment of the present disclosure provides Fig.17 Cross-sectional view of middle BB';

[0139] Fig.34 A schematic structural diagram of a first light shielding layer in another display panel provided in an embodiment of the present disclosure;

[0140] Fig.35 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0141] Fig.36 A schematic diagram of a driving method for a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0142] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. And in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in the field without creative work belong to the scope of protection of this application.

[0143] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. "First", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and other similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0144] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present application. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0145] The present disclosure provides a display panel. Figure 1 to Figure 3 As shown, the display panel includes:

[0146] A first substrate 1;

[0147] A plurality of scanning lines 2 are located on one side of the first substrate 1, and the plurality of scanning lines 2 extend along a first direction X and are arranged along a second direction Y; the first direction X and the second direction Y intersect;

[0148] A plurality of data lines 3 are located on the same side of the first substrate 1 as the scanning lines 2. The plurality of data lines 3 extend along the second direction Y and are arranged along the first direction X.

[0149] A plurality of sub-pixels 4 are respectively located in areas divided by a plurality of scanning lines 2 and a plurality of data lines 3; at least two sub-pixels 4 adjacent to each other along a first direction X and a second direction Y constitute a pixel island 5; a plurality of sub-pixels 4 constitute a plurality of pixel islands 5; each pixel island 5 includes n rows of sub-pixel rows 6 in the second direction Y;

[0150] A plurality of scanning signal input lines 7, corresponding to the scanning lines 2 one by one, extending along the first direction X and arranged along the second direction Y;

[0151] A plurality of control signal lines 8 extending along the second direction Y and arranged along the first direction X;

[0152] A plurality of fixed potential lines 9;

[0153] A plurality of control circuits 10 are located between adjacent sub-pixels 4; one pixel island 5 is connected to at least n control circuits 10; one control circuit 10 corresponds to one sub-pixel row 6 in the pixel island 5;

[0154] The control circuit 10 is configured to transmit the signal provided by the scanning signal input line 7 or the signal provided by the fixed potential line 9 to the scanning line 2 under the control of the control signal line 8 .

[0155] The display panel provided by the embodiment of the present disclosure includes a control circuit and a control signal line, a fixed potential line, and a scanning signal input line electrically connected to the control circuit, so that the control circuit can be used to transmit the signal provided by the scanning signal input line or the signal provided by the fixed potential line to the scanning line. That is to say, during the image display process, for the area that needs to be refreshed, the control circuit can be used to input a normal scanning signal to the corresponding scanning line, and for the area that does not need to be refreshed, the control circuit can be used to input a fixed potential signal transmitted by the fixed potential line to the corresponding scanning line. That is, the partition drive of the pixel island can be realized, thereby saving the power consumption of the display product. In addition, the pixel island array is arranged, and each pixel island is electrically connected to the control circuit, which can realize the partition control of each pixel island in the display panel in the second direction.

[0156] In a specific implementation, the display panel may be a rigid display panel or a flexible display panel, that is, the display panel is bendable and foldable.

[0157] In some embodiments, the display panel provided by the embodiments of the present disclosure is a liquid crystal display panel, which can be a twisted nematic (TN) type, a vertical alignment (VA) type, an in-plane switching (IPS) type, or an advanced super dimension switch (ADS) type liquid crystal display panel.

[0158] In some embodiments, the liquid crystal display panel includes: an array substrate and an opposite substrate that are arranged opposite to each other, and a liquid crystal layer located between the array substrate and the opposite substrate. Figure 1 to Figure 3 The signal lines and control circuits in the array substrate can be arranged on the array substrate, for example. Figure 1 to Figure 3The sub-pixel 4 includes a driving transistor T3. The sub-pixel 4 also includes a pixel electrode electrically connected to the driving transistor in a one-to-one correspondence. The opposite substrate includes a first light shielding layer and a color filter. The opening area of ​​the first light shielding layer is provided with a color filter corresponding to the color of the sub-pixel. In some embodiments, the liquid crystal display panel also includes a common electrode layer, which can be provided in the array substrate or in the opposite substrate.

[0159] In some embodiments, the display panel provided in the embodiments of the present disclosure is an electroluminescent display panel. The electroluminescent display panel may be, for example, an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, etc. In a specific implementation, each sub-pixel includes, for example, a pixel driving circuit and an electroluminescent device electrically connected to the pixel driving circuit, and the pixel driving circuit includes, for example, a transistor, a capacitor, etc.

[0160] In some embodiments, the fixed potential line inputs a low level signal.

[0161] In some embodiments, the display panel further includes a gate driving circuit, and the plurality of scan signal input lines are electrically connected to the gate driving circuit.

[0162] Therefore, the gate driving circuit can be used to realize the partition control of multiple rows of pixel islands, that is, to realize the horizontal partition control, that is, each pixel island in the display panel can be partitioned and controlled in the first direction and the second direction.

[0163] In some embodiments, Figure 4 As shown, a row of sub-pixels 4 arranged in the first direction X have the same color.

[0164] It should be noted that Figure 4 Only some of the sub-pixels are shown.

[0165] In some embodiments, Figure 1 to Figure 3 As shown, the plurality of pixel islands 5 are divided into a plurality of control areas 56, and each control area 56 includes at least one pixel island 5;

[0166] Each scan line 2 includes: a plurality of sub-scan lines 11 arranged in a first direction X and disconnected from each other; in each scan line 2, the number of sub-scan lines 11 is the same as the number of a row of control areas 56 arranged in the first direction X, and each sub-scan line 11 corresponds to a row of sub-pixels 4 in a control area 56.

[0167] That is, the scan lines are disconnected between the control areas, so that each control area can be independently controlled by the control circuit.

[0168] In some embodiments, Figure 1 to Figure 3 As shown, one pixel island 5 is connected to n control circuits.

[0169] In some embodiments, Figure 1 to Figure 3 As shown, in each control area 56 , a row of pixel islands 5 arranged in the first direction X is correspondingly connected to n control circuits 10 .

[0170] Of course, in a specific implementation, each pixel island may be connected to n control circuits.

[0171] In some embodiments, Figure 1 to Figure 3 As shown, each pixel island 5 includes three sub-pixel rows 6. That is, n=3, and each pixel island 5 is connected to three control circuits 10 accordingly.

[0172] In some embodiments, Figure 1 to Figure 3 As shown, the control circuit 10 includes: a first transistor T1 and a second transistor T2;

[0173] The control electrode of the first transistor T1 is electrically connected to a control signal line 8, the first electrode of the first transistor T1 is electrically connected to the scan signal input line 7, and the second electrode of the first transistor T1 is electrically connected to the scan line 2;

[0174] The control electrode of the second transistor T2 is electrically connected to a control signal line 8 , the first electrode of the second transistor T2 is electrically connected to the fixed potential line 9 , and the second electrode of the second transistor T2 is electrically connected to the scanning line 2 .

[0175] In a specific implementation, for a plurality of control circuits corresponding to a control area, under the control of a control signal inputted by a control signal line, when the first transistor is turned on and the second transistor is turned off, a signal inputted by a scanning signal input line is transmitted to the scanning line through the first transistor to refresh the pixel island of the control area. Under the control of a control signal inputted by a control signal line, when the second transistor is turned on and the first transistor is turned off, a low-level signal inputted by a fixed potential line is transmitted to the scanning line through the second transistor, i.e., the pixel island of the control area does not need to be refreshed.

[0176] In some embodiments, the second electrode of the first transistor T1 and the second electrode of the second transistor T1 in one control circuit are electrically connected to the same sub-scan line.

[0177] In some embodiments, Figure 1 As shown, the control electrode of the first transistor T1 and the control electrode of the second transistor T1 are electrically connected to the same control signal line 8;

[0178] The first transistor is an N-type transistor, and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0179] In some embodiments, Figure 2 , Figure 3 As shown, the control electrode of the first transistor T1 and the control electrode of the second transistor T2 are electrically connected to different control signal lines 8 .

[0180] In some embodiments, Figure 2 , Figure 3 As shown, the plurality of control signal lines 8 include: a plurality of first control signal lines 12 and a plurality of second control signal lines 13;

[0181] The control electrode of the first transistor T1 is electrically connected to the first control signal line 12 , and the control electrode of the second transistor T2 is electrically connected to the second control signal line 13 .

[0182] In a specific implementation, when the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines, the first transistor can be an N-type transistor or a P-type transistor, and the second transistor can be an N-type transistor or a P-type transistor.

[0183] In some embodiments, Figure 1 , Figure 2 As shown, the control circuit 10 is located between two adjacent sub-pixels 4 in the first direction X;

[0184] The plurality of fixed potential lines 9 extend along the first direction X and are arranged along the second direction Y.

[0185] That is Figure 1 , Figure 2 As shown, the control circuit 10 is located between two adjacent columns of sub-pixels 4 .

[0186] Next, the structure of the display panel is described by taking the example that the control circuit is located between two adjacent columns of sub-pixels.

[0187] In some embodiments, Figure 5 As shown, the display panel specifically includes:

[0188] The first conductive layer 14 includes a scan line 2, a scan signal input line 7, a fixed potential line 9, a control electrode G1 of the first transistor T1, and a control electrode G2 of the second transistor T2;

[0189] The second conductive layer 15 is located on the side of the first conductive layer 14 away from the first substrate, and includes the data line 3 and the control signal line 8;

[0190] The third conductive layer 17 is located on a side of the second conductive layer 15 away from the first conductive layer 14 , and includes a first electrode S1 and a second electrode D2 of the first transistor T1 , and a first electrode S2 and a second electrode D2 of the second transistor T2 .

[0191] and Figure 5 The corresponding patterns of the first conductive layer 14, the second conductive layer 15, and the third conductive layer 17 are as follows: Figure 8 , Fig.10 , Fig.12 shown.

[0192] In some embodiments, Figure 5 As shown, in each control circuit, the first transistors T1 and the second transistors T2 are arranged in two rows along a first direction.

[0193] In some embodiments, Figure 5 , Figure 8 As shown, in each control circuit, the orthographic projection of the control electrode G1 of the first transistor T1 on a plane perpendicular to the first direction and the orthographic projection of the control electrode G2 of the second transistor T2 on a plane perpendicular to the first direction do not overlap each other. That is, the control electrode G1 of the first transistor T1 and the control electrode G2 of the second transistor T2 are not arranged along a straight line parallel to the first direction, so that even if the control electrode G1 of the first transistor T1 and the control electrode G2 of the second transistor T2 have an overlapping area in the second direction, the control electrode G1 of the first transistor T1 and the control electrode G2 of the second transistor T2 will not have a short circuit problem. Accordingly, the total width of the first transistor T1 and the second transistor T2 in the first direction can be reduced, thereby minimizing the impact of the setting of the control circuit on the aperture ratio.

[0194] In some embodiments, Figure 5 , Fig.10 As shown, in the second direction, in each first transistor T1, the first electrode S1 of the first transistor T1 is located on the side of the second electrode D2 of the first transistor T1; in the second direction, in each second transistor T2, the first electrode S2 of the second transistor T2 is located on the side of the second electrode D2 of the second transistor T2. That is, the first electrode S1 and the second electrode D2 of the first transistor T1 are arranged along the second direction, and the first electrode S2 and the second electrode D2 of the second transistor T2 are also arranged along the second direction. In this way, it is possible to further avoid increasing the width of the first transistor T1 in the first direction and the width of the second transistor T2 in the first direction, thereby minimizing the influence of the setting of the control circuit on the aperture ratio.

[0195] In some embodiments, when the display panel is a liquid crystal display panel, the sub-pixel includes a driving transistor; the first conductive layer further includes: a control stage of the driving transistor electrically connected to the scan line 2;

[0196] The second conductive layer also includes: a first electrode of the driving transistor;

[0197] The third conductive layer also includes: a second electrode of the driving transistor.

[0198] In a specific implementation, the first electrode and the second electrode of the driving transistor are located in different conductive layers, and the first electrode and the second electrode of each transistor of the control circuit and the control signal line are located in different conductive layers, thereby reducing the distance between the second electrode of the driving transistor and the data line and reducing the distance between the first electrode and the second electrode of each transistor of the control circuit and the control signal line, without causing a short circuit between the second electrode of the driving transistor and the data line, or between the first electrode and the second electrode of each transistor of the control circuit and the control signal line, thereby reducing the difficulty of display panel layout design.

[0199] In some embodiments, the display panel further includes: a pixel electrode layer located on the side of the third conductive layer away from the second conductive layer 15, and a common electrode layer located on the side of the pixel electrode layer away from the third conductive layer. The pixel electrode layer includes pixel electrodes corresponding to the sub-pixels one by one. The common electrode layer includes a common electrode. It should be noted that in order to facilitate the clear illustration of the structure of the control circuit, Figure 5 The patterns of the common electrode layer and the pixel electrode layer are not shown. In a specific implementation, the pattern of the pixel electrode layer 21 is as follows: Fig.14 As shown, the pattern of the common electrode layer 35 is as shown in Fig.15 shown.

[0200] In some embodiments, Figure 5 , Figure 6 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 As shown, the display panel further includes a second light shielding layer 16 between the first conductive layer 14 and the first base substrate, an active layer 18 between the second light shielding layer 16 and the first conductive layer 14, a buffer layer (not shown) between the active layer 18 and the second light shielding layer 16, a gate insulating layer between the first conductive layer 14 and the active layer 18, a first interlayer insulating layer 19 between the first conductive layer 14 and the second conductive layer 15, a second interlayer insulating layer 20 between the second conductive layer 15 and the third conductive layer 17, a first planarizing layer 22 between the third conductive layer 17 and the pixel electrode layer, and a second planarizing layer between the pixel electrode layer and the common electrode layer. Among them, Figure 6 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 The patterns of the second light shielding layer 16, the active layer 18, the first interlayer insulating layer 19, the second interlayer insulating layer 20, and the first planarizing layer 22 are respectively, Fig. 9 , Fig.11 , Fig.13 The dotted line area is the area of ​​the via holes of the first interlayer insulating layer 19 , the second interlayer insulating layer 20 , and the first planarizing layer 22 .

[0201] In some embodiments, Figure 5 As shown, the third conductive layer further includes: a first input lead 23, a second input lead 24, a first output lead 25, and a second output lead 26. The first input lead 23 is electrically connected to the first electrode S1 of the first transistor T1, and is electrically connected to the scan signal input line 7 through a via hole penetrating the second interlayer insulating layer and the first interlayer insulating layer. The second input lead 24 is electrically connected to the first electrode S2 of the second transistor T2, and is electrically connected to the fixed potential line 9 through a via hole penetrating the second interlayer insulating layer and the first interlayer insulating layer. The first output lead 25 is electrically connected to the second electrode D2 of the first transistor T1, and is electrically connected to the scan line 2 through a via hole penetrating the second interlayer insulating layer and the first interlayer insulating layer, and the second output lead 26 is electrically connected to the second electrode D2 of the second transistor T2, and is electrically connected to the scan line 2 through a via hole penetrating the second interlayer insulating layer and the first interlayer insulating layer. The first input lead 23, the second input lead 24, the first output lead 25, and the second output lead 26 all extend along the second direction Y.

[0202] In a specific implementation, the first input lead 23 is integrally connected to the first electrode S1 of the first transistor T1. The second input lead 24 is integrally connected to the first electrode S2 of the second transistor T2. The first output lead 25 is integrally connected to the second electrode D2 of the first transistor T1. The second output lead 26 is integrally connected to the second electrode D2 of the second transistor T2.

[0203] In some embodiments, the first control signal line 12 is electrically connected to the control electrode G1 of the first transistor T1 through a via hole penetrating the first interlayer insulating layer. The second control signal line 13 is electrically connected to the control electrode G2 of the second transistor T2 through a via hole penetrating the first interlayer insulating layer. The first electrode S1 and the second electrode D2 of the first transistor T1, and the first electrode S2 and the second electrode D2 of the second transistor T2 are electrically connected to the active layer through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer and the gate insulating layer. The pixel electrode is electrically connected to the second electrode of the driving transistor through a via hole penetrating the first planarizing layer. The first electrode of the driving transistor is electrically connected to the active layer through a via hole penetrating the first interlayer insulating layer and the gate insulating layer, and the second electrode of the driving transistor is electrically connected to the active layer through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer and the gate insulating layer.

[0204] In some embodiments, the control circuit array is arranged so that the control stages of the first transistors in the same column in the second direction are electrically connected to the same first control signal line, and the control stages of the second transistors in the same column in the second direction are electrically connected to the same second control signal line. The first electrodes of the first transistors in the same row in the first direction are electrically connected to the same scan signal input line, and the first electrodes of the second transistors in the same row in the first direction are electrically connected to the same fixed potential line.

[0205] In some embodiments, Fig.16 As shown, the first light shielding layer in the opposite substrate includes a plurality of first light shielding portions 36 extending along the first direction X and a plurality of second light shielding portions 37 extending along the second direction Y. Among them, the first light shielding portion 36 covers the space between adjacent sub-pixel rows, that is, the first light shielding portion 36 covers the scanning line, the fixed potential line and the scanning signal input line. When the sub-pixels arranged in the first direction X have the same color, the second light shielding portion 37 only covers the space between the sub-pixel columns provided with the control circuit, that is, the second light shielding portion covers the control circuit, the control signal line and each input lead and output lead. There is no need to set the second light shielding portion between the sub-pixel columns without the control circuit, so that the sub-pixel aperture ratio can be increased as much as possible while shielding the control circuit and the control.

[0206] Or, in some embodiments, Figure 3 As shown, the control circuit 10 is located between two adjacent sub-pixels 4 in the second direction Y;

[0207] The plurality of fixed potential lines 9 extend along the second direction Y and are arranged along the first direction X.

[0208] That is, the control circuit 10 is located between adjacent sub-pixel rows.

[0209] In some embodiments, the control circuits corresponding to each pixel island are arranged in a row in the first direction X.

[0210] In some embodiments, control electrodes of first transistors arranged in a row in the second direction are electrically connected to the same first control signal line. Control electrodes of second transistors arranged in a row in the second direction are electrically connected to the same second control signal line, and first electrodes of second transistors arranged in a row in the second direction are electrically connected to the same fixed potential line.

[0211] Next, the structure of the display panel is described by taking the example that the control circuit is located between adjacent sub-pixel rows.

[0212] In some embodiments, Fig.17 As shown, the display panel specifically includes:

[0213] The first conductive layer 14 includes a scan line 2, a control electrode G1 of the first transistor T1, and a control electrode G2 of the second transistor T2;

[0214] The second conductive layer 15 is located on the side of the first conductive layer 14 away from the first substrate, and includes a scanning signal input line 7;

[0215] The third conductive layer 17 is located on a side of the second conductive layer 15 away from the first conductive layer 14 and includes the data line 3;

[0216] The fourth conductive layer 38 is located on the side of the third conductive layer 17 away from the second conductive layer 15, and includes a control signal line 8, a fixed potential line 9, a first electrode S1 and a second electrode D1 of the first transistor T1, and a first electrode S2 and a second electrode D2 of the second transistor T2; the orthographic projections of the control signal line 8 and the fixed potential line 9 on the first substrate overlap with a partial area of ​​the orthographic projection of the data line 3 on the first substrate.

[0217] in, Fig. 20 , Fig.21 , Fig.23 , Fig.26 Shown respectively with Fig.17 The corresponding patterns of the first conductive layer 14 , the second conductive layer 15 , the third conductive layer 17 , and the fourth conductive layer 38 .

[0218] It should be noted that Fig.17 This is a pattern of a partial area within a control area, so the disconnected area between the sub-scanning lines is not shown.

[0219] In a specific implementation, since the control signal line, the fixed potential line and the data line are located in different conductive layers, the orthographic projections of the control signal line and the fixed potential line on the first substrate overlap with part of the orthographic projections of the data line on the first substrate, thereby avoiding the signal lines electrically connected to the control circuit from affecting the sub-pixel aperture ratio.

[0220] In some embodiments, the subpixel includes a drive transistor;

[0221] The first conductive layer also includes: a control stage of a drive transistor electrically connected to the scan line;

[0222] The second conductive layer also includes: a first electrode of the driving transistor;

[0223] like Fig.17 , Fig.28 As shown, the display panel also includes:

[0224] The fifth conductive layer 42 is located on a side of the fourth conductive layer 38 away from the third conductive layer 17 and includes the second electrode D3 of the driving transistor.

[0225] in, Fig.28 For Fig.17 The corresponding pattern of the fifth conductive layer 42 .

[0226] In a specific implementation, the first electrode and the second electrode of the driving transistor are located in different conductive layers, thereby reducing the distance between the second electrode of the driving transistor and the data line without causing a short circuit between the second electrode of the driving transistor and the data line, thereby reducing the difficulty of display panel layout design.

[0227] In some embodiments, the display panel further includes: a pixel electrode layer located on the side of the fifth conductive layer away from the fourth conductive layer, and a common electrode layer located on the side of the pixel electrode layer away from the fifth conductive layer. The pixel electrode layer includes pixel electrodes corresponding to the sub-pixels one by one. The common electrode layer includes a common electrode. It should be noted that in order to facilitate the clear illustration of the structure of the control circuit, Fig.17 The patterns of the common electrode layer and the pixel electrode layer are not shown. In a specific implementation, the pattern of the pixel electrode layer 21 is as follows: Fig.30 As shown, the pattern of the common electrode layer 35 is as shown in Fig.31 shown.

[0228] It should be noted that the pixel electrode layer and the common electrode layer can be made of materials with higher transmittance. The pixel electrode layer and the common electrode layer can include, for example, indium tin oxide (ITO). That is, the array substrate can be provided with two layers of ITO layers. The first layer of ITO is used as the pixel electrode layer, so that the number of vias can be reduced and the aperture ratio can be improved. In some embodiments, the display panel also includes a metal common electrode line located in the same layer as the common electrode. In a specific implementation, for example, a common electrode line is formed on the second passivation layer, and then an ITO common electrode electrically connected to the common electrode line is formed.

[0229] In some embodiments, Fig.17 , Fig.18 , Fig.19 , Fig. 22 , Fig.24 , Fig.25 , Fig. 27 , Fig.29 , Fig.32 , Fig.33 As shown, the display panel further includes a second light shielding layer 16 between the first conductive layer 14 and the first substrate, an active layer 18 between the second light shielding layer 16 and the first conductive layer 14, a buffer layer 27 between the active layer 18 and the second light shielding layer 16, a first gate insulating layer 28 between the first conductive layer 14 and the active layer 18, a second gate insulating layer 29 between the first conductive layer 14 and the second conductive layer 15, a first interlayer insulating layer 19 between the second conductive layer 15 and the third conductive layer 17, a second interlayer insulating layer 20 between the third conductive layer 17 and the fourth conductive layer 38, a third interlayer insulating layer 43 between the fourth conductive layer 38 and the fifth conductive layer 42, a first passivation layer 44 between the fifth conductive layer and the pixel electrode layer, and a second passivation layer 30 between the pixel electrode layer and the common electrode layer. Among them, Fig.18 , Fig.19 , Fig. 22 , Fig. 27 , Fig.29 They are patterns of the second light shielding layer 16 , the active layer 18 , the first interlayer insulating layer 19 , the third interlayer insulating layer 43 , and the first passivation layer 44 . Fig.32 For along Fig.17 The cross-sectional view of AA', Fig.33 For along Fig.17 Cross-sectional view of BB'. Fig. 22 , Fig. 27 , Fig.29 The dotted line areas are the via holes of the first interlayer insulating layer 19 , the third interlayer insulating layer 43 , and the first passivation layer 44 . Fig.24 , Fig.25 The middle dotted line area corresponds to the area where the via hole is formed after the second interlayer insulating layer 20 is formed.

[0230] In a specific implementation, the second interlayer insulating layer plays the role of a planarizing layer. After forming the second interlayer insulating layer 20, first Fig.24 The dotted line area shown in FIG. 1 is subjected to a first patterning process to form a via hole. Then, based on the via hole formed by the first patterning process, a second patterning process is performed in the following manner: Fig.25 The dotted line area shown in the figure is subjected to a second patterning process to form a via hole. It should be noted that after forming the first interlayer insulating layer, the Fig.25 The dotted area shown in FIG. 1 forms a via hole, so that Fig.25 The dotted line area shown in the figure is subjected to a second patterning process, and corresponding via holes can be formed in the first interlayer insulating layer and the film layer below it, and the fourth conductive layer can be subsequently formed through the Fig.25 The via hole formed in the dashed area is electrically connected to the active layer or the first conductive layer.

[0231] In some embodiments, Fig.17 As shown, the first transistor T1 and the second transistor T2 in each control circuit are arranged in a row in the first direction.

[0232] In some embodiments, Fig.17 As shown, in each first transistor, the first electrode S1 of the first transistor T1, the control stage G1 of the first transistor T1 and the second electrode D1 of the first transistor T1 are arranged along the first direction;

[0233] In each second transistor T2 , the first electrode S1 of the second transistor T2 , the control stage G1 of the second transistor T2 , and the second electrode D1 of the second transistor T are arranged along the first direction.

[0234] That is, when the first transistor and the second transistor in each control circuit are arranged in a row in the first direction X, the first electrode, the control electrode, and the second electrode of each transistor in the control circuit are also arranged in a row in the first direction X, thereby reducing the size of the control circuit in the second direction Y, and further avoiding the influence of the control circuit on the sub-pixel aperture ratio.

[0235] In some embodiments, Fig.17As shown, the active layer of the first transistor T1 includes a portion extending along the first direction;

[0236] The active layer of the second transistor T2 includes a portion extending along the first direction.

[0237] In some embodiments, Fig.17 , Fig.26 As shown, the fourth conductive layer 38 further includes: a plurality of first output leads 25 and a plurality of second output leads 26 extending along the second direction Y;

[0238] The second electrode D1 of the first transistor T1 is electrically connected to the scan line 2 through the first output lead 25;

[0239] The second electrode D2 of the second transistor T2 is electrically connected to the scan line 2 through the second output lead 26;

[0240] The orthographic projections of the first output lead 25 and the second output lead 26 on the first substrate overlap a portion of the orthographic projection of the data line 3 on the first substrate.

[0241] In a specific implementation, since the first output lead, the first input lead and the second input lead are located in different conductive layers with the data line, the orthographic projections of the first output lead, the first input lead and the second input lead on the first substrate overlap with a partial area of ​​the orthographic projection of the data line on the first substrate, thereby avoiding the signal lines electrically connected to the control circuit from affecting the sub-pixel aperture ratio.

[0242] In some embodiments, Fig.17 , Fig.26 As shown, the fourth conductive layer 38 further includes: a first input lead 23 , and the first electrode S1 of the first transistor T1 is electrically connected to the scan signal input line 7 through the first input lead 23 .

[0243] In some embodiments, Fig.17 , Fig.26 As shown, the fourth conductive layer 38 further includes: a plurality of first connection pads 39, a plurality of second connection pads 40, a plurality of third connection pads 41, a plurality of fourth connection pads 45, and a plurality of fifth connection pads 46. The first input lead 23 is electrically connected to the first connection pad 39, and the first connection pad 39 is electrically connected to the scan signal input line 7 through a via hole penetrating the second interlayer insulating layer and the first interlayer insulating layer. Fig.32As shown, the first output lead 25 is electrically connected to the second connection pad 40, and the second connection pad 40 is electrically connected to the scan line 2 through the via 33 penetrating the second interlayer insulating layer 20, the first interlayer insulating layer 19, and the second gate insulating layer 29. The first control signal line 12 is electrically connected to the third connection pad 41, and the third connection pad 41 is electrically connected to the control stage of the first transistor through the via penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer. The second control signal line 13 is electrically connected to the fourth connection pad 45, and the fourth connection pad 45 is electrically connected to the control stage of the second transistor through the via penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer. The second output lead 26 is electrically connected to the fifth connection pad 46, and the fifth connection pad 46 is electrically connected to the scan line through the via penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer.

[0244] In some embodiments, Fig.32 As shown, the second connection pad 40 is electrically connected to the scanning line 2 through the fourth via hole 33 that penetrates the second interlayer insulating layer 20, the first interlayer insulating layer 19, and the second gate insulating layer 29. In a specific implementation, after the second interlayer insulating layer 20 is formed, a patterning process is first performed in the area corresponding to the fourth via hole 33 to form a via hole in the second interlayer insulating layer 20, and then a second patterning process is performed to form a via hole in the first interlayer insulating layer 19 and the second gate insulating layer 29. The via hole size h1 of the second interlayer insulating layer 20 is larger than the via hole size of the second gate insulating layer 29. Accordingly, the second connection pad 40 extends in a stepped shape in the area of ​​the fourth via hole 33, and the size of the plane area of ​​the second connection pad 40 at the via hole of the second gate insulating layer 29 is h2. In a specific implementation, h1 is, for example, 4 microns, and h2 is, for example, 2.5 microns.

[0245] In some embodiments, Fig.33As shown, the second electrode D3 of the driving transistor is electrically connected to the active layer 18 through a via hole penetrating the third interlayer insulating layer 43, the second interlayer insulating layer 20, the first interlayer insulating layer 19, the second gate insulating layer 29, and the first gate insulating layer 28. The second connection pad 40 is electrically connected to the scan line 2 through a via hole penetrating the second interlayer insulating layer 20, the first interlayer insulating layer 19, and the second gate insulating layer 29. In the region where the second electrode D3 of the driving transistor is electrically connected to the active layer 18, the first interlayer insulating layer 19, the second gate insulating layer 29, and the first gate insulating layer 28 have a first via hole 55, and in the region where the second connection pad 40 is electrically connected to the scan line 2, the first interlayer insulating layer 19 and the second gate insulating layer 29 have a second via hole 32; in the region where the second electrode D3 of the driving transistor is electrically connected to the active layer 18 and in the region where the second connection pad 40 is electrically connected to the scan line 2, the second interlayer insulating layer 20 has a third via hole 34 exposing the first via hole 55 and the second via hole 32. In a specific implementation, when two patterning processes are required to form vias after forming the second interlayer insulating layer 20, a patterning process is first performed to remove the second interlayer insulating layer 20 in the area of ​​the third via 34, and then a second patterning process is performed to form the second via 32. In a specific implementation, the dimension h4 of the first via 55 exposing the active layer 18 is, for example, 3 microns. The distance h3 between the edge of the first via 55 exposing the active layer 18 and the edge of the second interlayer insulating layer 20 exposing the first interlayer insulating layer 19 is, for example, 1.5 microns. The distance h5 between the edge of the first via 55 exposing the active layer 18 and the scan line is, for example, 2.05 microns. The dimension h6 of the second via 32 exposing the scan line 2 is, for example, 2.5 microns, and the distance h7 between the edge of the second via 32 exposing the scan line 2 and the scan signal input line 7 is, for example, 2.5 microns.

[0246] In some embodiments, the display panel further comprises:

[0247] an opposite substrate, located at a side of the support portion away from the common electrode layer, and comprising a light shielding portion;

[0248] The liquid crystal layer is located between the opposite substrate and the common electrode layer.

[0249] In some embodiments, the opposite substrate includes a first light shielding layer, and the first light shielding layer includes a light shielding portion. When the display panel is a liquid crystal display panel, the sub-pixels arranged in the first direction X have the same color, and the control circuit is located between adjacent sub-pixel rows, such as Fig.34As shown, the light shielding portion of the first light shielding layer in the counter substrate may only include a plurality of first light shielding portions 36 extending along the first direction X. The first light shielding portions 36 cover between adjacent sub-pixel rows, that is, the first light shielding portions 36 cover the scanning lines, the fixed potential lines, the scanning signal input lines, and the control circuit. Since no control circuit is provided between sub-pixel columns, and the positive projections of each control signal line, each fixed potential line, each input sub-lead, and each output sub-lead overlap with a partial area of ​​the scanning line, there is no need to provide a second light shielding portion between sub-pixel columns, thereby improving the sub-pixel aperture ratio.

[0250] In some embodiments, Fig.34 As shown, the display panel also includes:

[0251] A plurality of support portions 47 are located on a side of the common electrode layer away from the pixel electrode layer. The orthographic projection of the support portion 47 on the first substrate is located between adjacent sub-pixel rows 6 , and the control circuit is located between the sub-pixel rows where the support portions 47 are provided.

[0252] In some embodiments, Fig.34 As shown, each pixel island 5 includes: a first sub-pixel row 48, a second sub-pixel row 49 and a third sub-pixel row 50;

[0253] The first sub-pixel row 48 includes a plurality of first color sub-pixels arranged along a first direction X;

[0254] The second sub-pixel row 49 includes a plurality of second color sub-pixels arranged along the first direction X;

[0255] The third sub-pixel row 50 includes a plurality of third color sub-pixels arranged along the first direction X;

[0256] In some embodiments, Fig.34 As shown, in the second direction Y, the width of the first light shielding portion 36 covering between the first sub-pixel row 48 and the second sub-pixel row 49, and the width of the first light shielding portion 36 covering between the second sub-pixel row 49 and the third sub-pixel row 50 are both smaller than the width of the first light shielding portion 36 covering between the first sub-pixel row 48 and the third sub-pixel row 50;

[0257] The orthographic projection of the support portion 47 on the base substrate is located between the first sub-pixel row 48 and the third sub-pixel row 50 .

[0258] Correspondingly, the control circuit is arranged between the first sub-pixel row and the third sub-pixel row.

[0259] In a specific implementation, the orthographic projection of the light shielding portion on the first substrate covers the orthographic projection of the supporting portion on the first substrate and the orthographic projection of the control circuit on the first substrate. Since the supporting portion is disposed in the area where the width of the first light shielding portion is relatively wide in the second direction Y, the display panel provided by the embodiment of the present disclosure arranges the control circuit in the area of ​​the supporting portion, thereby avoiding affecting the aperture ratio of the display panel.

[0260] In some embodiments, Fig.34 As shown, the first color sub-pixel is a red sub-pixel R, the second color sub-pixel is a green sub-pixel G, and the third color sub-pixel is a blue sub-pixel B.

[0261] It should be noted that, compared with the red sub-pixels and the blue sub-pixels, the luminous efficiency of the green sub-pixels is more affected by the aperture ratio. Therefore, the display panel provided by the embodiment of the present disclosure has a first light shielding portion with a wider width in the second direction Y disposed between the red sub-pixel row and the blue sub-pixel row, which can avoid the influence of increasing the width of the first light shielding portion in the second direction Y on the green sub-pixels.

[0262] Next, taking the case where the display panel is a liquid crystal display panel and the control circuit is located between adjacent sub-pixel rows as an example, the preparation of the display panel provided by the embodiment of the present disclosure is described by way of example. The preparation method of the array substrate includes the following steps:

[0263] S101, depositing a second light shielding layer material on a first substrate, and forming a pattern of the second light shielding layer by a patterning process;

[0264] S102, depositing a buffer layer material to form a buffer layer;

[0265] S103, depositing semiconductor material, and etching to form a pattern of an active layer;

[0266] S103, depositing a gate insulating layer material to form a first gate insulating layer;

[0267] S104, depositing gate metal material, and etching to form an initial pattern of scan lines, a pattern of the control stage of the first transistor, and a pattern of the control stage of the second transistor, and performing a semiconductor self-aligned doping process to form a conductor region in the active layer; wherein each scan line in the initial pattern of scan lines is connected as one;

[0268] S105, performing an etching process on the initial pattern of the scan line, so that each scan line forms a plurality of sub-scan lines that are disconnected from each other;

[0269] S106, depositing a gate insulating layer material to form a second gate insulating layer;

[0270] S107, depositing a metal material to form a second conductive layer, and etching to form a pattern of a scan signal input line;

[0271] S108, depositing a first interlayer insulating layer material, and etching to form a via hole;

[0272] S109, depositing a metal material to form a third conductive layer, and etching to form a pattern of a data line and a first electrode of a driving transistor;

[0273] S110, depositing a planarization layer material to form a second interlayer insulating layer, and using a first etching process to form a via hole;

[0274] S111, forming a via hole by etching again;

[0275] S112, depositing a metal material to form a fourth conductive layer, and etching to form a control signal line, a fixed potential line, an input lead, an output lead, a connection pad, a pattern of a first electrode and a second electrode of the first transistor, and a pattern of a first electrode and a second electrode of the second transistor;

[0276] S113, depositing a third interlayer insulating layer material, and etching to form a via hole;

[0277] S114, depositing a metal material to form a fifth conductive layer, and etching to form a pattern of the second electrode of the driving transistor;

[0278] S115, depositing a material for a first passivation layer to form a first passivation layer, and forming a via hole by using an exposure process;

[0279] S116, depositing ITO to form a pixel electrode layer, and etching to form a pixel electrode;

[0280] S117, depositing a material for a second passivation layer to form a second passivation layer and etching to form a peripheral area via hole;

[0281] S118, depositing a metal material, and etching to form a pattern of a common electrode line;

[0282] S119, depositing ITO, and etching to form a common electrode pattern.

[0283] In some embodiments, forming the pattern of the common electrode further comprises the step of forming a protective layer. When the support portion comprises a portion disposed on one side of the array substrate, forming the protective layer further comprises the step of forming the support portion.

[0284] The present disclosure provides a display device, such as Fig.35 As shown, including:

[0285] The display panel 51 provided in the embodiment of the present disclosure;

[0286] The cylindrical lens structure 52 is located at the light-emitting side of the display panel 51; the cylindrical lens structure 52 includes a plurality of cylindrical lenses arranged in an array;

[0287] The controller (not shown) is connected to the display panel and is configured to provide a driving signal to the display panel.

[0288] In a specific implementation, during the image display process, for areas that need to be refreshed, the drive signal provided by the controller can be used to drive the control circuit to input a normal scan signal to the scan line corresponding to the pixel island. For areas that do not need to be refreshed, the drive signal provided by the controller can be used to drive the control circuit to input a fixed potential signal transmitted by the fixed potential line to the scan line corresponding to the pixel island, thereby realizing partitioned driving of the pixel island and saving power consumption of the display device.

[0289] In some embodiments, Figure 6 As shown, the display device also includes:

[0290] A light-transmitting spacer layer 53 is located between the display panel 51 and the cylindrical lens structure 52;

[0291] The flat layer 54 is located on a side of the cylindrical lens structure 52 away from the light-transmitting spacer layer 53 .

[0292] In some embodiments, when the display panel is a liquid crystal display panel, the display device further includes a backlight module located on the display panel away from the cylindrical lens structure.

[0293] In some embodiments, the display device further comprises:

[0294] Eye-tracking is used to determine the user's gaze area on the display device in real time.

[0295] In a specific implementation, the fixation area may be refreshed at a high frequency, while the non-fixation area may be refreshed at a low frequency.

[0296] In specific implementation, since the sub-pixel subdivision is performed in the pixel island (which can be used as a pixel for two-dimensional image (2D) display), the same resolution as 2D display can be maintained in the three-dimensional image (3D) display mode, and combined with eye-tracking, a multi-viewpoint display with a large viewing angle can be achieved, and a 3D display with a higher pixel density (PPI) can be achieved, with a larger amount of information, lower color crosstalk between adjacent viewpoints, and the user's dizziness when watching 3D images can be reduced, thereby improving the user experience. When the display device is provided with a cylindrical lens array, the cylindrical lens array can not only perform pixel mapping on the sub-pixels in the pixel island, but also perform light field modulation on the outgoing light of the pixel island, so that the final outgoing light of the pixel island forms multiple viewpoints, thereby realizing light field 3D display.

[0297] The display device provided in the embodiment of the present disclosure is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be described in detail here, nor should they be used as limitations on the present disclosure. The implementation of the display device can refer to the above-mentioned embodiment of the display panel, and the repeated parts will not be described in detail.

[0298] Based on the same inventive concept, the embodiment of the present disclosure also provides a method for driving a display device, such as Fig.36 As shown, including:

[0299] S201, determining in real time a gaze area and a non-gaze area of ​​a user on a display device;

[0300] S202: driving the attention area to display images at a first refresh rate, and driving the non-attention area to display images at a second refresh rate; wherein the first refresh rate is higher than the second refresh rate.

[0301] In the driving method of the display device provided in the embodiment of the present disclosure, the refresh frequency of the attention area is higher than the refresh frequency of the non-attention area, so that the refresh rate of the display device can be controlled by zone without affecting the user's normal viewing of the display screen, thereby saving power consumption of the display device.

[0302] In some embodiments, determining in real time a gaze area and a non-gaze area of ​​a user on the display device includes:

[0303] Determine the user's gaze area on the display device using an eye tracking system;

[0304] The other areas of the display device except the attention area are determined as non-attention areas.

[0305] In some embodiments, driving the attention area to display an image at a first refresh rate, and driving the non-attention area to display an image at a second refresh rate specifically includes:

[0306] Drive each sub-pixel in the focus area to refresh A times;

[0307] Driving each sub-pixel in the non-attention area to refresh B times;

[0308] Among them, A and B are positive integers, and A is greater than B.

[0309] In some embodiments, driving each sub-pixel in the focus area to refresh specifically includes:

[0310] Driving each scanning signal input line corresponding to the attention area to transmit effective level signals in sequence;

[0311] Control each control signal line to transmit a control signal, transmit the signal provided by the scan signal input line to the scan line corresponding to the attention area, and transmit the signal provided by the fixed potential line to the scan line corresponding to the non-attention area;

[0312] Driving each sub-pixel in the non-attention area to refresh, including:

[0313] Driving each scanning signal input line in the display panel to transmit effective level signals in sequence;

[0314] When scanning the sub-pixel rows corresponding to the attention area, control the control signal lines to transmit control signals, transmit the signals provided by the fixed potential lines to the scanning lines corresponding to the attention area, and transmit the signals provided by the scanning signal input lines to the scanning lines corresponding to the non-attention area.

[0315] In a specific implementation, when the control stage of the first transistor and the control stage of the second transistor are electrically connected to the same control signal line;

[0316] Controlling each control signal line to transmit a control signal, transmitting the signal provided by the scan signal input line to the scan line corresponding to the attention area, and transmitting the signal provided by the fixed potential line to the scan line corresponding to the non-attention area, specifically includes:

[0317] Drive each control signal line of the attention area to transmit a first control signal, and drive each control signal line of the non-annotation area to transmit a second control signal, so as to control the first transistor of the attention area to turn on and the second transistor to turn off, and the first transistor of the non-attention area to turn off and the second transistor to turn on, and transmit the signal provided by the scanning signal input line to the scanning line corresponding to the control area through each first transistor of the control area, and at the same time transmit the signal provided by the fixed potential line to the scanning line corresponding to the non-attention area through the second transistor of the non-attention area;

[0318] When scanning each sub-pixel row corresponding to the attention area, controlling each control signal line to transmit a control signal, transmitting the signal provided by the fixed potential line to the scanning line corresponding to the attention area, and transmitting the signal provided by the scanning signal input line to the scanning line corresponding to the non-attention area, specifically includes:

[0319] The control signal lines of the attention area are driven to transmit the second control signal, and the control signal lines of the non-annotation area are driven to transmit the first control signal, so as to control the first transistor of the attention area to be turned off and the second transistor to be turned on, and the first transistor of the non-attention area to be turned on and the second transistor to be turned off, and the signal provided by the scanning signal input line is transmitted to the scanning line corresponding to the non-control area through the first transistors of the non-control area, and at the same time, the signal provided by the fixed potential line is transmitted to the scanning line corresponding to the attention area through the second transistor of the attention area.

[0320] In a specific implementation, when the first transistor is a P-type transistor and the second transistor is an N-type transistor, the first signal is a low-level signal and the second signal is a high-level signal; when the first transistor is an N-type transistor and the second transistor is a P-type transistor, the first signal is a high-level signal and the second signal is a low-level signal.

[0321] In a specific implementation, when the control stage of the first transistor is electrically connected to the first control signal line, and the control stage of the second transistor is electrically connected to the second control signal line;

[0322] Controlling each control signal line to transmit a control signal, transmitting the signal provided by the scan signal input line to the scan line corresponding to the attention area, and transmitting the signal provided by the fixed potential line to the scan line corresponding to the non-attention area, specifically includes:

[0323] Drive each first control signal line of the attention area to transmit the first control signal and each second control signal line to transmit the second control signal, drive each first control signal line of the non-annotation area to transmit the third control signal and each second control signal line to transmit the fourth control signal, so as to control the first transistor of the attention area to turn on and the second transistor to turn off, and the first transistor of the non-attention area to turn off and the second transistor to turn on, transmit the signal provided by the scan signal input line to the scan line corresponding to the control area through each first transistor of the control area, and transmit the signal provided by the fixed potential line to the scan line corresponding to the non-attention area through the second transistor of the non-attention area;

[0324] When scanning each sub-pixel row corresponding to the attention area, controlling each control signal line to transmit a control signal, transmitting the signal provided by the fixed potential line to the scanning line corresponding to the attention area, and transmitting the signal provided by the scanning signal input line to the scanning line corresponding to the non-attention area, specifically includes:

[0325] The first control signal lines of the attention area are driven to transmit the third control signal and the second control signal lines are driven to transmit the fourth control signal. The first control signal lines of the non-annotation area are driven to transmit the first control signal and the second control signal lines are driven to transmit the second control signal, so as to control the first transistor of the attention area to be turned off and the second transistor to be turned on, and the first transistor of the non-attention area to be turned on and the second transistor to be turned off. The signal provided by the scanning signal input line is transmitted to the scanning line corresponding to the non-control area through the first transistors of the non-control area, and the signal provided by the fixed potential line is transmitted to the scanning line corresponding to the attention area through the second transistor of the attention area.

[0326] In some embodiments, when the first transistor and the second transistor are both P-type transistors, the first signal and the fourth signal are low-level signals, and the second signal and the third signal are high-level signals. When the first transistor and the second transistor are both N-type transistors, the first signal and the fourth signal are high-level signals, and the second signal and the third signal are low-level signals. When the first transistor is a P-type transistor and the second transistor is an N-type transistor, the first signal and the second signal are low-level signals, and the third signal and the fourth signal are high-level signals; when the first transistor is an N-type transistor and the second transistor is a P-type transistor, the first signal and the second signal are high-level signals, and the third signal and the fourth signal are low-level signals.

[0327] In summary, the display panel, display device and driving method thereof provided by the embodiment of the present disclosure, the display panel includes a control circuit, and a control signal line, a fixed potential line, and a scanning signal input line electrically connected to the control circuit, so that the control circuit can be used to transmit the signal provided by the scanning signal input line or the signal provided by the fixed potential line to the scanning line. That is to say, in the image display process, for the area that needs to be refreshed, the control circuit can be used to input a normal scanning signal to the scanning line corresponding to the pixel island, and for the area that does not need to be refreshed, the control circuit can be used to input a fixed potential signal transmitted by the fixed potential line to the scanning line corresponding to the pixel island. That is, the control circuit and the control signal line, the fixed potential line, and the scanning signal input line can be used to realize the partition drive of the pixel island. Thereby, the power consumption of the display product can be saved. In addition, the pixel island array is arranged, and each pixel island is electrically connected to the control circuit, and the partition control of each pixel island in the display panel can also be realized in the second direction.

[0328] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0329] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: The display panel comprises: a first substrate base plate; A plurality of scanning lines are located on one side of the first substrate, the plurality of scanning lines extend along a first direction and are arranged along a second direction; the first direction intersects the second direction; a plurality of data lines, located on the same side of the first substrate as the scan lines, the plurality of data lines extending along the second direction and arranged along the first direction; A plurality of sub-pixels are respectively located in areas divided by the plurality of scan lines and the plurality of data lines; at least two sub-pixels adjacent to each other along the first direction and the second direction constitute a pixel island; the plurality of sub-pixels constitute a plurality of pixel islands; each of the pixel islands includes n rows of sub-pixel rows in the second direction; a plurality of scanning signal input lines, corresponding one to one with the scanning lines, extending along the first direction and arranged along the second direction; a plurality of control signal lines extending along the second direction and arranged along the first direction; a plurality of fixed potential lines extending along the first direction and arranged along the second direction; A plurality of control circuits are located between the adjacent sub-pixels in the first direction; one pixel island is connected to at least n control circuits; one control circuit corresponds to a row of sub-pixels in the pixel island; The control circuit is configured to: under the control of the control signal line, transmit the signal provided by the scan signal input line to the scan line corresponding to the area where the image is displayed at a first refresh rate, and transmit the signal provided by the fixed potential line to the scan line corresponding to the area where the image is displayed at a second refresh rate; wherein the first refresh rate is higher than the second refresh rate; Wherein, the control circuit comprises: a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to one of the control signal lines, the first electrode of the first transistor is electrically connected to the scan signal input line, and the second electrode of the first transistor is electrically connected to the scan line; The control electrode of the second transistor is electrically connected to one of the control signal lines, the first electrode of the second transistor is electrically connected to the fixed potential line, and the second electrode of the second transistor is electrically connected to the scan line; The display panel specifically comprises: A first conductive layer, including the scan line, the scan signal input line, the fixed potential line, the control electrode of the first transistor and the control electrode of the second transistor; A second conductive layer, located on a side of the first conductive layer away from the first substrate, comprising the data line and the control signal line; The third conductive layer is located on a side of the second conductive layer away from the first conductive layer, and includes a first electrode and a second electrode of the first transistor and a first electrode and a second electrode of the second transistor.

2. The display panel according to claim 1, wherein: The sub-pixel includes a driving transistor; The first conductive layer further comprises: a control stage of the driving transistor electrically connected to the scanning line; The second conductive layer further includes: a first electrode of the driving transistor; The third conductive layer further includes: a second electrode of the driving transistor.

3. The display panel according to claim 2, wherein: In each of the control circuits, the first transistors and the second transistors are arranged in two rows along the first direction.

4. The display panel according to claim 3, wherein: In each of the control circuits, an orthographic projection of the control electrode of the first transistor on a plane perpendicular to the first direction and an orthographic projection of the control electrode of the second transistor on a plane perpendicular to the first direction do not overlap each other.

5. The display panel according to claim 4, wherein: The first electrode and the second electrode of the first transistor are arranged along the second direction; The first electrode and the second electrode of the second transistor are arranged along the second direction.

6. The display panel according to claim 5, wherein: The third conductive layer further includes: a first input lead, a second input lead, a first output lead and a second output lead; The first input lead is electrically connected to the first electrode of the first transistor and to the scan signal input line; The second input lead is electrically connected to the first electrode of the second transistor and to the fixed potential line; The first output lead is electrically connected to the second electrode of the first transistor and to the scan line; The second output lead is electrically connected to the second electrode of the second transistor and to the scan line; The first input lead, the second input lead, the first output lead, and the second output lead all extend along the second direction.

7. A display panel, wherein: The display panel comprises: a first substrate base plate; A plurality of scanning lines are located on one side of the first substrate, the plurality of scanning lines extend along a first direction and are arranged along a second direction; the first direction intersects the second direction; a plurality of data lines, located on the same side of the first substrate as the scan lines, the plurality of data lines extending along the second direction and arranged along the first direction; A plurality of sub-pixels are respectively located in areas divided by the plurality of scan lines and the plurality of data lines; at least two sub-pixels adjacent to each other along the first direction and the second direction constitute a pixel island; the plurality of sub-pixels constitute a plurality of pixel islands; each of the pixel islands includes n rows of sub-pixel rows in the second direction; a plurality of scanning signal input lines, corresponding one to one with the scanning lines, extending along the first direction and arranged along the second direction; a plurality of control signal lines extending along the second direction and arranged along the first direction; a plurality of fixed potential lines extending along the second direction and arranged along the first direction; A plurality of control circuits are located between the adjacent sub-pixels in the second direction; one pixel island is connected to at least n control circuits; one control circuit corresponds to a row of sub-pixels in the pixel island; The control circuit is configured to: under the control of the control signal line, transmit the signal provided by the scanning signal input line to the scanning line corresponding to the area where the image is displayed at a first refresh rate, and transmit the signal provided by the fixed potential line to the scanning line corresponding to the area where the image is displayed at a second refresh rate; wherein the first refresh rate is higher than the second refresh rate.

8. The display panel according to claim 7, wherein: The control circuit comprises: a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to one of the control signal lines, the first electrode of the first transistor is electrically connected to the scan signal input line, and the second electrode of the first transistor is electrically connected to the scan line; The control electrode of the second transistor is electrically connected to one of the control signal lines, the first electrode of the second transistor is electrically connected to the fixed potential line, and the second electrode of the second transistor is electrically connected to the scan line.

9. The display panel according to claim 8, wherein: The display panel specifically comprises: A first conductive layer, comprising the scan line, a control electrode of the first transistor and a control electrode of the second transistor; A second conductive layer, located on a side of the first conductive layer away from the first substrate, comprising the scan signal input line; a third conductive layer, located on a side of the second conductive layer away from the first conductive layer, and comprising the data line; The fourth conductive layer is located on the side of the third conductive layer away from the second conductive layer, and includes the control signal line, the fixed potential line, the first electrode and the second electrode of the first transistor, and the first electrode and the second electrode of the second transistor; the orthographic projection of the control signal line and the fixed potential line on the first substrate overlaps with a partial area of ​​the orthographic projection of the data line on the first substrate.

10. The display panel according to claim 9, wherein: The fourth conductive layer further includes: a plurality of first output leads and a plurality of second output leads extending along the second direction; The second electrode of the first transistor is electrically connected to the scan line through the first output lead; The second electrode of the second transistor is electrically connected to the scan line through the second output lead; The orthographic projections of the first output lead and the second output lead on the first base substrate overlap a portion of the orthographic projection of the data line on the first base substrate.

11. The display panel according to claim 10, wherein: The sub-pixel includes a driving transistor; The first conductive layer further comprises: a control stage of the driving transistor electrically connected to the scanning line; The second conductive layer further includes: a first electrode of the driving transistor; The display panel further includes: The fifth conductive layer is located on a side of the fourth conductive layer away from the third conductive layer, and includes a second electrode of the driving transistor.

12. The display panel according to claim 11, wherein: The control circuits corresponding to each pixel island are arranged in a row in the first direction.

13. The display panel according to claim 12, wherein: In each of the first transistors, the first electrode of the first transistor, the control stage of the first transistor, and the second electrode of the first transistor are arranged along the first direction; In each of the second transistors, the first electrode of the second transistor, the control stage of the second transistor, and the second electrode of the second transistor are arranged along the first direction.

14. The display panel according to claim 13, wherein: The display panel further includes: an active layer located between the first conductive layer and the first base substrate; the active layer includes an active layer of the first transistor and an active layer of the second transistor; The active layer of the first transistor includes a portion extending along the first direction; The active layer of the second transistor includes a portion extending along the first direction.

15. The display panel according to claim 14, wherein: The display panel further includes: a first gate insulating layer located between the first conductive layer and the active layer, a second gate insulating layer located between the first conductive layer and the second conductive layer, a first interlayer insulating layer located between the second conductive layer and the third conductive layer, a second interlayer insulating layer located between the third conductive layer and the fourth conductive layer, and a third interlayer insulating layer located between the fourth conductive layer and the fifth conductive layer; The fourth conductive layer further includes: a first input lead, a plurality of first connection pads, a plurality of second connection pads, a plurality of third connection pads, a plurality of fourth connection pads, and a plurality of fifth connection pads; The plurality of control signal lines include: a plurality of first control signal lines and a plurality of second control signal lines; The second electrode of the driving transistor is electrically connected to the active layer through a via hole penetrating the third interlayer insulating layer, the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer; The first input lead is electrically connected to the first connection pad, and the first connection pad is electrically connected to the scan signal input line through a via hole penetrating the second interlayer insulating layer and the first interlayer insulating layer; The first output lead is electrically connected to the second connection pad, and the second connection pad is electrically connected to the scan line through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer; The first control signal line is electrically connected to the third connection pad, and the third connection pad is electrically connected to the control stage of the first transistor through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer; The second control signal line is electrically connected to the fourth connection pad, and the fourth connection pad is electrically connected to the control stage of the second transistor through a via hole penetrating the second interlayer insulation layer, the first interlayer insulation layer, and the second gate insulation layer; The second output lead is electrically connected to the fifth connection pad, and the fifth connection pad is electrically connected to the scan line through a via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer, and the second gate insulating layer; In which, in the area where the second electrode of the driving transistor is electrically connected to the active layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer have a first via hole; in the area where the second connection pad is electrically connected to the scan line, the first interlayer insulating layer and the second gate insulating layer have a second via hole; in the area where the second electrode of the driving transistor is electrically connected to the active layer and in the area where the second connection pad is electrically connected to the scan line, the second interlayer insulating layer has a third via hole exposing the first via hole and the second via hole.

16. The display panel according to claim 12, wherein: The display panel further includes: a pixel electrode layer, located on a side of the fifth conductive layer away from the fourth conductive layer, comprising a plurality of pixel electrodes corresponding to the sub-pixels one by one; the pixel electrodes are electrically connected to the second electrode of the driving transistor; a common electrode layer, located at a side of the pixel electrode layer away from the fifth conductive layer; A plurality of support parts are located on a side of the common electrode layer away from the pixel electrode layer, the orthographic projections of the support parts on the first substrate are located between adjacent sub-pixel rows, and the control circuit is located between the sub-pixel rows provided with the support parts; The opposing substrate is located on the side of the supporting portion away from the common electrode layer, and includes a plurality of shading portions extending along the first direction and arranged along the second direction; the orthographic projection of the shading portion on the first substrate covers the orthographic projection of the supporting portion on the first substrate and the orthographic projection of the control circuit on the first substrate.

17. The display panel according to claim 16, wherein: Each of the pixel islands includes: a first sub-pixel row, a second sub-pixel row and a third sub-pixel row; The first sub-pixel row includes a plurality of first color sub-pixels arranged along the first direction; The second sub-pixel row includes a plurality of second color sub-pixels arranged along the first direction; The third sub-pixel row includes a plurality of third color sub-pixels arranged along the first direction; The orthographic projection of the support portion on the base substrate is located between the first sub-pixel row and the third sub-pixel row.

18. The display panel according to claim 17, wherein: The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

19. The display panel according to claim 8, wherein: The control electrode of the first transistor and the control electrode of the second transistor are electrically connected to the same control signal line; The first transistor is an N-type transistor, and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

20. The display panel according to claim 8, wherein: The control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines.

21. The display panel according to claim 7, wherein: The colors of the sub-pixels in a row arranged in the first direction are all the same.

22. The display panel according to claim 21, wherein: The plurality of pixel islands are divided into a plurality of control areas, each of the control areas including at least one pixel island; Each of the scan lines includes: a plurality of sub-scan lines arranged in the first direction and disconnected from each other; in each of the scan lines, the number of the sub-scan lines is the same as the number of a row of the control areas arranged in the first direction, and each of the sub-scan lines corresponds to a row of sub-pixels in the control area.

23. The display panel according to claim 22, wherein: In each of the control areas, a row of pixel islands arranged in the first direction is correspondingly connected to n control circuits.

24. A display device, wherein: include: The display panel according to any one of claims 1 to 23; A cylindrical lens structure, located at the light-emitting side of the display panel; The cylindrical lens structure comprises a plurality of cylindrical lenses arranged in an array; The controller is connected to the display panel and is configured to provide a driving signal to the display panel.

25. A method for driving a display device according to claim 24, wherein: The method comprises: Determine in real time the gaze area and non-gaze area of ​​the user on the display device; The attention area is driven to display images at a first refresh rate, and the non-attention area is driven to display images at a second refresh rate; wherein the first refresh rate is higher than the second refresh rate.

26. The method according to claim 25, wherein: Driving the attention area to display an image at a first refresh rate, and driving the non-attention area to display an image at a second refresh rate, specifically includes: Driving each sub-pixel in the attention area to refresh A times; Driving each sub-pixel in the non-attention area to refresh B times; Among them, A and B are positive integers, and A is greater than B.

27. The method according to claim 26, wherein: Driving each sub-pixel in the attention area to refresh specifically includes: Driving each scanning signal input line corresponding to the attention area to transmit a valid level signal in sequence; Controlling each of the control signal lines to transmit a control signal, transmitting the signal provided by the scan signal input line to the scan line corresponding to the attention area, and transmitting the signal provided by the fixed potential line to the scan line corresponding to the non-attention area; The driving each sub-pixel in the non-attention area to refresh includes: Driving each scanning signal input line in the display panel to transmit effective level signals in sequence; When scanning each sub-pixel row corresponding to the attention area, each control signal line is controlled to transmit a control signal, the signal provided by the fixed potential line is transmitted to the scanning line corresponding to the attention area, and the signal provided by the scanning signal input line is transmitted to the scanning line corresponding to the non-attention area.

Images