Display Substrate and Display Device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate includes: a substrate; a plurality of thin film transistors on the substrate, each thin film transistor including: a gate on the substrate; a gate insulating layer on a side of the gate away from the substrate; a semiconductor layer on a side of the gate insulating layer away from the gate; and a first electrode and a second electrode on a side of the semiconductor layer away from the gate insulating layer, the first electrode and the second electrode being spaced apart by a gap; wherein the gate includes an inner portion and a peripheral portion surrounding the inner portion, wherein a positive projection of the inner portion on the substrate completely overlaps a positive projection of the semiconductor layer on the substrate, the peripheral portion includes a first portion and a second portion, a positive projection of the second portion on the substrate is closer to a positive projection of an end portion of the gap on the substrate than a positive projection of the first portion on the substrate, and a width of the first portion is smaller than a width of the second portion.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Rapid prototyping technology is also known as 3D (three-dimensional) printing technology. In this technology, a physical object or physical model can be manufactured by accumulating materials through molding equipment. 3D printing technology has developed rapidly in recent years due to its advantages of greatly reducing production costs, improving the utilization rate of raw materials and energy, being customizable according to needs, and greatly saving product production time. Photopolymerization molding is the use of near-ultraviolet light to photocuring liquid photosensitive resin. One of the lower-cost implementation methods is to use a transmissive liquid crystal display as a mask that transmits ultraviolet light to make the liquid photosensitive resin sensitive to light to control 3D molding.

[0003] For 3D printing products, clients require the product's transmittance to be as high as possible. The higher the transmittance, the higher the light energy that passes through the product. Here, the light transmitted by 3D printing is used for polymerization and curing, where transmittance = light energy that passes through the product ÷ light energy emitted by the light source. On the one hand, the higher the transmittance, the more light energy that passes through, and the shorter the resin curing time. On the other hand, at the same light density per unit area, products with high transmittance can reduce the backlight power and save product power consumption. Therefore, customers usually demand products with high transmittance. The aperture ratio of the product is directly related to the transmittance. The larger the aperture ratio, the higher the transmittance. Summary of the invention

[0004] According to one aspect of an embodiment of the present disclosure, a display substrate is provided, comprising: a base substrate; a plurality of thin film transistors on the base substrate, each thin film transistor comprising: a gate on the base substrate; a gate insulating layer on a side of the gate away from the base substrate; a semiconductor layer on a side of the gate insulating layer away from the gate; and a first electrode and a second electrode on a side of the semiconductor layer away from the gate insulating layer, the first electrode and the second electrode being separated by a gap; wherein the gate comprises an inner portion and a peripheral portion surrounding the inner portion, wherein an orthographic projection of the inner portion on the base substrate completely overlaps with an orthographic projection of the semiconductor layer on the base substrate, and the peripheral portion comprises a first portion and a second portion, wherein the orthographic projection of the second portion on the base substrate is closer to an orthographic projection of an end of the gap on the base substrate than the orthographic projection of the first portion on the base substrate, and wherein a width of the first portion is smaller than a width of the second portion.

[0005] In some embodiments, a ratio of a width of the second portion to a width of the first portion is less than or equal to 2.06.

[0006] In some embodiments, the line width of the second electrode ranges from 3 micrometers to 4 micrometers; the dimension of the portion of the first electrode overlapping with the semiconductor layer along the extending direction of the first electrode ranges from 5.1 micrometers to 7.65 micrometers.

[0007] In some embodiments, the display substrate further includes: a gate line connected to the gate, and the gate line is in the same layer as the gate; wherein, the included angle formed by the extending direction of the first electrode and the extending direction of the gate line is an acute angle.

[0008] In some embodiments, the range of the acute angle is from 30° to 60°.

[0009] In some embodiments, the display substrate further includes: an organic insulating layer on a side of the plurality of thin film transistors away from the substrate, and the organic insulating layer includes a via exposing the first electrode, and a positive projection of the via on the substrate at least partially overlaps with a positive projection of the first electrode on the substrate.

[0010] In some embodiments, a positive projection of the via on the substrate is located inside a positive projection of the first electrode on the substrate, and is located between a positive projection of a portion of the first electrode on the substrate and a positive projection of the gate on the substrate; wherein, the length of the portion of the first electrode along the extending direction of the first electrode ranges from 2.4 micrometers to 3.15 micrometers.

[0011] In some embodiments, the first electrode includes a third portion and a fourth portion connected to the third portion, a positive projection of the third portion on the substrate at least partially overlaps with a positive projection of the gate on the substrate, a positive projection of the fourth portion on the substrate does not overlap with a positive projection of the gate on the substrate, and the width of the third portion in a direction perpendicular to the extending direction of the first electrode is less than the width of the fourth portion in a direction perpendicular to the extending direction of the first electrode.

[0012] In some embodiments, the width of the fourth portion in a direction perpendicular to the extending direction of the first electrode ranges from 3.3 micrometers to 3.7 micrometers.

[0013] In some embodiments, the display substrate further includes: a pixel electrode on a side of the organic insulating layer away from the plurality of thin film transistors; wherein, a positive projection of the gate line on the substrate does not overlap with a positive projection of the pixel electrode on the substrate, and a distance between an edge of the positive projection of the gate line on the substrate and an edge of a positive projection of an adjacent pixel electrode on the substrate ranges from 0.5 micrometer to 1.8 micrometers.

[0014] In some embodiments, the pixel electrode at least partially overlaps with the via hole, and the pixel electrode is electrically connected to the first electrode through the via hole.

[0015] In some embodiments, the display substrate further includes: a data line connected to the second electrode, the data line being in the same layer as the second electrode; a passivation layer on a side of the pixel electrode away from the organic insulating layer; and a common electrode on a side of the passivation layer away from the pixel electrode; wherein, the common electrode includes a plurality of sub-parts extending along an extending direction of the gate line and a plurality of strip electrodes between adjacent sub-parts, adjacent strip electrodes among the plurality of strip electrodes are spaced apart, the plurality of strip electrodes are directly connected to the adjacent sub-parts, and an extending direction of the plurality of strip electrodes is the same as an extending direction of the data line.

[0016] In some embodiments, the display substrate further includes: a black matrix on a side of the common electrode away from the passivation layer, the black matrix including a first extending part extending along an extending direction of the data line and a second extending part extending along an extending direction of the gate line; wherein, a positive projection of the data line on the substrate is located inside a positive projection of the first extending part of the black matrix on the substrate; a width of the data line in a direction perpendicular to the extending direction of the data line ranges from 2.6 micrometers to 3 micrometers; a width of the first extending part of the black matrix in a direction perpendicular to the extending direction of the data line ranges from 5 micrometers to 7 micrometers; a positive projection of the gate line on the substrate is located inside a positive projection of the second extending part of the black matrix on the substrate; a width of the gate line in a direction perpendicular to the extending direction of the gate line ranges from 2.5 micrometers to 3 micrometers; a width of the second extending part of the black matrix in a direction perpendicular to the extending direction of the gate line ranges from 6 micrometers to 10 micrometers.

[0017] In some embodiments, a positive projection of the second extending part of the black matrix on the substrate does not overlap with a positive projection of at least one end of at least some of the strip electrodes among the plurality of strip electrodes that are connected to the adjacent sub-parts on the substrate.

[0018] According to another aspect of the embodiments of the present disclosure, a display device is provided, including: the display substrate as described above.

[0019] Other features and advantages of the present disclosure will become clear from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0021] With reference to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, where:

[0022] Figure 1 is a schematic top view showing a display substrate according to an embodiment of the present disclosure;

[0023] Figure 2 is a schematic enlarged view showing a partial structure of the display substrate according to an embodiment of the present disclosure at Figure 1 the circular frame 101;

[0024] Figure 3 is a schematic cross-sectional view showing the structure of the display substrate according to an embodiment of the present disclosure taken along Figure 1 the line A-A' in;

[0025] Figure 4 is a schematic cross-sectional view showing the structure of the display substrate according to an embodiment of the present disclosure taken along Figure 1 the line B-B' in;

[0026] Figure 5 is a schematic top view showing a partial structure of the display substrate according to another embodiment of the present disclosure;

[0027] Figure 6 is a schematic top view showing a partial structure of the display substrate according to another embodiment of the present disclosure;

[0028] Figure 7 is a schematic enlarged view showing a partial structure of the display substrate according to an embodiment of the present disclosure at Figure 1 the square frame 102;

[0029] Figure 8 is a schematic cross-sectional view showing the structure taken along Figure 7 the line C-C' in;

[0030] Figure 9 is a schematic top view showing a partial structure of the display substrate according to another embodiment of the present disclosure;

[0031] Figure 10 is an enlarged schematic view showing a partial structure of a display substrate in accordance with an embodiment of the present disclosure Figure 1 in

[0032] It should be understood that the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components Detailed Description of the Invention

[0033] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and in no way limits the present disclosure or its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, the compositions of materials, numerical expressions and values set forth in these embodiments should be construed as merely exemplary and not as limitations

[0034] The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different parts. The terms such as "comprising" or "including" mean that the elements before the term cover the elements listed after the term, and do not exclude the possibility of also covering other elements. The terms such as "upper", "lower", "left", "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly

[0035] In the present disclosure, when it is described that a specific device is located between a first device and a second device, there may or may not be an intermediate device between the specific device and the first device or the second device. When it is described that a specific device is connected to other devices, the specific device may be directly connected to the other devices without an intermediate device, or may not be directly connected to the other devices but have an intermediate device

[0036] All terms used in the present disclosure (including technical terms or scientific terms) have the same meaning as understood by those of ordinary skill in the art to which the present disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary such as should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless specifically defined as such herein

[0037] Technologies, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods and devices should be regarded as part of the specification

[0038] Currently, the market demands products with high PPI (Pixels Per Inch). Therefore, it is necessary to improve the printing fineness of the products. PPI is a unit of image resolution, representing the number of pixels per inch. The higher the PPI value, the higher the density at which the display screen can display images. However, the higher the PPI, the smaller the pixel pitch. To achieve normal display of the product, there need to be light-blocking TFT (Thin Film Transistor) switches, gate traces, and data traces inside the pixels. And to prevent light leakage, BM (Black Matrix) is covered on the traces and TFTs. Therefore, in the field of LCD (Liquid Crystal Display) products, the higher the PPI of the product, the lower the pixel aperture ratio. For example, for some products, the PPI is 538 and the aperture ratio is 43.5%, while for other products, the PPI is 635 and the aperture ratio of the product may be around 40%. Therefore, in the related art, the aperture ratio of display products needs to be further improved.

[0039] In view of this, embodiments of the present disclosure provide a display substrate. By optimizing some parameters of the display substrate, the aperture ratio of the display product can be improved.

[0040] Figure 1 is a schematic top view showing a display substrate according to an embodiment of the present disclosure. Figure 2 is shown in a display substrate according to an embodiment of the present disclosure Figure 1 an enlarged schematic view of a partial structure at the circular frame 101. Figure 3 is shown in a display substrate according to an embodiment of the present disclosure along Figure 1 a cross-sectional schematic view of the structure taken along the line A - A' in. Figure 4 is shown in a display substrate according to an embodiment of the present disclosure along Figure 1 a cross-sectional schematic view of the structure taken along the line B - B' in. The following will describe in detail the structure of the display substrate according to an embodiment of the present disclosure with reference to Figures 1 to 4 in detail.

[0041] As Figure 3 and 4 shown, the display substrate includes a substrate 11 and a plurality of thin film transistors on the substrate 11.

[0042] As Figures 1 - 4As shown, the thin film transistor includes a gate 121 on a substrate 11. The thin film transistor further includes a gate insulating layer 122 on a side of the gate 121 away from the substrate 11. The gate insulating layer 122 is on the gate 121. For the convenience of showing the gate 121, Figure 1 and Figure 2 the gate insulating layer 122 is not shown in

[0043] As Figure 2 shown, the gate 121 includes an inner portion 212 and a peripheral portion 211 surrounding the inner portion 212. A positive projection of the inner portion 212 on the substrate 11 completely overlaps a positive projection of the semiconductor layer 123 on the substrate 11. Or rather, in the case of positively projecting the semiconductor layer 123 onto the gate 121, the gate 121 is divided into two parts according to the boundary of the positive projection of the semiconductor layer 123 on the gate 121. Among them, one part is the part that completely overlaps the positive projection of the semiconductor layer 123 on the gate 121, which is called the inner portion, and the other part is the part that does not overlap the positive projection of the semiconductor layer 123 on the gate 121, which is called the peripheral portion.

[0044] As Figure 2 shown, the peripheral portion 211 includes a first portion 2111 and a second portion 2112. The peripheral portion 211 is divided into two parts 2111 and 2112. Here, a positive projection of the second portion 2112 on the substrate 11 is closer to a positive projection of an end portion of the gap 160 on the substrate 11 than a positive projection of the first portion 2111 on the substrate 11. As Figure 2 shown, the first portion 2111 is the right half of the gate, and the second portion 2112 is the left half of the gate. Or rather, from a top view perspective, the first portion 2111 is the part of the peripheral portion of the gate located on the drain side (e.g., the right side) of the gap 160, and the second portion 2112 is the part of the peripheral portion of the gate located on the source side (e.g., the left side) of the gap, as Figure 2 the two parts separated by a dashed line in

[0045] In some embodiments, as Figure 2As shown, the gap 160 may include channel opening regions 221 and 222 located at the ends of the gap. During the operation of the thin film transistor, a channel that conducts the first electrode 124 and the second electrode 125 is formed in the semiconductor layer 123. The above-mentioned channel opening regions 221 and 222 are located at both ends of the channel, that is, at both ends of the gap 160.

[0046] The width W1 of the first part 2111 is smaller than the width W2 of the second part 2112. Here, both the first part and the second part are strip-shaped. The width of the first part is the dimension of the first part in the direction perpendicular to the extension direction of the first part, and the width of the second part is the dimension of the second part in the direction perpendicular to the extension direction of the second part.

[0047] In some embodiments, the ratio of the width of the second part 2112 to the width of the first part 2111 is less than or equal to 2.06.

[0048] In some embodiments, the width W1 of the first part 2111 ranges from 1.7 microns to 3 microns. For example, the width of the first part 2111 is 2 microns.

[0049] In some embodiments, the width W2 of the second part 2112 ranges from 2.5 microns to 3.5 microns. For example, the width of the second part can be the width of the vicinity part of the second part shown in Figure 2 the channel opening regions 211 and 222. For example, the width W2 of the second part 2112 is 3 microns. This can prevent the characteristics of the thin film transistor from changing due to light illumination during the use of the display product, and further prevent the problem of signal crosstalk caused by an increase in leakage current.

[0050] So far, a display substrate according to some embodiments of the present disclosure has been provided. The display substrate includes a substrate and a plurality of thin film transistors on the substrate. Each thin film transistor includes: a gate on the substrate; a gate insulating layer on the side of the gate away from the substrate; a semiconductor layer on the side of the gate insulating layer away from the gate; and a first electrode and a second electrode on the side of the semiconductor layer away from the gate insulating layer. The first electrode and the second electrode are separated by a gap. The gate includes an inner part and a peripheral part surrounding the inner part. The orthographic projection of the inner part on the substrate completely overlaps the orthographic projection of the semiconductor layer on the substrate. The peripheral part includes a first part and a second part. The orthographic projection of the second part on the substrate is closer to the orthographic projection of the end of the gap on the substrate than the orthographic projection of the first part on the substrate. The width of the first part is smaller than the width of the second part. In this embodiment, the width of the first part is smaller than the width of the second part, which reduces the area of the gate, combined with Figure 1It can be seen that the area of the pixel opening (i.e., the opening corresponding to the pixel electrode (to be described later)) of the display substrate can be made larger, thereby increasing the aperture ratio of the display substrate.

[0051] In some embodiments, as Figure 2 shown, the second electrode 125 and the first electrode 124 are in a line shape.

[0052] In some embodiments, as Figure 2 shown, the line width W3 of the second electrode 125 ranges from 3 micrometers to 4 micrometers. Here, the line width of the second electrode 125 is the dimension of the second electrode in the direction perpendicular to the extension direction of the second electrode. For example, the line width of the second electrode is 3.5 micrometers. Here, the width of the second electrode is optimized so that it is smaller than the width of the second electrode in the related art, thereby reducing the size of the thin film transistor and further increasing the aperture ratio of the display substrate.

[0053] In some embodiments, as Figure 2 shown, the dimension L1 of the overlapping portion of the first electrode 124 with the semiconductor layer 123 along the extension direction of the first electrode 124 ranges from 5.1 micrometers to 7.65 micrometers. For example, this dimension L1 can be 5.3 micrometers. This dimension range can reduce the size of the thin film transistor as much as possible while ensuring the overlap of the first electrode and the semiconductor layer, and further increase the aperture ratio of the display substrate.

[0054] Figure 5 is a schematic top view showing a partial structure of a display substrate according to another embodiment of the present disclosure.

[0055] Similar to Figure 2 Figure 5 Figure 5 shows the gate 121', the semiconductor layer 123', the first electrode 124' and the second electrode 125'. There is a gap 160' between the first electrode 124' and the second electrode 125'. For the convenience of showing the gate, Figure 5 the gate insulating layer is not shown in Figure 5 Similar to Figure 5 shown, the gate 121' includes an internal portion 212' and a peripheral portion 211' surrounding the internal portion 212'. The orthographic projection of the internal portion 212' on the substrate (

[0056] not shown in Figure 5As shown, the peripheral portion 211' includes a first portion 2111' and a second portion 2112'. Here, the orthographic projection of the second portion 2112' on the substrate is closer to the orthographic projection of the gap 160' on the substrate than the orthographic projection of the first portion 2111' on the substrate. The first portion 2111' includes a first sub-portion 21111' and a second sub-portion 21112', and the second portion 2112' includes a third sub-portion 21121' and a fourth sub-portion 21122'.

[0057] The width of the first portion 2111' is less than the width of the second portion 2112'. For example, the width W11' of the first sub-portion 21111' is 2 micrometers, the width W12' of the second sub-portion 21112' is 1.7 micrometers, the width W21' of the third sub-portion 21121' is 3 micrometers, and the width W22' of the fourth sub-portion 21122' is 3 micrometers. Such a design can reduce the size of the thin-film transistor, thereby increasing the aperture ratio of the display substrate.

[0058] For example, as Figure 5 shown, the diagonal dimension L1' of the overlapping portion of the first electrode 124' and the semiconductor layer 123' is 6.25 micrometers. This can reduce the size of the thin-film transistor as much as possible while ensuring the overlap of the first electrode and the semiconductor layer as much as possible, thereby increasing the aperture ratio of the display substrate.

[0059] In some embodiments, as Figure 5 shown, the second electrode 125' is in a line shape. The line width of the second electrode 125' ranges from 3 micrometers to 4 micrometers. The second electrode 125' includes: a first portion extending along a direction parallel to the extension direction of the data line (to be described later), a second portion adjacent to the first portion, and a third portion extending along a direction parallel to the extension direction of the gate line (to be described later). As Figure 5As shown, the second part of the second electrode 125' is the connecting part between the first part and the third part of the second electrode 125'. The width W31' of the first part of the second electrode 125' is the dimension of the first part of the second electrode 125' in the direction perpendicular to the extending direction of the data line. For example, the width W31' of the first part of the second electrode 125' is 3.5 micrometers. The width W32' of the second part of the second electrode 125' is the dimension of the second part of the second electrode 125' in the direction perpendicular to the extending direction of the second part. For example, the width W32' of the second part of the second electrode 125' is 3.5 micrometers. The width W33' of the third part of the second electrode 125' is the dimension of the third part of the second electrode 125' in the direction perpendicular to the extending direction of the gate line. For example, the width W33' of the third part of the second electrode 125' is 3.5 micrometers. The above design of the second electrode can reduce the size of the thin film transistor, and further improve the aperture ratio of the display substrate.

[0060] Figure 6 is a schematic top view showing a partial structure of a display substrate according to another embodiment of the present disclosure.

[0061] is similar to Figure 2 Similarly, Figure 6 shows the gate 121", the semiconductor layer 123", the first electrode 124" and the second electrode 125". There is a gap 160" between the first electrode 124" and the second electrode 125". For the convenience of showing the gate, Figure 5 the gate insulating layer is not shown in Figure 6 Similarly, as shown in Figure 6 the gate 121" includes an inner part 212" and a peripheral part 211" surrounding the inner part 212". The orthographic projection of the inner part 212" on the substrate substrate (

[0062] not shown in Figure 6 completely overlaps with the orthographic projection of the semiconductor layer 123" on the substrate substrate.

[0063] The width of the first part 2111" is less than the width of the second part 2112". For example, the width W11" of the first sub - part 21111" is 2 microns, the width W12" of the second sub - part 21112" is 1.7 microns, the width W13" of the third sub - part 21113" is 1.75 microns, the width W21" of the fourth sub - part 21121" is 3 microns, and the width W22" of the fifth sub - part 21122" is 3 microns. Such a design can reduce the size of the thin - film transistor, thereby increasing the aperture ratio of the display substrate.

[0064] For example, as Figure 6 shown, the diagonal dimension L1" of the overlapping portion of the first electrode 124" and the semiconductor layer 123" is 6.2 microns. This can reduce the size of the thin - film transistor as much as possible while ensuring the overlap of the first electrode and the semiconductor layer as much as possible, thereby increasing the aperture ratio of the display substrate.

[0065] In some embodiments, as Figure 6 shown, the second electrode 125" is in a line shape. The line width of the second electrode 125" ranges from 3 microns to 4 microns. For example, the second electrode 125" includes: a first part extending along a direction parallel to the extension direction of the data line (to be described later) and a second part extending along a direction parallel to the extension direction of the gate line (to be described later). The width W31" of the first part of the second electrode 125" is the dimension of the first part of the second electrode in a direction perpendicular to the extension direction of the data line. For example, the width W31" of the first part of the second electrode 125" is 3.5 microns. The width W32" of the second part of the second electrode 125" is the dimension of the second part of the second electrode in a direction perpendicular to the extension direction of the gate line. For example, the width W32" of the second part of the second electrode 125" is 3.5 microns. The above design of the second electrode can reduce the size of the thin - film transistor, thereby increasing the aperture ratio of the display substrate.

[0066] Figure 7 is an enlarged schematic diagram showing a partial structure of the display substrate at Figure 1 box 102 according to an embodiment of the present disclosure. It should be noted that the Figure 7 does not show the black matrix.

[0067] As Figure 7As shown, the display substrate further includes a gate line 310 connected to the gate 121. The gate line 310 and the gate 121 are on the same layer. For example, both the gate line 310 and the gate 121 are located on the substrate 11. For example, the gate line and the gate are made of the same material. The gate line and the gate can be formed by the same lithography process. As described above, the first electrode 124 is in a line shape. The included angle α formed by the extending direction of the first electrode 124 and the extending direction of the gate line 310 is an acute angle. In some embodiments, the range of the acute angle α is from 30° to 60°. For example, the acute angle α can be 45°. Here, by designing the included angle formed by the extending direction of the first electrode 124 and the extending direction of the gate line 310 as an acute angle, that is, designing the first electrode not to be horizontally or vertically arranged, it is convenient to make the first electrode overlap with the via hole (to be described later) of the organic insulating layer while reducing the size of the thin film transistor, thus not affecting the performance of the display substrate.

[0068] Back to Figure 3 and Figure 4 , in some embodiments, the display substrate further includes an organic insulating layer 131 on the side of the plurality of thin film transistors away from the substrate 11. For example, the material of the organic insulating layer includes resin, etc. The organic insulating layer can reduce the load effect of the display panel. The organic insulating layer 131 includes a via hole 140 exposing the first electrode 124 (as Figure 7 shown). For the convenience of illustration, Figure 7 the contour of the via hole 140 is shown in Figure 7 without showing the organic insulating layer. As

[0069] shown, the orthographic projection of the via hole 140 on the substrate 11 and the orthographic projection of the first electrode 124 on the substrate 11 at least partially overlap. The via hole can electrically connect the pixel electrode (to be described later) to the first electrode 124.

[0069] In some embodiments, as Figure 7 shown, the orthographic projection of the via hole 140 on the substrate 11 is located inside the orthographic projection of the first electrode 124 on the substrate 11, and is located between the orthographic projection of a part of the first electrode 124 on the substrate 11 and the orthographic projection of the gate 121 on the substrate 11. Here, the length L2 of the part of the first electrode 124 along the extending direction of the first electrode 124 is from 2.4 micrometers to 3.15 micrometers. Here, the length L2 is the distance from the end of the part of the first electrode 124 away from the via hole 140 to the nearest edge to the via hole 140. This can ensure that the orthographic projection of the first electrode completely wraps the orthographic projection of the via hole, so that the first electrode and the via hole are fully overlapped.

[0070] It should be noted that in the process of manufacturing the display substrate, in order to make the length L2 of the part of the first electrode 124 satisfy 2.4 microns to 3.15 microns, the corresponding dimension of the mask used can be slightly larger, for example, it can be 4.75 microns. This can ensure that the first electrode and the via can still be fully overlapped considering the process alignment and line width fluctuation.

[0071] In some embodiments, the above-mentioned via 140 can be arranged in a manner parallel to the first electrode 124 (the extension direction of the front projection of the first via 140 is parallel to the extension direction of the front projection of the first electrode 124) to minimize the area of the first electrode as much as possible.

[0072] In some embodiments, as Figure 7 shown, the first electrode 124 includes a third part 1241 and a fourth part 1242 connected to the third part 1241. The front projection of the third part 1241 on the substrate 11 at least partially overlaps with the front projection of the gate 121 on the substrate 11. The front projection of the fourth part 1242 on the substrate 11 does not overlap with the front projection of the gate 121 on the substrate 11. The width W4 of the third part 1241 in the direction perpendicular to the extension direction of the first electrode 124 is smaller than the width W5 of the fourth part 1242 in the direction perpendicular to the extension direction of the first electrode 124. This can reduce the facing area between the first electrode and the gate, thereby reducing the parasitic capacitance formed between the first electrode and the gate.

[0073] In some embodiments, the width W5 of the fourth part 1242 in the direction perpendicular to the extension direction of the first electrode 124 is 3.3 microns to 3.7 microns. This can make the overlapping area between the via 140 and the first electrode 124 relatively large.

[0074] In some embodiments, the first electrode 124 further includes a connecting portion 1243 between the third part 1241 and the fourth part 1242, and the width of this connecting portion 1243 gradually becomes wider along the direction from the third part 1241 to the fourth part 1242. This can make the first electrode gradually transition from its third part to its fourth part. The width of the connecting portion 1243 indicates the dimension of this connecting portion in the direction perpendicular to the extension direction of the first electrode 124.

[0075] In addition, as Figure 4 shown, a part of the connecting portion 1243 (i.e., the part close to the third part 1241) has a front projection on the substrate that overlaps with the front projection of the gate 121 on the substrate, and another part of the connecting portion 1243 (i.e., the part close to the fourth part 1242) has a front projection on the substrate that does not overlap with the front projection of the gate 121 on the substrate.

[0076] In some embodiments, such as Figure 3 shown, the display substrate may further include a buffer layer 132 covering the semiconductor layer 123, the first electrode 124, and the second electrode 125. The organic insulating layer 131 is on the buffer layer 132. That is, the buffer layer 132 is located between the organic insulating layer 131 and the semiconductor layer 123, the first electrode 124, and the second electrode 125. For example, the material of the buffer layer 132 includes inorganic insulating materials such as silicon oxide or silicon nitride.

[0077] In some embodiments, such as Figure 4 and Figure 7 shown, the display substrate further includes a pixel electrode 133 on a side of the organic insulating layer 131 away from the plurality of thin film transistors. Figure 7 The edge 1331 of the pixel electrode 133 is shown in Figure 7 shown. As Figure 7 shown, the orthographic projection of the gate line 310 on the substrate 11 does not overlap with the orthographic projection of the pixel electrode 133 on the substrate 11, and the distance d1 between the edge of the orthographic projection of the gate line 310 on the substrate 11 and the edge of the orthographic projection of the adjacent pixel electrode 133 on the substrate 11 ranges from 0.5 micrometer to 1.8 micrometers. Here, the overlapping area between the pixel electrode and the via 140 can be made relatively large.

[0078] For example, when the above distance d1 is changed from 3 micrometers in the related art to 1.8 micrometers, the overlapping distance between the pixel electrode and the via can be changed from 2.75 micrometers to 3.95 micrometers, thereby increasing the overlapping area between the pixel electrode and the via and avoiding the problem of placing the via inside the pixel to occupy the pixel opening area in order to ensure a large enough overlapping area between the pixel electrode and the via.

[0079] In some embodiments, the distance between the gate line and an adjacent pixel electrode is equal to the distance between the gate line and another adjacent pixel electrode. From a top view perspective, the one pixel electrode and the other pixel electrode are respectively located on both sides of the gate line.

[0080] In the above embodiments, such as Figure 7 shown, the overlapping distance between the pixel electrode and the via is the dimension d3 of the overlapping portion of the orthographic projection of the pixel electrode 133 on the substrate and the orthographic projection of the via 140 on the substrate. The dimension is the dimension of the overlapping portion along the extension direction of the first electrode 124. In some embodiments, the dimension d3 is from 3.3 micrometers to 5 micrometers. That is, the overlapping distance between the pixel electrode and the via is from 3.3 micrometers to 5.0 micrometers, such as 3.95 micrometers. This can make the overlapping area between the pixel electrode and the via relatively large.

[0081] In some embodiments, the distance d2 between the orthographic projection of the via 140 on the substrate and the orthographic projection of the semiconductor layer 123 on the substrate is 3.1 micrometers to 4 micrometers. This minimizes the area of the semiconductor layer, thereby achieving the purpose of keeping the via as far away from the interior of the pixel as possible. Since placing the via at a position far from the boundary of the semiconductor layer can avoid affecting the characteristics of the thin-film transistor, reducing the area of the semiconductor layer can keep the via as far away from the interior of the pixel as possible, which is beneficial to increasing the aperture ratio of the display substrate.

[0082] In addition, in the previous embodiments, by making the width of the first part of the peripheral portion of the gate smaller than the width of the second part, the area of the gate is reduced. This can correspondingly increase the area of the pixel electrode, and expand the boundary of the pixel electrode as far as possible towards the periphery of the pixel to ensure that the overlapping area between the via of the organic insulating layer and the pixel electrode is as large as possible, avoiding the problem of moving the via of the organic insulating layer towards the interior of the pixel to affect the aperture ratio in order to ensure a large enough overlapping area between the pixel electrode and the via.

[0083] Figure 8 is a schematic cross-sectional view showing the structure taken along the Figure 7 line C-C' in. It should be noted that for the convenience of illustration, Figure 8 only the first electrode 124, the buffer layer 132, the organic insulating layer 131, the via 140, and the pixel electrode 133 are shown. The via 140 includes a conductive material layer 141 (such as a metal). For example, the material of the conductive material layer is the same as that of the pixel electrode.

[0084] As Figure 7 and Figure 8 shown, the pixel electrode 133 at least partially overlaps with the via 140, and the pixel electrode 133 is electrically connected to the first electrode 124 through the via 140 (such as the conductive material layer 141 in the via 140).

[0085] In some embodiments, as Figure 7 shown, the display substrate further includes a data line 320 connected to the second electrode 125. The data line 320 and the second electrode 125 are in the same layer. For example, the data line and the second electrode 125 are made of the same material. The data line 320 and the second electrode 125 can be formed by the same lithography process.

[0086] In some embodiments, as Figure 4 and Figure 7 shown, the display substrate further includes a passivation layer 134 on the side of the pixel electrode 133 away from the organic insulating layer 131. For example, the material of the passivation layer 134 includes an inorganic insulating material such as silicon oxide or silicon nitride.

[0087] In some embodiments, as Figure 4And Figure 7 As shown, the display substrate further includes a common electrode 135 on a side of the passivation layer 134 away from the pixel electrode 133. Figure 7 The edge 1351 of the common electrode 135 is also shown.

[0088] Figure 9 is a schematic top view showing a partial structure of a display substrate according to another embodiment of the present disclosure.

[0089] Figure 9 The gate 121d, the semiconductor layer 123d, the first electrode 124d, the second electrode 125d, and the via 140d are shown. As Figure 9 shown, the first electrode 124d includes a first sub - part 1241d, a second sub - part 1242d, and a third sub - part 1243d. The orthographic projection of the first sub - part 1241d of the first electrode 124d on the substrate overlaps with the orthographic projection of the gate 121d on the substrate. The orthographic projection of the second sub - part 1242d of the first electrode 124d on the substrate does not overlap with the orthographic projection of the gate 121d on the substrate. The third sub - part 1243d is connected between the first sub - part 1241d and the second sub - part 1242d. As Figure 9 shown, the width of the third sub - part 1243d in a direction perpendicular to the extending direction of the first electrode 124d is smaller than the width of the second sub - part 1242d in a direction perpendicular to the extending direction of the first electrode 124d, and the width of the first sub - part 1241d in a direction perpendicular to the extending direction of the first electrode 124d is smaller than the width of the second sub - part 1242d in a direction perpendicular to the extending direction of the first electrode 124d. This can not only ensure a relatively large overlapping area between the second sub - part 1242d of the first electrode 124d and the via 140, but also make the parasitic capacitance formed by the first sub - part 1241d of the first electrode 124d and the gate 121 relatively small, thereby improving the performance of the display substrate.

[0090] Figure 10 is an enlarged schematic view showing a partial structure of the Figure 1 display substrate in.

[0091] As Figure 7 And Figure 10 shown, the common electrode 135 includes a plurality of sub - parts 1355 extending along the extending direction of the gate line and a plurality of strip - shaped electrodes 1356 between adjacent sub - parts 1355. Adjacent strip - shaped electrodes among the plurality of strip - shaped electrodes 1356 are spaced apart. The plurality of strip - shaped electrodes 1356 are directly connected to adjacent sub - parts 1355, and the extending direction of the plurality of strip - shaped electrodes 1356 is the same as the extending direction of the data line 320. That is, the corner portions of the strip - shaped electrodes are removed.

[0092] In some embodiments, the common electrode 135 further includes: an inclined portion between the strip-shaped electrode and a sub-portion extending along the extending direction of the gate line.

[0093] In some embodiments, as Figure 4 and Figure 10 shown, the display substrate further includes a black matrix 136 on a side of the common electrode 135 away from the passivation layer 134. The black matrix 136 includes a first extending portion 1361 extending along the extending direction of the data line 320 and a second extending portion 1362 extending along the extending direction of the gate line 310. The black matrix 136 may further include an intersecting portion 1363 connecting the first extending portion 1361 and the second extending portion 1362.

[0094] As Figure 10 shown, the orthographic projection of the data line 320 on the substrate is located inside the orthographic projection of the first extending portion 1361 of the black matrix 136 on the substrate.

[0095] In some embodiments, the width W61 of the data line 320 in a direction perpendicular to the extending direction of the data line ranges from 2.6 micrometers to 3 micrometers. The width W62 of the first extending portion 1361 of the black matrix 136 in a direction perpendicular to the extending direction of the data line ranges from 5 micrometers to 7 micrometers. For example, the width of the first extending portion 1361 is 6 micrometers. In this way, while ensuring that the black matrix completely blocks the data line, the blocking area of the black matrix is reduced, thereby increasing the aperture ratio of the display substrate.

[0096] As Figure 10 shown, the orthographic projection of the gate line 310 on the substrate is located inside the orthographic projection of the second extending portion 1362 of the black matrix 136 on the substrate.

[0097] In some embodiments, the width W71 of the gate line 310 in a direction perpendicular to the extending direction of the gate line ranges from 2.5 micrometers to 3 micrometers. The width W72 of the second extending portion 1362 of the black matrix 136 in a direction perpendicular to the extending direction of the gate line ranges from 6 micrometers to 10 micrometers. For example, the width of the second extending portion 1362 is 8 micrometers. In this way, while ensuring that the black matrix can completely block the gate line, the blocking area of the black matrix is reduced, thereby increasing the aperture ratio of the display substrate.

[0098] In some embodiments, the orthographic projection of the second extending portion 1362 of the black matrix 136 on the substrate does not overlap with the orthographic projection of at least one end portion of at least a part of the strip-shaped electrodes 1356 connected to the adjacent sub-portions on the substrate, as Figure 10as shown at the square 402 in Figure 10 As shown, the orthographic projection of the upper end of a strip-shaped electrode may overlap with the orthographic projection of the second extension part 1362 of the black matrix 136, while the orthographic projection of the lower end of the strip-shaped electrode may not overlap with the orthographic projection of the second extension part 1362 of the black matrix 136. For another example, the orthographic projection of the upper end of another strip-shaped electrode may not overlap with the orthographic projection of the second extension part 1362 of the black matrix 136, while the lower end of the other strip-shaped electrode may overlap with the orthographic projection of the second extension part 1362 of the black matrix 136. As described above, the corner part of the strip-shaped electrode is removed. In this embodiment, by removing the corner part of the strip-shaped electrode in the related art and making the orthographic projection of the second extension part of the black matrix not overlap with the orthographic projection of at least one end of the partial strip-shaped electrode, the width W72 of the second extension part of the black matrix in the direction perpendicular to the extending direction of the gate line can be minimized as much as possible while ensuring the light effect design of the display substrate, thereby increasing the aperture ratio of the display substrate.

[0099] In some embodiments, as Figure 10 shown, the distances d4 and d5 between the edge of the orthographic projection of the via hole 140 on the substrate and the edge of the orthographic projection of the black matrix on the substrate are both 5.25 micrometers to 6 micrometers. For example, the distances d4 and d5 can be 5.5 micrometers.

[0100] In the display substrate of the embodiments of the present disclosure, by optimizing various line widths and other width, distance, and / or length parameters of the thin-film transistor, the size of the thin-film transistor of the product is minimized while ensuring that the characteristics of the thin-film transistor are not affected, and the size parameters related to the via hole are optimized while ensuring that the overlapping area between the via hole of the organic insulating layer and other structural layers is relatively large, so that the via hole is as far away from the inside of the pixel as possible, improving the aperture ratio of the pixel. In addition, the line width of the black matrix is optimized to further improve the aperture ratio. In this way, the aperture ratio of the display product can be maximally improved. For example, adopting the thin-film transistor design and the via hole position of the above solution of the present disclosure can increase the aperture ratio of the display substrate from 50% in the related art to 57.4%.

[0101] In some embodiments of the present disclosure, a display device is further provided. The display device includes the display substrate as described above. For example, the display device can be: a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function.

[0102] Thus far, the embodiments of the present disclosure have been described in detail. To avoid obscuring the concept of the present disclosure, some details well known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0103] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present disclosure. Those skilled in the art should understand that the above embodiments can be modified or some technical features can be equivalently replaced without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A display substrate, comprising: A substrate substrate; A plurality of thin film transistors on the substrate substrate, each thin film transistor comprising: A gate on the substrate substrate; A gate insulating layer on a side of the gate away from the substrate substrate; A semiconductor layer on a side of the gate insulating layer away from the gate; and A first electrode and a second electrode on a side of the semiconductor layer away from the gate insulating layer, the first electrode and the second electrode being spaced apart by a gap; An organic insulating layer on a side of the plurality of thin film transistors away from the substrate substrate; A pixel electrode on a side of the organic insulating layer away from the plurality of thin film transistors; A passivation layer on a side of the pixel electrode away from the organic insulating layer; and A common electrode on a side of the passivation layer away from the pixel electrode; A gate line connected to the gate, the gate line being in the same layer as the gate; A data line connected to the second electrode; and A black matrix on a side of the common electrode away from the passivation layer, the black matrix comprising a first extension portion extending along an extending direction of the data line and a second extension portion extending along an extending direction of the gate line; Wherein, the gate comprises an inner portion and a peripheral portion surrounding the inner portion, wherein, a positive projection of the inner portion on the substrate substrate completely overlaps with a positive projection of the semiconductor layer on the substrate substrate, the peripheral portion comprises a first portion and a second portion, wherein, a positive projection of the second portion on the substrate substrate is closer to a positive projection of an end portion of the gap on the substrate substrate than a positive projection of the first portion on the substrate substrate, and a width of the first portion is smaller than a width of the second portion; An included angle formed by an extending direction of the first electrode and an extending direction of the gate line is an acute angle; The organic insulating layer comprises a via exposing the first electrode, and a positive projection of the via on the substrate substrate at least partially overlaps with a positive projection of the first electrode on the substrate substrate; A positive projection of the data line on the substrate substrate is located inside a positive projection of the first extension portion of the black matrix on the substrate substrate; a width of the data line in a direction perpendicular to an extending direction of the data line ranges from 2.6 micrometers to 3 micrometers; a width of the first extension portion of the black matrix in a direction perpendicular to the extending direction of the data line ranges from 5 micrometers to 7 micrometers; A positive projection of the gate line on the substrate substrate is located inside a positive projection of the second extension portion of the black matrix on the substrate substrate; a width of the gate line in a direction perpendicular to an extending direction of the gate line ranges from 2.5 micrometers to 3 micrometers; a width of the second extension portion of the black matrix in a direction perpendicular to the extending direction of the gate line ranges from 6 micrometers to 10 micrometers.

2. The display substrate according to claim 1, wherein, A ratio of a width of the second portion to a width of the first portion is less than or equal to 2.

06.

3. The display substrate according to claim 1, wherein, The line width of the second electrode ranges from 3 microns to 4 microns; The size of the portion of the first electrode overlapping with the semiconductor layer in the extending direction of the first electrode ranges from 5.1 microns to 7.65 microns.

4. The display substrate according to claim 1, wherein, The range of the acute angle is from 30° to 60°.

5. The display substrate according to claim 1, wherein, The orthographic projection of the via hole on the substrate is located inside the orthographic projection of the first electrode on the substrate, and is located between the orthographic projection of a part of the first electrode on the substrate and the orthographic projection of the gate on the substrate; Wherein, the length of the part of the first electrode in the extending direction of the first electrode is from 2.4 microns to 3.15 microns.

6. The display substrate according to claim 1, wherein, The first electrode includes a third part and a fourth part connected to the third part. The orthographic projection of the third part on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate, and the orthographic projection of the fourth part on the substrate does not overlap with the orthographic projection of the gate on the substrate. The width of the third part in the direction perpendicular to the extending direction of the first electrode is less than the width of the fourth part in the direction perpendicular to the extending direction of the first electrode.

7. The display substrate according to claim 6, wherein, The width of the fourth part in the direction perpendicular to the extending direction of the first electrode is from 3.3 microns to 3.7 microns.

8. The display substrate according to claim 1, wherein, The orthographic projection of the gate line on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate, and the distance between the edge of the orthographic projection of the gate line on the substrate and the edge of the orthographic projection of the adjacent pixel electrode on the substrate ranges from 0.5 microns to 1.8 microns.

9. The display substrate according to claim 1, wherein, The pixel electrode at least partially overlaps with the via hole, and the pixel electrode is electrically connected to the first electrode through the via hole.

10. The display substrate according to claim 1, wherein, The data line and the second electrode are on the same layer; The common electrode includes a plurality of sub-parts extending along the extending direction of the gate line and a plurality of strip electrodes between adjacent sub-parts. The adjacent strip electrodes among the plurality of strip electrodes are spaced apart. The plurality of strip electrodes are directly connected to the adjacent sub-parts, and the extending direction of the plurality of strip electrodes is the same as the extending direction of the data line.

11. The display substrate according to claim 10, wherein, The orthographic projection of the second extending part of the black matrix on the substrate does not overlap with the orthographic projection of at least one end of at least a part of the strip electrodes among the plurality of strip electrodes connected to the adjacent sub-parts on the substrate.

12. A display device, comprising: The display substrate according to any one of claims 1 to 11.

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