Method for manufacturing a mems device and a mems wafer

Abstract

Embodiments of the present application relate to a preparation method of a MEMS device and a MEMS wafer, wherein the method comprises: providing a first wafer, the first wafer being provided with a first alignment mark and a first bonding mark on a bonding surface thereof; providing a second wafer; forming a second alignment mark and a second bonding mark on a bonding surface of the second wafer; the second alignment mark extending from the bonding surface of the second wafer to an inner portion of the second wafer, the second alignment mark having a first end on the bonding surface of the second wafer and a second end in the inner portion of the second wafer; bonding the second wafer on the first wafer in such a manner that the bonding surface of the first wafer faces the bonding surface of the second wafer and the first bonding mark and the second bonding mark are aligned with each other; and removing part of the second wafer to expose the second end of the second alignment mark. Thus, the loss of effective area on the wafer is avoided, the shadow problem is avoided, and the number of actual effective dies on the wafer is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a MEMS device and a MEMS wafer. Background Technology

[0002] MEMS devices are devices fabricated using Micro-Electro-Mechanical Systems (MEMS) technology, with internal structures typically on the micrometer or even nanometer scale. Common MEMS devices include MEMS accelerometers, MEMS microphones, micromotors, micropumps, microoscillators, MEMS optical sensors, MEMS pressure sensors, MEMS gyroscopes, MEMS humidity sensors, MEMS gas sensors, and their integrated products. MEMS devices offer advantages such as small size, low cost, high reliability, strong resistance to harsh environments, low power consumption, high level of intelligence, ease of calibration, and ease of integration, making them widely used in consumer electronics products.

[0003] Wafer-level bonding is a crucial process step in the fabrication of MEMS devices. MEMS devices, especially MEMS inertial products, typically consist of a device wafer and a cover wafer. After bonding, these two wafers form a cavity; therefore, the bonding of these two wafers can also be called cavity bonding. After wafer bonding, the patterned functional layers and various markings on the device wafer are covered by the cover wafer. The alignment equipment cannot directly locate the previous alignment mark. Typically, blind exposure followed by etching a large pit is required to expose the previous alignment mark on the device wafer before proceeding with subsequent photolithography processes. Due to the blind exposure, the opening size is generally large, resulting in a loss of wafer area. Furthermore, the depth of the pit can easily create shadows during subsequent photoresist coating, reducing the number of usable dies and affecting the product's appearance. Summary of the Invention

[0004] In view of this, the present application provides a method for fabricating a MEMS device and a MEMS wafer to solve at least one problem existing in the background art.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a MEMS device, the method comprising:

[0006] A first wafer is provided, wherein a first alignment mark and a first bonding mark are formed on the bonding surface of the first wafer;

[0007] Provide a second wafer;

[0008] A second alignment mark and a second bonding mark are formed on the bonding surface of the second wafer; wherein the positional relationship between the second alignment mark and the second bonding mark is the same as the positional relationship between the first alignment mark and the first bonding mark; the second alignment mark extends from the bonding surface of the second wafer to the interior of the second wafer, and the second alignment mark has a first end located on the bonding surface of the second wafer and a second end located inside the second wafer;

[0009] The second wafer is bonded to the first wafer with the bonding surface of the first wafer facing the bonding surface of the second wafer and the first bonding mark and the second bonding mark aligned with each other.

[0010] Remove a portion of the second wafer to expose the second end of the second alignment mark.

[0011] In conjunction with the first aspect of this application, in an optional embodiment, the second wafer includes a substrate layer, an intermediate dielectric layer, and a top semiconductor layer, wherein the bonding surface of the second wafer is the surface of the top semiconductor layer away from the intermediate dielectric layer;

[0012] The step of forming a second alignment mark on the bonding surface of the second wafer includes: forming a second alignment mark extending to the intermediate dielectric layer on the bonding surface of the second wafer;

[0013] The removal of a portion of the second wafer includes: removing the substrate layer and the intermediate dielectric layer.

[0014] In conjunction with the first aspect of this application, in an optional embodiment, forming the second alignment mark and the second bonding mark on the bonding surface of the second wafer includes:

[0015] A second bonding mark and a third alignment mark are formed on the bonding surface of the second wafer;

[0016] The second alignment mark is formed based on the position of the third alignment mark.

[0017] In conjunction with a first aspect of this application, in an alternative embodiment, the second alignment mark is formed in the scribbling area.

[0018] In conjunction with the first aspect of this application, in an optional embodiment, the method further includes:

[0019] Using the second end of the second alignment mark as a photolithographic alignment mark, a pattern is formed on the second wafer.

[0020] In conjunction with a first aspect of this application, in an alternative embodiment, the MEMS device includes a MEMS inertial sensor;

[0021] The process of forming a pattern on the second wafer includes forming a comb pattern and / or a mass block pattern on the second wafer.

[0022] In conjunction with the first aspect of this application, in an optional embodiment, the method further includes:

[0023] An overlay measurement mark is formed on the bonding surface of the second wafer. The overlay measurement mark extends from the bonding surface of the second wafer to the interior of the second wafer. The overlay measurement mark has a third end located on the bonding surface of the second wafer and a fourth end located inside the second wafer.

[0024] The removal of a portion of the second wafer also exposes the fourth end of the overlay measurement mark.

[0025] Secondly, embodiments of this application provide a MEMS wafer, comprising: a first wafer and a second wafer bonded together; wherein...

[0026] A first alignment mark and a first bonding mark are formed on the first wafer;

[0027] A second alignment mark and a second bonding mark are formed on the second wafer;

[0028] The first bonding mark and the second bonding mark are aligned with each other, and the first alignment mark and the second alignment mark are aligned with each other;

[0029] The second alignment mark extends through the second wafer.

[0030] In conjunction with a second aspect of this application, in an alternative embodiment, the second alignment mark is formed within the scribbling lane area.

[0031] In conjunction with a second aspect of this application, in an optional embodiment, an overlay measurement mark is further formed on the second wafer, the overlay measurement mark penetrating the second wafer.

[0032] The MEMS device fabrication method and MEMS wafer provided in this application embodiment take into account that the first alignment mark and the second alignment mark will be aligned with each other when the first wafer and the second wafer are bonded. Therefore, by utilizing the positional relationship between the first alignment mark and the first bonding mark, a second alignment mark is formed at the corresponding position on the second wafer. In this way, after wafer bonding, the second alignment mark will be aligned with the first alignment mark, thereby transferring the alignment mark to the second wafer. The second alignment mark is formed on the second wafer, so it is no longer necessary to expose the first alignment mark on the first wafer by blind exposure and etching, avoiding the loss of effective area on the wafer, avoiding the arrow shadow problem, and increasing the actual effective number of dies on the wafer.

[0033] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0035] Figure 1 and Figure 2 A schematic diagram of a cross-sectional structure exposing the front-layer alignment marks on the device wafer in the fabrication method of MEMS devices provided by related technologies;

[0036] Figure 3 A schematic flowchart illustrating the fabrication method of the MEMS device provided in the embodiments of this application;

[0037] Figures 4 to 9 This is a cross-sectional structural diagram of the MEMS device provided in the embodiments of this application during the fabrication process. Detailed Implementation

[0038] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0045] Please refer to Figure 1 In the figure, the first wafer 100 is, for example, a device wafer, which can also be referred to as a "MEMS wafer" in a specific example. Patterned device functional layers and various markings are formed on the first wafer 100, such as a first dielectric layer 110, a conductive layer 120, a second dielectric layer 130, and a first alignment mark 101. The second wafer 200 is a capwafer, bonded to the first wafer 100, forming several cavities between the two wafers. As shown in the figure, after wafer bonding, only the back side of the second wafer 200 is visible; the first alignment mark 101 is covered by the second wafer 200, and the alignment machine cannot directly locate it.

[0046] Please refer to Figure 2 In order to expose the first alignment mark 101, a large pit 204 needs to be etched after blind exposure. The large pit 204 penetrates the second wafer 200, so that the alignment machine can find the first alignment mark 101 on the first wafer 100 through the large pit 204, and then continue the next photolithography process.

[0047] Understandably, due to the blind exposure method, the linewidth of the large pit 204 is relatively large, resulting in a certain area loss on the second wafer 200. Furthermore, the depth of the large pit 204 is relatively deep, causing some photoresist to fall from the pit 204 into the cavity or onto the first wafer 100 during subsequent photoresist coating. This not only easily leads to arrow shadows but also causes uneven photoresist coating, affecting the lithography effect and ultimately reducing the number of effective dies, thus impacting the product's appearance. Moreover, since the photoresist of the current layer cannot be well coated onto the first alignment mark 101 of the previous layer, this method obviously cannot monitor alignment accuracy.

[0048] Based on this, embodiments of this application provide a method for fabricating a MEMS device, such as... Figure 3 As shown, the method includes:

[0049] Step S01: A first wafer is provided, and a first alignment mark and a first bonding mark are formed on the bonding surface of the first wafer;

[0050] Step S02, providing a second wafer;

[0051] Step S03: Form a second alignment mark and a second bonding mark on the bonding surface of the second wafer;

[0052] The positional relationship between the second alignment mark and the second bonding mark is the same as that between the first alignment mark and the first bonding mark; the second alignment mark extends from the bonding surface of the second wafer to the interior of the second wafer, and the second alignment mark has a first end located on the bonding surface of the second wafer and a second end located inside the second wafer;

[0053] Step S04: Bond the second wafer to the first wafer with the bonding surface of the first wafer facing the bonding surface of the second wafer and the first bonding mark and the second bonding mark aligned with each other.

[0054] Step S05: Remove a portion of the second wafer to expose the second end of the second alignment mark.

[0055] It should be understood that, although Figure 3 The steps in the flowchart shown are displayed sequentially according to the arrows. However, these steps are not necessarily executed in the order indicated by the arrows; moreover, these steps are not necessarily performed sequentially. This application does not exclude the possibility that at least two steps are completed at the same time or are completed alternately. For example, steps S02 and S03 may be executed before step S01, or simultaneously with step S01. The execution order between steps should still be determined according to the specific logical relationship.

[0056] Next, we will combine Figures 4 to 9 The schematic diagram of the cross-sectional structure of the MEMS device shown in this embodiment further illustrates the fabrication method of the MEMS device and its beneficial effects.

[0057] First, please refer to Figure 4 Execute step S01 to provide the first wafer 100.

[0058] Here, the first wafer 100 can be a silicon wafer, a germanium wafer, a silicon-on-insulator (SOI) wafer, a germanium-on-insulator (GeOI) wafer, etc., and this application does not make specific limitations on it.

[0059] The first wafer 100 has two surfaces that are opposite to each other. The surface that faces the second wafer and is bonded to the second wafer is called the bonding surface (refer to the upper surface of the first wafer 100 in the figure); after wafer bonding, this surface can be called the bonding surface; the other surface opposite to the bonding surface can be called the back surface of the first wafer 100 (refer to the lower surface of the first wafer 100 in the figure).

[0060] like Figure 4 As shown, a first alignment mark 101 and a first bonding mark 102 are formed on the bonding surface of the first wafer 100.

[0061] Understandably, the alignment mark described in this application context is a mark used in the photolithography process and can be observed using an alignment machine; while the bonding mark is a mark used in the wafer bonding process. Although it also serves an alignment function during bonding, this mark is for observation on a bonding machine. Therefore, alignment marks and bonding marks are completely different. In fact, those skilled in the art should be able to clearly distinguish between alignment marks and bonding marks.

[0062] Patterned device functional layers, such as patterned first dielectric layer 110, conductive layer 120, and second dielectric layer 130, can also be formed on the bonding surface of the first wafer 100. The patterned device functional layers can define the location of cavities, and device units can be formed at the location of cavities in subsequent processes. After dicing, the device units can be formed into dies.

[0063] The patterned device functional layer can, of course, have alignment marks that coincide with the position of the first alignment mark 101, thereby gradually transferring the alignment mark from the previous layer to the current layer. Furthermore, if the patterned device functional layer is thin, even if it covers the first alignment mark 101 on the first wafer 100, it will not affect the observation of the first alignment mark 101; therefore, the patterned device functional layer may not have alignment marks. This application does not impose specific limitations in this regard.

[0064] Optionally, the first alignment mark 101 is formed in the scribe line region; correspondingly, the second alignment mark on the second wafer will also be formed in the scribe line region. In this way, the alignment mark does not need to occupy additional die space, increasing the actual number of effective dies on the wafer.

[0065] Next, please refer to Figure 5 and Figure 6Steps S02 and S03 are performed to provide a second wafer 200 and form a second alignment mark 201 and a second bonding mark 202 on the bonding surface of the second wafer 200.

[0066] The second wafer 200 has two surfaces that face each other. Similar to the first wafer 100, the surface of the second wafer 200 that faces and bonds to the first wafer 100 is called the bonding surface (see reference). Figure 5 The upper surface of the second wafer 200; after wafer bonding, this surface can be called the bonding surface; the other surface opposite to the bonding surface can be called the back surface of the second wafer 200 (refer to the lower surface of the second wafer 200 in the figure). Figures 7 to 9 In the process, the second wafer 200 will be flipped so that the bonding side / bonding side is facing down and the back side is facing up.

[0067] like Figure 5 As shown, the second wafer 200 may include a substrate layer 210, an intermediate dielectric layer 220, and a top semiconductor layer 230. Specifically, the second wafer 200 may be a silicon-on-insulator (SOI) wafer or a germanium-on-insulator (GeOI) wafer. Taking a silicon-on-insulator wafer as an example, the substrate layer 210 is a bottom silicon layer, the intermediate dielectric layer 220 is a buried oxide layer, and the top semiconductor layer 230 is a top silicon layer.

[0068] The bonding surface of the second wafer 200 is specifically the surface of the top semiconductor layer 230 on the side away from the intermediate dielectric layer 220.

[0069] In this embodiment, the positional relationship between the second alignment mark 201 and the second bonding mark 202 is the same as that between the first alignment mark 101 and the first bonding mark 102. Considering that the first bonding mark 102 and the second bonding mark 202 will be aligned with each other when the first wafer 100 and the second wafer 200 are bonded, the second alignment mark 201 is formed at the corresponding position on the second wafer 200 using the positional relationship between the first alignment mark 101 and the first bonding mark 102. Thus, after wafer bonding, the second alignment mark 201 will be aligned with the first alignment mark 101, thereby transferring the alignment mark to the second wafer 200. The second alignment mark 201 is formed on the second wafer 200, so it is no longer necessary to expose the first alignment mark 101 on the first wafer 100 by blind exposure and etching, avoiding the loss of effective area on the wafer, avoiding the arrow shadow problem, and increasing the actual effective number of dies on the wafer.

[0070] The positional relationship between the second alignment mark 201 and the second bonding mark 202 is the same as that between the first alignment mark 101 and the first bonding mark 102. This can be understood as the distance between the second alignment mark 201 and the second bonding mark 202 along the wafer plane being equal to the distance between the first alignment mark 101 and the first bonding mark 102. More specifically, the second alignment mark 201 and the second bonding mark 202 as a whole are mirror images of the first alignment mark 101 and the first bonding mark 102 as another whole. Ultimately, after wafer bonding, when the first bonding mark 102 and the second bonding mark 202 are aligned, the first alignment mark 101 and the second alignment mark 201 can also be aligned.

[0071] Optionally, a second alignment mark 201 is formed in the dicing area. As previously mentioned, this avoids occupying additional die space for the alignment mark, increasing the actual number of usable dies on the wafer.

[0072] like Figure 6 As shown, the second alignment mark 201 extends from the bonding surface of the second wafer 200 into the interior of the second wafer 200. The second alignment mark 201 has a first end 2011 located on the bonding surface of the second wafer 200 and a second end 2012 located inside the second wafer 200. The depth of the second alignment mark 201 is greater than the depth of the second bonding mark 202, thereby making it easier to expose the second end 2012 of the second alignment mark 201 in subsequent processes.

[0073] Please continue to refer to this. Figure 6 In an embodiment where the second wafer 200 includes a base layer 210, an intermediate dielectric layer 220, and a top semiconductor layer 230, forming a second alignment mark 201 on the bonding surface of the second wafer 200 may include forming a second alignment mark 201 extending to the intermediate dielectric layer 220 on the bonding surface of the second wafer 200. In actual fabrication, the second alignment mark 201 is formed by an etching process, and the etching stops on the intermediate dielectric layer 220. Although in actual processes, the etching may stop at the interface between the intermediate dielectric layer 220 and the top semiconductor layer 230, or it may be located in the surface layer of the intermediate dielectric layer 220, this document does not make a specific distinction. Considering that the second alignment mark 201 penetrates the top semiconductor layer 230, it can be generally considered that the second end 2012 of the second alignment mark 201 is located on the surface of the top semiconductor layer 230 facing the intermediate dielectric layer 220.

[0074] As an optional implementation, forming a second alignment mark 201 on the bonding surface of the second wafer 200 may include: first forming a second bonding mark 202 and a third alignment mark 203 (e.g., ...) on the bonding surface of the second wafer 200. Figure 5(As shown); In actual processes, this step can be called zero-layer marking, where the third alignment mark 203 and the second bonding mark 202 are formed simultaneously. Then, the second alignment mark 201 is formed according to the position of the third alignment mark 203 (as shown). Figure 6 (As shown). Thus, the second alignment mark 201 is etched using the third alignment mark 203 as the alignment mark. The relative position of the third alignment mark 203 and the second bonding mark 202 is fixed during the 0 layer marking. Therefore, the second alignment mark 201 and the second bonding mark 202 can be formed to meet the positional relationship required by the process. After wafer bonding is completed in a manner where the first bonding mark 102 and the second bonding mark 202 are aligned with each other (i.e., in the case of the bonding mark being applied), the second alignment mark 201 is aligned with the first alignment mark 101 on the first wafer 100.

[0075] Next, please refer to Figure 7 Step S04 is executed to bond the second wafer 200 to the first wafer 100.

[0076] During wafer bonding, the bonding surface of the first wafer 100 faces the bonding surface of the second wafer 200, and the first bonding mark 102 and the second bonding mark 202 are aligned with each other. Thus, the second alignment mark 201 is aligned with the first alignment mark 101. However, at this time, the second alignment mark 201 cannot be observed from the back side of the second wafer 200.

[0077] Next, please refer to Figure 8 and Figure 9 Step S05 is performed to remove a portion of the second wafer 200 to expose the second end 2012 of the second alignment mark 201.

[0078] Removing a portion of the second wafer 200 can specifically involve thinning the back side of the second wafer 200 until the second end 2012 of the second alignment mark 201 is exposed. Of course, this application does not exclude the possibility of etching a portion of the back side of the second wafer 200 to expose the second end 2012 of the second alignment mark 201.

[0079] In an embodiment where the second wafer 200 includes a substrate layer 210, an intermediate dielectric layer 220, and a top semiconductor layer 230, removing a portion of the second wafer 200 may include removing the substrate layer 210 and the intermediate dielectric layer 220. Please refer to [the previous text]. Figure 8 The back side of the second wafer 200 is thinned to remove the substrate layer 210; please refer to the following... Figure 9The intermediate dielectric layer 220 is removed to expose the second end 2012 of the second alignment mark 201. Understandably, if the second wafer 200 is entirely made of the same material in the thickness direction, it is typically thinned using a grinding process until the second end 2012 of the second alignment mark 201 is exposed. However, this process can easily damage the second end 2012 of the second alignment mark 201. In this embodiment, the intermediate dielectric layer 220 is ground down first without damaging the second end 2012 of the second alignment mark 201, and then the second end 2012 is exposed by removing the intermediate dielectric layer 220. This results in a clearer and more accurate alignment mark.

[0080] Next, the method may further include: using the second end 2012 of the second alignment mark 201 as a photolithographic alignment mark to form a pattern on the second wafer 200. In other words, in the subsequent photolithography process, the second end 2012 of the second alignment mark 201 will be used as the alignment mark, replacing the alignment method in the original process that used the first alignment mark 101 on the first wafer 100 as the alignment mark. This not only eliminates the need to form a large pit 204 to expose the first alignment mark 101, but also allows for more precise subsequent alignment as the alignment mark is located on the second wafer 200.

[0081] Optionally, the MEMS device in this application may specifically be a MEMS inertial sensor; correspondingly, forming a pattern on the second wafer 200 may include forming a comb pattern and / or a mass block pattern (not shown in the figure) on the second wafer 200.

[0082] Furthermore, although this application only mentions the first wafer 100 and the second wafer 200, depending on the specific structural requirements of the MEMS device, the MEMS device may obviously also include a third wafer, or even a fourth wafer, etc. Accordingly, the fabrication method of the MEMS device provided in this embodiment may also include the step of bonding the third wafer onto the second wafer 200. If a fourth wafer is also included, the corresponding bonding steps are similar and will not be elaborated here.

[0083] Furthermore, the above method may also include: forming an overlay measurement mark (not shown in the figure, but reference can be made to the second alignment mark 201) on the bonding surface of the second wafer 200, the overlay measurement mark extending from the bonding surface of the second wafer 200 into the interior of the second wafer 200, the overlay measurement mark having a third end located on the bonding surface of the second wafer 200 and a fourth end located inside the second wafer 200; removing a portion of the second wafer 200, thereby exposing the fourth end of the overlay measurement mark.

[0084] Overlay accuracy (OVL accuracy) is one of the key parameters for evaluating photolithography processes. Specifically, overlay accuracy refers to the offset between the current layer and the preceding layer, i.e., the overlay error. In this field, overlay error is typically measured by measuring the offset between two overlay measurement marks (OVL marks) to evaluate overlay accuracy. Understandably, since the method provided in this application can transfer the marks used in photolithography to the back side of the second wafer 200, i.e., to the current layer, it solves the problem of the original process's inability to monitor alignment accuracy. Alignment accuracy can be monitored using the fourth end of the overlay measurement mark.

[0085] Here, the third and fourth ends are only for easy distinction from the first end 2011 and the second end 2012 of the second alignment mark 201, and do not mean that the finger ferrule measurement mark includes four ends.

[0086] Based on this, the embodiments of this application also provide a MEMS wafer, which can be further referenced. Figure 9 The MEMS wafer includes a first wafer 100 and a second wafer 100 bonded to each other; wherein, a first alignment mark 101 and a first bonding mark 102 are formed on the first wafer 100; a second alignment mark 201 and a second bonding mark 202 are formed on the second wafer 200; the first bonding mark 102 and the second bonding mark 202 are aligned with each other, and the first alignment mark 101 and the second alignment mark 201 are aligned with each other; the second alignment mark 201 penetrates through the second wafer 200.

[0087] As an optional implementation, a second alignment mark 201 is formed in the scribbling area.

[0088] As an optional implementation, overlay measurement marks are also formed on the second wafer 200, and the overlay measurement marks penetrate the second wafer 200.

[0089] It should be noted that the MEMS wafer embodiments and the MEMS wafer fabrication method embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0090] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for fabricating a MEMS device, characterized in that, The method includes: A first wafer is provided, wherein a first alignment mark and a first bonding mark are formed on the bonding surface of the first wafer; Provide a second wafer; A second alignment mark and a second bonding mark are formed on the bonding surface of the second wafer; wherein the positional relationship between the second alignment mark and the second bonding mark is the same as the positional relationship between the first alignment mark and the first bonding mark; the second alignment mark extends from the bonding surface of the second wafer to the interior of the second wafer, and the second alignment mark has a first end located on the bonding surface of the second wafer and a second end located inside the second wafer; the first alignment mark and the second alignment mark are marks used in the photolithography process and can be observed by an alignment machine; the first bonding mark and the second bonding mark are marks used in the wafer bonding process and can play an alignment role during the bonding process, and are used for observation on the bonding machine; The second wafer is bonded to the first wafer with the bonding surface of the first wafer facing the bonding surface of the second wafer and the first bonding mark and the second bonding mark aligned with each other. Remove a portion of the second wafer to expose the second end of the second alignment mark.

2. The method for fabricating a MEMS device according to claim 1, characterized in that, The second wafer includes a base layer, an intermediate dielectric layer, and a top semiconductor layer, wherein the bonding surface of the second wafer is the surface of the top semiconductor layer away from the intermediate dielectric layer; The step of forming a second alignment mark on the bonding surface of the second wafer includes: forming a second alignment mark extending to the intermediate dielectric layer on the bonding surface of the second wafer; The removal of a portion of the second wafer includes: removing the substrate layer and the intermediate dielectric layer.

3. The method for fabricating a MEMS device according to claim 1, characterized in that, The process of forming a second alignment mark and a second bonding mark on the bonding surface of the second wafer includes: A second bonding mark and a third alignment mark are formed on the bonding surface of the second wafer; The second alignment mark is formed based on the position of the third alignment mark.

4. The method for fabricating a MEMS device according to claim 1, characterized in that, The second alignment mark is formed within the scribbling area.

5. The method for fabricating a MEMS device according to claim 1, characterized in that, The method further includes: Using the second end of the second alignment mark as a photolithographic alignment mark, a pattern is formed on the second wafer.

6. The method for fabricating a MEMS device according to claim 5, characterized in that, The MEMS device includes a MEMS inertial sensor; The process of forming a pattern on the second wafer includes forming a comb pattern and / or a mass block pattern on the second wafer.

7. The method for fabricating a MEMS device according to claim 1, characterized in that, The method further includes: An overlay measurement mark is formed on the bonding surface of the second wafer. The overlay measurement mark extends from the bonding surface of the second wafer to the interior of the second wafer. The overlay measurement mark has a third end located on the bonding surface of the second wafer and a fourth end located inside the second wafer. The removal of a portion of the second wafer also exposes the fourth end of the overlay measurement mark.

8. A MEMS wafer, characterized in that, include: A first wafer and a second wafer bonded together; wherein, A first alignment mark and a first bonding mark are formed on the first wafer; A second alignment mark and a second bonding mark are formed on the second wafer; The first bonding mark and the second bonding mark are aligned with each other, and the first alignment mark and the second alignment mark are aligned with each other; The second alignment mark extends through the second wafer; The first alignment mark and the second alignment mark are marks used in the photolithography process and can be observed by an alignment machine; the first bonding mark and the second bonding mark are marks used in the wafer bonding process and can play an alignment role during the bonding process, and are used for observation on the bonding machine.

9. The MEMS wafer according to claim 8, characterized in that, The second alignment mark is formed within the scribbling area.

10. The MEMS wafer according to claim 8, characterized in that, The second wafer also has overlay measurement marks formed on it, and the overlay measurement marks penetrate the second wafer.

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