Semiconductor measurement structure and method of measuring the same

Abstract

The application provides a semiconductor measurement structure and a measurement method thereof, and belongs to the technical field of semiconductor measurement. The semiconductor measurement structure comprises a grating original element and a measurement assembly. The grating original element comprises a plurality of grating line patterns arranged in parallel and at equal intervals. The measurement assembly comprises a plurality of first line patterns arranged in parallel and at equal intervals and a plurality of second line patterns arranged in parallel and at equal intervals. The extension directions of the grating line patterns, the first line patterns and the second line patterns are the same. The grating width of the grating line patterns is the same as the first width of the first line patterns. The grating interval between adjacent grating line patterns is the same as the second interval between adjacent second line patterns. The first interval between adjacent first line patterns is the same as the second width of the second line patterns. The application calculates the actual values of the grating width and the grating interval by obtaining the measurement values of the first interval and the second width, thereby reducing the measurement complexity and time cost and realizing the rapid detection of the qualification of the grating original element.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor measurement structure and a measurement method thereof. Background Art

[0002] Figure 1 A schematic diagram of the structure of a grating element. Figure 2 and Figure 3 for Figure 1 The cross-sectional structure diagram of different regions in the grating element is shown. Figure 1 A plurality of grating elements 2 with the same structure are arranged in an array on a silicon wafer 1. The grating element 2 includes a first region X1 and a second region X2. Figures 1 to 3 The grating element 2 includes a substrate 100 and a silicon oxide layer 110 from bottom to top, wherein the silicon oxide layer 110 in the first area X1 is a thin film covering the substrate 100, and the silicon oxide layer 110 in the second area X2 is composed of a plurality of line graphics (Line) 21 with the same spacing and parallel to each other.

[0003] In the conventional manufacturing process of the grating element, a mask (not shown) is usually used to pattern the silicon oxide layer 110 so that the shape of the silicon oxide layer 110 is as follows: Figure 1 As shown, the exposed portion of the substrate 100 is etched to form a grating element 2 (see Figure 2 and Figure 3 Although the silicon-based manufacturing process for grating elements is relatively simple, it places stringent requirements on process stability.

[0004] Continue reading Figure 1 To ensure that the grating element 2 meets the process requirements, it is necessary to measure the width W of all line patterns 21 and the spacing D between adjacent line patterns 21 in the second area X2 one by one. Since the width W and spacing D of the line patterns 21 are usually orders of magnitude different from the error value (Error) Δ allowed by the process, when measuring the width W and spacing D, in order to ensure the accuracy of the measurement results, it is necessary to measure at a higher magnification. However, see Figure 4 When the magnification is large, the area that can be displayed by the measuring device in a single sampling is correspondingly reduced, and it may even be impossible to simultaneously display the width W and spacing D of a line graphic 21, which greatly increases the measurement complexity and time cost. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor measurement structure and a measurement method thereof, which reduce the measurement complexity and time cost and realize the rapid detection of the qualification of the grating element.

[0006] In order to achieve the above-mentioned object, the present invention provides a semiconductor measurement structure, comprising a grating element and a measurement component, wherein:

[0007] The grating element comprises a plurality of grating line patterns, and the plurality of grating line patterns are arranged in parallel and at equal intervals;

[0008] The measuring component includes a plurality of first line patterns and a plurality of second line patterns, wherein the plurality of first line patterns are arranged in parallel and at equal intervals, and the plurality of second line patterns are arranged in parallel and at equal intervals, and the grating line patterns, the first line patterns, and the second line patterns extend in the same direction;

[0009] The grating width of the grating line pattern is the same as the first width of the first line pattern, the grating spacing between adjacent grating line patterns is the same as the second spacing between adjacent second line patterns, and the first spacing between adjacent first line patterns is the same as the second width of the second line pattern.

[0010] Optionally, the semiconductor measurement structure includes a substrate and a dielectric layer disposed on the substrate, and the dielectric layer includes the grating line pattern, the first line pattern, and the second line pattern.

[0011] Optionally, the grating line pattern, the first line pattern and the second line pattern are all formed in the same process.

[0012] Optionally, a surface of a portion of the substrate covered with the grating line pattern, the first line pattern, and the second line pattern is higher than a surface of a remaining portion of the substrate.

[0013] Optionally, portions of the substrate located between adjacent grating line patterns, between adjacent first line patterns, and between adjacent second line patterns are all provided with V-shaped grooves, and an extension direction of the V-shaped grooves is the same as an extension direction of the grating line patterns.

[0014] Optionally, the first spacing is of the same order of magnitude as the minimum error value allowed by the manufacturing process of the grating element.

[0015] Accordingly, the present invention further provides a measurement method for a semiconductor measurement structure, wherein the semiconductor measurement structure is used for measurement, comprising:

[0016] Obtaining a first characteristic dimension and a second characteristic dimension of the measurement component, where the first characteristic dimension is the sum of a design value of the first width and a design value of the first spacing, and the second characteristic dimension is the sum of a design value of the second width and a design value of the second spacing;

[0017] Acquire a scanned image of the measurement component, and measure and obtain a measurement value of the first spacing and a measurement value of the second width; and

[0018] The grating width and the grating spacing are calculated to determine whether the grating element is qualified.

[0019] Optionally, the actual value of the grating width is equal to the difference between the first characteristic size and the measured value of the first spacing, and the actual value of the grating spacing is equal to the difference between the second characteristic size and the measured value of the second width.

[0020] Optionally, the process of determining whether the grating original is qualified includes:

[0021] Obtaining a design value of the grating width and a design value of the grating spacing;

[0022] If the absolute value of the difference between the design value and the actual value of the grating width is less than the first error value, and the absolute value of the difference between the design value and the actual value of the grating pitch is less than the second error value, then the grating original is qualified;

[0023] If not, the grating original is unqualified.

[0024] Optionally, the method for manufacturing the semiconductor measurement structure includes:

[0025] providing a substrate, and forming a dielectric layer on the substrate;

[0026] Performing a patterning process to simultaneously form the grating line pattern, the first line pattern, and the second line pattern in the dielectric layer;

[0027] performing a first etching process to etch the portion of the substrate exposed by the dielectric layer so that the surface of the portion of the substrate covered with the grating line pattern, the first line pattern, and the second line pattern is higher than the surface of the remaining portion of the substrate; and

[0028] A second etching process is performed to further etch the portion of the substrate exposed by the dielectric layer to form the V-shaped grooves between adjacent grating line patterns, between adjacent first line patterns, and between adjacent second line patterns.

[0029] Optionally, the first etching process is a dry etching process, and the second etching process is a wet etching process.

[0030] In summary, the present invention provides a semiconductor measurement structure and a measurement method thereof. The semiconductor measurement structure includes a grating element and a measurement component, wherein the grating element includes a plurality of parallel and equally spaced grating line patterns; the measurement component includes a plurality of parallel and equally spaced first line patterns and a plurality of parallel and equally spaced second line patterns, and the grating line patterns, the first line patterns, and the second line patterns extend in the same direction; wherein the grating width of the grating line patterns is the same as the first width of the first line patterns, the grating spacing between adjacent grating line patterns is the same as the second spacing between adjacent second line patterns, and the first spacing between adjacent first line patterns is the same as the second width of the second line pattern. The present invention obtains the measurement value of the first spacing and the measurement value of the second width in the scanned image of the measurement component, reducing the measurement complexity and time cost, and calculates the actual values ​​of the grating width and grating spacing based on the geometric relationship between the grating line patterns, the first line patterns, and the second line patterns, thereby achieving rapid detection of the grating element's quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the structure of a grating element;

[0032] Figure 2 for Figure 1 The schematic diagram of the cross-sectional structure of the grating element along the AB direction is shown;

[0033] Figure 3 for Figure 1 The cross-sectional structure diagram of the grating original along the CD direction is shown;

[0034] Figure 4 for Figure 1 Scanning electron microscope image of the grating original shown;

[0035] Figure 5 A schematic structural diagram of a semiconductor measurement structure provided by one embodiment of the present invention;

[0036] Figure 6 A schematic structural diagram of a grating element in a semiconductor measurement structure provided by one embodiment of the present invention;

[0037] Figure 7 A schematic structural diagram of a measurement component in a semiconductor measurement structure provided by an embodiment of the present invention;

[0038] Figure 8 for Figure 5 Schematic diagram of the cross-sectional structure of the semiconductor measurement structure along the AB direction;

[0039] Figure 9 A flow chart of a method for measuring a semiconductor measurement structure according to an embodiment of the present invention;

[0040] Figure 10 A scanned image of a measurement structure in a method for measuring a semiconductor measurement structure provided by an embodiment of the present invention;

[0041] Figures 11 to 13 A schematic structural diagram corresponding to each step in the formation process of a semiconductor measurement structure provided by an embodiment of the present invention;

[0042] The accompanying drawings are numerals as follows:

[0043] 1- silicon wafer; 2- grating element; 21- line pattern;

[0044] 100-substrate; 110-silicon oxide layer; X1-first region; X2-second region; W-width; D-spacing;

[0045] 3-semiconductor measurement structure; 4-grating element; 41-grating line pattern; 5-measurement component; 51-first line pattern; 52-second line pattern;

[0046] W1-grating width; D1 grating spacing; W2-first width; D2-first spacing; W3-second width; D3-second spacing;

[0047] 200 - substrate; 201 - V-shaped groove; 210 - dielectric layer. DETAILED DESCRIPTION

[0048] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0049] Figure 5 A schematic diagram of a semiconductor measurement structure according to an embodiment of the present invention is shown. Figure 6 and Figure 7 They are Figure 5 Schematic diagram of the structure of the grating element and the measurement component. Figures 5 to 7 The semiconductor measurement structure 3 described in this embodiment includes a grating element 4 and a measurement component 5. The grating element 4 includes a plurality of grating line patterns 41, and the plurality of grating line patterns 41 are arranged in parallel and at equal intervals. The measurement component 5 includes a plurality of first line patterns 51 and a plurality of second line patterns 52, and the plurality of first line patterns 51 are arranged in parallel and at equal intervals. The plurality of second line patterns 52 are arranged in parallel and at equal intervals. The grating line patterns 41, the first line patterns 51, and the second line patterns 52 extend in the same direction (i.e., Figures 5 to 7 in the X direction).

[0050] The grating width W1 of the grating line pattern 41 is the same as the first width W2 of the first line pattern 51; the grating spacing D1 between adjacent grating line patterns 41 is the same as the second spacing D3 between adjacent second line patterns 52; and the first spacing D2 between adjacent first line patterns 51 is the same as the second width W3 of the second line pattern 52. That is, the geometric relationship between the grating line pattern 41, the first line pattern 51, and the second line pattern 52 satisfies the following set conditions: W1 = W2, D1 = D3, and D2 = W3.

[0051] For example, W1 = 10 μm, D1 = 74 μm, W2 = 10 μm, D2 = 0.5 μm, W3 = 0.5 μm, and D3 = 74 μm. In other embodiments of the present invention, the specific values ​​of W1, D1, W2, D2, W3, and D3 can be set according to the size and process requirements of the semiconductor device, wherein the values ​​of the first spacing D2 and the second width W3 should be on the same order of magnitude as the minimum error value allowed by the process of the grating element 4 (for example, 0.1 μm), so as to facilitate subsequent inspection of the grating element for qualification. Optionally, the length L1 of the first line pattern 51 and the length L2 of the second line pattern 52 are both greater than 2 μm.

[0052] Figure 8 for Figure 5 Schematic diagram of the cross-sectional structure of the semiconductor measurement structure along the AB direction. Figures 6 to 8 The semiconductor measurement structure 3 includes a substrate 200 and a dielectric layer 210 disposed on the substrate 200, the dielectric layer 210 includes the grating line pattern 41, the first line pattern 5 and the second line pattern 52, and the grating line pattern 41, the first line pattern 52 and the second line pattern 52 are all formed in the same process to ensure that the geometric relationship between the actually manufactured grating line pattern, the first line pattern and the second line pattern still meets the set conditions.

[0053] Continue reading Figure 8 , the surface of the portion of the substrate 200 covered with the grating line pattern 41, the first line pattern 51, and the second line pattern 52 is higher than the surface of the remaining portion of the substrate 200. Optionally, the height difference between the surface of the portion of the substrate 200 covered with the grating line pattern 41, the first line pattern 51, and the second line pattern 52 and the surface of the remaining portion is 250 μm.

[0054] In this embodiment, portions of the substrate 200 located between adjacent grating line patterns 41, between adjacent first line patterns 51, and between adjacent second line patterns 52 are all provided with V-shaped grooves 201, and the extension direction of the V-shaped grooves 201 is the same as the extension direction of the grating line patterns 41 (both along the X direction).

[0055] See Figure 9 This embodiment further provides a method for measuring a semiconductor measurement structure, wherein the semiconductor measurement structure is used for measurement, and the method includes:

[0056] Step S01: obtaining a first characteristic dimension and a second characteristic dimension of the measurement component, wherein the first characteristic dimension is the sum of a design value of the first width and a design value of the first spacing, and the second characteristic dimension is the sum of a design value of the second width and a design value of the second spacing;

[0057] Step S02: acquiring a scanned image of the measurement component, and measuring the first spacing and the second width; and

[0058] Step S03: Calculate the grating width and the grating spacing, and determine whether the grating original is qualified.

[0059] Below is Figures 5 to 8 The semiconductor measurement structure shown is taken as an example to illustrate the measurement method of the semiconductor measurement structure according to this embodiment.

[0060] First, see Figures 5 to 8 , executing step S01 to obtain a first characteristic dimension CD1 and a second characteristic dimension CD2 of the measurement component 5. The first characteristic dimension is the sum of the design value of the first width W2 and the design value of the first spacing D2, and the second characteristic dimension is the sum of the design value of the second width W3 and the design value of the second spacing D3. That is, CD1 = W2 + D2, CD2 = W3 + D3.

[0061] It should be noted that during the manufacturing process of the semiconductor measurement structure 3, the first characteristic size and the second characteristic size of the measurement component 5 are fixed, that is, the design value and the actual value of the first characteristic size are the same, and the design value and the actual value of the second characteristic size are also the same.

[0062] Then, see Figure 10 , execute step S02, obtain the scanning image of the measuring component 5, and measure the measurement value of the first distance D2 and the measurement value of the second width W3.

[0063] In this embodiment, the scanned image includes Figure 7In the area selected by the solid line, the scanned image includes at least a first spacing D2 and a second width W3. It should be noted that, since the first spacing D2 is equal to the second width W3 in the setting conditions of the semiconductor measurement structure, the measured value of the first spacing D2 and the measured value of the second width W3 in the actual measurement structure are equal or very close, and it is almost impossible for there to be a difference in order of magnitude. Furthermore, since the measured value of the first spacing D2 and the measured value of the second width W3 are equal or very close, the measured value of the first spacing D2 and the measured value of the second width W3 can be directly obtained in the scanned image with the same magnification, thereby reducing the measurement time.

[0064] Next, step S03 is executed to calculate the grating width and the grating spacing, and determine whether the grating original is qualified.

[0065] Since the semiconductor measurement structure's set conditions satisfy W1=W2, D1=D3, and D2=W3, the measurement structure satisfies CD1=W2+D2 and CD2=W3+D3. Therefore, according to mathematical principles, W1=CD1-D2 and D1=CD2-W3. In this embodiment, since the design value and actual value of the first characteristic dimension CD1 are the same, the design value and actual value of the second characteristic dimension CD2 are the same, and the measured value of the first spacing D2 and the measured value of the second width W3 are the same, the actual value of the grating width W1 is equal to the difference between the measured values ​​of the first characteristic dimension CD1 and the first spacing D2, and the actual value of the grating spacing D1 is equal to the difference between the measured values ​​of the second characteristic dimension CD2 and the second width W3.

[0066] In this embodiment, the process of determining whether the grating element 4 is qualified includes: obtaining a design value of the grating width W1 and a design value of the grating spacing D1; if the absolute value of the difference between the design value and the actual value of the grating width W1 is less than a first error value, and the absolute value of the difference between the design value and the actual value of the grating spacing D1 is less than a second error value, then the grating element 4 is qualified; otherwise, the grating element 4 is unqualified. In this embodiment, the first error value and the second error value are the same, both being 0.1 μm. In other embodiments of the present invention, the first error value and the second error value may also be different, and the present invention is not limited thereto.

[0067] In addition, the manufacturing method of the semiconductor measurement structure includes: referring to Figure 11 , providing a substrate 200, and forming a dielectric layer 210 on the substrate 200; referring to Figure 12, performing a patterning process to simultaneously form the grating line pattern 41, the first line pattern 51, and the second line pattern 52 in the dielectric layer 210; performing a first etching process to etch the portion of the substrate 200 exposed by the dielectric layer 210, so that the surface of the portion of the substrate 200 covered with the grating line pattern 41, the first line pattern 51, and the second line pattern 52 is higher than the surface of the remaining portion of the substrate 200; referring to Figure 13 , a second etching process is performed to further etch the portion of the substrate 200 exposed by the dielectric layer 210 to form the V-shaped grooves 201 between adjacent grating line patterns 41 , between adjacent first line patterns 51 and between adjacent second line patterns 52 .

[0068] In this embodiment, the first etching process is a dry etching process, and the second etching process is a wet etching process. Optionally, the dielectric layer 210 is a silicon oxide layer.

[0069] contrast Figure 4 and Figure 10 It can be seen that in existing inspection processes, when the magnification is high, the measurement equipment has difficulty simultaneously displaying the width W and spacing D of a line pattern 21, making it impossible to measure the actual values ​​of the width W and spacing D. At a low magnification, although the measurement equipment can simultaneously display the width W and spacing D of one or more line patterns 21, the accuracy of the measured actual values ​​of the width W and spacing D is low, making it impossible to determine whether the grating element meets process requirements. In the semiconductor two-sided structure and its measurement method described in this embodiment, the design value of the first spacing D2 and the design value of the second width W3 are the same. The measurement value of the first spacing D2 and the measurement value of the second width W3 can be obtained simultaneously at the same magnification, thereby calculating the grating width W1 and grating spacing D1 of the grating element, reducing measurement complexity and time cost, and achieving rapid detection of grating element qualification.

[0070] In summary, the present invention provides a semiconductor measurement structure and a measurement method thereof. The semiconductor measurement structure includes a grating element and a measurement component, wherein the grating element includes a plurality of parallel and equally spaced grating line patterns; the measurement component includes a plurality of parallel and equally spaced first line patterns and a plurality of parallel and equally spaced second line patterns, and the grating line patterns, the first line patterns, and the second line patterns extend in the same direction; wherein the grating width of the grating line patterns is the same as the first width of the first line patterns, the grating spacing between adjacent grating line patterns is the same as the second spacing between adjacent second line patterns, and the first spacing between adjacent first line patterns is the same as the second width of the second line pattern. The present invention obtains the measurement value of the first spacing and the measurement value of the second width in the scanned image of the measurement component, reducing the measurement complexity and time cost, and calculates the actual values ​​of the grating width and grating spacing based on the geometric relationship between the grating line patterns, the first line patterns, and the second line patterns, thereby achieving rapid detection of the grating element's quality.

[0071] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A semiconductor measurement structure, characterized in that: It includes grating elements and measurement components, including: The grating element comprises a plurality of grating line patterns, and the plurality of grating line patterns are arranged in parallel and at equal intervals; The measuring component includes a plurality of first line patterns and a plurality of second line patterns, wherein the plurality of first line patterns are arranged in parallel and at equal intervals, and the plurality of second line patterns are arranged in parallel and at equal intervals, and the grating line patterns, the first line patterns, and the second line patterns extend in the same direction; The grating width of the grating line pattern is the same as the first width of the first line pattern, the grating spacing between adjacent grating line patterns is the same as the second spacing between adjacent second line patterns, and the first spacing between adjacent first line patterns is the same as the second width of the second line pattern.

2. The semiconductor measurement structure according to claim 1, wherein: The semiconductor measurement structure includes a substrate and a dielectric layer disposed on the substrate, wherein the dielectric layer includes the grating line pattern, the first line pattern, and the second line pattern.

3. The semiconductor measurement structure according to claim 1 or 2, wherein: The grating line pattern, the first line pattern and the second line pattern are all formed in the same process.

4. The semiconductor measurement structure according to claim 2, wherein: A surface of a portion of the substrate covered with the grating line pattern, the first line pattern, and the second line pattern is higher than a surface of a remaining portion of the substrate.

5. The semiconductor measurement structure according to claim 4, wherein: Portions of the substrate located between adjacent grating line patterns, between adjacent first line patterns, and between adjacent second line patterns are all provided with V-shaped grooves, and the extending direction of the V-shaped grooves is the same as the extending direction of the grating line patterns.

6. The semiconductor measurement structure according to claim 1, wherein: The first spacing is of the same order of magnitude as the minimum error value allowed by the manufacturing process of the grating element.

7. A method for measuring a semiconductor measurement structure, comprising: include: Obtaining a first characteristic dimension and a second characteristic dimension of the measurement component, where the first characteristic dimension is the sum of a design value of the first width and a design value of the first spacing, and the second characteristic dimension is the sum of a design value of the second width and a design value of the second spacing; Acquire a scanned image of the measurement component, and measure and obtain a measurement value of the first spacing and a measurement value of the second width; and The grating width and the grating spacing are calculated to determine whether the grating element is qualified.

8. The semiconductor measurement structure measurement method according to claim 7, wherein: The actual value of the grating width is equal to the difference between the first characteristic size and the measured value of the first spacing, and the actual value of the grating spacing is equal to the difference between the second characteristic size and the measured value of the second width.

9. The semiconductor measurement structure measurement method according to claim 8, wherein: The process of judging whether the grating original is qualified includes: Obtaining a design value of the grating width and a design value of the grating spacing; If the absolute value of the difference between the design value and the actual value of the grating width is less than the first error value, and the absolute value of the difference between the design value and the actual value of the grating pitch is less than the second error value, then the grating original is qualified; If not, the grating original is unqualified.

10. The semiconductor measurement structure measurement method according to claim 7, wherein: The method for manufacturing the semiconductor measurement structure includes: providing a substrate, and forming a dielectric layer on the substrate; Performing a patterning process to simultaneously form the grating line pattern, the first line pattern, and the second line pattern in the dielectric layer; performing a first etching process to etch the portion of the substrate exposed by the dielectric layer so that the surface of the portion of the substrate covered with the grating line pattern, the first line pattern, and the second line pattern is higher than the surface of the remaining portion of the substrate; and A second etching process is performed to further etch the portion of the substrate exposed by the dielectric layer to form V-shaped grooves between adjacent grating line patterns, between adjacent first line patterns, and between adjacent second line patterns.

11. The semiconductor measurement structure measurement method according to claim 10, wherein: The first etching process is a dry etching process, and the second etching process is a wet etching process.

Images