Capacitive mems accelerometer

Abstract

The application provides a capacitive MEMS accelerometer, which comprises: a MEMS device comprising a first differential capacitor, a first pad, a second differential capacitor, a second pad, a second end of the first differential capacitor and a second end of the second differential capacitor being coupled to a first node to which a first alternating current signal is applied; a processing circuit comprising a third pad, a third pad isolation component, a fourth pad, a fourth pad isolation component, a first compensation capacitor coupled to the third pad, a second compensation capacitor coupled to the fourth pad, a detection circuit coupled to the third pad and the fourth pad, wherein the first pad is coupled to the third pad, the second pad is coupled to the fourth pad, the second end of the third pad isolation component, the second end of the fourth pad isolation component, the second end of the first compensation capacitor and the second end of the second compensation capacitor are coupled to a second node to which a second alternating current signal is applied, the second alternating current signal being the same frequency and opposite phase to the first alternating current signal. In this way, the parasitic capacitance of the input end of the detection circuit is reduced, thereby improving the sensitivity of the accelerometer.

Description

[Technical Field]

[0001] This invention relates to the field of MEMS (Micro-Electro-Mechanical System) devices, and more particularly to a capacitive MEMS accelerometer. [Background Technology]

[0002] Due to manufacturing processes and other factors, parasitic capacitance is unavoidable at the output of capacitive MEMS devices. This parasitic capacitance increases circuit noise and reduces the sensitivity of the capacitive accelerometer.

[0003] Therefore, there is an urgent need to propose a new technical solution to address the above problems. [Summary of the Invention]

[0004] One of the objectives of this invention is to provide a capacitive MEMS accelerometer that reduces the parasitic capacitance at the input of the detection circuit, thereby improving the sensitivity of the accelerometer.

[0005] To address the aforementioned problems, according to one aspect of the present invention, a capacitive MEMS accelerometer is provided, comprising: a MEMS device including a first differential capacitor, a first pad coupled to a first terminal of the first differential capacitor, a first pad isolation component spaced apart from the first pad, a second differential capacitor, a second pad coupled to a first terminal of the second differential capacitor, and a second pad isolation component spaced apart from the second pad; the second terminal of the first differential capacitor and the second terminal of the second differential capacitor are coupled to a first node, the first node being subjected to a first AC signal; and a processing circuit including a third pad, A third pad isolation component spaced apart from the third pad, a fourth pad, a third pad isolation component spaced apart from the fourth pad, a first compensation capacitor whose first end is coupled to the third pad, a second compensation capacitor whose first end is coupled to the fourth pad, and a detection circuit coupled to the third pad and the fourth pad, wherein the first pad is coupled to the third pad, the second pad is coupled to the fourth pad, the third pad isolation component, the fourth pad isolation component, the second end of the first compensation capacitor and the second end of the second compensation capacitor are coupled to a second node, which is subjected to a second AC signal that is in phase and has the same frequency as the first AC signal.

[0006] Compared with the prior art, the present invention has the following technical effects:

[0007] This invention utilizes the parasitic capacitance of the third and fourth pads to compensate for the common-mode capacitance. This not only reduces the capacitance of the first and second compensation capacitors but also lowers the parasitic capacitance at the input of the detection circuit, thereby improving the sensitivity of the accelerometer. [Attached Image Description]

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0009] Figure 1 This is a circuit diagram of a capacitive MEMS accelerometer.

[0010] Figure 2 for Figure 1 The differential capacitance of the capacitive MEMS accelerometer and the single-sided equivalent circuit of the input stage in the analog-to-digital converter;

[0011] Figure 3 for Figure 1 A circuit diagram showing the common-mode current introduced by the common-mode capacitor of the capacitive MEMS accelerometer flowing into the input stage of the analog-to-digital converter.

[0012] Figure 4 This is a circuit diagram showing how to cancel the common-mode current of a capacitive MEMS accelerometer by using a compensation capacitor attached to the input stage of the analog-to-digital converter.

[0013] Figure 5 This is a circuit diagram showing that only the differential small-signal current representing the acceleration signal flows into the input stage of the analog-to-digital converter.

[0014] Figure 6 This is a circuit diagram of the capacitive MEMS accelerometer of the present invention in one embodiment;

[0015] Figure 7 This is a circuit diagram of another embodiment of the capacitive MEMS accelerometer of the present invention.

Detailed Implementation Methods

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. Unless otherwise specified, the terms "connected," "linked," and "connected" used herein to indicate electrical connection refer to direct or indirect electrical connection.

[0018] In this invention, unless otherwise specified, terms such as connection, link, interlock, and coupling, which indicate electrical connection, refer to direct or indirect electrical connection. For example, A and B being connected can be a direct connection or an indirect connection through an intermediate medium. This intermediate medium can be a basic electrical component (resistor, capacitor, inductor, switch, transistor, etc.) or a resistor with a specific function, such as a filter or amplifier. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0019] Figure 1 This is a circuit diagram of a capacitive MEMS accelerometer. (Example:) Figure 1 As shown, the capacitive MEMS accelerometer includes a MEMS device 110 and a processing circuit 120.

[0020] The MEMS device 110 includes a first differential capacitor C0p, a first pad 111 coupled to a first end of the first differential capacitor C0p, a first pad isolation component 113 spaced apart from the first pad 111, a second differential capacitor C0n, a second pad 112 coupled to a first end of the second differential capacitor C0n, and a second pad isolation component 114 spaced apart from the second pad 112. The second ends of the first differential capacitor C0p and the second differential capacitor C0n are coupled to a first node A. A first AC signal is applied to the first node A. The first pad 111 and the first pad isolation component 113 form the parasitic capacitance Cpadp of the first pad 111, and the second pad 112 and the second pad isolation component 114 form the parasitic capacitance Cpadn of the second pad 112. Figure 1 In the circuit diagram, parasitic capacitances Cpadp and Cpadn are also shown.

[0021] The processing circuit 120 is an ASIC (Application Specific Integrated Circuit) circuit, which includes a third pad 121, a third pad isolation component 123 spaced apart from the third pad 121, a fourth pad 122, a fourth pad isolation component 124 spaced apart from the fourth pad 122, a first compensation capacitor Cofsp with its first end coupled to the third pad 121, a second compensation capacitor Cofsn with its first end coupled to the fourth pad 122, and a detection circuit 125 coupled to the third pad 121 and the fourth pad 122. The third pad 121 and the third pad isolation component 123 form the parasitic capacitance of the third pad 121, and the fourth pad 122 and the fourth pad isolation component 124 form the parasitic capacitance of the fourth pad 122.

[0022] The first pad 111 is coupled to the third pad 121 via lead 130, and the second pad 112 is coupled to the fourth pad 122 via lead 130. The first pad isolation component 113, the second pad isolation component 114, the third pad isolation component 123, and the fourth pad isolation component 124 are grounded. The second terminal of the first compensation capacitor Cofsp and the second terminal of the second compensation capacitor Cofsn are coupled to a second node B, which is subjected to a second AC signal that is in phase and at the same frequency as the first AC signal. The MEMS device 110 is disposed on the first chip, and the processing circuit 120 is disposed on the second chip. The pads used in this text can also be referred to as spacers or PADs.

[0023] The detection circuit 125 includes an analog-to-digital converter (ADC), which includes a signal amplifier as an input stage. The signal amplifier may also be positioned before the ADC.

[0024] The MEMS device 110 includes a movable mass block, upon which a first differential capacitor C0p and a second differential capacitor C0n are formed, forming a differential capacitor pair. When the mass block moves, the capacitances of the first differential capacitor C0p and the second differential capacitor C0n change in opposite directions. The capacitance of the differential capacitor pair is determined based on the capacitance difference between the first differential capacitor C0p and the second differential capacitor C0n. When acceleration is applied, the mass block moves, causing the capacitances of the first differential capacitor C0p and the second differential capacitor C0n to change in opposite directions, thereby changing the capacitance of the differential capacitor pair. The analog-to-digital converter (ADC) can detect the change in capacitance of the differential capacitor pair and thus obtain the value of the acceleration.

[0025] Figure 2 for Figure 1 The differential capacitance of the capacitive MEMS accelerometer and the single-sided equivalent circuit of the input stage in the analog-to-digital converter, wherein the input stage is a signal amplifier. Figure 2 As shown, the input parasitic capacitance Cp of the signal amplifier includes the output parasitic capacitance of the MEMS device 110, the equivalent parasitic capacitance introduced by the third pad and the fourth pad, and the parasitic capacitance of the processing circuit 120, etc.

[0026] The first node A is given a first AC signal as a carrier. When a low-frequency acceleration signal is applied to the mass block of the MEMS device 110, the capacitance value of the differential capacitor pair will change, and a differential current will flow into the input stage of the analog-to-digital converter (ADC). The ADC can then obtain the value of the acceleration signal.

[0027] However, as Figure 3 As shown, it is Figure 1The diagram illustrates the circuit diagram of a capacitive MEMS accelerometer where the common-mode capacitor introduces a common-mode current that flows into the input stage of the analog-to-digital converter (ADC). The differential capacitor pair always has a portion of its capacitance as a constant common-mode capacitor (C0). Even without an acceleration signal, this common-mode capacitor introduces a common-mode current signal into the ADC. This common-mode current is typically large, causing saturation of the ADC's input stage, thus preventing the detection of acceleration signals.

[0028] To counteract the common-mode current, a pair of compensation capacitors with a capacitance value approximately equal to that of the common-mode capacitor (C0) is connected externally to the input of the analog-to-digital converter (ADC). Specifically, a first compensation capacitor Cofsp and a second compensation capacitor Cofsn are coupled to the input of the ADC. The capacitance values ​​of the first compensation capacitor Cofsp and the second compensation capacitor Cofsn are determined based on the capacitance value of the common-mode capacitor C0. A second AC signal (Anti-phase pulses) with the same frequency but opposite direction to the first AC signal is applied to one end of the first compensation capacitor Cofsp and the second compensation capacitor Cofsn to counteract the common-mode input current. Figure 4 This is a circuit diagram showing how to cancel the common-mode current of a capacitive MEMS accelerometer by using a compensation capacitor attached to the input stage of the analog-to-digital converter.

[0029] After eliminating the common-mode current, only the differential small-signal current containing acceleration information flows into the analog-to-digital converter (ADC), thus avoiding saturation of the input stage of the ADC. Figure 5 This is a circuit diagram showing that only the differential small-signal current representing the acceleration signal flows into the input stage of the analog-to-digital converter.

[0030] However, for Figure 5 The differential small signal in the circuit, the single-sided equivalent circuit diagram of the input stage of the analog-to-digital converter (ADC) and Figure 2 The same, that is, the first compensation capacitor Cofsp or the second compensation capacitor Cofsn is equivalent to Figure 2 A portion of the parasitic capacitance Cp input to the signal amplifier in the circuit is equal to the common-mode capacitance C0, while the other portion of the parasitic capacitance Cp is... Figure 1 The parasitic capacitance from each pad (PAD) to ground is Cp = C0 + Cpad, where Cpad includes the parasitic capacitances of the first, second, third, and fourth pads. The presence of parasitic capacitance Cp increases the noise at the output of the signal amplifier in the input stage, and the capacitance values ​​of the compensation capacitors Cofsp or Cofsn used to compensate for common-mode capacitance also need to be set relatively large, increasing the size of the processing circuit.

[0031] To overcome the aforementioned technical problems, this invention further proposes an improved capacitive MEMS accelerometer. For example... Figure 6 The diagram shown is a circuit schematic of the capacitive MEMS accelerometer of the present invention in one embodiment.

[0032] Figure 6 Capacitive MEMS accelerometers and Figure 1 The capacitive MEMS accelerometers shown are basically the same in structure, and the similarities will not be repeated here. The differences between the two are: Figure 6 The first pad isolation component 113 and the second pad isolation component 114 are grounded. The third pad isolation component 123, the fourth pad isolation component 124, the second terminal of the first compensation capacitor Cofsp, and the second terminal of the second compensation capacitor Cofsn are coupled to the second node B, which is subjected to a second AC signal that is in phase and at the same frequency as the first AC signal. This allows the parasitic capacitance of the third pad 121 and the first differential capacitor Cofsp to compensate for the common-mode capacitance C0, and the parasitic capacitance of the fourth pad 122 and the second differential capacitor Cofsn to compensate for the common-mode capacitance C0. In other words, the parasitic capacitance of the third pad 121 becomes part of the first differential capacitor Cofsp, and the parasitic capacitance of the fourth pad 122 becomes part of the second differential capacitor Cofsn. Compared to... Figure 1 In the proposed solution, the parasitic capacitances of the third pad 121 and the fourth pad 122 are used to cancel the common-mode capacitance C0. This reduces the size of the first differential capacitance Cofsp and the second differential capacitance Cofsn, thereby saving area in the processing circuit 120. Furthermore, the overall input parasitic capacitance Cp of the signal amplifier is reduced, which reduces the output noise of the signal amplifier caused by the parasitic capacitance Cp, thereby improving the sensitivity of the accelerometer.

[0033] In another embodiment, to overcome the above-mentioned technical problems, the present invention also proposes an improved capacitive MEMS accelerometer. For example... Figure 7 The diagram shown is a circuit schematic of another embodiment of the capacitive MEMS accelerometer of the present invention.

[0034] Figure 7 Capacitive MEMS accelerometers and Figure 1 The capacitive MEMS accelerometers shown are basically the same in structure, and the similarities will not be repeated here. The differences between the two are: Figure 7The first pad isolation component 113, the second pad isolation component 114, the third pad isolation component 123, the fourth pad isolation component 124, the second terminal of the first compensation capacitor Cofsp, and the second terminal of the second compensation capacitor Cofsn are all coupled to the second node B, which is subjected to a second AC signal that is in phase and at the same frequency as the first AC signal. This allows the parasitic capacitance of the first pad 111, the parasitic capacitance of the third pad 121, and the first differential capacitor Cofsp to compensate for the common-mode capacitance C0, and the parasitic capacitance of the second pad 112, the parasitic capacitance of the fourth pad 122, and the second differential capacitor Cofsn to compensate for the common-mode capacitance C0. That is, the parasitic capacitances of the first pad 111 and the third pad 121 become part of the first differential capacitor Cofsp, and the parasitic capacitances of the second pad 112 and the fourth pad 122 become part of the second differential capacitor Cofsn. Compared to... Figure 1 The proposed solution utilizes the parasitic capacitances of the first pad 111, the third pad 121, the second pad 112, and the fourth pad 122 to offset the common-mode capacitance C0. This allows for further reduction of the first differential capacitance Cofsp and the second differential capacitance Cofsn, thereby saving area in the processing circuit 120. Furthermore, the overall input parasitic capacitance Cp of the signal amplifier is further reduced, thus decreasing the output noise of the signal amplifier caused by the parasitic capacitance Cp and improving the sensitivity of the accelerometer.

[0035] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0036] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications and variations to the above embodiments within the scope of the present invention.

Claims

1. A capacitive MEMS accelerometer, characterized in that, It includes: The MEMS device includes a first differential capacitor, a first pad coupled to a first end of the first differential capacitor, a first pad isolation component spaced apart from the first pad, a second differential capacitor, a second pad coupled to a first end of the second differential capacitor, and a second pad isolation component spaced apart from the second pad. The second end of the first differential capacitor and the second end of the second differential capacitor are coupled to a first node, and a first AC signal is applied to the first node. The processing circuit includes a third pad, a third pad isolation component spaced apart from the third pad, a fourth pad, a fourth pad isolation component spaced apart from the fourth pad, a first compensation capacitor whose first end is coupled to the third pad, a second compensation capacitor whose first end is coupled to the fourth pad, and a detection circuit coupled to the third pad and the fourth pad. The first pad is coupled to the third pad, and the second pad is coupled to the fourth pad. The third pad isolation component, the fourth pad isolation component, the second terminal of the first compensation capacitor, and the second terminal of the second compensation capacitor are coupled to the second node, which is subjected to a second AC signal that is in phase but at the same frequency as the first AC signal. The first differential capacitor and the second differential capacitor form a differential capacitor pair. The differential capacitor pair includes a fixed common-mode capacitor. The capacitance values ​​of the first compensation capacitor and the second compensation capacitor are determined based on the capacitance value of the common-mode capacitor. The parasitic capacitance of the first compensation capacitor and the third pad is used to compensate for the common-mode capacitance; the parasitic capacitance of the second compensation capacitor and the fourth pad is used to compensate for the common-mode capacitance; or... The first compensation capacitor, the parasitic capacitance of the first pad, and the parasitic capacitance of the third pad are used to compensate for the common-mode capacitance. The second compensation capacitor, the parasitic capacitance of the second pad, and the parasitic capacitance of the fourth pad are also used to compensate for the common-mode capacitance.

2. The capacitive MEMS accelerometer according to claim 1, characterized in that, The first pad isolation component and the second pad isolation component are coupled to ground or to the second node.

3. The capacitive MEMS accelerometer according to claim 1, characterized in that, The MEMS device is disposed on the first chip, the processing circuit is disposed on the second chip, and the first compensation capacitor and the second compensation capacitor are disposed within the second chip. The first pad is coupled to the third pad via a lead, and the second pad is coupled to the fourth pad via a lead.

4. The capacitive MEMS accelerometer according to claim 1, characterized in that, The detection circuit includes an analog-to-digital converter, which includes a signal amplifier as an input stage.

5. The capacitive MEMS accelerometer according to claim 1, characterized in that, The MEMS device includes a movable mass block, upon which a first differential capacitor and a second differential capacitor are formed. The first differential capacitor and the second differential capacitor form a differential capacitor pair. After the mass block moves, the capacitances of the first differential capacitor and the second differential capacitor change in opposite directions. The capacitance of the differential capacitor pair is determined based on the capacitance difference between the first differential capacitor and the second differential capacitor. When acceleration is applied, the mass block moves, causing the capacitances of the first differential capacitor and the second differential capacitor to change in opposite directions, thereby causing the capacitance of the differential capacitor pair to change.

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