Backlight source and display device

Abstract

The present application provides a backlight source and a display device. The present application includes a signal input line, a signal output line, a plurality of light control lines, and pairs of signal input pads, signal output pads, and a plurality of light control pads arranged in the same layer through the circuit layer. The plurality of light control pads are respectively located at the plurality of ends of the drive chip close to the light-emitting unit. The signal input line and the signal output line are located between the light control pads and are used to transmit signals to the drive chip. It is only necessary to change the layer layout of the pins of the drive chip on the market without re-laying the drive chip itself to meet the requirements of a single-layer metal line. The cost is low, and there is no yield issue such as short circuit between different metal layers.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a backlight source and a display device. Background Art

[0002] Mini LED (mini light emitting diode), also known as "sub-millimeter light emitting diode", refers to LED with a grain (chip) size of 50 microns to 200 microns. Applications include Mini LED display screens and LCDs using Mini LED backlight screens. Since Mini LED display screens have excellent performance in terms of energy consumption, color gamut, contrast, etc., and the process difficulty is not as great as Micro LED, Mini LED is expected to become the leading product for LCD upgrades.

[0003] The existing backlight products on the market are all based on two or more layers of metal routing. Two or more layers of metal routing will cause problems such as short circuits between different metal layers and high costs. The channels of existing driver ICs on the market are not compatible with single-layer metal designs.

[0004] Therefore, there is an urgent need to solve the problems of short circuits between different metal layers of the above-mentioned backlight products and high costs. Summary of the invention

[0005] The embodiments of the present application provide a backlight source and a display device to solve the problems of short circuits between different metal layers and high cost in the prior art backlight products.

[0006] The present application provides a backlight source, the backlight source comprising:

[0007] substrate;

[0008] A circuit layer is disposed on the substrate;

[0009] A plurality of light emitting units are arranged in an array on the circuit layer; and

[0010] A driver chip is arranged on the circuit layer and located between adjacent light-emitting units, and is used to drive the light-emitting units to emit light; wherein the circuit layer includes a signal input wiring, a signal output wiring, a plurality of light-control wirings and corresponding signal input pads, signal output pads and a plurality of light-control pads arranged on the same layer, the signal input wiring is connected to the signal input pad, the signal output wiring is connected to the signal output pad, the light-control wiring is connected to the light-control pad, the signal input pad, the signal output pad and the light-control pad are respectively connected to the driver chip, the plurality of light-control pads are respectively located at a plurality of ends of the driver chip close to the light-emitting units, the signal input wiring and the signal output wiring are located between the light-control pads, and are used to transmit signals to the driver chip;

[0011] The backlight source further includes a plurality of partitions, the plurality of partitions are arranged in a plurality of columns, the circuit layer further includes a ground trace and an auxiliary ground trace, and the end of the ground trace of the last partition in at least one column of the partitions is connected to the auxiliary ground trace.

[0012] In some embodiments of the backlight source of the present application, the circuit layer also includes: data routing and data pads connected to the data routing, wherein the data pads are arranged between the multiple light control pads, and the data routing and the multiple light control routings, the signal input routing and the signal output routing are all arranged on the same layer, and the signal input routing and the signal output routing are located on the same extension line.

[0013] In the backlight source of some embodiments of the present application, the data wiring and the plurality of light-control wirings, the signal input wiring and the signal output wiring are not intertwined with each other.

[0014] In the backlight source of some embodiments of the present application, the circuit layer also includes: a power line, and a power pad connected to the power line, wherein the power pad is arranged between the multiple light control pads, and the power line and the multiple light control lines, the signal input line and the signal output line are all arranged on the same layer.

[0015] In the backlight source of some embodiments of the present application, the power supply line and the plurality of light control lines, the signal input line and the signal output line are not intertwined with each other.

[0016] In some embodiments of the backlight source of the present application, the circuit layer also includes: a ground pad connected to the ground trace, each of the partitions is in the shape of a quadrilateral, including 4 light-emitting units, and respectively distributed at the four corners of the partition, each of the partitions includes 4 light-control pads, and the 4 light-control pads define a quadrilateral pad area, and the ground pad, the signal input pad and the signal output pad are all arranged in the pad area.

[0017] In the backlight source of some embodiments of the present application, the ground pad, the signal input pad and the signal output pad are all disposed between the plurality of light control pads.

[0018] In the backlight source of some embodiments of the present application, the signal output wiring of the last partition of the first column is connected to the signal input wiring of the last partition of the second column.

[0019] In the backlight source of some embodiments of the present application, the circuit layer includes high-potential traces, each of which is located between adjacent light-emitting units and is simultaneously connected to the other end of the light-emitting unit.

[0020] On the other hand, the present application provides a display device, characterized in that the display device includes any of the backlight sources described above, and a liquid crystal display panel arranged on the backlight source.

[0021] This application has at least the following advantages:

[0022] The backlight source and the display device provided by the present application include a signal input line, a signal output line, a plurality of light control lines and corresponding signal input pads, signal output pads and a plurality of light control pads arranged on the same layer through the circuit layer. The plurality of light control pads are respectively located at the plurality of ends of the driver chip close to the light-emitting unit. The signal input line and the signal output line are located between the light control pads for transmitting signals to the driver chip. It is only necessary to change the design of the existing driver chip pins on the market without redesigning the driver chip itself to meet the requirements of a single-layer metal line. The cost is low and there is no yield problem such as short circuit between different metal layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1is a schematic diagram of the structure of a backlight source provided in an embodiment of the present application;

[0025] Figure 2 It is a structural schematic diagram of a substrate and a circuit layer provided in an embodiment of the present application;

[0026] Figure 3 It is a schematic diagram of the structure of the partition provided in the embodiment of the present application;

[0027] Figure 4 is a schematic diagram of the circuit layer structure in the partition provided in an embodiment of the present application;

[0028] Figure 5 yes Figure 3 Schematic diagram of the cross-sectional structure of the partition along the AA line;

[0029] Figure 6 is a schematic diagram of a circuit layer structure in a partition provided by another embodiment of the present application;

[0030] Figure 7 is a schematic diagram of a circuit layer structure in a partition provided by another embodiment of the present application;

[0031] Figure 8 is a schematic structural diagram of a backlight source provided by another embodiment of the present application;

[0032] Fig. 9 is a schematic diagram of the structure of a backlight source provided by another embodiment of the present application; and

[0033] Fig.10 It is a schematic diagram of the structure of the display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0035] Please refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 ,in, Figure 2 , Figure 4The driver chip DU is not shown in the figure so that the wiring under the driver chip DU can be clearly presented in the figure. An embodiment of the present application provides a backlight source 100, which includes a substrate SB, a circuit layer CL, a plurality of light-emitting units LU and a driver chip DU. The circuit layer CL is disposed on the substrate SB; a plurality of light-emitting units LU are arrayed on the circuit layer CL; the driver chip DU is disposed on the circuit layer CL, includes a plurality of pins PN and is located between adjacent light-emitting units LU, so as to drive the light-emitting units LU to emit light; wherein the circuit layer CL includes a signal input wiring DIL, a signal output wiring DOL, a plurality of light control wirings OL and corresponding signal input pads DIP, a signal output pad DOP and a plurality of light control pads OP disposed on the same layer, and the signal input wiring DIL is connected to the signal output wiring DOL and the plurality of light control wirings OL. The signal input pad DIP is connected to the signal output wiring DOL and the signal output pad DOP, the light control wiring OL is connected to the light control pad OP, the signal input pad DIP, the signal output pad DOP and the light control pad OP are respectively connected to the driver chip DU, a plurality of the light control pads OP are respectively located at a plurality of ends of the driver chip DU close to the light-emitting unit LU, the signal input wiring DIL and the signal output wiring DOL are located between the light control pads OP, and are used to transmit signals to the driver chip DU.

[0036] Specifically, the plurality of light-controlling lines OL, the grounding lines GL, the signal input lines DIL, and the signal output lines DOL are all arranged on the same layer, for example, a metal copper film arranged on the substrate SB is exposed and developed to form the pattern of the plurality of light-controlling lines OL, the grounding lines GL, the signal input lines DIL, and the signal output lines DOL. The requirements of a single-layer metal line can be met, the cost is low, and there is no yield problem such as short circuit between different metal layers.

[0037] In the backlight source of some embodiments of the present application, the circuit layer CL includes high potential wirings HL, each of which is located between adjacent light emitting units LU and is connected to the other end of the light emitting unit LU.

[0038] For details, please refer to Figure 1 , Figure 2 , Figure 3 and Figure 4The ground pad GP, the signal input pad DIP and the signal output pad DOP are all arranged between the multiple light-control pads OP, so that the multiple light-control pads OP are located at the outermost side of the pad area PA. Therefore, the wiring required by the driver chip DU arranged between the multiple light-emitting units LU, such as the ground wiring GL, the signal input wiring DIL and the signal output wiring DOL, can be arranged between two adjacent columns of light-emitting units LU and directly pulled out from the fan-out area FA to the edge of the substrate SB, and will not be intertwined with the light-control wiring OL or the high-potential wiring HL required by the light-emitting unit LU, which can meet the requirements of a single-layer metal wiring, has a low cost, and does not have yield problems such as short circuits between different metal layers.

[0039] Specifically, the backlight source 100 uses a semiconductor component as a light-emitting unit LU. In the backlight source of some embodiments of the present application, the light-emitting unit LU is a mini light-emitting diode (mini Light Emitting Diode, mini-LED). In other embodiments, the light-emitting unit LU is a light-emitting diode (Light Emitting Diode, LED), an organic light-emitting diode (Organic Light Emitting Diode, OLED) or a micro light-emitting diode (Micro Light Emitting Diode, micro-LED), etc., but the present application is not limited thereto. The number of light-emitting components such as mini-LED or micro-LED in the light-emitting unit LU is at least one, and can also be one of two lamps, four lamps, six lamps, eight lamps, ten lamps, twelve lamps, fourteen lamps, sixteen lamps, etc. Multiple light-emitting components can be connected in series, or first connected in series and then in parallel to form multiple rows of light-emitting components, but the present application is not limited thereto. The distance between each lamp is also not limited.

[0040] Specifically, the material of the substrate SB includes glass, a printed circuit board (PCB) or a BT resin board (Bismaleimide Triazine, BT).

[0041] For details, please refer to Figure 5, the circuit layer CL is arranged on the substrate SB. The light-emitting unit LU and the driving chip DU are arranged on the circuit layer CL. The driving chip DU is a ball grid array package (Ball Grid Array, BGA), a lead frame package (Lead Frame), a surface mount device package (Surface Mounted Devices package, SMD package) or other packaging methods. The figures of this application all take the ball grid array package as an example, but this application is not limited to this. Specifically, the multiple pins PN of the driving chip DU refer to the pins (Pin) in the lead frame package or the solder balls in the ball grid array package. Specifically, the package size of the driving chip DU is less than 1500μm*1500μm.

[0042] Specifically, the signal input wiring DIL is used to provide the driver chip DU with the brightness data and the corresponding address data of each light emitting unit LU required by each light emitting unit LU, and transmits the signal to the driver chip DU of the next partition MD through the signal output wiring DOL in a cascade manner.

[0043] Please refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 In some embodiments of the backlight source 100 of the present application, the circuit layer CL further includes: data lines DL and data pads DP connected to the data lines DL.

[0044] Specifically, the data line DL is used to provide the driver chip DU with pulse width modulation (PWM), address data or scanning signal, etc., depending on the design of the driver chip DU, and the present application is not limited thereto. The data pad DP is arranged between the multiple light control pads OP, and the data line DL and the multiple light control lines OL, the signal input line DIL and the signal output line DOL are all arranged on the same layer, and one of the multiple pins PN of the driver chip DU contacts the data pad DP. The signal input line DIL and the signal output line DOL are located on the same extension line.

[0045] Specifically, another data structure of the signal input line DIL, the signal output line DOL and the data line DL is a daisy chain structure. The address is transmitted through the signal input line DIL and the signal output line DOL, and the brightness data is transmitted to all driving chips DU at the same time through the data line DL. The present application is not limited to this.

[0046] In the backlight source 100 of some embodiments of the present application, the data line DL and the plurality of light control lines OL, the signal input line DIL, and the signal output line DOL are not interlaced with each other. Specifically, the data line DL, the plurality of light control lines OL, the signal input line DIL, and the signal output line DOL are used to transmit different signals, and therefore must be insulated from each other. Since the data line DL, the plurality of light control lines OL, the signal input line DIL, and the signal output line DOL are all disposed on the same metal layer, the lines are not interlaced with each other.

[0047] In the backlight source 100 of some embodiments of the present application, the circuit layer CL further includes: a power line PL and a power pad PP connected to the power line PL.

[0048] Specifically, the power line PL is used to provide the power required for the operation of the driver chip DU. The power pad PP is arranged between the plurality of light control pads OP, and the power line PL and the plurality of light control lines OL, the signal input line DIL and the signal output line DOL are all arranged on the same layer, and one of the plurality of pins PN of the driver chip DU contacts the power pad PP.

[0049] In the backlight source 100 of some embodiments of the present application, the power line PL and the plurality of light-control lines OL, the signal input line DIL, and the signal output line DOL are not intertwined with each other.

[0050] In the backlight source 100 of some embodiments of the present application, the circuit layer CL further includes a ground line GL and a ground pad GP connected to the ground line GL, and the backlight source further includes a plurality of partitions MD.

[0051] Specifically, the present application does not limit the shape of the partition MD, and the number and distribution position of the multiple light-emitting units LU in each partition MD. In the backlight source 100 of some embodiments of the present application, each partition MD is in the shape of a quadrilateral, including 4 light-emitting units LU, and respectively distributed at the four corners of the partition MD, each partition MD includes 4 light-control pads OP, and the 4 light-control pads OP define a quadrilateral pad area PA, and the ground pad GP, the signal input pad DIP, and the signal output pad DOP are all arranged in the pad area PA.

[0052] For details, please refer to Figure 3 , Figure 4In the pad area PA of the embodiment of the present application, 10 pads are arranged in two rows, which are 2 rows × 5 columns, wherein the four corners of the pad area PA are the four light control pads OP, the signal input pad DIP and the signal output pad DOP are in the same column, and the positions of the other power pads PP, ground pads GP, vacant pads NP, and data pads DP can be interchanged, and their corresponding routing designs need to be replaced synchronously when interchanged. Specifically, in the pad area PA of the present embodiment, the upper row from left to right is the light control pad OP, the power pad PP, the signal input pad DIP, the ground pad GP, and another light control pad OP. The lower row from left to right is: the light control pad OP, the vacant pad NP, the signal output pad DOP, the data pad DP, and another light control pad OP. Among them, the power pad PP, the signal input pad DIP, the ground pad GP, the vacant pad NP, the signal output pad DOP, and the data pad DP are all arranged between the four light control pads OP, so that the wiring connecting the power pad PP, the signal input pad DIP, the ground pad GP, the vacant pad NP, the signal output pad DOP, and the data pad DP can be concentrated between adjacent light-emitting units LU, and the wiring is directly pulled out from the fan-out area FA to the edge of the substrate SB, and will not be intertwined with the light control wiring OL or the high-potential wiring HL required by the light-emitting unit LU, which can meet the requirements of a single-layer metal wiring, has a low cost, and does not have yield problems such as short circuits between different metal layers.

[0053] Specifically, the present application does not limit the package pins, pin naming and pin functions of the driver chip DU. Specifically, the shapes of each pad, such as round, square, rectangular, etc., are also not limited in the present application.

[0054] For details, please refer to Figure 6In the pad area PA' of the partition MD' of another embodiment of the present application, a plurality of pads are arranged in two rows. The upper row is, from left to right, a light control pad OP, a signal input pad DIP, a power pad PP, a ground pad GP and another light control pad OP. The lower row is, from left to right, a light control pad OP, a signal output pad DOP, a vacant pad NP, a data pad DP and another light control pad OP. In conjunction with the corresponding plurality of light control lines OL, power lines PL, ground lines GL, signal input lines DIL, signal output lines DOL and data lines DL, different circuit layers CL' are formed. The circuit of the driver chip DU' itself does not need to be redesigned, and only the pins of the package need to be changed accordingly. Among them, the power pad PP, signal input pad DIP, ground pad GP, vacant pad NP, signal output pad DOP, and data pad DP of the circuit layer CL' are all arranged between four light control pads OP, so that the wiring connecting the power pad PP, signal input pad DIP, ground pad GP, vacant pad NP, signal output pad DOP, and data pad DP can be concentrated between adjacent light-emitting units LU, and the wiring is directly pulled out from the fan-out area FA to the edge of the substrate SB, and will not be intertwined with the light control wiring OL or high-potential wiring HL required by the light-emitting unit LU, which can meet the requirements of single-layer metal wiring, has low cost, and does not have yield problems such as short circuits between different metal layers.

[0055] For details, please refer to Figure 7 In the pad area PA" of the partition MD" of another embodiment of the present application, multiple pads are arranged in two rows, and the upper row is, from left to right, a light control pad OP, a power pad PP, a ground pad GP, a signal input pad DIP and another light control pad OP. The lower row is, from left to right, a light control pad OP, a vacant pad NP, a data pad DP, a signal output pad DOP and another light control pad OP. In conjunction with the corresponding multiple light control lines OL, power lines PL, ground lines GL, signal input lines DIL, signal output lines DOL and data lines DL, different circuit layers CL" are formed. The circuit of the driver chip DU" itself does not need to be redesigned, and only the pins of the package need to be changed accordingly. Among them, the power pad PP, signal input pad DIP, ground pad GP, vacant pad NP, signal output pad DOP, and data pad DP of the circuit layer CL" are all arranged between the four light control pads OP, so that the wiring connecting the power pad PP, signal input pad DIP, ground pad GP, vacant pad NP, signal output pad DOP, and data pad DP can be concentrated between adjacent light-emitting units LU, and the wiring is directly pulled out from the fan-out area FA to the edge of the substrate SB, and will not be intertwined with the light control wiring OL or high-potential wiring HL required by the light-emitting unit LU, which can meet the requirements of single-layer metal wiring, has low cost, and does not have yield problems such as short circuits between different metal layers.

[0056] Please refer to Figure 8 In some embodiments of the present application, in the backlight source 100', the plurality of partitions MD 11 ,MD 12 ...arranged into multiple columns C1, C2..., the circuit layer CL also includes an auxiliary grounding line AGL, the last partition (e.g. MD) of each column of the partition (e.g. C1) 1N )'s end of the ground line GL is connected to the auxiliary ground line AGL.

[0057] Specifically, when a relatively close arrangement of the light-emitting units LU results in insufficient routing width between the light-emitting units LU, the width of the grounding routing GL can be reduced to make way for other routings, and the design of the auxiliary grounding routing AGL is additionally adopted to improve the voltage drop or voltage instability caused by the insufficient width of the grounding routing GL. The auxiliary grounding routing AGL includes a horizontal segment and two vertical segments, the vertical segments are parallel to the distribution direction of each column of the partition (e.g., C1) and are located at the edge of the substrate SB to provide voltage stabilization and shielding effects.

[0058] Please refer to Fig. 9 In some embodiments of the present application, in the backlight source 100 ″, the plurality of partitions MD 11 ,MD 12 ...arranged into multiple columns C1, C2..., where the last primary partition MD of the first column partition C1 1N The signal output trace DOL is connected to the last partition MD of the second row partition C2. 2N In this embodiment, since the last partition MD of the second row partition C2 2N The signal input trace DIL connects the last partition MD of the first row partition C1 1N The signal output line DOL, that is, the last partition MD of the second row partition C2 2N The brightness data required by the driver chip DU comes from the last partition MD of the first column partition C1. 1N The signal output line DOL of the driver chip DU is Figure 8 In the embodiment, the second column partition C2 of this embodiment does not need to set the signal input wiring DIL in the fan-out area FA, which can reduce the number of wirings in the fan-out area FA, save the space of the fan-out area FA, and reduce the design complexity of the fan-out area FA.

[0059] Please refer to Fig. 9 In some embodiments of the backlight source 100 of the present application, the last partition MD of the first column partition C1 1NThe power line PL is connected to the last partition MD of the second column partition C2 2N In this embodiment, the last partition MD of the second column partition C2 2N The operating voltage required by the driver chip DU comes from the last partition MD of the first column partition C1. 1N The power supply line PL of the driver chip DU is Figure 8 In the embodiment, the second column partition C2 of this embodiment does not need to set the power line PL in the fan-out area FA, which can reduce the number of lines in the fan-out area FA, save the space of the fan-out area FA, and reduce the design complexity of the fan-out area FA.

[0060] Please refer to Fig. 9 In some embodiments of the backlight source 100 of the present application, the last partition MD of the first column partition C1 1N The data line DL is connected to the last partition MD of the second column partition C2. 2N In this embodiment, the last partition MD of the second column partition C2 2N The signal required by the driver chip DU comes from the last partition MD of the first row partition C1. 1N The data line DL of the driver chip DU is Figure 8 In the embodiment of the second column partition C2 of this embodiment, it is not necessary to set the data line DL in the fan-out area FA, which can reduce the number of lines in the fan-out area FA, save the space of the fan-out area FA, and reduce the design complexity of the fan-out area FA. Figure 8 In some embodiments of the present application, in the backlight source (eg, 100'), the plurality of partitions MD 11 ,MD 12 ...arranged into multiple columns C1, C2..., in each column of the partition (such as C1), the previous partition (such as MD 11 ) of the signal output line DOL to the next partition (such as MD 12 )’s signal input trace DIL.

[0061] Please refer to Fig.10On the other hand, the present application provides a display device 1000, characterized in that the display device 1000 includes any of the backlight sources described above, such as the backlight source 100, and a liquid crystal display panel 200 disposed on the backlight source 100. The backlight source 100 is used to provide the backlight required by the liquid crystal display panel 200. Specifically, the backlight source 100 also includes a backlight control unit B-con connected to the driver chip to provide brightness data, address data, PWM data, or scanning data required by the driver chip. The liquid crystal display panel 200 also includes a liquid crystal control unit T-con connected to the liquid crystal display panel 200 to control the liquid crystal display panel 200 to display. The backlight control unit B-con and the liquid crystal control unit T-con are both connected to an image signal source IS, and the liquid crystal control unit T-con is used to display the image data provided by the image signal source IS, while the backlight control unit B-con performs regional dimming in accordance with the image data provided by the image signal source IS.

[0062] The backlight source and the display device provided by the present application include a signal input line, a signal output line, a plurality of light control lines and corresponding signal input pads, signal output pads and a plurality of light control pads arranged on the same layer through the circuit layer. The plurality of light control pads are respectively located at the plurality of ends of the driver chip close to the light-emitting unit. The signal input line and the signal output line are located between the light control pads for transmitting signals to the driver chip. It is only necessary to change the design of the existing driver chip pins on the market without redesigning the driver chip itself to meet the requirements of a single-layer metal line. The cost is low and there is no yield problem such as short circuit between different metal layers.

[0063] The backlight source and the display device provided in the embodiments of the present application are introduced in detail above.

[0064] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A backlight source, characterized in that: The backlight source comprises: substrate; A circuit layer is disposed on the substrate; A plurality of light emitting units are arranged in an array on the circuit layer; and A driver chip is arranged on the circuit layer and located between adjacent light-emitting units to drive the light-emitting units to emit light; wherein the circuit layer includes a signal input wiring, a signal output wiring, a plurality of light-control wirings, a data wiring and corresponding signal input pads, a signal output pad, a plurality of light-control pads and a data pad arranged on the same layer, the signal input wiring is connected to the signal input pad, the signal output wiring is connected to the signal output pad, the light-control wiring is connected to the light-control pad, the data pad, the signal input pad, the signal output pad and the light-control pad are respectively connected to the driver chip, the plurality of light-control pads are respectively located at a plurality of ends of the driver chip close to the light-emitting units, the data pad is arranged between the plurality of light-control pads, the signal input wiring and the signal output wiring are located between the light-control pads, and are used to transmit signals to the driver chip; The backlight source further includes a plurality of partitions, the plurality of partitions are arranged in a plurality of columns, the circuit layer further includes a ground trace and an auxiliary ground trace, and the end of the ground trace of the last partition in each column of the partitions is connected to the auxiliary ground trace; The data wiring and the plurality of light control wirings, the signal input wiring and the signal output wiring are not interlaced with each other, and the signal input wiring and the signal output wiring are located on the same extension line; In a column of the partitions, a data line extends along the column direction of the partition and connects a plurality of data pads, and a light-control line is correspondingly connected to an end of the light-emitting unit close to the driving chip.

2. The backlight source according to claim 1, characterized in that: The circuit layer also includes: a power line and a power pad connected to the power line, wherein the power pad is arranged between the multiple light control pads, and the power line and the multiple light control lines, the signal input line and the signal output line are all arranged on the same layer.

3. The backlight source according to claim 2, characterized in that: The power supply wiring, the plurality of light control wirings, the signal input wiring and the signal output wiring are not intertwined with each other.

4. The backlight source according to claim 1, characterized in that: The circuit layer also includes: a ground pad connected to the ground trace, each of the partitions is in the shape of a quadrilateral, including 4 light-emitting units, and are respectively distributed at the four corners of the partition, each of the partitions includes 4 light-control pads, and the 4 light-control pads define a quadrilateral pad area, and the ground pad, the signal input pad and the signal output pad are all arranged in the pad area.

5. The backlight source according to claim 4, characterized in that: The ground pad, the signal input pad and the signal output pad are all arranged between the plurality of light control pads.

6. The backlight source according to claim 4, characterized in that: The signal output trace of the last partition of the first column partition is connected to the signal input trace of the last partition of the second column partition.

7. The backlight source according to claim 1, characterized in that: The circuit layer further includes a plurality of high potential wirings, each of which is located between adjacent light emitting units and is simultaneously connected to the other end of the light emitting unit.

8. A display device, characterized in that: The display device comprises the backlight source according to any one of claims 1 to 7, and a liquid crystal display panel arranged on the backlight source.

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