A multi-level parallelism development method for a multi-array coarse-grained reconfigurable architecture

Abstract

This invention discloses a multi-level parallelism development method for a coarse-grained reconfigurable architecture with multiple arrays, relating to the field of coarse-grained reconfigurable architecture compilers. The input C++ file is processed by Polygeist into an intermediate expression composed of the Affine dialect and the SCF dialect in MLIR. The task undergoes loop-level optimization and uses parallelism analysis and inter-array mapping algorithms to develop high-level task-level and data-level parallelism. Parallel information is stored in the CGRA dialect form, and the MLIR dialect is translated back into an edited C++ file containing parallel information. The edited C++ file is then processed by Clang to generate a low-level intermediate expression, and loop-level and instruction-level parallelism are developed using intra-array mapping algorithms. After integrating inter-array information, a configuration file is finally generated, completing the entire process. This invention reduces mapping complexity, develops multi-level parallelism, and effectively improves mapping performance; it is highly scalable and can be combined and collaborate with different intra-array mapping methods.

Description

Technical Field

[0001] This invention relates to the field of coarse-grained reconfigurable architecture compilers, and more particularly to a multi-level parallelism development method for multi-array coarse-grained reconfigurable architectures. Background Technology

[0002] Coarse-grained reconfigurable architecture (CGRA) is a type of accelerated architecture with high energy efficiency and good flexibility. Therefore, it is widely used in computationally intensive applications such as image processing, signal processing, and machine learning.

[0003] With the advent of the big data era, the scale of CGRA (Chip-on-a-Chip Array Replication) is also growing rapidly. However, due to the requirements for configuration speed, interconnection costs, and benefits, the scale of single-array CGRA is limited. Multi-array CGRA connects single-array CGRA through an on-chip interconnect structure, allowing different arrays to operate as independent entities. Figure 1 The typical architecture of a multi-array CGRA is shown, which includes M×N arrays (processing element arrays, PEAs). Each array interacts with the others via on-chip interconnects, such as network on chip or ring interconnects.

[0004] Different applications may contain different loop structures and dependencies, and there may be data interactions between each loop statement, where each loop can be considered an acceleration task. In a multi-array CGRA, each array can execute different tasks or different iterations within the same task. Each array contains several processing elements (PEs) and can perform computations using soft pipelining techniques. The compiler abstracts the loop kernel parts of different tasks in the program into a data flow graph (DFG) and maps it to different arrays and processing elements.

[0005] The compiler of the coarse-grained reconfigurable architecture will extract the loop kernel part of the accelerated program and abstract it into a data flow graph for mapping. The mapping will map each operator to the PE and generate the corresponding configuration information. Since the mapping of CGRA has been proven to be an NP-complete problem [1], many works have focused on how to improve the mapping speed and achieve higher performance by optimizing the mapping algorithm. [1] proposed EPIMap to transform the mapping problem into a homomorphic surjective problem of a graph and introduce a recalculation mechanism to reduce the use of duplicate resources. [2] proposed REGIMap based on EPIMap, and added the use of local registers inside the PE. [3] proposed MEMmap based on this, combined on-chip data memory in the consideration of the mapping problem and designed a memory management mechanism based on double buffering. [4] proposed RAMP takes into account various resources before mapping. [5] pointed out that time domain mapping (scheduling) should have higher priority, so the boundary between scheduling and mapping was redefined, and various resources were fully considered during scheduling to reduce the failure rate during mapping. Some other works will analyze the characteristics of the program and optimize it before mapping. [6] The proposed PolyMap uses polyhedral compilation to analyze the inter-loop mapping flow, adjusts the hierarchical structure of the loop kernel, and expands the inner loop to achieve parallelism. [7] Similarly, polyhedral models are used to represent the transformation process of the program, and genetic algorithms are used for loop transformation to improve efficiency. However, the algorithms mentioned above are mainly for single-layer abstraction of reconfigurable arrays. When the structure of reconfigurable arrays becomes complex (e.g., the execution mode of multiple arrays), single-layer abstraction will have a great obstacle in terms of hardware structure expression and mapping algorithm optimization. When facing programs with task-level parallelism, the current abstraction method will lose the extraction of this part of parallelism, resulting in insufficient performance development. In addition, since CGRA mapping is an NP-complete problem, the increase in the number of PEs also makes the mapping complexity increase rapidly.

[0006] In multi-array CGRA, different arrays can employ different parallel execution modes to enhance task-level parallelism performance. Multi-array CGRA executed in data-parallel mode uses k arrays to execute the same task simultaneously. Each array can execute {1, ..., N / k}, {N / k+1, ..., 2*N / k}... iterations of the task, i.e., executing a subtask of that task. Parallel execution reduces the number of iterations per array, significantly decreasing execution latency, but it increases the cost of data transfer between arrays. Only tasks without inter-iteration dependencies can be accelerated through parallel execution. Pipeline execution, compared to parallel execution, cannot reduce the latency of data flow execution, but it can reduce the execution time of each stage in the pipeline. Furthermore, pipeline execution does not have the same strict inter-iteration constraints as parallel execution.

[0007] Multi-array reconfigurable architectures can accelerate the entire application by combining parallel and pipelined execution methods. The entire program executes through a software pipeline, where each stage is derived from a task within the program through parallel or pipelined execution. For example... Figure 2 After parallel execution of tasks 1 and 2 and pipelined execution of task 3, the execution time of each stage in the pipelined execution of the entire program is reduced from 200, 300, 200 to 100, 100, 100. 202 in the figure is called the subtask dependence graph (SDG).

[0008] MLIR[8] is a compilation framework based on LLVM that includes multi-level intermediate expressions. Each level of intermediate expression adopts the expression form of single static assignment (SSA), which includes task-specific Operations to abstractly describe different computations. The Operation is also the smallest unit of code description. Each Operation receives several Operands and produces corresponding Results, which are connected through static single assignment. Operations can also be modified by Attributes that contain key information about the execution. Multiple consecutive Operations that do not contain control flow form a Block, and multiple Blocks and the control flow between them form a Region. An Operation can contain a Region, thus forming the representation of each level of intermediate expression.

[0009] Based on Operation, Block, Region, Attribute and Type, dialects of MLIR can be defined. Dialects can abstract common representations and improve reusability. MLIR itself has dialects defined for common operations such as loops, functions and mathematical calculations. Developers can also customize dialects according to different needs. Different dialects can be converted to each other, and different types of dialects can be mixed together. MLIR has been widely used in fields including FPGA[9], circuit design

[10] , machine learning

[11] and polyhedron optimization

[12] .

[0010] Existing CGRA compilers are primarily designed for single-array CGRA, mainly employing a single-level abstraction model. With advancements in hardware architecture, multi-array CGRA, offering higher computing power, has become a superior choice. This type of architecture features multi-layered hardware structures and interconnection methods, which traditional compilation methods cannot match, leading to insufficient parallelism and performance development, as well as excessively high mapping complexity.

[0011] Therefore, those skilled in the art are dedicated to developing a multi-level parallelism development method for a multi-array coarse-grained reconfigurable architecture, reducing mapping complexity, developing multi-level parallelism, and effectively improving mapping performance.

[0012] [1] M.Hamzeh, A.Shrivastava, and S.Vrudhula, "EPIMap: using epimorphism tomap applications on CGRAs," in Proceedings of the 49th Annual DesignAutomation Conference on-DAC'12, San Francisco, California, 2012, p.1284.doi:10.1145 / 2228360.2228600.

[0013] [2] M.Hamzeh, A.Shrivastava, and S.Vrudhula, “REGIMap: register-awareapplication mapping on coarse-grained reconfigurable architectures(CGRAs),” inProceedings of the 50th Annual Design Automation Conference on-DAC'13,Austin,Texas,2013,p.1.doi:10.1145 / 2463209.2488756.

[0014] [3] S.Yin, 2016,doi:10.1109 / TVLSI.2015.2474129.

[0015] [4]S.Dave,M.Balasubramanian,and A.Shrivastava,“RAMP:resource-awaremapping for CGRAs,”in Proceedings of the 55th Annual Design AutomationConference,San Francisco California,Jun.2018,pp.1–6.doi:10.1145 / 3195970.3196101.

[0016] [5]Z.Zhao et al.,“Towards Higher Performance and Robust Compilationfor CGRA Modulo Scheduling,”IEEE Trans.Parallel Distrib.Syst.,vol.31,no.9,pp.2201–2219,Sep.2020,doi:10.1109 / TPDS.2020.2989149.

[0017] [6]Liu,D.,Yin,S.,Peng,Y.,Liu,L.,&Wei,S.(2015).OptimizingSpatialMapping of Nested Loop for Coarse-Grained Reconfigurable Architectures.IEEETransactions on Very Large Scale Integration(VLSI)Systems,23(11),2581–2594.

[0018] [7]Ganser S, Armin,Siegmund N,et al.Speeding up IterativePolyhedral Schedule Optimization with Surrogate Performance Models[J].AcmTransactions on Architecture&Code Optimization,2018,15(4):1-27.

[0019] [8]Chris Lattner,Mehdi Amini,Uday Bondhugula,Albert Cohen,Andy Davis,Jacques Pienaar,River Riddle,Tatiana Shpeisman,Nicolas Vasilache,andOleksandr Zinenko.Mlir:A compiler infrastructure for the end of moore’slaw.arXiv preprint arXiv:2002.11054,2020.

[0020] [9]Hanchen Ye,Cong Hao,Jianyi Cheng,Hyunmin Jeong,Jack Huang,StephenNeuendorffer,and Deming Chen.Scalehls:A new scalable high-level synthesisframework on multi-level intermediate representation.In 2022 IEEEInternational Symposium on High-Performance Computer Architecture(HPCA),pages741–755.IEEE,2022.

[0021]

[10] Schuyler Eldridge,Prithayan Barua,Aliaksei Chapyzhenka,AdamIzraelevitz,Jack Koenig,Chris Lattner,Andrew Lenharth,George Leontiev,FabianSchuiki,Ram Sunder,et al.Mlir as hardware compiler infrastructure.In Workshopon Open-Source EDA Technology(WOSET),2021.

[0022]

[11] Ingo Lütkebohle.IREE:Intermediate representation executionenvironment.https: / / github.com / google / iree,2021.

[0023]

[12] William S Moses, Lorenzo Chelini, Ruizhe Zhao, and OleksandrZinenko. Polygeist: Raising c to polyhedral mlir. In 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 45–59. IEEE, 2021 Summary of the Invention

[0024] In view of the aforementioned deficiencies in the prior art, the technical problem to be solved by this invention is the lack of reasonable software abstraction in multi-array CGRAs, leading to insufficient parallelism and performance development and excessively high mapping complexity. This invention proposes a high-level intermediate representation design method and a multi-level compilation framework. Multi-level abstractions are established for the multi-level hardware structure, decoupling the inter-array mapping problem from the intra-array mapping problem, and performing optimizations at corresponding levels. Regarding the issue of parallelism development in multi-array CGRAs, this invention proposes performing loop-level optimization and inter-array mapping at the high-level intermediate representation level, selecting the optimal parallel execution mode, and developing task-level parallelism and data-level parallelism. Furthermore, it combines low-level intermediate representation optimization techniques to perform corresponding parallelism development at different levels of the program.

[0025] To achieve the above objectives, this invention provides a multi-level parallelism development method for a multi-array coarse-grained reconfigurable architecture, comprising the following steps:

[0026] Step 1: The C++ file input by the compiler is processed by Polygeist into an intermediate expression composed of the Affine dialect and the SCF dialect in MLIR;

[0027] Step 2: Optimize the task at the loop level and use parallelism analysis and inter-array mapping algorithms to develop high-level task-level parallelism and data-level parallelism;

[0028] Step 3: Store the parallel information in the CGRA dialect. The MLIR dialect will be translated back into an edited C++ file containing the parallel information.

[0029] Step 4: The edited C++ file is processed by Clang to generate low-level intermediate expressions, and loop-level parallelism and instruction-level parallelism are developed through the mapping algorithm within the array. After integrating the information between the arrays, the configuration file is finally generated to complete the entire process.

[0030] Furthermore, in step 2, during the loop-level optimization process, each task is traversed, and the size of the data flow graph of each task is analyzed based on the number of operators contained in each task. If the size of the data flow graph is smaller than the number of nodes in a single array, a loop unrolling method is used to increase the number of operators in the innermost loop to improve utilization.

[0031] Furthermore, in step 2, for each task in the input program, the program selects whether to perform parallel execution or pipelined execution, and selects different numbers of partitions to map each partitioned subtask.

[0032] Furthermore, in step 2, for all tasks, the number of subtasks that can be divided into and whether to use parallel or pipelined execution are calculated, and a subtask dependency graph is constructed based on the dependencies after division; an integer quadratic programming algorithm is used to model and solve the mapping relationship and select the optimal value.

[0033] Furthermore, the constraints that the integer quadratic programming needs to satisfy include task placement constraints, array placement constraints, partitioning constraints, routing constraints, and pipeline time constraints.

[0034] Furthermore, the objective of the integer quadratic programming is to minimize the execution time of the entire multi-array CGRA.

[0035] Furthermore, in step 3, the CGRA dialect is introduced in MLIR to represent the execution mode of each task as key information for inter-array mapping.

[0036] Furthermore, in step 3, the mode identifier in the CGRA dialect indicates whether the task is executed in parallel mode or pipeline mode, and the factor identifier specifies the number of partitions under mode execution, that is, the number of subtasks corresponding to the task; the two identifiers mode and factor together determine the execution mode of the task.

[0037] Furthermore, in step 3, the CGRA dialect, after translation, is marked at the beginning of the task with a preprocessed form starting with #pragma.

[0038] Furthermore, in step 4, the subtasks are mapped in the corresponding array, taking into account hardware resource constraints during the mapping process.

[0039] In a preferred embodiment of the present invention, a multi-level parallelism development scheme for a multi-array coarse-grained reconfigurable architecture is provided.

[0040] 1. Multi-level compilation process

[0041] The compiler's computation flowchart is as follows Figure 3As shown, the input C++ file is first processed by Polygeist[1] into an intermediate expression composed of the Affine dialect and SCF dialect in MLIR. Then, each task is analyzed at the loop level, and parallelism analysis and inter-array mapping algorithms are used to accelerate and map each task. After that, the relevant parameters are stored in the form of CGRA dialect. Different dialects in MLIR will be further translated back to C++ for identification. The edited C++ file is completed after Clang analysis and mapping within the array and a configuration file is generated.

[0042] 2. CGRA dialect representation

[0043] As shown in Figure 402, MLIR introduces the CGRA dialect to represent the execution mode of each task as key information for inter-array mapping. The `mode` flag in the dialect indicates whether the task is executed in parallel or pipeline mode, and the `factor` flag specifies the number of partitions under `mode` execution, i.e., the number of subtasks corresponding to the task. The `mode` and `factor` flags together determine the task's execution mode. The `idx` instruction contains a series of integers indicating the array index to which each subtask is mapped. After translation, the CGRA dialect becomes a preprocessed identifier starting with `#pragma` at the beginning of the corresponding task.

[0044] For example Figure 4 Task 1 is executed in a pipelined manner, with two subtasks mapped to arrays 1 and 2. Task 2 uses the same execution mode and number of subtasks, with its two subtasks mapped to arrays 3 and 4 respectively.

[0045] 3. High-level mapping

[0046] 3.1 Loop-level optimization

[0047] For small-scale tasks, directly mapping them to a single array leads to low resource utilization. Loop unrolling aggregates multiple iterative tasks, increasing resource utilization and reducing the total number of iterations. Furthermore, combining loop unrolling with pipelined or parallel execution as mentioned in Section 3.2.2 further improves task-level parallelism performance. During loop-level optimization, each task is traversed, and the size of the corresponding data flow graph is analyzed based on the number of operators in each task. If the corresponding data flow graph size is much smaller than the number of nodes in a single array, loop unrolling is first used to increase the number of operators in the innermost loop to improve utilization. The initial number of loop unrolls is... This number can be modified based on the success or failure of subsequent lower-level mappings.

[0048] 3.2 Parallelism Analysis and Inter-array Mapping

[0049] For each task in the input program, it can be executed in parallel or pipelined, and different numbers of partitions can be selected, with each partitioned subtask mapped. Each of these steps affects the final performance of the multi-array CGRA execution. The choice of appropriate acceleration strategy and the mapping of the partitioned results will influence subsequent outcomes.

[0050] For all tasks, we first calculate the number of possible subtasks into which they can be divided, and whether to use parallel or pipelined execution. Then, we construct a subtask dependency graph based on the dependencies after division. For each possible state, we use an integer quadratic programming algorithm to model and solve the mapping relationship and select the optimal value.

[0051] To better quantify the quadratic programming problem during modeling, the following variables are defined:

[0052] Mr ij The j-th subtask is mapped onto the i-th array.

[0053] Data transfer cost from i1 arrays to i2 arrays

[0054] te j : Execution time of the j-th subtask

[0055] st k :G s The set of all edges in the k-th stage

[0056] ts k Execution time of the kth stage

[0057] And define the following constants:

[0058] There exists a route from the i1th array to the i2th array.

[0059] The cost of transferring data from the i1th array to the i2th array

[0060] K: Number of pipeline stages

[0061] P: The set of different arrays in a multi-array CGRA

[0062] The constraints that need to be satisfied in integer quadratic programming are:

[0063] Task placement constraint: V s All nodes can only be placed in one array.

[0064]

[0065] Array placement constraints: Due to resource constraints, each array can only receive one subtask at most.

[0066]

[0067] Partition constraint: Each task can only be accelerated using either parallel or pipelined execution. Furthermore, the size of the partition parameters cannot exceed the upper limit of the number of iterations. This constraint is fulfilled before the function call for the integer quadratic programming.

[0068] Routing constraint: For any two dependent subtasks, after mapping them to a multi-array CGRA, there must be a route between the two mapped arrays.

[0069]

[0070]

[0071] Pipeline time constraints: The execution time of the k-th stage pipeline consists of the maximum instruction execution time and its data transfer time.

[0072]

[0073] The performance objective of integer quadratic programming is to minimize the execution time of the entire multi-array CGRA, which can be expressed as the execution time of each stage in the critical path of the pipeline and the number of stages in the critical path, where STAGE_NUM is the number of stages in the critical path.

[0074] min{STAGE_NUM·ts k}

[0075] 4. Low-level mapping

[0076] The low-level mapping mainly completes the mapping part within the array, that is, mapping each subtask after the high-level mapping in the corresponding array. The hardware resource constraints are mainly considered during the mapping. For the mapping within each array, different mapping algorithms within the array can be reused. This invention completes the low-level mapping based on the heuristic mapping algorithm in [2].

[0077] 5. Result Evaluation

[0078] Using a simulation environment based on a typical CGRA structure designed by ADRES, the array representation and multi-level mapping algorithms proposed in this invention were tested on nine typical computationally intensive application test sets. Figure 5To compare the performance of the compiler integrating this invention with the configuration packages generated by the original compiler on a 4×4 multi-array, the baseline represents the acceleration result for a single array, manual represents the result after manual optimization, and acceleration limit is the upper limit of the acceleration achievable without considering factors such as data transfer. The results show that the present invention achieves an average speedup of 11.3 times compared to a single array, a performance improvement of 1.2 times compared to manual optimization, and reaches 85.5% of the acceleration limit, indicating that the solution described in this invention can effectively improve the performance of a multi-array coarse-grained reconfigurable architecture.

[0079] Figure 6 This paper demonstrates the acceleration performance of the present invention for multi-array CGRA with varying array sizes, ranging from 4×4, 5×5 to 6×6, while maintaining a consistent number of computational units within each array. The acceleration performance relative to the upper limit varies from 85.5% and 83.9% to 82.0% across the three array size configurations, demonstrating the good scalability of the method. The slight performance degradation is primarily due to the increased complexity of inter-array mapping and the higher data transfer overhead as the number of arrays increases.

[0080] [1]William S Moses,Lorenzo Chelini,Ruizhe Zhao,and OleksandrZinenko.Polygeist:Raising c to polyhedral mlir.In 2021 30th InternationalConference on Parallel Architectures and Compilation Techniques(PACT),pages45–59.IEEE,2021

[0081] [2]Z.Zhao et al., "Towards Higher Performance and Robust Compilation for CGRA Modul oScheduling," in IEEE Transactions on Parallel and DistributedSystems, vol.31, no.9, pp.2201-2219, 1Sept.2020, doi:10.1109 / TPDS.2020.2989149.

[0082] Compared with the prior art, the present invention has the following obvious substantive features and significant advantages:

[0083] 1. In the field of multi-array CGRA compilers, this invention innovatively proposes a high-level intermediate representation design method. It introduces a CGRA dialect to provide a higher-level abstract representation for multi-array CGRA, helping to decouple the mapping process into inter-array mapping and intra-array mapping, thus reducing mapping complexity. Simultaneously, high-level optimizations are performed at the high-level intermediate representation level, developing task-level parallelism and data-level parallelism. Furthermore, the inter-array mapping problem of the task is abstracted into an integer quadratic programming approach for solution, effectively improving mapping performance.

[0084] 2. This method is orthogonal to existing array mapping algorithms, has strong scalability, and can be combined and work collaboratively with different array mapping methods.

[0085] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description

[0086] Figure 1 This is a typical architecture diagram of a multi-array CGRA according to a preferred embodiment of the present invention;

[0087] Figure 2 This is a schematic diagram illustrating parallel and pipelined execution according to a preferred embodiment of the present invention;

[0088] Figure 3 This is a schematic diagram of the compilation flow backend of a preferred embodiment of the present invention;

[0089] Figure 4 This is a schematic diagram of the CGRA dialect of a preferred embodiment of the present invention;

[0090] Figure 5 This is the running time of a preferred embodiment of the present invention under a 4x4 array;

[0091] Figure 6 This is a comparison of the relative performance of different array sizes in a preferred embodiment of the present invention. Detailed Implementation

[0092] The following description, with reference to the accompanying drawings, illustrates several preferred embodiments of the present invention to make its technical content clearer and easier to understand. The present invention can be embodied in many different forms, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0093] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of some components has been appropriately exaggerated in the drawings.

[0094] This invention relates to the field of coarse-grained reconfigurable architecture compilers, and more specifically, to a high-level intermediate representation design and multi-level parallelism development strategy for multi-array coarse-grained reconfigurable architectures. Figure 3 As shown, this includes the high-level compilation flow (303-306); the parallelism analysis and inter-array mapping strategy (304); the MLIR-based CGRAA dialect representation for multi-array CGRAA architectures (305); and the translation strategy from MLIR to C++ (306). It includes the following steps:

[0095] Step 1: For 302, use the C++ to MLIR (Multi-Level Intermediate Representation) compiler based on Polygeist[1] to translate the front-end source program into the Affine and SCF dialects in MLIR.

[0096] Step 2: For tasks 303-304, perform high-level optimization, parallelism analysis, and high-level inter-array mapping.

[0097] Step 2.1: For 303, perform loop-level optimization on each task in the program and expand some of the smaller tasks.

[0098] Step 2.2, corresponding to 304, select acceleration parameters based on the array's hardware resource limitations and the different characteristics of the task, and use an integer quadratic programming algorithm to perform inter-array mapping.

[0099] Step 3: For steps 305-306, store the parallel information in the form of the CGRA dialect, and translate the MLIR dialect into an edited C++ file containing the parallel information.

[0100] Step 3.1, corresponding to 305, represent the parallel information in the form of CGRA dialect.

[0101] Step 3.2, corresponding to 306, translate the different MLIR dialects into annotated C++ files, where the MLIR dialects of CGRA are translated into preprocessing directives starting with #pragma as identifiers.

[0102] Step 4, corresponding to steps 308-311, involves the edited C++ file being processed by Clang to generate low-level intermediate expressions. Then, loop-level parallelism and instruction-level parallelism are developed using an array-based mapping algorithm. After integrating information between arrays, a configuration file is finally generated, completing the entire process.

[0103] Step 4.1: For 308, use the Clang frontend to generate a low-level intermediate expression.

[0104] Step 4.2: For 309, use the algorithm of [2] to schedule and map each subtask in the corresponding array to obtain the mapping result.

[0105] Step 4.3: For 310-311, generate configuration files based on inter-array mapping information and intra-array mapping information.

[0106] [1]William S Moses,Lorenzo Chelini,Ruizhe Zhao,and OleksandrZinenko.Polygeist:Raising c to polyhedral mlir.In 2021 30th InternationalConference on Parallel Architectures and Compilation Techniques(PACT),pages45–59.IEEE,2021

[0107] [2]Z.Zhao et al., "Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling," in IEEE Transactions on Parallel and DistributedSystems, vol.31, no.9, pp.2201-2219,1Sept.2020, doi:10.1109 / TPDS.2020.2989149.

[0108] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A multi-level parallelism development method for a multi-array coarse-grained reconfigurable architecture, characterized in that, The method comprises the following steps: Step 1: the C++ file input by the compiler is processed by Polygeist into an intermediate expression composed of the Affine dialect and the SCF dialect in MLIR; Step 2: loop-level optimization is performed on the tasks, and high-level task-level parallelism and data-level parallelism are developed by using parallelism analysis and inter-array mapping algorithms; Step 3: the parallel information is stored in the form of the CGRA dialect, and the dialect of MLIR is translated back to the edited C++ file with the parallel information; Step 4: the edited C++ file generates low-level intermediate expressions through Clang, and loop-level parallelism and instruction-level parallelism are developed by using intra-array mapping algorithms; after integrating the inter-array information, a configuration file is finally generated, and the whole process is completed.

2. The method for developing multi-level parallelism of a multi-array coarse-grained reconfigurable architecture according to claim 1, wherein, In the step 2, in the process of loop-level optimization, each task is traversed, and the data flow graph size of the task is analyzed according to the number of operators contained in each task; if the data flow graph size is less than the number of nodes of a single array, the number of operators of the innermost loop is increased by using loop unrolling to improve the utilization.

3. The method for developing multi-level parallelism of a multi-array coarse-grained reconfigurable architecture according to claim 1, wherein, In the step 2, for each task in the input program, parallel execution or pipeline execution is selected, and different partition numbers are selected, and each partitioned subtask is mapped.

4. The method of claim 1, wherein the multi-array coarse-grained reconfigurable architecture is a multi-tiered parallelism development method, characterized by, In the step 2, for all tasks, the number of subtasks that can be partitioned and whether parallel execution or pipeline execution is adopted are calculated, and a subtask dependency graph is constructed according to the partitioned dependency relationship. Integer quadratic programming algorithm is used for modeling and solving the mapping relationship and selecting the optimal value.

5. The method for developing multi-level parallelism of a multi-array coarse-grained reconfigurable architecture according to claim 4, wherein, The integer quadratic programming needs to meet the constraints including task placement constraint, array placement constraint, partition constraint, routing constraint, pipeline time constraint.

6. The method of claim 4, wherein the multi-array coarse-grained reconfigurable architecture's multi-level parallelism development method is characterized by, The objective of the integer quadratic programming is to minimize the execution time of the whole multi-array CGRA.

7. The method for developing multi-level parallelism of a multi-array coarse-grained reconfigurable architecture according to claim 1, wherein, In the step 3, the CGRA dialect is introduced in MLIR to represent the execution mode of each task as the key information of inter-array mapping.

8. The multi-level parallelism development method for a multi-array coarse-grained reconfigurable architecture as described in claim 1, characterized in that, In the step 3, the mode identifier in the CGRA dialect represents whether the execution mode of the task is parallel mode or pipeline mode, and the factor identifier specifies the partition number under the mode, that is, the number of subtasks corresponding to the task; The execution mode of the task is determined by the two identifiers mode and factor.

9. The method for developing multi-level parallelism of a multi-array coarse-grained reconfigurable architecture according to claim 1, wherein, In the step 3, the CGRA dialect is translated into a preprocessor form identified by #pragma at the beginning of the task.

10. The multi-level parallelism development method for a multi-array coarse-grained reconfigurable architecture as described in claim 1, characterized in that, In the step 4, the subtasks are mapped in the corresponding array, and the constraints of hardware resources are considered during the mapping.

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