An apparatus for enabling a parallel bus processor to access a CAN bus controller SJA1000 single step
By using hardware-matched timing methods, a parallel bus processor can access the SJA1000 CAN bus controller in a single step, solving the problems of high cost, slow speed, and poor reliability, and achieving low-cost and high-efficiency access.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG INST OF AEROSPACE ELECTRONICS TECH
- Filing Date
- 2022-12-03
- Publication Date
- 2026-06-05
AI Technical Summary
In the existing technology, processors that use parallel buses and do not have address latch signals (ALE) cannot directly access the CAN bus controller SJA1000, resulting in high design costs, slow access speeds, and poor reliability.
By adopting a hardware-matched timing method, and by setting up a timing conditioning module, a time-division multiplexing module, and a drive control module, the parallel bus processor can complete the access to the SJA1000 in a single read/write operation. The processor's original timing I/O chip select signal and clock signal are used to generate a delayed control signal to match the timing requirements of the SJA1000.
It achieves low-cost, low-PCB-area bridging, improves CAN bus access speed, simplifies software design, and enhances reliability and access efficiency.
Smart Images
Figure CN116049052B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design, and more specifically to a device that enables a parallel bus processor to access the CAN bus controller SJA1000 in a single step. Background Technology
[0002] The SJA1000 CAN bus controller boasts superior performance and a wide range of applications, commonly used in various circuits. However, its address and data lines employ time-division multiplexing; its read timing is as follows... Figure 10 As shown, the write timing is as follows Figure 11 As shown. However, for processors that use parallel buses (data lines, address lines, and control lines, etc.) and lack the address latch signal ALE, it is impossible to directly generate a signal that conforms to the standard. Figure 10 and Figure 11 The timing of the circuit breaker prevents direct access to the SJA1000, which affects the design of integrated circuits and forces the user to choose between two options in certain situations, thus reducing the performance of the final product.
[0003] To allow processors using parallel buses that lack address latching (ALE) signals to directly access the SJA1000, a common approach is to use programmable logic devices such as FPGAs as bridge chips to match the timing of the two. However, the following problems still exist:
[0004] 1) Using programmable logic devices as bridge chips results in higher costs for the devices themselves, as well as additional costs for the power supply system and PCB area.
[0005] 2) Programmable logic devices need to use an internal clock to sample the processor's parallel bus. Especially in applications with high reliability requirements, multiple samplings are required, which reduces the access speed to the CAN bus.
[0006] Another common method is to access the SJA1000 in two steps. First, the address is written to the SJA1000 and latched by its ALE signal. Second, data is read from or written to the SJA1000. However, this method has the following problems:
[0007] 1) When frequently exchanging data on the CAN bus, the two-step operation will consume a lot of CPU time and reduce the access speed of the CAN bus.
[0008] 2) When a higher priority interrupt interrupts the current CAN bus access, the process of saving and restoring the interrupt context between the two operations is cumbersome; and it will also reduce the access speed to the CAN bus. Summary of the Invention
[0009] To address the aforementioned problems, this invention provides a device that enables a parallel bus processor to access the CAN bus controller SJA1000 in a single step. By employing a hardware-matched timing method and utilizing the timing characteristics of the parallel bus processor, the device allows the parallel bus processor to complete access to the SJA1000 in a single read / write operation, thereby improving the efficiency of CAN bus access.
[0010] To achieve the above objectives, the technical solution of the present invention is as follows:
[0011] This invention provides a device for enabling a parallel bus processor to access a CAN bus controller SJA1000 in a single step. The device is positioned between the parallel bus processor and the SJA1000, with the processor's original timing I / O chip select signal connected to the ALE pin of the SJA1000. The device includes:
[0012] The timing conditioning module receives the processor's original timing I / O chip select signal, original timing read enable signal, and original timing write enable signal. The original timing I / O chip select signal is the first-level chip select. It also generates a second-level chip select, a second-level read enable signal, and a second-level write enable signal with timings later than the first-level chip select. These signals are received by the SJA1000 as the chip select signal, read enable signal, and write enable signal, respectively. The second-level read enable signal and the second-level write enable signal are established simultaneously with the second-level chip select, or later than the establishment of the second-level chip select.
[0013] The time-division strobing module is used to receive the first-level chip select and the second-level chip select, and logically combine the first-level chip select and the second-level chip select to generate address line strobe signals and data line strobe signals in sequence; wherein the address line strobe signals are generated before the data line strobe signals.
[0014] The drive control module is used to receive the processor's address lines and data lines, as well as address line strobe signals and data line strobe signals. The address line strobe signal is active first, and the address lines are connected to the SJA1000's address / data multiplexed bus. The data line strobe signal is active later, and the data lines are connected to the SJA1000's address / data multiplexed bus.
[0015] In one embodiment, the timing conditioning module generates secondary chip select, secondary read enable, and secondary write enable signals with timings later than the primary chip select by sampling and latching the original timing I / O chip select signal using the processor's clock signal to delay the establishment of the primary chip select.
[0016] In one embodiment, the timing conditioning module includes a latch and an OR gate of model 54AC374.
[0017] In one embodiment, the time-division strobing module receives a first-level chip select and a second-level chip select. The first-level chip select and the second-level chip select are passed through an NOR gate to obtain an address line strobing signal. The address line strobing signal is inverted and then ORed with the first-level chip select to obtain a data line strobing signal.
[0018] The beneficial effects achieved by this invention are as follows:
[0019] 1) Compared with FPGA and its peripheral circuits, the circuit used in this invention is more economical and practical, and can bridge the parallel bus processor and SJA1000 with lower cost and smaller PCB area.
[0020] 2) This invention is more efficient and faster; when data is frequently exchanged on the CAN bus, the single-step access SJA1000 implemented by this invention can save a lot of CPU time and improve the access speed of the CAN bus compared with the traditional two-step access operation.
[0021] 3) Compared with two-step access operation, the present invention is simpler and more reliable. During the single-step access of SJA1000, when the current CAN bus access is not interrupted by a higher priority interrupt, the software does not need to design the saving and restoration operation of the interrupt context, which greatly simplifies the software design and improves the reliability. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of the overall structure of the present invention.
[0024] Figure 2 This is a timing diagram of the single-step read access SJA1000 of the parallel bus processor of the present invention.
[0025] Figure 3 This is a timing diagram of the single-step write access SJA1000 of the parallel bus processor of the present invention.
[0026] Figure 4 This is a schematic diagram of the timing conditioning module structure of the present invention.
[0027] Figure 5 This is a schematic diagram of the time-division gating module structure of the present invention.
[0028] Figure 6 This is the truth table of the time-division strobe module.
[0029] Figure 7 This is a schematic diagram of the drive control module structure of the present invention.
[0030] Figure 8 This is the I / O read timing diagram for the BM3803 processor.
[0031] Figure 9 This is the I / O write timing diagram for the BM3803 processor.
[0032] Figure 10 This is the timing diagram for read operations of SJA1000 in Intel mode.
[0033] Figure 11 This is a timing diagram of the write operation of SJA1000 in Intel mode.
[0034] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0036] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.
[0037] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, if the word "and / or" appears throughout the text, it means including three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.
[0038] like Figure 1As shown, this invention provides a device for enabling a parallel bus processor to access the CAN bus controller SJA1000 in a single step. The device is positioned between the parallel bus processor and the SJA1000, serving as a bridge circuit for single-step access to the SJA1000. The processor's original timing I / O chip select signal is connected to the ALE pin of the SJA1000. This invention also includes:
[0039] The timing conditioning module receives the original timing I / O chip select signal, the original timing read enable signal, and the original timing write enable signal from the processor. The original timing I / O chip select signal is the first-level chip select. By sampling and latching the original timing I / O chip select signal using the processor's clock signal to delay the establishment of the first-level chip select, or by using electrical link delay or other methods, it generates the second-level chip select, second-level read enable signal, and second-level write enable signal, which are timing later than the first-level chip select. These signals are received by the SJA1000 as the chip select signal, read enable signal, and write enable signal, respectively. The second-level read enable signal and second-level write enable signal are established simultaneously with the second-level chip select, or later than the establishment of the second-level chip select.
[0040] The time-division strobing module is used to receive the first-level chip select and the second-level chip select, and logically combine the first-level chip select and the second-level chip select to generate address line strobe signals and data line strobe signals in sequence; wherein the address line strobe signals are generated before the data line strobe signals.
[0041] The drive control module is used to receive the processor's address lines and data lines, as well as address line strobe signals and data line strobe signals. The address line strobe signal is active first, and the address lines are connected to the SJA1000's address / data multiplexed bus. The data line strobe signal is active later, and the data lines are connected to the SJA1000's address / data multiplexed bus.
[0042] When the processor is not accessing the SJA1000, the primary chip select output by the parallel bus processor and the secondary chip select output by the timing conditioning module are both invalid. The time-division strobe module controls the address line strobe signal to be valid, and the drive control module controls the address line to be connected to the SJA1000.
[0043] When the processor begins accessing the SJA1000, the processor's primary chip select is enabled first, while the timing conditioning module's secondary chip select is disabled. The time-multiplexing strobe module's address line strobe signal is enabled, and the driver control module's address line is connected to the SJA1000. The falling edge of the primary chip select is used as the SJA1000's ALE signal to latch the address line. When both the processor's primary chip select and the timing conditioning module's secondary chip select are enabled, the time-multiplexing strobe module's address line strobe signal is disabled, and the driver control module's address line is disconnected from the SJA1000. After a reasonably set delay, the time-multiplexing strobe module's data line strobe signal becomes enabled, and the driver control module's data line is connected to the SJA1000.
[0044] At this point, the processor's parallel address and data lines are connected to the SJA1000 in a time-sharing manner. During read / write operations, the address lines have been latched in the initial stage, and the SJA1000's data lines are connected to the CPU's data lines, allowing for normal reading and writing. Figures 2-3 As shown in the figure, the timing of I_CAN_CS* (corresponding to ALE of SJA1000), II_CAN_CS* (corresponding to CS* of SJA1000), II_CAN_OE* (corresponding to RD* of SJA1000), II_CAN_WR* (corresponding to WR* of SJA1000), and II_CAN_AD (corresponding to AD[7-0] of SJA1000) can be matched with the timing of SJA1000.
[0045] Example
[0046] The device for single-step access to the CAN bus controller SJA1000 by a parallel bus processor is applied to a spaceborne computer. This embodiment uses the I / O access timing of the BM3803 processor as an example to describe the structure of the present invention in detail.
[0047] The BM3803 uses a parallel bus for its data and address lines, a typical EMIF interface. Its I / O access timing is as follows: Figure 8 , 9 As shown.
[0048] The BM3803's I / O chip select signal IOSN is used as the first-level chip select (I_CAN_CS*), the read enable signal OEN as the first-level read enable (I_CAN_OE*), the write enable signal WRITEN as the first-level write enable (I_CAN_WE*), the data lines as the first-level data lines (I_DATA), and the address lines as the first-level address lines (I_ADDR). These first-level chip select, read enable, and write enable signals are collectively referred to as the first-level control signals. The first-level chip select is connected to the ALE pin of the SJA1000.
[0049] The structure of the timing conditioning module is as follows: Figure 4 As shown, the circuit includes a latch and an OR gate of model 54AC374, and the connection relationship is shown in the figure. The timing conditioning module receives the first-level control signal and can use the processor's main clock to perform timing conditioning on the first-level control signal to obtain the second-level chip select II_CAN_CS*, second-level read enable II_CAN_OE*, and second-level write enable II_CAN_WE* (collectively referred to as the second-level control signals) established one clock cycle later than the first-level control signal.
[0050] The secondary control signal can also be obtained by delaying the primary control signal through electrical links (such as RC delay, gate delay, etc.). The final secondary control signal should be established at least 10ns later than the primary control signal to meet the SJA1000's requirements for tLLRL and tLLWL. The secondary chip select, secondary read enable, and secondary write enable are connected to the SJA1000's chip select, read enable, and write enable pins, respectively.
[0051] Due to the processing of the timing conditioning module, the secondary chip select is established later than the primary chip select, providing the time-division multiplexing module with four combinations of primary and secondary chip selects: primary chip select is invalid, secondary chip select is invalid; primary chip select is valid, secondary chip select is invalid; primary chip select is invalid, secondary chip select is valid; primary chip select is invalid, secondary chip select is invalid.
[0052] like Figure 5 As shown, the time-division multiplexing module receives the first-level chip select and the second-level chip select. The first-level chip select and the second-level chip select are passed through a NOR gate to obtain the address line strobe signal (low level is active). The address line strobe signal is inverted and then ORed with the first-level chip select to obtain the data line strobe signal (low level is active).
[0053] The truth table of the time-sharing gating module is as follows: Figure 6 As shown in the table, when both the primary and secondary chip selects are invalid, the data line strobe signals are invalid, and the address line strobe signals are valid; when the primary chip select is invalid and the secondary chip select is valid, the data line strobe signals are invalid, and the address line strobe signals are valid; when the primary chip select is valid and the secondary chip select is invalid, the data line strobe signals are invalid, and the address line strobe signals are valid; when both the primary and secondary chip selects are valid, the data line strobe signals are valid, and the address line strobe signals are invalid. This ensures that the data line strobe signals and the address line strobe signals are not valid simultaneously.
[0054] like Figure 7 As shown, the drive control module is implemented by B54ACS164245. Section 1 of the A terminal is connected to the first-level address line, and the enable terminal is controlled by the address line strobe signal. Section 2 is connected to the first-level data line, and the enable terminal is controlled by the data line strobe signal. The B terminal is connected to the address / data multiplexed bus II_CAN_DATA of SJA1000.
[0055] When the address line strobe signal is active, the address line is connected to the address / data multiplexed bus of the SJA1000; when the data line strobe signal is active, the data line is connected to the address / data multiplexed bus of the SJA1000.
[0056] Based on the above circuitry, the steps for the BM3803 processor to perform a single-step read access to the SJA1000 include:
[0057] In the first CPU clock cycle, the primary address lines are stable; all primary control signals are invalid; the time-division multiplexing module connects the primary address lines to the SJA1000's address / data multiplexing bus.
[0058] During the second CPU clock cycle, the primary address lines remain stable; the primary chip select and primary read enable are established; the secondary chip select and read enable are not established. The time-division multiplexing module controls the drive control module to connect the primary address lines to the SJA1000's address / data multiplexed bus. The falling edge of the primary chip select latches the address lines into the SJA1000's address / data multiplexed bus.
[0059] In the third CPU clock cycle, the first-level address lines remain stable; the first-level chip select and first-level read enable remain active; the second-level chip select and read enable are established, and control of the SJA1000 begins. The time-division multiplexing module controls the drive control module to disconnect the first-level address lines from the SJA1000's address / data multiplexed bus. After a gate delay consisting of an NOT gate and an OR gate, the first-level data lines are connected to the SJA1000's address / data multiplexed bus.
[0060] From the 3rd to the Nth clock cycles, the primary address and data lines remain stable; the primary chip select and primary read enable remain active; the secondary chip select and read enable remain active, continuing to control the SJA1000. The primary data lines are connected to the SJA1000's address / data multiplexed bus. Generally, the processor should insert read wait cycles to meet the SJA1000's maximum 50ns setup time (tRLQV). The value of N depends on the ratio of the processor's clock cycle length to 50ns.
[0061] In the (N+1)th clock cycle, the primary address and data lines remain stable; the primary chip select and primary read enable remain active; the secondary chip select and read enable remain active, continuing to control the SJA1000. The primary data lines are connected to the SJA1000's address / data multiplexed bus. The processor reads data from the SJA1000 on the (N+1)th rising edge of the clock cycle.
[0062] Based on the above circuit, the BM3803 processor uses single-step write access to SJA1000, which is basically similar to read access. The main difference is that in the Nth clock cycle, the rising edge of the secondary write enable signal drives the data line to write to the memory cell in SJA1000, which will not be described in detail here.
[0063] The method for a parallel bus processor to access the SJA1000 CAN bus controller in a single step has been verified for more than 300 hours and is working stably.
[0064] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.
Claims
1. A device for enabling a parallel bus processor to access a CAN bus controller SJA1000 in a single step, disposed between the parallel bus processor and the SJA1000, wherein the processor's original timing I / O chip select signal is connected to the ALE pin of the SJA1000; characterized in that, include: The timing conditioning module is used to receive the original timing I / O chip select signal, the original timing read enable signal, and the original timing write enable signal from the processor. The original timing I / O chip select signal is the first-level chip select. It also generates a second-level chip select signal, a second-level read enable signal, and a second-level write enable signal with timings later than the first-level chip select, which are received by the SJA1000 as the chip select signal, read enable signal, and write enable signal, respectively. The secondary read enable signal and the secondary write enable signal are established simultaneously with the secondary chip select, or later than the secondary chip select. The time-division strobing module is used to receive the first-level chip select and the second-level chip select, and logically combine the first-level chip select and the second-level chip select to generate address line strobe signals and data line strobe signals in sequence; wherein the address line strobe signals are generated before the data line strobe signals. The drive control module is used to receive the processor's address lines and data lines, as well as address line strobe signals and data line strobe signals. The address line strobe signal is active first, and the address lines are connected to the SJA1000's address / data multiplexed bus. The data line strobe signal is active later, and the data lines are connected to the SJA1000's address / data multiplexed bus.
2. The apparatus according to claim 1 for enabling a parallel bus processor to access the CAN bus controller SJA1000 in a single step, characterized in that: The timing conditioning module generates secondary chip select, secondary read enable, and secondary write enable signals with timings later than the primary chip select by sampling and latching the original timing I / O chip select signal using the processor's clock signal, thus delaying the establishment of the primary chip select.
3. The apparatus according to claim 2 for enabling a parallel bus processor to access the CAN bus controller SJA1000 in a single step, characterized in that: The timing conditioning module includes a latch and an OR gate of model 54AC374.
4. The apparatus according to claim 1 or 3 that enables a parallel bus processor to access the CAN bus controller SJA1000 in a single step, characterized in that: The time-division multiplexing module receives the first-level chip select and the second-level chip select. The first-level chip select and the second-level chip select are passed through an NOR gate to obtain the address line selection signal. The address line selection signal is inverted and then ORed with the first-level chip select to obtain the data line selection signal.