Systems, apparatus and methods for identifying integrated circuit functions via clock signal overlap

Abstract

Systems, apparatuses, and methods are provided for identifying integrated circuit functions via clock signal overlay. In one embodiment, an apparatus includes: an oscillator for outputting a clock signal on a first line; a switch coupled to the first line; and a voltage divider coupled to the switch. The switch can be controlled to output the clock signal to a pin via the first line through the voltage divider in a non-reset mode, and to prevent the clock signal from being provided to the pin in a reset mode.

Description

Background Technology

[0001] Integrated circuits (ICs) are being adopted in an increasing number of devices, including many different types of consumer devices. These devices include Internet of Things (IoT) devices, which provide monitoring, sensing, and other types of functionality that are incorporated with wireless capabilities for enabling communication in a network.

[0002] Such devices comprise one or more ICs, and it can be difficult to ascertain—for example, in troubleshooting scenarios—whether a given IC is functioning or active, whether at least part of the correct boot sequence has been executed, or whether the device even has a bootloader installed, and if so, what kind. One such example is when the IC is encased in a "bricked" device, and it is impossible to unbrick or unlock the IC, or to connect it to a debugger or reprogram it, or even witness any signs of activity. Summary of the Invention

[0003] In one aspect, an apparatus includes: an oscillator for outputting a clock signal on a first line; a switch coupled to the first line; and a voltage divider coupled to the switch. The switch can be controlled to output the clock signal to a pin via the first line through the voltage divider in a non-reset mode, and to prevent the clock signal from being provided to the pin in a reset mode.

[0004] In one example, the voltage divider includes: a first resistor coupled between the switch and the pin; and a second resistor coupled between the pin and the supply voltage pin. The device may be an integrated circuit having a single semiconductor die, with the first and second resistors formed on the single semiconductor die. The clock signal, attenuated to a small signal level, is output via the pin through the voltage divider. The output of the clock signal at the small signal level includes an activity signal indicating the functionality of the device. Modulation of the clock signal at the small signal level can indicate the type of bootloader.

[0005] In one example, the clock signal, at a decaying small-signal level, lies between the supply voltage level and a second voltage level greater than a logic high threshold level. This clock signal is output via a pin at a decaying small-signal level superimposed on a reset signal, which is essentially at the supply voltage level in non-reset mode, and this pin is the reset pin.

[0006] In one example, the device further includes control circuitry coupled to a switch, the control circuitry being used to control the switch to couple the clock signal to the pin in response to completion of a reset mode. The control circuitry can control the switch to open during reset mode, and after reset mode, the control circuitry is used to control the switch to close.

[0007] In one example, the device may further include monitoring circuitry coupled to the pin for identifying the presence of the clock signal at a low-attenuation level. The monitoring circuitry may include an oscilloscope for displaying the clock signal at a low-attenuation level. The monitoring circuitry may also include a comparator having: a first input terminal coupled to the pin; and a second input terminal for receiving a reference voltage, wherein the comparator outputs a comparison signal based on a comparison of the voltage at the pin with the reference voltage; and a light-emitting diode coupled to the comparator, wherein the light-emitting diode illuminates when the clock signal at a low-attenuation level is present.

[0008] In another approach, one method includes: disconnecting a switch of the integrated circuit coupled between a reset pin of the integrated circuit and an oscillator used to provide a clock signal; performing a pre-boot sequence of the integrated circuit in response to the release of a logic low voltage at the reset pin; and closing the switch such that a decayed version of the clock signal is superimposed on a reset signal output at the reset pin to indicate the functionality of the integrated circuit.

[0009] In one example, the method further includes identifying at least one parameter of the integrated circuit in response to an attenuated version of a clock signal. The method may further include modulating the clock signal using a first modulation to identify at least one parameter of the integrated circuit. The method may further include identifying the bootloader type of the integrated circuit based on the first modulation.

[0010] In another aspect, an integrated circuit includes: a switch; core circuitry for controlling the switch; an oscillator for outputting a clock signal; a first resistor coupled between the switch and a pad on the integrated circuit; and a second resistor coupled between the pad and a supply voltage pad on the integrated circuit, wherein the clock signal is superimposed on a reset signal at the pad when the core circuitry enables the switch. In one example, the voltage of the reset signal with the superimposed clock signal is maintained above a logic high threshold. The superimposed clock signal can be used to identify the functionality of the integrated circuit. Attached Figure Description

[0011] Figure 1 This is a block diagram of an apparatus according to one embodiment.

[0012] Figure 2 This is a graphical illustration of an activity signal according to one embodiment.

[0013] Figure 3 This is a block diagram of a device according to one embodiment.

[0014] Figure 4 This is a block diagram of a device according to another embodiment.

[0015] Figure 5 This is a flowchart of a method according to one embodiment.

[0016] Figure 6 This is a flowchart of a method according to another embodiment.

[0017] Figure 7 This is a block diagram of a representative integrated circuit according to one embodiment.

[0018] Figure 8 This is a block diagram of a system according to one embodiment. Detailed Implementation

[0019] In various embodiments, the integrated circuit is provided with circuit modules that enable the confirmation of available functionality (indicators of activity) and / or the presence and type of the bootloader, among other states. Such circuit modules can utilize existing functional blocks and include additional circuit modules to provide this indication. Furthermore, existing pin space can be used, so that no additional general-purpose input / output (GPIO) or other pins need to be dedicated to this functionality determination. Simultaneously, there is no adverse impact on the functionality of existing devices. Further still, the mechanisms described herein can be disabled (e.g., by application) so as not to trigger any power consumption penalties under certain power states.

[0020] The implementation can be used in a variety of situations. In one use case, the circuit module can indicate device functionality during the product testing phase when the IC is powered on. As used herein, the term "functionality" in relation to such functional indication means that the IC is active and / or in operation when powered on, and does not necessarily mean that it performs one or more specific functions or other operations. In another use case, after the IC has been used to populate a production board, the feasibility of the IC can be quickly checked without having to connect a debugger and before programming the device. A third example is when a device with the IC appears to be partially unresponsive, and it is desirable to know whether the bootloader has been satisfactorily programmed and executed. It should be noted that the bootloader can be stored in the IC's non-volatile memory (e.g., flash memory).

[0021] Now for reference Figure 1 A block diagram of an apparatus according to one embodiment is shown. Figure 1As shown, an integrated circuit (IC) 100 is present and coupled to a reset pin 102 and a supply voltage pin 104. It should be noted that, as used herein, the terms "pin" and "pad" are used interchangeably and refer to any conductive element that enables interconnection between the IC and other circuit modules. Therefore, it should be noted that although pins 102 and 104 are shown outside the die of IC 100, they may be part of the IC's package or other socket. In any case, it should be understood that corresponding pads (not shown) may be present within the die of IC 100, which are then coupled to pins 102 and 104, for example, via wire bonding.

[0022] As illustrated, IC 100 includes an oscillator 110, which can operate to continuously generate a clock signal when power is available. While embodiments are not limited in this respect, oscillator 110 can be implemented as a low-power RC oscillator to generate the clock signal at an extremely low frequency (e.g., 1 kHz). Other examples are, of course, possible. It is to be understood that this clock signal can be used by various circuit modules within IC 100.

[0023] In addition, such as Figure 1 As further shown, when switch SW1 is closed, the clock signal (or more specifically, a decayed version of the clock signal) can be transmitted along the signal line to reset pin 102. As will be described herein, when this decayed clock signal is provided, it acts as an activity or activity indicator to indicate to an external entity that IC 100 is functioning or has performed at least a portion of the correct boot sequence. In a further case, the activity signal can also indicate status information about IC 100, such as whether a bootloader is installed, and if so, what kind it is. Of course, the clock signal can also provide other indications to an external entity in other cases, such as whether IC 100 is debug locked.

[0024] Still referencing Figure 1 It is important to note that switch SW1 can be controlled under the control of core 120. In embodiments, core 120 may be the main processor of IC 100, such as a microcontroller. Based on the operating mode, core 120 can control switch SW1 to be in an open or closed position, as will be further described herein. Although the embodiments described herein may use a general-purpose processing core that can execute instructions stored in a non-transitory storage medium to generate an activity signal, other control circuitry modules may also be used. That is, in other cases, shared or dedicated control circuitry, state machines, or other programmable circuitry may be configured to control switch SW1 (e.g., under program control) to achieve the generation of an activity signal as described herein.

[0025] The ability to provide the clock signal to the reset pin 102 at a decaying level can be achieved via a voltage divider formed by the first resistor R1 and the second resistor R2. As shown, resistor R1 is located on the signal path between switch SW1 and reset pin 102. Furthermore, resistor R2, which may be an internal pull-up resistor of IC 110, is coupled between the supply voltage pin 104 and reset pin 102. Although the embodiment is not limited in this respect, in one example, the values ​​of these resistors could be set to approximately 400 kΩ for resistor R1 and approximately 40 kΩ for resistor R2. It should be understood that although... Figure 1 This high-level representation is shown in the embodiments, but many variations and alternatives are possible. For example, in other cases, at least one of the resistors (e.g., a pull-up resistor) may be an external resistor present on the circuit board on which the IC 100 is adapted.

[0026] It is important to note that the activity signal does not affect normal device reset operations. During normal boot, switch SW1 is open, and the activity signal is absent. During this boot or reset mode, the voltage at reset pin 102 (which is used as the reset signal) is pulled to a logic low level in some way, for example via a manual button or a logic low digital signal from an external IC, which triggers the reset process of IC 100.

[0027] Sometime after the release of reset pin 102 (causing the reset signal to become the supply voltage level) and before the execution of the bootloader code (which may be installed) (the exact timing start can vary depending on the implementation), core 120 closes switch SW1 to connect the always-operable oscillator 110 to resistor R1. This oscillator clock signal is transformed into a decaying small-signal clock signal superimposed on the upper end of the reset pin voltage (i.e., the reset signal) by a voltage divider formed by resistors R1 and R2. This small-signal clock signal can be used, for example, as an activity signal. It is important to note that, in the embodiment, the activity signal has a sufficiently small swing so that it does not violate the minimum logic high level (0.8*VDD) by going down, but large enough (e.g., 150-300 millivolts (mV)) to be easily distinguishable by external hardware. In other words, both the activity signal and the reset signal can share the reset pin simultaneously, both providing their information without conflict.

[0028] Now for reference Figure 2 A graphical illustration of an activity signal according to one embodiment is shown. Figure 2As shown, the activity signal 200 can be provided to the reset pin at a low, attenuated signal level (e.g., with a signal swing of approximately 0.1VDD). This low signal can be achieved using a voltage divider, as described above. Figure 1 The discussion focuses on the clock signal 200 via the voltage divider, which can be used as an activity signal. When output via reset or other pins, this activity signal provides an indication to an external entity that the IC is active and functioning, and may provide other information about the IC and its environment.

[0029] It is important to note that, in Figure 2 In this circuit, the activity signal 200 is a square wave clock signal with a frequency of, for example, 1 kHz, output from an on-chip oscillator; other shapes and frequencies are, of course, possible. It should also be noted that the activity signal 200 overlaps with the supply voltage level (i.e., the reset signal typically present on the reset pin during normal operation). That is, given... Figure 2 The attenuation signal swing shown indicates that even at the minimum value of the signal swing, the active signal 200 remains above the threshold voltage level of the logic high signal. Figure 2 (As shown at level 210 in the diagram). Therefore, a normal consumer can still receive the reset signal in its high state during normal operation.

[0030] like Figure 2 As shown, the active signal (if present at the reset pin) has a frequency (e.g., 1 kHz) corresponding to the output clock signal of oscillator 110, and its amplitude ranges from VDD down to ~0.91*VDD. The minimum high logic level 210 at 0.8VDD differs significantly from the minimum active signal swing (by ~300-350 mV). Figure 2 A table showing typical associated voltage levels according to one embodiment is also shown.

[0031] As discussed above, the generated activity signals, as described herein, can provide indications about the IC to an external entity. This external entity could be the designer of the IC or a device incorporating the IC. Alternatively, the external entity could be a troubleshooter, such as a commissioning engineer, field engineer, or others seeking to perform troubleshooting on the device to determine if the IC is operating correctly. Of course, the activity signals can also serve as an indicator to other entities, or even the end user of a device incorporating the IC according to one embodiment.

[0032] Now for reference Figure 3 A block diagram of a device according to one embodiment is shown. Figure 3As shown, device 300 can be any type of device having an IC according to one embodiment. As an example, device 300 can be implemented as a prototype or evaluation board including the IC and additional circuitry modules. In other cases, device 300 can be an end-user device, such as an IoT device, including circuitry modules for monitoring the presence of activity signals. This implementation may be appropriate where the size and cost of the components used to monitor activity signals are guaranteed for a given design.

[0033] In any case, device 300 is shown in a test environment, which can be implemented in the device designer's test bench or other laboratory setup. In other cases, it is implemented separately from or isolated from other circuit modules of the test environment, which can be achieved using an external oscilloscope coupled to the reset pin.

[0034] like Figure 3 As shown, device 300 includes components that can interact with... Figure 1 The same IC 100 shown (and therefore, using the same...) Figure 1 The same numbering scheme applies, although it is the "300 series" (and the components labeled with letters remain the same). In addition to IC 100, device 300 also includes a monitoring circuit module (generally illustrated at 350). In this embodiment, monitoring circuit module 350 includes an oscilloscope 360, which may be an external device coupled to reset pin 302. The presence of the oscilloscope is optional and may occur in a laboratory environment where the designer, application engineer, troubleshooter, or others can couple oscilloscope probes to reset pin 302.

[0035] As further shown, the monitoring circuit 350 further includes a comparator 370. The comparator 370 has a first input terminal coupled to a reset pin 302 and a second input terminal coupled to a reference node 372. In one embodiment, the comparator 370 may be implemented as a low-power analog comparator in an external SOT-23 (or similar) package. In the illustrated embodiment, the comparator 370 may have an enable function (to be turned off when not in use for power saving). The reference node 372 may provide a threshold voltage, which the comparator 370 uses to compare the voltage at the reset pin 302. As an example, the reference voltage may be set at a level midway between the supply voltage level (VDD) and the low swing of the activity signal (~0.95*VDD (approximately halfway between the high and low amplitudes of the activity signal)). As illustrated, the reference node 372 is coupled to a reference circuit with series-coupled resistors R11 and R12, which are coupled to the supply voltage node and the reference voltage node, respectively. As further shown, the reference circuit may include a capacitor C coupled in parallel with resistor R12.

[0036] As further illustrated, the output of comparator 370—the comparison signal—is then coupled to a light-emitting diode (LED) 375 via resistor R13. Using this arrangement, LED 375 can illuminate when an activity signal is present. Of course, instead of visual indication, another method can be provided to identify the presence of an activity signal, such as audible indication or vibration. Alternatively, the output of comparator 370 can be provided to another microcontroller or IC in the system.

[0037] Depending on the circumstances, there may be one or more capabilities for detecting the presence of activity signals. These capabilities may be provided simultaneously or individually to visually or audibly indicate activity signals to the designer / troubleshooter.

[0038] By connecting the oscilloscope to the reset pin 302, the activity signal can be seen overlapping the reset signal, as illustrated in the diagram on the oscilloscope 360's display. With this configuration, the comparator output oscillates synchronously with the clock signal and drives an LED that appears to be continuously illuminated, thus providing an indication of device activity. If comparator 370 is connected and the oscilloscope signal is as desired, the user can directly probe the comparator output instead of the reset pin.

[0039] In one implementation, when the clock signal is output at VSS, connecting the probe with a 1 megaohm (MΩ) resistor in parallel with the 13 pF capacitor at the reset pin effectively parallels that 1 MΩ with the internal resistor R1 (resulting in ~286 kΩ). This arrangement increases the swing or amplitude of the active signal, thereby extending its lower excursion from ~0.91*VDD to ~0.877*VDD.

[0040] Now for reference Figure 4 A block diagram of a device according to another embodiment is shown. Figure 4 As shown, device 400 can generally be as follows: Figure 3 It is configured with IC 100 and monitoring circuit module 450 (and therefore in Figure 1 (and Figure 3 The same numbering scheme is used in (although it is "400 series"), so similar components will not be discussed further.

[0041] As illustrated, transistor 480 is present and coupled between reset pin 402 and VSS. In the illustrated embodiment, transistor 480 can be implemented as an N-channel junction field-effect transistor (JFET) having a drain terminal coupled to reset pin 402, a source terminal coupled in parallel with the drain terminal via Schottky diode 490, and a gate terminal coupled to VSS. Furthermore, another capacitor C2, acting as a timing capacitor, is coupled between the gate and source terminals.

[0042] This implementation is often desirable because many designers use an external capacitor coupled between the reset pin and a reference voltage level (e.g., VSS) to extend the reset pulse, providing an RC time constant formed by the capacitor and the internal pull-up resistor. This ensures that the main power supply has sufficient time to ramp up from near zero volts and properly stabilizes within its tolerances before allowing the device to exit the reset state. Placing the capacitor directly on the reset pin can drown out active signals because its associated impedance at the 1kHz oscillator frequency is much smaller than other impedances at the reset node. With respect to typical capacitor values ​​used in today's designs, the active signal may be too small to be practically distinguishable by external circuitry without expensive equipment, and the signal is likely to be in noise.

[0043] Therefore, as in Figure 4 As shown, the small JFET 480 can be introduced in series with the timing capacitor C2 (shown as the symbol for a polarized capacitor, indicating that any large value of a uniform electrolytic capacitor can be used without any problem). When the reset pin 402 is released from actuation (and the activity indicator is not yet activated), the JFET 480 provides a low-impedance path for the internal pull-up resistor R2 to charge the external timing capacitor C2. Except for the Schottky reverse leakage current application of a top-off charge to ensure that the JFET 480 does not always remain at the very edge of pinch-off but rather penetrates deeper into it, as the capacitor charges, the Vgs of the JFET 480 becomes increasingly negative in magnitude until pinch-off occurs in its channel (i.e., the FET drain-source channel becomes very high impedance), and the capacitor C2 is effectively disconnected from the reset pin 402. When the next logic low voltage is applied at the reset pin, the timing capacitor C2 discharges through the Schottky diode 490, and the JFET 480 will once again have a low impedance from drain to source, allowing the timing capacitor C2 to be recharged within the expected RC reset delay.

[0044] In an embodiment, an application or other entity may be configured to optionally disable the activity indication functionality in order to conserve energy whenever the oscillator output is at a logic low level, which would otherwise be depleted by the current flowing through the internal pull-up resistor to VSS.

[0045] Now for reference Figure 5 A flowchart of a method according to one embodiment is shown. Figure 5 As shown, method 500 is a method for operating an IC having activity indicator circuitry as described herein. This operation may occur in various environments, such as laboratory environments, debugging environments, manufacturing environments, or even in the field. In any case, method 500 begins by supplying power to the IC (block 510). For example, a device including the IC may be turned on, and power may be supplied to the IC via at least one supply voltage pin coupled to at least one pad of the IC. Next, at block 520, the switch coupled between the oscillator (such as a low-power oscillator that is always on as described herein) and the reset pin may be disconnected. It should be noted that this disconnection of the switch may be the default configuration of the switch.

[0046] Still referencing Figure 5 Next, it can be determined whether the reset pin has been released (diamond box 530). This release can be controlled by the device's reset controller, which releases the reset signal at logic low when the voltage regulator or other power supply has reached a sufficiently high supply voltage level to turn on the IC's circuitry and the IC has completed its reset mode. The reset pin can also be released via a manual button with electrical contacts; otherwise, the electrical contacts will hold the reset pin at logic low.

[0047] At this point, a typical pre-boot sequence can be executed (box 540). While embodiments are not limited in this respect, such pre-boot operations may include turning on a low-power oscillator, running a state machine that reads calibration values ​​from non-volatile memory and populates various registers. It should be noted that this pre-boot sequence can be executed before any code execution, and even before the installed bootloader is executed.

[0048] Once the pre-boot sequence is complete, at box 550, the switch can be closed to allow the voltage divider (such as the one above) to operate. Figure 1 The voltage divider described herein outputs a decaying small-signal clock signal superimposed on the reset signal. In other words, by closing the switch, the presence of an activity signal becomes available via the reset pin, allowing the user to identify its presence. At the same time, this activity signal does not interfere with the normal operation of the reset pin to maintain the reset signal at a high level (or at least until the reset pin is pulled low, for example, by the user pressing the device's reset button or other mechanism to seek a reset).

[0049] It is important to understand that, although Figure 5 This high-level approach is illustrated in the embodiments, but many variations and alternatives are possible. It is important to note that after this point, additional operations can be performed on the complete boot sequence from power-on to code execution. Such operations may include checking for the presence of a bootloader, and if present, execution may jump to its location in non-volatile memory and begin code execution. Otherwise, if the bootloader is absent, control may jump to the beginning of the application code to begin code execution.

[0050] Now for reference Figure 6 A flowchart of a method according to another embodiment is shown. More specifically, Figure 6 Method 600 can be performed by a user seeking to identify or detect the presence of activity signals to confirm IC functionality and / or various parameters of the IC.

[0051] As shown, method 600 begins by coupling an observation instrument (scope), such as an oscilloscope, and / or test circuitry to an IC (box 610). Although described as coupling to an IC, it should be noted that this connection can be to a connection point, such as a contact available on a circuit board to which the IC is adapted. It should also be noted that the test circuitry may include, as described above... Figure 3 Or the monitoring circuit module described in 4. Of course, in some cases, the device itself may include the test circuit, such as an evaluation board that includes the circuit module, to make it easy to identify the presence of active signals.

[0052] Next, regarding Figure 5 A similar approach, as described, allows power to be supplied to the IC at block 620 and the reset pin to be released at block 630. Thereafter, it can be determined at diamond block 640 whether the attenuated small-signal clock signal is superimposed on the reset signal. In other words, the user can seek to determine the presence of an activity signal, for example, via a coupled oscilloscope or via a test circuit with output indicators such as LEDs described above. If the signal is not detected when power is properly supplied and the timeout period for transitioning to normal operation has elapsed, the IC can be identified as not functioning (block 650).

[0053] Instead, if the activity signal is detected, control is passed to box 660, where the IC can be identified as active. It should be noted that in some cases, method 600 may end here, where the activity signal is used to identify the IC's liveness or basic functionality.

[0054] As described above, it is also possible to use the activity signal to identify certain parameters of the IC, such as whether a bootloader is installed, and if so, the type of bootloader present. Therefore, as further shown at diamond box 670, it can be determined whether the superimposed activity signal is modulated. If not, as described above, basic functionality is confirmed, and the method can terminate. If it is determined that the activity signal is modulated, control is passed to box 680, where one or more parameters of the IC environment can be identified based on the modulation applied to the signal. For example, different modulation schemes can be used to identify the presence of different types of bootloaders.

[0055] As an example, different modulation schemes can be used to identify whether a bootloader is installed, and if so, to indicate the presence of a conventional UART bootloader, a dummy stub, or another type of bootloader. These bootloader types can be revealed by modulating the activity signal using amplitude or frequency shift keying techniques, such as on-off keying (OOK) modulation with varying symbol durations, for viewing on an oscilloscope. It is important to understand that, although... Figure 6 This high level is shown in the embodiments, but many variations and alternatives are possible.

[0056] Implementation examples can be carried out in many different environments. Reference now. Figure 7 A block diagram of a representative integrated circuit 700 is shown, which can be configured to generate activity signals as described herein. Figure 7 In the embodiments shown, the integrated circuit 700 may be, for example, a microcontroller, a wireless transceiver that can operate according to one or more wireless protocols (among others, such as WLAN-OFDM, WLAN-DSSS, Bluetooth), or other devices that can be used in a variety of use cases including sensing, metering, monitoring, embedded applications, communications, applications, etc., and may be particularly suitable for use in IoT devices.

[0057] In the illustrated embodiment, integrated circuit 700 includes memory system 710. In one embodiment, memory system 710 may include non-volatile memory, such as flash memory, and volatile memory devices, such as RAM. In one embodiment, the non-volatile memory may be implemented as a non-transitory storage medium capable of storing instructions and data. Such non-volatile memory may store instructions, including instructions for closing a switch to cause the output of an activity signal according to one embodiment (and possibly later disable the activity signal).

[0058] The memory system 710 is coupled to a digital core 720 via a bus 750. The digital core 720 may include one or more cores and / or microcontrollers that act as the main processing unit of the integrated circuit. Furthermore, the digital core 720 may be coupled to a clock generator 730, which may provide one or more phase-locked loops or other clock generator circuit modules to generate various clocks for use by the circuit modules of the IC, including low-power clock signals on which active signals may be superimposed.

[0059] As further illustrated, IC 700 further includes a power circuit module 740, which may include one or more voltage regulators. Depending on the specific implementation, additional circuit modules may optionally be present to provide various functionalities and interaction with external devices. Such circuit modules may include an interface circuit module 760, which can provide an interface with various off-chip devices; and a sensor circuit module 770, which may include various on-chip sensors, including digital and analog sensors, to sense desired signals, such as for metering applications.

[0060] In addition, such as Figure 7 As shown, the transceiver circuit module 780 can be provided to enable the transmission and reception of wireless signals, for example, according to one or more local or wide-area wireless communication schemes such as Zigbee, Bluetooth, IEEE 802.11, IEEE 802.15.4, cellular communication, etc. It should be understood that although shown in this high-level view, many variations and alternatives are possible.

[0061] It is important to note that ICs such as those described in this article can be implemented in a variety of different devices, such as IoT devices. As two examples, the IoT device could be a smart light bulb in a home or industrial automation network, or a smart utility meter used in a smart utility network, such as a mesh network in which communication is based on the IEEE 802.15.4 specification or other such wireless protocols.

[0062] Now for reference Figure 8 A high-level diagram of a network according to one embodiment is shown. Figure 8 As shown, network 800 includes various devices, including smart devices (such as IoT devices), routers, and remote service providers. Figure 8 In embodiments, the mesh network 805 may exist, for example, in a network with multiple IoT devices 810. 0-nIn buildings. This IoT device enables the generation of activity signals as described herein. As shown, at least one IoT device 810 is coupled to a router 830, which in turn communicates with a remote service provider 860 via a wide area network 850 (e.g., the Internet). In one embodiment, the remote service provider 860 may be a back-end server of a utility handling communications with the IoT device 810. It should be understood that, although... Figure 8 This high level is shown in the embodiments, but many variations and alternatives are possible.

[0063] In this embodiment, the activity signal provided via the reset pin provides developers (such as the IC designer or a downstream customer incorporating the IC into the device) with the immediate ability to determine whether the device is active or not upon boot. For example, this mechanism can determine whether the device is likely to be damaged due to overvoltage or permanent damage caused by electrostatic discharge. As a result, this early identification of the device's functionality or activity can save development time. Furthermore, by providing different modulation modes to the activity signal, certain parameters of the IC and / or its environment can be easily determined simply by identifying the activity signal with a specific modulation type.

[0064] While this disclosure has described a limited number of implementations, many modifications and variations will be apparent to those skilled in the art upon which this disclosure is made. The appended claims are intended to cover all such modifications and variations.

Claims

1. An apparatus comprising: An oscillator is used to output a clock signal on the first line; A switch, which is coupled to the first line; as well as A voltage divider, which is coupled to a switch; The switch is controlled to output the clock signal to the pin via a voltage divider through the first line in non-reset mode, and to prevent the clock signal from being provided to the pin in reset mode. The clock signal will be output via the pin at a low signal level.

2. The apparatus of claim 1, wherein the voltage divider comprises: The first resistor coupled between the switch and the pin; as well as A second resistor is coupled between the pin and the supply voltage pin.

3. The apparatus of claim 2, wherein the apparatus comprises an integrated circuit having a single semiconductor die, and a first resistor and a second resistor are formed on the single semiconductor die.

4. The apparatus of claim 1, wherein the output of the clock signal at a low attenuation level includes an activity signal for indicating the functionality of the apparatus.

5. The apparatus of claim 1, wherein the modulation of the clock signal at a low attenuation level is used to indicate the type of bootloader.

6. The apparatus of claim 1, wherein the clock signal at a decaying small signal level is between a supply voltage level and a second voltage level, the second voltage level being greater than a logic high threshold level.

7. The apparatus of claim 1, wherein the clock signal is output via a pin at a low-attenuation signal level superimposed on a reset signal, the reset signal being substantially at the supply voltage level in a non-reset mode, and the pin includes a reset pin.

8. The apparatus of claim 1, further comprising control circuitry coupled to a switch, the control circuitry being configured to control the switch to couple the clock signal to a pin in response to completion of a reset mode.

9. The apparatus of claim 8, wherein the control circuit is configured to control the switch to open in a reset mode, and after the reset mode, the control circuit is configured to control the switch to close.

10. The apparatus of claim 1, further comprising a monitoring circuit coupled to the pin, the monitoring circuit being used to identify the presence of the clock signal at a decaying small signal level.

11. The apparatus of claim 10, wherein the monitoring circuit includes an oscilloscope for displaying the clock signal at a low-attenuation signal level.

12. The apparatus of claim 10, wherein the monitoring circuit comprises: A comparator has: The first input terminal is coupled to the pin; as well as The second input terminal is used to receive a reference voltage, wherein the comparator is used to output a comparison signal based on the comparison between the voltage at the pin and the reference voltage; as well as A light-emitting diode coupled to the comparator, wherein the light-emitting diode is used to illuminate when the clock signal at a low decaying signal level is present.

13. A method comprising: Disconnect the switch of the integrated circuit that is coupled between the reset pin of the integrated circuit and the oscillator, which is used to provide a clock signal; In response to the release of a logic low voltage at the reset pin, the pre-boot sequence of the integrated circuit is executed; as well as The switch is closed so that a decayed version of the clock signal is superimposed on the reset signal output at the reset pin to indicate the functionality of the integrated circuit.

14. The method of claim 13, further comprising identifying at least one parameter of the integrated circuit in response to an attenuated version of the clock signal.

15. The method of claim 13, further comprising modulating the clock signal using a first modulation to identify at least one parameter of the integrated circuit.

16. The method of claim 15, further comprising identifying the bootloader type of the integrated circuit based on a first modulation.

17. An integrated circuit, comprising: switch; The core circuit is used to control the switch; An oscillator is used to output a clock signal; A first resistor is coupled between the switch and the pad of the integrated circuit; as well as A second resistor is coupled between the pads of the integrated circuit and the supply voltage pads; When the core circuit is activated, the clock signal will be superimposed on the reset signal at the pad. When the core circuit closes the switch, the attenuated version of the clock signal will be superimposed on the reset signal output at the pad.

18. The integrated circuit of claim 17, wherein the voltage of the reset signal having superimposed clock signals remains above a logic high threshold.

19. The integrated circuit of claim 17, wherein the superimposed clock signal is used to identify the functionality of the integrated circuit.

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