Chip verification method, verification platform and storage medium

Abstract

Embodiments of the present invention provide a chip verification method, verification platform, and storage medium. The method includes: establishing a slave chip environment, the slave chip environment including an instantiated first wide area functional connection module, an instantiated first port physical layer, and a communication verification component; wherein the communication verification component provides the first wide area functional connection module with behavioral incentives to initiate a bootstrap program; and verifying the communication function between a master chip and the slave chip based on the slave chip environment. The chip verification method can improve chip verification efficiency.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of chip technology, and in particular to a chip verification method, a verification platform, and a storage medium. Background Art

[0002] Multi-die architecture refers to the complete SOC (System on Chip) design based on die (chip), and encapsulating multiple dies into a package through high-speed bus links and expansion.

[0003] However, when performing multi-die architecture verification, the verification efficiency needs to be improved. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a chip verification method, a verification platform, and a storage medium to improve verification efficiency.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a chip verification method, comprising:

[0007] Constructing a slave chip environment, the slave chip environment including an instantiated first wide area function connection module, an instantiated first port physical layer, and a communication verification component; wherein the communication verification component is used to provide a behavioral incentive for the first wide area function connection module to start a boot program;

[0008] Based on the slave chip environment, the communication function of the master chip is verified.

[0009] In a second aspect, an embodiment of the present invention provides a verification platform, which is used to execute the chip verification method provided by an embodiment of the present invention.

[0010] In a third aspect, an embodiment of the present invention provides a storage medium, wherein the storage medium stores the chip verification method provided by an embodiment of the present invention.

[0011] An embodiment of the present invention provides a chip verification method, verification platform and storage medium, the method comprising: constructing a slave chip environment, the slave chip environment comprising an instantiated first wide area functional connection module, an instantiated first port physical layer, and a communication verification component; wherein the communication verification component is used to provide behavioral incentives for starting a boot program for at least the first wide area functional connection module; and based on the slave chip environment, verifying the communication function between a master chip and the slave chip.

[0012] It can be seen that the chip verification method in the embodiment of the present invention provides behavioral incentives for the boot program to the first wide area functional connection module directly through the communication verification component in the chip environment, so that there is no need to provide a large number of components and timings in the chip environment to load the complete boot program. Instead, the corresponding verification process can be directly performed based on these behavioral incentives, thereby avoiding the large number of circuit modules and timings required by the verification platform to load the complete boot program, as well as the time consumed in compiling and simulating these circuit modules and timings, thereby improving the verification efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0014] Figure 1 An optional flow chart of a chip verification method provided by an embodiment of the present invention;

[0015] Figure 2 A schematic diagram of an optional structure of a slave chip environment provided by an embodiment of the present invention;

[0016] Figure 3 A schematic diagram of the connection structure between the slave chip environment and the master chip provided in an embodiment of the present invention;

[0017] Figure 4 An optional structural diagram of a chip provided in an embodiment of the present invention;

[0018] Figure 5 An optional flow chart of step S200 provided in an embodiment of the present invention;

[0019] Figure 6 An optional flowchart of step S11 provided in an embodiment of the present invention;

[0020] Figure 7 An optional flowchart of step S220 provided in an embodiment of the present invention;

[0021] Figure 8 An optional flowchart of step S230 provided in an embodiment of the present invention;

[0022] Figure 9 This is an optional flowchart of step S240 provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0024] Based on the background technology, when verifying a multi-die architecture, the verification efficiency needs to be improved.

[0025] The inventors discovered that when verifying a multi-Die architecture, cross-Die communication verification is required. Specifically, it is necessary to use a boot program to verify the wide-area functional connection module of each Die in a multi-Die architecture. For example, taking one Die as the Master Die (master chip) and another Die as the Slave Die (slave chip), when verifying the communication function from the Master Die to the Slave Die, it is necessary to use a boot program to initialize and configure the wide-area functional connection module of each Die, and perform synchronous link training. However, this process requires each Die to load a complete boot program. Therefore, a large number of circuit modules and timings need to be provided in the verification environment for adaptation, and these circuit modules and timings need to be compiled and simulated before they can be used, which requires the verification platform to further consume a large amount of compilation and simulation time to provide these circuit modules and timings, thereby resulting in low chip verification efficiency.

[0026] Based on this, an embodiment of the present invention provides a chip verification method, which includes: constructing a slave chip environment, the slave chip environment including an instantiated first wide area functional connection module, an instantiated first port physical layer, and a communication verification component; wherein the communication verification component is used to provide behavioral incentives for starting a boot program for at least the first wide area functional connection module; based on the slave chip environment, verifying the communication function between the master chip and the slave chip.

[0027] It can be seen that the chip verification method in the embodiment of the present invention provides behavioral incentives for the boot program to the first wide area functional connection module directly through the communication verification component in the chip environment, so that there is no need to provide a large number of components and timings in the chip environment to load the complete boot program. Instead, the corresponding verification process can be directly performed based on these behavioral incentives, thereby avoiding the large number of circuit modules and timings required by the verification platform to load the complete boot program, as well as the time consumed in compiling and simulating these circuit modules and timings, thereby improving the verification efficiency of the chip.

[0028] Figure 1 An optional flow chart of the chip verification method provided by an embodiment of the present invention is shown as an example. Figure 1 As shown, the method includes:

[0029] Step S10: Constructing a slave chip environment.

[0030] The slave chip environment includes an instantiated first wide area functional connection module, an instantiated first port physical layer, and a communication verification component; wherein the communication verification component is used to provide behavioral incentives for starting a boot program for the first wide area functional connection module.

[0031] The first wide area function connection module is the wide area function connection module instantiated from the chip environment, and the first port physical layer is the port physical layer instantiated from the chip environment.

[0032] It should be noted that behavioral stimuli (also called stimuli) are signals generated by the platform or analog components to drive the verification process. These signals are distinct from the test signals generated by instantiated structures or the test signals generated by various structures in the chip design. In the embodiments of the present invention, the verification process is driven by behavioral stimuli, thereby eliminating the need for instantiation of unnecessary circuit modules.

[0033] It can be seen that the embodiment of the present invention only instantiates the necessary circuit modules, while other circuit modules that run the boot program cooperate by using the communication verification component to provide behavioral incentives for the first wide area functional connection module, and no longer provide components and timing for loading a complete boot program. Therefore, the communication function of the main chip can be verified in the single-chip verification process, and the verification process is simple and efficient, thereby improving the verification efficiency of the chip.

[0034] Step S11: Based on the slave chip environment, verify the communication function of the master chip.

[0035] It is understandable that based on the constructed slave chip environment, the communication functions of the master chip can be verified, especially the functional connection module of the master chip and the communication functions of the physical layer of the port of the master chip.

[0036] The embodiment of the present invention creates a slave chip environment to verify the communication function of the main chip. The communication function of the main chip can be verified through a single-chip verification process, thereby avoiding the construction of a multi-chip architecture. At the same time, a communication verification component is used to provide behavioral incentives for the first wide area function connection module, and no longer provides components and timing for loading a complete boot program. The verification process is simple and efficient, thereby improving the verification efficiency of the chip.

[0037] In an alternative example, refer to Figure 2The optional structural diagram of the slave chip environment shown in the figure shows that the slave chip environment constructed in step S11 in the embodiment of the present invention includes an instantiated first wide area function connection module 200, an instantiated first port physical layer 210, and a communication verification component 220. The communication verification component includes a simulated boot program 221 and a slave chip excitation component 222;

[0038] The simulated boot program 221 is used to simulate the action stimulus generated by the boot program in the slave chip environment, and the slave chip stimulus component 222 is used to provide the slave chip environment with the action stimulus generated by the slave chip end;

[0039] It can be understood that in the process of executing the boot program, in addition to the boot program issuing corresponding action instructions, the chip also needs to perform corresponding adaptation and response. Therefore, in an embodiment of the present invention, the simulated boot program 221 is used to simulate the action stimulus generated by the boot program in the chip environment, and the chip stimulus component 222 can generate corresponding action stimulus from the perspective of the chip end, thereby cooperating to complete the execution process of the boot program.

[0040] In addition, in some further examples, the execution process of the boot program may also involve the main chip to perform corresponding adaptation and response. Therefore, the communication verification component 220 may further include a main chip excitation component 223. The main chip excitation component 223 is used to provide action excitation of the main chip end to the slave chip environment, and then generate corresponding action excitation from the perspective of the main chip end, thereby cooperating to complete the execution process of the boot program.

[0041] Among them, in an embodiment of the present invention, each part of the communication verification component is a bus verification component, for example, it can be an AXI (Advanced eXtensible Interface, a bus protocol) bus verification component, so that the corresponding models and components can be constructed based on a unified bus protocol, simplifying the construction process from the chip environment.

[0042] In a further example, refer to Figure 3The schematic diagram of the connection structure of the slave chip environment and the master chip is shown. In the constructed slave chip environment, the first port physical layer includes: a first physical coding sublayer (shown in the figure as PCS1), a first transmitter interface (shown in the figure as TX1), a first receiver interface (shown in the figure as RX1) and a first synchronization signal port (shown in the figure as SYNC_OK port 1). The first physical coding sublayer (shown in the figure as PCS1) further includes a first register group (shown in the figure as REGS1). Correspondingly, the port physical layer in the master chip is a second port physical layer, and the second port physical layer is correspondingly provided with a second physical coding sublayer (shown in the figure as PCS2), a second transmitter interface (shown in the figure as TX2), a second receiver interface (shown in the figure as RX2) and a second synchronization signal port (shown in the figure as SYNC_OK port 2), wherein the second physical coding sublayer (shown in the figure as PCS2) further includes a second register group (shown in the figure as REGS2).

[0043] Different from the actual chip structure (taking the main chip in the figure as an example), the actual chip is provided with a clock circuit and a reset circuit (refer to the CLK / RESET in the main chip in the figure). In the slave chip environment constructed in the embodiment of the present invention, the clock circuit and the reset circuit are not provided in the physical layer of the first port, thereby further simplifying the structure of the slave chip environment and improving the chip verification efficiency.

[0044] Specifically, in an embodiment of the present invention, the constructed slave chip environment can reuse the clock signal and reset signal of the master chip, thereby further reducing the circuit modules that need to be instantiated in the slave chip environment, simplifying the slave chip environment, reducing the time spent on loading related circuit modules and timing, and compiling and simulating these circuit modules and timing, thereby improving the verification efficiency of the chip.

[0045] Specifically in one example, during the process of verifying the communication function of the master chip in step S11, the master chip excitation component can generate an action excitation, so that the master chip generates a clock signal and / or a reset signal, and the slave chip environment can receive the clock signal and / or reset signal of the master chip, thereby executing a preset verification process based on the clock signal and / or reset signal of the master chip. Specifically, the master chip excitation component can act on the clock signal circuit and / or reset chip circuit of the master chip to generate the clock signal and / or reset signal required by the entire master chip system, and the slave chip environment can receive the clock signal and / or reset signal of the master chip through the first port physical layer, thereby multiplexing the clock signal and / or reset signal.

[0046] In a further example, in the constructed slave chip environment, the first wide area function connection module includes: a third register group (shown as REGS3 in the figure) and a first resetter group, wherein the first resetter group includes a first cold resetter (shown as COLD reset1 in the figure) and a first hard resetter (shown as HARD reset1 in the figure). Correspondingly, in the master chip, the second wide area function connection module includes: a fourth register group (shown as REGS4 in the figure) and a second resetter group, wherein the second resetter group includes a second cold resetter (shown as COLD reset2 in the figure) and a second hard resetter (shown as HARDreset2 in the figure).

[0047] The first resetter group may perform a cold reset and a hard reset on the slave chip environment based on the reset signal of the master chip received by the physical layer of the first port.

[0048] In the process of verifying the communication function of chip components, it is usually necessary to synchronize the various processes between chips. Figure 3 In the main chip structure shown in the figure, the second wide area function connection module includes a synchronization circuit (shown as SYNC_OK in the figure), and the second port physical layer is further provided with a second synchronization signal port (shown as SYNC_OK port 2 in the figure). In the actual chip communication process, the synchronization signal port lines of each chip are connected, thereby realizing the synchronous timing behavior of each chip driven by the synchronization signal between chips.

[0049] Next, combine Figure 4 The following figure shows an optional structure diagram of a chip, which introduces the synchronous driving process of the chip. Figure 4 The synchronization circuit in the wide area functional connection module of the chip includes an output enable register (also called an OE register, shown as Q_OE in the figure), an output enable port override (also called an OE port override, shown as QE_OVERRIDE in the figure), a synchronization signal write circuit (shown as sync in the figure) and a synchronization signal register (shown as SYNC_OK_Y in the figure); the port physical layer of the chip includes a synchronization signal port (shown as SYNC_OK port in the figure), and an input and output circuit (shown as dft_gpio in the figure).

[0050] Specifically, the synchronous driving process of the chip includes: when the chip executes a preset process that requires synchronization, the OE_OVERRIDE signal can be set to 1. If the preset process is completed, the Q_OE output enable is set to 0 and transmitted to the SYNC_OK port via the input and output circuit, so that the SYNC_OK port outputs a synchronization signal 1 to the outside of the chip based on the Q_OE enable signal (in one example, the SYNC_OK port pulls up the synchronization signal); if the preset process has not been completed, the Q_OE output enable is set to 1 and transmitted to the SYNC_OK port via the input and output circuit, so that the SYNC_OK port outputs an invalid synchronization signal 0 to the outside of the chip based on the Q_OE enable signal. At this time, based on the SYNC_OK port, each chip line is connected with logic. Only when the SYNC_OK ports of all chips complete the preset process and output the synchronization signal 1 to the outside of the chip, the SYNC_OK port outputs the SYNC_OK value 1 to the synchronization signal write circuit sync in the chip, and the synchronization signal write circuit sync stores the SYNC_OK value in the synchronization signal register SYNC_OK_Y.

[0051] Based on the above synchronization process, it can be seen that only when the signals of the SYNC_OK ports of all DIEs are 1, the SYNC_OK port can store the SYNC_OK value "1" in the synchronization signal register SYNC_OK_Y.

[0052] Correspondingly, the synchronous driving process of the main chip is as follows:

[0053] After the master chip configures the OE_OVERRIDE signal to 1 and Q_OE to 0 during the boot process, the SYNC_OK port continuously outputs the synchronization signal 1 and reads the value of the synchronization signal register SYNC_OK_Y until the SYNC_OK value reaches 1, indicating that the preset process has been synchronized and completed in all chips. After that, the Q_OE output enable can be configured to 1, causing SYNC_OK to output the invalid synchronization signal "0" and updating the synchronization signal register SYNC_OK_Y to 0.

[0054] In the embodiment of the present invention, in order to further simplify the structure of the slave chip environment, no synchronization circuit is provided in the first wide area function connection module in the slave chip environment.

[0055] Accordingly, to drive the synchronous timing behavior of the master chip in the verification platform of the embodiment of the present invention, a synchronization stimulus is further generated during the step of verifying the communication function of the master chip (rather than generating a synchronization signal based on the corresponding synchronization circuit). By generating the synchronization stimulus, the timing is adapted to the verification process of the master chip without instantiating the corresponding circuit module, thereby avoiding timing errors during the verification process.

[0056] Specifically in one example, during the process of verifying the communication function of the master chip in step S11, the verification platform can be controlled based on the verification process in the slave chip environment, and when it is determined that the slave chip environment has completed the preset process, a synchronization stimulus (for example, stimulus "1") is sent to the master chip; wherein the preset process can be understood as a process executed simultaneously by the slave chip environment and the master chip, and after the master chip receives the synchronization stimulus, it executes the synchronization timing behavior. In a further optional example, when the slave chip environment executes the preset process, an invalid synchronization stimulus (for example, stimulus "0") can also be sent to the master chip, thereby indicating that the slave chip environment has not completed the preset process.

[0057] In the embodiment of the present invention, in the step of verifying the communication function of the master chip, the synchronization function of the master chip and the slave chip environment can be further verified. Step S11 can include the following process:

[0058] Step S200: Verify the synchronization function of the master chip and the slave chip environment.

[0059] refer to Figure 5 The optional flow chart of step S200 is shown, and the specific verification process of the synchronization function in step S200 is as follows:

[0060] Step S201: Sending a synchronous stimulus to the master chip to indicate that the slave chip environment has completed the preset process;

[0061] Specifically, the verification platform may send a synchronous stimulus "1" to the master chip to indicate that the slave chip environment has completed a preset process.

[0062] Step S202: After the master chip completes the preset process, monitor the status of the output enable register and the synchronization register in the second wide area function connection module;

[0063] Among them, when monitoring the status of the output enable register (i.e., OE register) and the synchronization register on the main chip side, it can be determined whether the synchronization register is set to the synchronization completion state, for example, set to "1". If so, the synchronization function verification of the main chip to the slave chip environment is successful. If not, the synchronization function verification of the main chip to the slave chip environment fails. At the same time, it is determined whether the OE register is set to the confirmation state, for example, set to "1". If so, it indicates that there is an error in starting the boot program. If not, and the synchronization register is "0", it indicates that there is an error in the hardware circuit in the main chip.

[0064] It should be noted that the verification process of the above-mentioned synchronization function can be combined with other function verification steps of the chip verification process without being performed separately. For example, it can be combined with the following step S230, specifically after step S233, thereby simplifying the verification process and improving verification efficiency.

[0065] In an alternative example, refer to Figure 6 The optional flow chart of step S11 is shown, and step S11 may include the following process:

[0066] Step S210: Reset the slave chip environment;

[0067] Specifically, a reset signal from the master chip is received and used as a reset signal for the slave chip environment. Then, based on the reset signal, a first cold resetter and a first hard resetter of a first wide area functional connection module in the slave chip environment are configured, causing the first cold resetter and the first hard resetter to release the reset signal. In one specific example, a simulated bootloader can utilize a slave chip excitation component to configure the first cold resetter and the first hard resetter through a front door.

[0068] Through the above steps, the reset signal can be reused, so that the slave chip environment does not need to instantiate the reset circuit, thereby simplifying the verification process.

[0069] Continue to refer Figure 6 , step S11 may also include the following process:

[0070] Step S220: verifying the configuration function of the simulated boot program on the first hardware initialization register in the slave chip environment;

[0071] The first hardware initialization register is a register in the third register group of the first wide area function connection module in the slave chip environment.

[0072] Specifically, refer to Figure 7 The step S220 shown in the optional flow chart, the specific verification process of the step S220 verifying the configuration function can be as follows:

[0073] Step S222: enabling the slave chip excitation component to write microcode in the physical layer of the first port in the slave chip environment;

[0074] The simulated boot program can be used to enable the slave chip excitation component to write microcode into the first port physical layer of the slave chip environment through a backdoor.

[0075] Step S224: enabling the slave chip excitation component to configure the first hardware initialization register in the slave chip environment to a valid value;

[0076] The simulated boot program can be used to enable the chip excitation component to configure the first hardware initialization register to a valid value through a backdoor.

[0077] Step S226: monitoring and waiting for the main chip to run the boot program, loading the microcode on the physical layer of the second port of the main chip, and after the main chip configures the second hardware initialization register to a valid value, determining whether the waiting time has timed out;

[0078] If the timeout occurs, the configuration function verification fails; if the timeout does not occur, the configuration function verification succeeds.

[0079] The second hardware initialization register is a register in the fourth register group of the second wide area function connection module in the main chip.

[0080] It should be noted that the hardware initialization register (also called HWinitComplete register) is configured with a valid value, which can guide the update of the subsequent link training status value.

[0081] In an optional example, it is further determined whether the slave chip excitation component successfully writes the microcode to the port physical layer in the slave chip environment through the backdoor. Specifically, between step S222 and step S224, the following steps may be further included:

[0082] Step S223: enabling the slave chip excitation component to read the microcode of the physical layer of the first port, and determining whether the read microcode is consistent with the written microcode;

[0083] If they are consistent, the write function verification is successful and the subsequent steps are continued; if they are inconsistent, the write function verification fails, which indicates that the slave chip verification has failed.

[0084] The master chip excitation component can read the microcode of the physical layer of the first port through a backdoor, and then determine whether the read microcode is consistent with the written microcode. It can be understood that by ensuring that the microcode in the slave chip environment is consistent with the preset microcode, it is possible to avoid failures in subsequent link training with the master chip due to different slave chip microcode configurations.

[0085] Continue to refer Figure 6 , step S11 may also include the following process:

[0086] Step S230: verifying the hardware circuit function of the physical layer of the second port.

[0087] Specifically, refer to Figure 8 The optional flow chart of step S230 is shown, and the specific verification process of step S230 for verifying the hardware circuit function is as follows:

[0088] Step S231: configuring the training status register (FULL TRAIN) of the first wide area functional connection module to a valid value from the chip excitation component;

[0089] Specifically, the slave chip excitation component can be configured to a valid value for the training state register (FULLTRAIN) through the backdoor or frontdoor. When the slave chip excitation component configures the training state register through the frontdoor, the bootloader simulates the configuration of the training state register by issuing a corresponding action stimulus using the slave chip excitation component.

[0090] Step S232: The slave chip excitation component configures the coding command register (also called PCS-COMMAND register) of the physical layer of the first port to a first value, where the first value is used to indicate that the slave chip environment has not performed link training;

[0091] When the slave chip excitation component configures the encoding command register of the physical layer of the first port through the front door, the simulation boot program can configure the encoding command register of the physical layer of the first port using the slave chip excitation component by issuing corresponding action excitation.

[0092] Step S233: When the training state register of the first wide area function connection module is configured as a preset value, a synchronous stimulus is sent to the main chip;

[0093] After the above configuration, the link training state machine (LTSSM) of the first wide area functional connection module in the slave chip automatically enters the RECOVERY_NULLTRAINING state (i.e., only the port physical layer is performing link training, and the physical coding layer is not). In this state, the slave chip environment continuously monitors the value of the training status register (also known as the TrainDone register) of the first wide area functional connection module until the TrainDone register value reaches a preset value. In one example, the preset value can be a high level, indicating that only the port physical layer link training is complete.

[0094] When the training status register of the first wide area functional connection module is configured as a preset value, the verification platform will send a synchronization stimulus "1" to the master chip to indicate that the slave chip environment has completed the corresponding operation.

[0095] It is understandable that when the slave chip environment has not completed the relevant configuration, the verification platform can send an invalid synchronization stimulus (ie, "0") to the master chip, thereby indicating that the slave chip environment has not completed the corresponding operation.

[0096] Step S234: monitoring and waiting for the master chip to complete the same configuration as the slave chip environment, and determining whether the waiting time has timed out. If so, the configuration function verification fails; otherwise, the configuration function verification succeeds.

[0097] The master chip can perform the same configuration as steps S231 to S233 on the second wide area function connection module and the second port physical layer of the master chip based on the boot program, that is, configuring the training status register of the second wide area function connection module to a valid value, configuring the encoding command register of the second port physical layer to a first value, and configuring the training status register of the second wide area function connection module to a preset value.

[0098] It should be noted that after the master chip receives the synchronization stimulus from the slave chip environment and completes the same configuration as the slave chip environment, it can set its synchronization signal to a high potential "1" to complete the synchronization.

[0099] After the master chip completes the same configuration as the slave chip environment, it is determined whether the waiting time has timed out. If so, the configuration function verification fails; if not, the configuration function verification succeeds.

[0100] Continue to refer Figure 6 , step S11 may also include the following process:

[0101] Step S240: Verify the link training function of the master chip to the slave chip environment.

[0102] Specifically, refer to Figure 9 The optional flow chart of step S240 is shown, and the specific verification process of step S240 for verifying the link training function is as follows:

[0103] Step S241: configuring the encoding command register in the physical layer of the first port from the chip stimulus component to start the link training process;

[0104] The slave chip excitation component can configure the PCS_command register in the physical layer of the first port to the second value, thereby starting the link training process. At the same time, the slave chip excitation component can close the clock confirmation register (also known as the clk_ready register) in the wide area function connection module in the slave chip environment and invalidate the clock confirmation signal (also known as the clk_ready signal) in the clock confirmation register, so that after the master chip synchronously configures the encoding command register, the link training process is started synchronously with the master chip.

[0105] When the slave chip stimulus component configures the PCS_command register in the first port physical layer through the front door, the simulation boot program can configure the PCS_command register in the first port physical layer using the slave chip stimulus component by issuing corresponding action stimulus.

[0106] Step S242: Sending synchronization stimulus to the master chip until the master chip completes the synchronization operation;

[0107] Among them, the verification platform will send a synchronous stimulus "1" to the master chip to indicate that the slave chip environment has completed the corresponding operation; accordingly, the master chip simultaneously performs the corresponding PCS_command register configuration and clk_ready register to make the clk_ready signal invalid, thereby starting the link training process, and after receiving the synchronous stimulus sent by the slave chip environment, sets the master chip end synchronization signal to a high potential "1", and the synchronization operation is completed.

[0108] Step S243: The slave chip excitation component configures the clock confirmation register in the physical layer of the first port to be turned on until the slave chip environment link training process is completed;

[0109] In this embodiment, the slave chip excitation component reconfigures the clk ready register of the slave chip environment to make the clk_ready signal valid, thereby making the second value configured in the encoding command register in the physical layer of the first port valid, and the slave chip environment link training process starts to execute.

[0110] When the slave chip excitation component configures the clock confirmation register in the physical layer of the first port through the front door, the simulation boot program can use the slave chip excitation component to configure the clock confirmation register in the physical layer of the first port by issuing corresponding action excitation.

[0111] Step S244: monitoring and waiting for whether the physical layer link training process of the second port is completed. If completed, the link training function verification is successful.

[0112] The monitoring device monitors whether the physical layer link training process of the second port of the main chip is completed. If so, the link training function is verified to be successful. If the link training function is verified to be successful, bootloader execution identification information (also known as postcode print information) indicating successful link training can be output. If the postcode print information fails to be output, the link training function verification fails.

[0113] It should be noted that during the process of outputting the Postcode print information, the master chip's bootloader needs to read the training state value (also known as the training_state value) that indicates whether link training is complete. In the slave chip environment, a preset training_state value can be set for the mapping address of the training_state value, thereby allowing the master chip to read the training_state value based on the mapping address. In an optional example, based on the status of link training, the slave chip excitation component can modify the slave chip's training_state value through a backdoor.

[0114] Specifically, the specific process of outputting the Postcode printing information is as follows: the boot program of the master chip reads the training_state value of the slave chip environment, and outputs the Postcode printing information based on the training_state value.

[0115] It can be understood that the master chip can only read the training_state value of the slave chip environment when the master chip has unobstructed access to the slave chip environment. Therefore, the above steps of the embodiment of the present invention not only verify the printing information output function, but also verify whether the master chip has unobstructed access to the slave chip environment.

[0116] The chip verification method in the embodiment of the present invention provides behavioral incentives for the boot program to the first wide area functional connection module directly through the communication verification component in the chip environment, so that there is no need to provide a large number of components and timings in the chip environment to load the complete boot program. Instead, the corresponding verification process can be directly performed based on these behavioral incentives, thereby avoiding the large number of circuit modules and timings required by the verification platform to load the complete boot program, as well as the time consumed in compiling and simulating these circuit modules and timings, thereby improving the verification efficiency of the chip.

[0117] An embodiment of the present invention further provides a verification platform, which is equipped with the chip verification method provided by the embodiment of the present invention.

[0118] An embodiment of the present invention provides a storage medium, wherein the storage medium stores the chip verification method provided by the embodiment of the present invention.

[0119] The above describes multiple embodiment schemes provided by the embodiments of the present invention. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present invention.

[0120] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A chip verification method, characterized in that: include: Constructing a slave chip environment, the slave chip environment including an instantiated first wide area function connection module, an instantiated first port physical layer, and a communication verification component; wherein the communication verification component is used to provide a behavioral incentive for at least the first wide area function connection module to start a boot program; Based on the behavioral stimulus of the slave chip environment, the communication function of the master chip is verified.

2. The chip verification method according to claim 1, characterized in that: The communication verification component includes a simulated boot program, a slave chip excitation component and a master chip excitation component; Among them, the simulated boot program is used to simulate the action stimulus generated by the boot program in the slave chip environment; the slave chip stimulus component is used to provide the action stimulus generated by the slave chip end to the slave chip environment; the master chip stimulus component is used to provide the action stimulus of the master chip end to the slave chip environment.

3. The chip verification method according to claim 2, characterized in that: In the step of constructing the slave chip environment, the constructed slave chip environment multiplexes the clock signal and / or reset signal of the master chip; In the step of verifying the communication function of the main chip, the main chip excitation component generates an action excitation, so that the main chip generates a clock signal and / or a reset signal, and the slave chip environment receives the clock signal and / or reset signal of the main chip, and executes a preset verification process based on the clock signal and / or reset signal of the main chip.

4. The chip verification method according to claim 2, characterized in that: The step of verifying the communication function of the main chip includes: When it is determined that the slave chip environment completes the preset process, a synchronous stimulus is sent to the master chip; wherein the slave chip environment and the master chip execute the preset process simultaneously, and after the master chip receives the synchronous stimulus, the master chip executes the synchronous timing behavior.

5. The chip verification method according to claim 4, characterized in that: The step of verifying the communication function of the master chip further includes: sending an invalid synchronization stimulus to the master chip when the slave chip environment executes a preset process.

6. The chip verification method according to claim 3, characterized in that: The slave chip environment receives the clock signal and reset signal of the master chip, and executes a preset verification process based on the clock signal and reset signal of the master chip, including: receiving a reset signal from a master chip and using the reset signal from the master chip as a reset signal for the slave chip environment; Based on the reset signal, a first cold resetter and a first hard resetter of the first wide area function connection module are configured so that the first cold resetter and the first hard resetter release the reset signal.

7. The chip verification method according to claim 2, characterized in that: The first wide area function connection module includes at least a first hardware initialization register, the master chip includes a second wide area function connection module, and the second wide area function connection module includes at least a second hardware initialization register; the step of verifying the communication function of the master chip at least includes verifying the configuration function of the simulated boot program on the first hardware initialization register in the slave chip environment; The verifying of the configuration function of the simulated boot program on the first hardware initialization register in the slave chip environment includes: Enable the slave chip excitation component to write microcode in the physical layer of the first port in the slave chip environment; Enable the slave chip excitation component to configure the first hardware initialization register in the slave chip environment to a valid value; Monitor and wait for the main chip to run the boot program, load the microcode on the physical layer of the second port of the main chip, and after the main chip configures the second hardware initialization register to a valid value, determine whether the waiting time has timed out. If so, the configuration function verification fails. If not, the configuration function verification succeeds.

8. The chip verification method according to claim 7, characterized in that: After the step of causing the slave chip excitation component to write microcode into the physical layer of the first port in the slave chip environment, and before causing the slave chip excitation component to configure the first hardware initialization register in the slave chip environment to a valid value, the method further includes: The chip excitation component reads the test microcode of the port physical layer and determines whether the read test microcode is consistent with the written test microcode. If they are consistent, the write function verification is successful; if they are inconsistent, the write function verification fails.

9. The chip verification method according to claim 4, characterized in that: The master chip further includes a second port physical layer; the step of verifying the communication function of the master chip at least includes verifying the hardware circuit function of the second port physical layer; The verifying the hardware circuit function of the physical layer of the second port includes: The slave chip excitation component configures a training status register of the first wide area functional connection module to a valid value, wherein the training status register is used to identify a training status of a hardware circuit in the first wide area functional connection module; The slave chip excitation component configures the encoding command register of the physical layer of the first port to a first value, where the first value is used to indicate that the slave chip environment does not perform link training; When the training state register of the first wide area functional connection module is configured as a preset value, a synchronous stimulus is sent to the main chip; Monitor and wait for the master chip to complete the same configuration as the slave chip environment, and determine whether the waiting time has timed out. If so, the configuration function verification fails; if not, the configuration function verification succeeds.

10. The chip verification method according to claim 4, characterized in that: The step of verifying the communication function of the master chip at least includes verifying the link training function of the master chip to the slave chip environment; The verification of the link training function of the master chip to the slave chip environment includes: Configuring the encoding command register in the physical layer of the first port from the chip stimulus component to start a link training process; Send synchronization stimulus to the master chip until the master chip completes the synchronization operation; The clock confirmation register in the physical layer of the first port of the chip stimulus component is configured to be turned on until the link training process is completed; Monitor whether the physical layer link training process of the port waiting for the main chip is completed. If completed, the link training function verification is successful.

11. The chip verification method according to claim 4, characterized in that: The step of verifying the communication function of the master chip at least includes verifying the link training function of the master chip to the slave chip environment; Send synchronous stimulus to the master chip to indicate that the slave chip environment has completed the preset process; After the master chip completes the preset process, monitoring the state of the output enable register and the state of the synchronization register in the second wide area function connection module; If the synchronization register is set to the synchronization completion state, the synchronization function verification is successful; if the synchronization register is not set to the synchronization completion state, the synchronization function verification fails; If the synchronization function verification fails, determine whether the output enable register is set to the confirmation state. If so, there is an error in the startup boot program; if not, there is an error in the hardware circuit in the main chip; wherein, the confirmation state is used to indicate that the main chip has completed the preset process.

12. A verification platform, characterized in that: include: The verification platform is used to execute the chip verification method according to any one of claims 1 to 11.

13. A storage medium, characterized in that: The storage medium stores the chip verification method according to any one of claims 1 to 11.

Images