Chip verification structure, chip verification system and method

Abstract

The present invention discloses a chip verification structure, a chip verification system, and a chip verification method, comprising an analog chip, the analog chip comprising at least one analog module, the analog module being used to simulate the functions of an analog function module of a chip design; the analog chip and the sample of the chip design being homologous; the analog chip being connected to an FPGA chip via multiple types of interfaces, the FPGA chip comprising at least one digital module being used to simulate the functions of a digital function module of the chip design. Because the analog chip and the sample of the chip design are homologous, the functional differences between the analog chip and the analog function module of the chip design can be reduced. Because the analog chip is connected to the FPGA chip via multiple types of interfaces, the differences between the interfaces between the analog chip and the FPGA chip and the interfaces between the analog function module and the digital function module of the chip design can be reduced, thereby improving the verification accuracy of the chip design and reducing the verification cycle of the chip design.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a chip verification structure, a chip verification system and a method. Background Art

[0002] With the increasing integration density of chips and the diversification of market demands, designs that integrate digital and analog functional modules into a single chip, such as hybrid digital-analog chip designs or SOC (System on Chip) designs, are gradually gaining a larger share of the chip market. However, this design brings greater difficulties to chip simulation and verification.

[0003] Although chip design functionality can currently be verified by simulating the digital functional modules of a chip design using an FPGA (Field Programmable Gate Array) and the analog functional modules of a chip design using peripheral discrete circuits, discrete circuits are electronic circuits composed of resistors, capacitors, diodes, transistors, and field-effect transistors. These circuits differ from actual chips in terms of interface and functionality, leading to incomplete matching between the chip design verification results and the actual results, resulting in poor chip verification accuracy. Summary of the Invention

[0004] The invention discloses a chip verification structure, a chip verification system and a method to improve the verification accuracy of the chip.

[0005] In the first aspect, the present invention discloses a chip verification structure, including an analog chip, the analog chip including at least one analog module, the analog module being used to simulate the function of the analog functional module of the chip design; the analog chip being homologous to the sample of the chip design; the analog chip being connected to an FPGA chip through the multiple types of interfaces, the FPGA chip including at least one digital module, the digital module being used to simulate the function of the digital functional module of the chip design, so as to verify the function of the chip design based on the simulation results of the analog module and the digital module.

[0006] In some optional examples, the analog chip is connected to the FPGA chip through at least an IO interface and a communication protocol interface; the chip verification structure also includes a control module; the analog chip is connected to the GPIO interface of the FPGA chip through the IO interface; the first signal output by the analog chip is transmitted to the FPGA chip through the IO interface and the GPIO interface; the second signal output by the FPGA chip is transmitted to the analog chip through the IO interface and the GPIO interface; the analog chip is communicatively connected to the FPGA chip through the control module and the communication protocol interface; the third signal output by the analog chip is processed by the control module and then transmitted to the FPGA chip through the communication protocol interface; the fourth signal output by the FPGA chip is transmitted to the control module through the communication protocol interface, and then processed by the control module and transmitted to the analog chip.

[0007] In some optional examples, the analog chip includes multiple analog modules, which respectively simulate the functions of multiple analog functional modules of the chip design; the chip verification structure also includes a register stack, which includes multiple registers, and the multiple registers have a one-to-one mapping relationship with the multiple analog modules; the control module transmits the processed fourth signal to the corresponding analog module through the register stack.

[0008] In some optional examples, the communication protocol interface includes a serial communication interface; the control module includes a serial-to-parallel conversion unit, a codec unit and a processing unit; the serial-to-parallel conversion unit is used to perform serial-to-parallel conversion or parallel-to-serial conversion on the third signal or the fourth signal; the codec unit is used to encode or decode the third signal or the fourth signal; the processing unit is used to transmit the processed third signal to the analog chip and transmit the processed fourth signal to the serial communication interface.

[0009] In some optional examples, the control module further includes an error checking unit; the error checking unit is configured to perform error checking and correction on the third signal or the fourth signal.

[0010] In some optional examples, the timing-related signals include enable signals, reset signals, clock signals, handshake signals, bus signals, control signals, and status signals; and the timing-unrelated signals include adjustment signals and calibration signals.

[0011] In some optional examples, the simulation chip outputs a waveform through an IO interface so that the simulation result of the simulation chip can be observed based on the waveform.

[0012] In some optional examples, the analog chip and the sample of the chip design are homologous, including that the analog chip and the sample of the chip design are from the same MPW wafer.

[0013] In a second aspect, the present invention discloses a chip verification system, comprising a chip verification structure as described in any one of the above items and an FPGA chip.

[0014] In a third aspect, the present invention discloses a chip verification method, comprising: performing parameter configuration on an FPGA chip and a chip verification structure; the chip verification structure comprises an analog chip, the analog chip comprises at least one analog module, and the analog module is used to simulate the function of the analog functional module of the chip design; the FPGA chip comprises at least one digital module, and the digital module is used to simulate the function of the digital functional module of the chip design; the analog chip is connected to the FPGA chip through multiple types of interfaces; the analog chip is homologous to the chip design; the analog chip is simulated and tested by the FPGA chip; and according to the test results of the analog chip, determining whether the analog chip meets the verification requirements.

[0015] The chip verification structure, chip verification system and method disclosed in the present invention simulate the functions of the analog functional modules of a chip design through the analog module of the analog chip, and simulate the functions of the digital functional modules of the chip design through the digital module of the FPGA chip. Since the analog chip and the sample of the chip design are homologous, the functional differences between the analog chip and the analog functional modules of the chip design can be reduced. Since the analog chip is connected to the FPGA chip through multiple types of interfaces, the interface differences between the analog chip and the FPGA chip and the interface differences between the analog functional modules and the digital functional modules of the chip design can be reduced, thereby improving the verification accuracy of the chip design and reducing the verification cycle of the chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0017] Figure 1 A schematic diagram of a chip verification structure disclosed in an embodiment of the present invention.

[0018] Figure 2 A schematic diagram of a chip verification structure disclosed in another embodiment of the present invention.

[0019] Figure 3 A schematic diagram of a chip verification structure disclosed in another embodiment of the present invention.

[0020] Figure 4A schematic diagram of a chip verification structure disclosed in another embodiment of the present invention.

[0021] Figure 5 A schematic diagram of a chip verification structure disclosed in another embodiment of the present invention.

[0022] Figure 6 A schematic diagram of a chip verification system disclosed in one embodiment of the present invention.

[0023] Figure 7 The present invention discloses a flow chart of a chip verification method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a chip verification structure, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a chip verification structure disclosed in an embodiment of the present invention. The chip verification structure includes an analog chip 10. The analog chip 10 includes at least one analog module. The analog module is used to simulate the function of the analog functional module of the chip design. The analog chip 10 is homologous to the sample of the chip design.

[0026] Among them, the analog chip 10 and the chip design sample are of the same origin, including that the analog chip 10 and the chip design sample come from the same MPW (Multi Project Wafer) wafer. That is to say, the analog chip 10 and the chip design sample have the same manufacturing process, and the two are taped out on the same wafer. Based on this, not only can the peripheral discrete circuits be streamlined or omitted, but also the differences in FAB (Fabrication, semiconductor manufacturing) processes and PDK (Process Design Kit, process design kit) parameters between the analog chip 10 and the chip design can be reduced, thereby reducing the functional differences between the analog chip 10 and the analog functional modules of the chip design, thereby improving the verification accuracy of the chip design and reducing the verification cycle of the chip design.

[0027] Furthermore, analog chip 10 is connected to FPGA chip 11 via various interfaces. FPGA chip 11 includes at least one digital module, which is used to simulate the functions of the digital functional modules of the chip design. This allows verification of the chip design's functionality based on the simulation results of analog chip 10 and FPGA chip 11. An analog functional module is a functional module that transmits, transforms, processes, and amplifies analog signals, while a digital functional module is a functional module that uses digital signals to perform arithmetic and logical operations on digital quantities.

[0028] Since the analog chip 10 can be connected to the FPGA chip 11 through multiple types of interfaces, the interface differences between the analog chip 10 and the FPGA chip 11 and the interface differences between the analog functional modules and the digital functional modules of the chip design can be reduced, thereby improving the verification accuracy of the chip design and reducing the verification cycle of the chip design.

[0029] In some embodiments of the present invention, Figure 2 As shown, Figure 2 This is a schematic diagram of a chip verification structure disclosed in another embodiment of the present invention. The analog chip 10 is connected to the FPGA chip 11 at least through an IO (I / O interface) interface 12 and a communication protocol interface 13. The chip verification structure also includes a control module 14.

[0030] The analog chip 10 can be connected to the GPIO (General-purpose input / output) interface of the FPGA chip 11 through the IO interface 12. The first signal output by the analog chip is transmitted to the FPGA chip 11 through the IO interface 12 and the GPIO interface. The second signal output by the FPGA chip 11 is transmitted to the analog chip 10 through the IO interface 12 and the GPIO interface. The analog chip 10 is communicatively connected to the FPGA chip 11 through the control module 14 and the communication protocol interface 13. The third signal output by the analog chip 10 is processed by the control module 14 and then transmitted to the FPGA chip 11 through the communication protocol interface 13. The fourth signal output by the FPGA chip 11 is transmitted to the control module 14 through the communication protocol interface 13, and then processed by the control module 14 and transmitted to the analog chip 10.

[0031] Since the GPIO interface pins of the FPGA chip 11 are limited, if all the signals of the analog chip 10 are led out to the GPIO interface pins of the FPGA chip 11, there will often be a shortage of pins. Therefore, in some embodiments of the present invention, the transmission of some signals between the analog chip 10 and the FPGA chip 11 is achieved through the communication protocol interface 13, which not only reduces the restrictions on the selection of the FPGA chip 11, but also realizes the automation of signal transmission between the analog chip 10 and the FPGA chip 11 through the communication protocol interface 13 while occupying fewer GPIO interface pins.

[0032] In addition, analog chips 10 with different functions may be applied to the chip verification structure in the embodiment of the present invention to reuse the interface and control module 14 in the chip verification structure, thereby improving the reusability of the chip verification structure.

[0033] In some embodiments of the present invention, the first signal includes a timing-related signal, and the third signal includes a timing-independent signal. That is, the timing-related signal is transmitted through the IO interface 12, and the timing-independent signal is transmitted through the communication protocol interface 13. The timing-related signal may be a signal that is strongly related to timing control, and the timing-independent signal may be a signal that is weakly related to timing control.

[0034] In some embodiments, timing-related signals include enable signals, reset signals, clock signals, handshake signals, bus signals, control signals, and status signals, and timing-unrelated signals include trim signals and calibration signals. Of course, the present invention is not limited to this. In other embodiments, the first signal and the third signal may be classified according to other signal types, which will not be described in detail here.

[0035] Since there are numerous Trim and Calibration signals, and these signals belong to different analog function modules, a communication protocol interface 13 is required to ensure the transmission of these signals. It is understood that enable signals, reset signals, clock signals, handshake signals, bus signals, control signals, and status signals can be transmitted to the FPGA chip 11 through different IO interfaces, which will not be described in detail here.

[0036] In some embodiments of the present invention, Figure 3 As shown, Figure 3This is a schematic diagram of a chip verification structure disclosed in another embodiment of the present invention. An analog chip 10 includes multiple analog modules, each of which simulates the functions of multiple analog functional modules in the chip design. The chip verification structure also includes a register file 15, which includes multiple registers. Each register has a one-to-one mapping relationship with each analog module. A control module 14 transmits a processed fourth signal to the corresponding analog module via the register file 15.

[0037] Among them, the register stack 15 can be an array composed of multiple registers. Since multiple registers have a one-to-one mapping relationship with multiple analog modules, the control module 14 can determine the analog module source of the signal based on the register source of the signal, and then transmit the signal to the digital module corresponding to the analog module in the FPGA chip 11.

[0038] In some embodiments of the present invention, the communication protocol interface 13 includes a serial communication interface. Of course, the present invention is not limited thereto. In other embodiments, the communication protocol interface 13 may also include a JTAG (Joint Test Action Group) interface, etc.

[0039] On this basis, in some embodiments of the present invention, Figure 4 As shown, Figure 4 This is a schematic diagram of a chip verification structure disclosed in another embodiment of the present invention. The control module 14 includes a serial-to-parallel conversion unit, a codec unit, and a processing unit. The serial-to-parallel conversion unit is used to perform serial-to-parallel conversion or parallel-to-serial conversion on the third signal or the fourth signal; the codec unit is used to encode or decode the third signal or the fourth signal; and the processing unit is used to transmit the processed third signal to the analog chip and transmit the processed fourth signal to the serial communication interface.

[0040] Based on this, the third signal output by the analog module is subjected to parallel-to-serial conversion processing by the serial-to-parallel conversion unit, encoded by the codec unit, determined by the processing unit to correspond to the communication protocol interface 13, and transmitted to the FPGA chip 11 via the corresponding communication protocol interface 13. After the fourth signal output by the FPGA chip 11 is transmitted to the control module 14 via the corresponding communication protocol interface 13, the fourth signal is subjected to serial-to-parallel conversion processing by the serial-to-parallel conversion unit, decoded by the codec unit, determined by the processing unit to correspond to the analog module, and transmitted to the corresponding analog module via the register stack 15.

[0041] In some embodiments of the present invention, Figure 5 As shown, Figure 5This is a schematic diagram of a chip verification structure disclosed in another embodiment of the present invention. The control module 14 further includes an error checking unit, which is used to perform error checking and correction on the third signal or the fourth signal.

[0042] It is understandable that the functional units in the control module 14 may be configured according to actual needs. For example, if some control modules 14 do not need to perform error checking, then the control module 14 may not include an error checking unit.

[0043] In some embodiments of the present invention, the simulation chip 10 outputs a waveform through one of the IO interfaces so that the simulation results of the simulation chip 10 can be observed based on the waveform. The IO interface can be connected to a waveform display device such as an oscilloscope to observe the waveform through the oscilloscope and obtain the simulation results of the simulation chip 10.

[0044] As another optional implementation of the present invention, an embodiment of the present invention discloses a chip verification system, such as Figure 6 As shown, Figure 6 This is a schematic diagram of a chip verification system disclosed in one embodiment of the present invention. The chip verification system includes the chip verification structure disclosed in any of the above embodiments and an FPGA chip. This chip verification system can improve the verification accuracy of chip designs and reduce the verification cycle of chip designs.

[0045] As another optional implementation of the present invention, an embodiment of the present invention discloses a chip verification method, such as Figure 7 As shown, Figure 7 This is a flowchart of a chip verification method disclosed in one embodiment of the present invention. The chip verification method includes:

[0046] S101: Configuring parameters for the FPGA chip and chip verification structure;

[0047] like Figure 1 As shown, the chip verification structure includes an analog chip 10, which includes at least one analog module for simulating the functions of the analog functional modules of the chip design, and an FPGA chip 11, which includes at least one digital module for simulating the functions of the digital functional modules of the chip design. Furthermore, the analog chip 10 is connected to the FPGA chip 11 via various types of interfaces, and the analog chip 10 and the chip design are of the same origin. It is understood that this chip verification structure can be the chip verification structure disclosed in any of the above embodiments.

[0048] Before chip verification, the chip verification system needs to perform a power-on self-test to establish the initial power supply and clock system to ensure the normal operation of subsequent operations. Then, the FPGA chip 11 and the chip verification structure can be configured. Among them, configuration signals can be transmitted to the analog chip 10 through the GPIO interface and IO interface 12 of the FPGA chip 11 to configure the first signals of the analog chip 10, such as enable signals, reset signals, clock signals, and handshake signals.

[0049] Then, after configuring the FPGA chip 11 with the content related to the communication protocol, the analog module of the analog chip 10 can be configured through the communication protocol interface 13 of the FPGA chip 11. The content related to the communication protocol includes command words and data, etc. The command word consists of a read / write bit, an address, and a length, and the analog module in the analog chip 10 can be accessed and modified through the command word.

[0050] S102: Performing simulation testing on the analog chip through the FPGA chip;

[0051] After configuring the parameters of the FPGA chip and the chip verification structure, the test phase begins. The FPGA chip 11 continuously sends command words and data to the analog module of the analog chip 10 through the communication protocol interface 13 to complete the simulation test of the functions of all analog modules in the analog chip 10.

[0052] S103: Determine whether the analog chip meets the verification requirements based on the test result of the analog chip.

[0053] In some embodiments, the waveforms output by the analog chip 10 can be used to observe the test results of the analog modules of the analog chip 10 to determine whether the analog modules of the analog chip meet the verification requirements of the chip verification system. In particular, it can be determined whether the Trim and Calibration signals output by the analog modules meet the verification requirements of the chip verification system. In some embodiments, steps S101 and S102 are repeated multiple times to eliminate the impact of process variations.

[0054] It is understandable that once it is determined that the analog chip meets the verification requirements, the analog chip 10 and the FPGA chip 11 can be controlled to perform simulation verification, so as to verify the functions of the chip design based on the simulation results of the analog chip 10 and the FPGA chip 11.

[0055] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The above embodiments merely represent several implementation methods of this specification. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the scope of this specification, and these modifications and improvements fall within the scope of protection of this specification. Therefore, the scope of protection of the patent in this specification shall be subject to the appended claims.

Claims

1. A chip verification structure, characterized in that: The analog chip includes at least one analog module, and the analog module is used to simulate the function of the analog function module of the chip design; the analog chip is homologous to the sample of the chip design; The analog chip is connected to the FPGA chip through various types of interfaces. The FPGA chip includes at least one digital module, which is used to simulate the functions of the digital function modules of the chip design, so as to verify the functions of the chip design based on the simulation results of the analog module and the digital module. Wherein, the analog chip is connected to the FPGA chip at least through an IO interface and a communication protocol interface; the chip verification structure also includes a control module; The analog chip is connected to the GPIO interface of the FPGA chip through the IO interface; the first signal output by the analog chip is transmitted to the FPGA chip through the IO interface and the GPIO interface; the second signal output by the FPGA chip is transmitted to the analog chip through the IO interface and the GPIO interface; The analog chip is communicatively connected to the FPGA chip through the control module and the communication protocol interface; the third signal output by the analog chip is processed by the control module and then transmitted to the FPGA chip through the communication protocol interface; the fourth signal output by the FPGA chip is transmitted to the control module through the communication protocol interface, and then processed by the control module and transmitted to the analog chip.

2. The chip verification structure according to claim 1, characterized in that: The analog chip includes a plurality of analog modules, and the plurality of analog modules respectively simulate the functions of the plurality of analog function modules of the chip design; The chip verification structure further includes a register stack, which includes multiple registers. The multiple registers have a one-to-one mapping relationship with the multiple analog modules. The control module transmits the processed fourth signal to the corresponding analog module through the register stack.

3. The chip verification structure according to claim 1 or 2, characterized in that: The communication protocol interface includes a serial communication interface; the control module includes a serial-to-parallel conversion unit, a coding and decoding unit and a processing unit; The serial-to-parallel conversion unit is used to perform parallel-to-serial conversion processing on the third signal output by the analog chip or to perform serial-to-parallel conversion processing on the fourth signal output by the FPGA chip; the codec unit is used to encode the third signal output by the serial-to-parallel conversion unit or to decode the fourth signal output by the serial-to-parallel conversion unit; the processing unit is used to transmit the fourth signal output by the codec unit to the analog chip, and to transmit the third signal output by the codec unit to the serial communication interface.

4. The chip verification structure according to claim 3, characterized in that: The control module further includes an error checking unit; the error checking unit is configured to perform error checking and correction on the third signal or the fourth signal.

5. The chip verification structure according to claim 1, characterized in that: The first signal includes a timing-related signal, and the third signal includes a timing-independent signal; the timing-related signal includes an enable signal, a reset signal, a clock signal, a handshake signal, a bus signal, a control signal and a status signal; the timing-independent signal includes an adjustment signal and a calibration signal.

6. The chip verification structure according to claim 1, characterized in that: The simulation chip outputs a waveform through an IO interface so that the simulation result of the simulation chip can be observed based on the waveform.

7. The chip verification structure according to claim 1, characterized in that: The analog chip and the sample of the chip design are of the same origin, which includes that the analog chip and the sample of the chip design are from the same MPW wafer.

8. A chip verification system, characterized in that: The invention comprises the chip verification structure and FPGA chip described in any one of claims 1 to 7.

9. A chip verification method, characterized in that: include: Parameter configuration is performed on an FPGA chip and a chip verification structure; the chip verification structure includes the chip verification structure according to any one of claims 1 to 7; The analog chip is simulated and tested by the FPGA chip; and whether the analog chip meets the verification requirements is determined based on the test results of the analog chip.

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