Fault-Tolerant Generation Method and Device for Deep Learning Recommendation Model Based on RRAM

Abstract

This invention provides a fault-tolerant generation method and device for deep learning recommendation models based on Restricted Random Access Memory (RRAM). The method includes: applying to a DLRM architecture; the DLRM architecture includes a kernel, an RRAM computation unit, a register for the base pointer of a sparse index array, a register for the sparse index array, and memory; the method includes: training an RRAM model with different error matrices under the same variance, obtaining the accuracy of the RRAM model, and calculating the average accuracy; when the average accuracy converges or no longer increases, obtaining the RRAM model with the strongest robustness under that variance; adjusting the variance multiple times to obtain the RRAM model with the strongest robustness under each variance; and swapping the low-dimensional vector mapping to memory based on the importance and resistance distribution of the low-dimensional vector after mapping through a neural network. This invention can implement a fault-tolerant method for tightly coupled EL characteristics for Restricted Random Access Memory (RV) and Restricted Random Access Memory (SF).

Description

Technical Field

[0001] This invention relates to the field of resistive random access memory (RRAM) technology, and in particular to the field of deep learning recommendation model technology for RRAM. Background Technology

[0002] Resistive Random Access Memory (RRAM) is a new type of non-volatile memory, also known as a memristor. RRAM cells are passive bipolar devices, typically employing a metal-insulator-metal structure. The intermediate insulator, which exhibits resistive switching characteristics, can be made of various materials, such as HfO2, TiOx, and NiO.

[0003] The resistive switching characteristic originates from the conductive film between two electrodes. When a certain programming voltage is applied to the cell, the cell expands and connects the two electrodes together, thereby reducing the cell resistance and making it conductive. This process is called a SET operation, which switches the RRAM cell from a high-resistance state (HRS, representing "0") to a low-resistance state (LRS, representing "1"). Therefore, the reverse operation, which breaks the gap between the two electrodes, is called a RESET operation. Both SET and RESET are considered write operations to the RRAM. In the prior art, RRAM cells can be organized in a crossbar structure to achieve higher area efficiency. When used as a storage device, the row decoder opens a word line according to the address and sends a read voltage to read data from the selected bit line through a sensing amplifier.

[0004] Leveraging its crossbar structure and resistive switching characteristics, RRAM holds immense potential for in-memory computing. First, we can store an n×n matrix within an n×n resistor. Then, with all the crossbars turned on simultaneously, we set the input voltage in vector form. Therefore, the output current of the crossbars is the result of matrix-vector multiplication. Scalar multiplication is performed via voltage conductance multiplication, the result of which is the accumulation of all currents within the crossbars. Since RRAM conductance can only be positive, two crossbars are needed to represent the application matrix with both positive and negative parameters.

[0005] The basic operator of a Convolutional Neural Network (CNN) is the vector multiplication-addition (MAC) operation. In-memory computation in RRAM effectively accelerates CNNs. The input vector is converted to a voltage V by an ADC and applied to the horizontal wordline. The weights are stored in the RRAM crossbar's memory cells. According to Kirchhoff's Law, a current I is obtained on the vertical bitline. The current I is converted to a digital signal by sampling and holding (S&H) and digital-to-analog conversion (ADC), and then shift-and-add (S&A) to obtain the final result. Figure 1The specific vector multiplication and addition process is shown. The input vector [2, 1, 3] is converted to binary, the weights [1, 2, 4] are converted to binary and stored in the RRAM crossbar. In the first cycle, [1, 1, 0] is obtained, and in the second cycle, [1, 0, 1] is obtained. After S&A, [1, 0, 0, 0, 0] = 24 = 16 is finally obtained.

[0006] RRAM is widely used in neural network accelerators due to its large storage capacity, fast read / write speed, and high computational intensity. However, the unreliability of RRAM resistors leads to a significant decrease in accuracy during neural network inference. Common errors include resistance error (RV), stuck-in-the-wrong-position (SF), resistance voltage drop (IRDrop), thermal noise, and random electrical noise.

[0007] RRAM has various errors, with RV and SF being the main focus of this study. Firstly, regarding RV, we cannot program an accurate value for each memory cell; therefore, resistance error exists, categorized into end-to-end variation (DDV) and cycle-interval variation (CCV). The former is the error between the actual value written to each memory cell in the RRAM crossbar and the target value, while the latter is the error that occurs even when writing the same target value across multiple cycles. DDV follows a normal distribution, as shown in the formula below, where Wpj represents the ideal conductance value to be written to the memory cell, tqj represents the actual conductance value written, and N indicates a normal distribution with a mean of 0 and a variance of σ².

[0008] RRAM resistor error formula:

[0009] Another common issue degrading RRAM device performance is SF (Signal Default). Due to defects introduced during manufacturing, some memory cells cannot be programmed and remain stuck in a high-resistivity state (HRS) or a low-resistivity state (LRS), referred to as SF1 and SF0, respectively. In terms of conductivity, HRS and LRS represent low and high conductance, respectively. When small weights are mapped to SF1, the error is smaller, while when mapped to SF0, the error is larger; conversely, when large weights are mapped to SF1, the error is larger, while when mapped to SF0, the error is smaller. Previous work has tested the proportions of SF1 and SF0 in RRAM to be 9.04% and 1.75%, respectively.

[0010] With the explosive growth of data, deep learning recommendation models (DLRM) are increasingly widely used in advertising, social relationships, and information recommendation, more accurately capturing user attention. Examples include the deep neural networks in YouTube's recommendation system and deep recommendation models in personal recommendation systems. DLRM mainly consists of embedding lookup (EL), feature interaction (concatenation, inner product, outer product, etc.), and MLP. The features of users and products are transformed into a low-dimensional dense feature matrix through EL. In some models, user features are processed using bottom-MLP. The embedding vectors of users and products are concatenated, and inner and outer products are calculated to form a rich feature space. Finally, top-MLP is used to transform it into a classification problem. If it is a click-through rate (CTR) problem, it is transformed into binary classification; if it is a recommendation ranking problem, it is transformed into sorting the probability of each category in descending order.

[0011] Embedding Lookup (EL) transforms discrete, high-dimensional feature vectors into dense, low-dimensional feature vectors. It's a memory-intensive operator, encompassing embedding aggregation and scaling. The former quickly finds the target embedding vector by index, while the latter performs merging operations such as summation, weighted summation, or attention mechanisms on the found embedding vectors. RRAM's advantages of large storage capacity, fast read / write speeds, and in-memory computation make it ideal for accelerating EL computation. Furthermore, the inability of RRAM crossbars to activate multiple rows simultaneously also suits the sparsity of embedding aggregation. Assuming user 1's browsing history is [1, (1, 2, 4, 6), (3, 5)], indicating that user 1 viewed items 1, 2, 4, and 6, the algorithm recommends items 3 and 5, representing the user's clicked and unclicked items, tagged with 1 and 0 respectively. The embedding aggregation and scaling operations are as follows: Figure 2 Users 1 and 2 clicked on items (1, 2, 4, 6) and (3, 4, 5, 6) respectively. The results are then summed along the column direction to obtain scaled embedding vectors for both. The embedding table is stored in the RRAM crossbar. A high voltage is input to the row that needs to be activated, and the vector is scaled along the bitline direction to output the scaled embedding vector. Summary of the Invention

[0012] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a fault-tolerant generation method and device for deep learning recommendation models based on RRAM, which can achieve fault tolerance of tightly coupled EL characteristics for RV and SF.

[0013] To achieve the above and other related objectives, this invention provides a fault-tolerant generation method for deep learning recommendation models based on RRAM, applied to a DLRM architecture. The DLRM architecture includes a kernel, an RRAM computation unit, a register for the base pointer of a sparse index array, a register for the sparse index array, and memory. The method includes: training an RRAM model with different error matrices under the same variance, obtaining the accuracy of the RRAM model, and calculating the average accuracy; when the average accuracy converges or no longer increases, obtaining the RRAM model with the strongest robustness under that variance; adjusting the variance multiple times to obtain the RRAM model with the strongest robustness under each variance; and swapping the low-dimensional vector mappings to memory based on the importance and resistance distribution of the low-dimensional vectors mapped through the neural network.

[0014] In one embodiment of the present invention, the step of swapping the low-dimensional vectors mapped by the neural network to the memory based on the importance and resistance distribution of the low-dimensional vectors mapped by the neural network includes: calculating the sum of the minimum absolute deviations of each low-dimensional vector in the low-dimensional vector table, emb_L1_sum, and the sum of the minimum absolute deviations of the resistance error matrix, var_L1_sum; sorting the sums of the minimum absolute deviations, emb_L1_sum and var_L1_sum, in descending order respectively, and swapping the low-dimensional vectors that meet the preset conditions to the memory based on the index.

[0015] In one embodiment of the present invention, the step of exchanging low-dimensional vectors that meet preset conditions to memory based on indexes includes: obtaining the top-k rows of the sum of minimum absolute deviation and emb_L1_sum and the top-k rows of the sum of minimum absolute deviation and var_L1_sum respectively; if the top-k rows of the sum of minimum absolute deviation and var_L1_sum exist in the index of the top-k rows of the sum of minimum absolute deviation and emb_L1_sum, then the low-dimensional vectors that meet the preset conditions are exchanged to memory.

[0016] In one embodiment of the present invention, the RRAM calculation unit generates an error matrix by using a first percentage of the error in the low-resistivity state and a second percentage of the error in the high-resistivity state.

[0017] In one embodiment of the present invention, the first percentage is 1.75%; the second percentage is 9.04%.

[0018] In one embodiment of the present invention, the method further includes: calculating the sum of the minimum absolute deviations of each low-dimensional vector in the low-dimensional vector table, emb_L1_sum; sorting the sum of the minimum absolute deviations, emb_L1_sum, in descending order; and determining a distinction threshold for distinguishing important low-dimensional vectors from unimportant low-dimensional vectors based on the descending order result.

[0019] In one embodiment of the present invention, top-k and bottom-k are selected as the distinction thresholds based on the descending sort result.

[0020] In one embodiment of the present invention, when the low-dimensional vector is determined to be an important low-dimensional vector, it is mapped to the row with the least error in the high-resistivity state card at the wrong position and the smallest index among the adjacent n rows in the RRAM calculation unit.

[0021] In one embodiment of the present invention, when the low-dimensional vector is determined to be an unimportant low-dimensional vector, it is mapped to the row with the least error in the wrong position and the smallest index among the adjacent n rows in the RRAM calculation unit.

[0022] To achieve the above and other related objectives, the present invention also provides an electronic device, including a memory for storing a computer program; and a processor for running the computer program to implement the steps of the RRAM-based deep learning recommendation model fault-tolerant generation method as described above.

[0023] As described above, the fault-tolerant generation method and device for deep learning recommendation models based on RRAM of the present invention have the following beneficial effects:

[0024] This invention proposes a DLRM architecture based on RRAM. For resistance error (RV), this invention repeatedly trains the model by sensing the error to obtain a more robust model. Based on the importance of weights and errors, and combined with the characteristics of the EL operator, important low-dimensional vectors (embedding vectors) are swapped to map to smaller error storage units. Based on weight and SF-aware row redundancy priority mapping: This invention continues to train the model by sensing different stuck-at-the-misplace (SF) errors to obtain a more robust model. Based on the characteristics of weights and SF errors, in the row-redundant SF error matrix, important low-dimensional vectors (embedding vectors) are mapped to the row with the least high-resistivity stuck-at-the-misplace error (SF1) and the smallest index, while unimportant embedding vectors are mapped to the row with the least low-resistivity stuck-at-the-misplace error (SF0) and the smallest index. Therefore, this invention can implement a fault-tolerant method for tightly coupled EL characteristics for RV and SF. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1This is a schematic diagram of the vector multiplication and addition process in a convolutional neural network in the prior art;

[0027] Figure 2 This is a schematic diagram of the Embedding Lookup process in the prior art, which includes embedding aggregation and scaling.

[0028] Figure 3 The diagram shows a flowchart of a fault-tolerant generation method for a deep learning recommendation model based on RRAM in one embodiment of this application.

[0029] Figures 4a to 4c The diagram shown is a schematic diagram of the fault-tolerant generation method of RRAM-based deep learning recommendation model in one embodiment of this application, which is based on weight and RV-aware priority mapping.

[0030] Figures 5a to 5b The diagram shown is a schematic of row redundancy priority mapping based on weights and SF-awareness in a fault-tolerant generation method for a deep learning recommendation model based on RRAM in one embodiment of this application.

[0031] Figure 6 The diagram shown is a schematic block diagram of an electronic device according to an embodiment of this application.

[0032] Component designation explanation

[0033] 101 Electronic Devices

[0034] 1001 processor

[0035] 1002 Memory

[0036] S100~S400 Steps Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0038] The purpose of this embodiment is to provide a fault-tolerant generation method and device for deep learning recommendation models based on RRAM, which can achieve fault tolerance of tightly coupled EL characteristics for RV and SF.

[0039] The following will elaborate on the principles and implementation methods of the RRAM-based deep learning recommendation model fault-tolerant generation method and device of the present invention, so that those skilled in the art can understand the RRAM-based deep learning recommendation model fault-tolerant generation method and device of the present invention without creative effort.

[0040] Example 1

[0041] This embodiment provides a fault-tolerant generation method for deep learning recommendation models based on RRAM, and proposes for the first time an RRAM-based DLRM accelerator. Based on weight and RV-aware priority mapping: For RV, this embodiment repeatedly trains the model by perceiving errors to obtain a more robust model. According to the importance of weights and errors, combined with the characteristics of the EL operator, important embedding vectors are swapped to the storage units with smaller errors. Based on weight and SF-aware row redundancy priority mapping: This embodiment continues to train the model by perceiving different SF errors to obtain a more robust model. According to the characteristics of weights and SF errors, in the row-redundant SF error matrix, important embedding vectors are mapped to the row with the fewest SF1 and the smallest index, and unimportant embedding vectors are mapped to the row with the fewest SF0 and the smallest index.

[0042] The fault-tolerant generation method for deep learning recommendation models based on RRAM described in this embodiment is applied to the DLRM architecture; the DLRM architecture includes a kernel, an RRAM computing unit, a register of the sparse index array base pointer, a register of the sparse index array, and memory.

[0043] This embodiment's DLRM architecture primarily focuses on accelerating and fault-tolerant Embedding Lookup. The core is responsible for data and instruction scheduling and some computation; the RRAM compute unit (RRAMCB) is an RRAM crossbar compute unit that stores the low-dimensional variable table (embedding table) and performs low-dimensional variable (embedding) vector scaling. BPReg is a register holding the base pointer of the sparse index array, and SIAReg is a register storing the acquired sparse index array, which is a one / multi-hot matrix composed of user browsing records. Memory is responsible for storing all data and computation results. User 1's browsing history (1, 2, 4, 6) is converted into a multi-hot representation [110101]. When the Core issues a command to find User 1's browsing history, it calculates the address of User 1's browsing history based on User 1's ID and the base pointer in BPReg, finds User 1's browsing history [110101] in Memory, passes it to SIAReg, sends it to RRAM, activates the corresponding embedding vector, scales the embedding vector, returns it to the output register (OR), and outputs it to Memory. However, because RRAM cannot be written to multiple times at a high frequency, the next step is to address the problem of a sharp drop in accuracy caused by errors during DLRM inference on RRAMCB.

[0044] Specifically, such as Figure 3 As shown in this embodiment, the fault-tolerant generation method for the RRAM-based deep learning recommendation model includes:

[0045] Step S100: Under the same variance, train the RRAM model using different error matrices, obtain the accuracy of the RRAM model, and calculate the average accuracy.

[0046] Step S200: When the average accuracy converges or no longer increases, obtain the RRAM model with the strongest robustness to the error at that variance.

[0047] Step S300: Adjust the variance multiple times to obtain the most robust RRAM model for each variance.

[0048] Step S400: Based on the importance and resistance distribution of the low-dimensional vector after mapping through the neural network, the low-dimensional vector is swapped to memory.

[0049] The steps S100 to 5400 of the RRAM-based deep learning recommendation model fault-tolerant generation method of this embodiment will be described in detail below with reference to Figures 4 and 5.

[0050] In this embodiment, different variances (σ) and random seeds are used to initialize the resistance error, simulating the resistance error distribution on different RRAMs. We train the model using different errors. Under the same variance σ, the model is continuously trained with different error matrices, and the accuracy of these models is tested and averaged. If the average accuracy of the model converges or no longer increases, then this model has the strongest robustness for that variance. The variance is adjusted multiple times to obtain the most robust model for each variance. Subsequently, based on the importance of the embedding vector and the resistance distribution, important embedding vectors are mapped to memory cells with smaller errors.

[0051] Specifically, in this embodiment, the step of swapping the mapping of the low-dimensional vector obtained through the neural network to the memory based on the importance and resistance distribution of the low-dimensional vector obtained through the neural network mapping includes:

[0052] 1) Calculate the sum of the minimum absolute deviations of each low-dimensional vector in the low-dimensional vector table (emb_L1_sum) and the sum of the minimum absolute deviations of the resistance error matrix (var_L1_sum);

[0053] 2) Sort the sums of the minimum absolute deviations, emb_L1_sum and var_L1_sum, in descending order respectively, and swap the low-dimensional vectors that meet the preset conditions to memory based on the index.

[0054] In this embodiment, the step of exchanging low-dimensional vectors that meet preset conditions to memory based on indexes includes: obtaining the top-k rows of the sum of minimum absolute deviation and emb_L1_sum and the top-k rows of the sum of minimum absolute deviation and var_L1_sum respectively; if the top-k rows of the sum of minimum absolute deviation and var_L1_sum exist in the index of the top-k rows of the sum of minimum absolute deviation and emb_L1_sum, then the low-dimensional vectors that meet the preset conditions are exchanged to memory.

[0055] In this embodiment, we first restore and read the saved model parameters. We calculate the sum of L1-Norm for each embedding vector in the embedding table, called emb_L1_sum. The larger the sum, the more important the embedding vector is. Similarly, the same calculation process is used for the resistance error matrix of RRAMCB. The larger the sum of L1-Norm (var_L1_sum) of the row vector, the larger the error.

[0056] Then, emb_L1_sum and var_L1_sum are sorted in descending order, and their top-k rows are selected and named emb_L1_sum_ds_k and var_L1_sum_ds_k, respectively. If var_L1_sum_ds_k_idx exists in the index emb_L1_sum_ds_k_idx of the top-k rows, it indicates that some important embedding vectors emb[i] are mapped to the row var[i] with large errors in RRAMCB. Then, emb_ds_k[i] is swapped with the unimportant embedding vector emb_ds_k_out[m] outside the top-k rows, where m represents the row index outside the top-k rows.

[0057] Finally, using different error matrices, the model with altered mapping relationships was inferred multiple times, and the average inference accuracy was calculated.

[0058] like Figures 4a to 4c As shown, firstly, in the original mapping relationship between the embedding table and the variation table, the important weights of rows 4 and 5 are mapped to rows with large errors. Then, `emb_L1_sum` and `var_L1_sum` are calculated and sorted in descending order, with k=3, resulting in `emb_L1_sum_ds_k` and `var_L1_sum_ds_k`. Rows 4 and 5 in the indexlist [4, 5, 3] of `emb_L1_sum_ds_k` exist in the index list [5, 4, 1] of `var_L1_sum_ds_k`, indicating that the important weights of rows 4 and 5 are mapped to rows with large errors. Row 3 is mapped to row 3 in the variation table with smaller errors and does not need to be swapped. Finally, rows 4 and 6, and rows 5 and 2 in the embedding table are swapped to map them to rows with smaller errors. Similar to CNNs, DLRMs possess a degree of robustness, meaning relatively small errors do not lead to a significant drop in accuracy. However, the weight matrices of the convolutional kernels in CNNs cannot be interchanged internally, as the interchanged weight matrix differs from the original, resulting in incorrect calculations. This is a fault-tolerant method that leverages the characteristics of tightly coupled EL operators.

[0059] In this embodiment, in RRAMCB, error matrices are generated with 1.75% SF0 and 9.04% SF1. The model is continuously trained using different SF error matrices. The generated model is trained under each error class, and its accuracy is tested with different errors until the test accuracy converges or no longer improves, indicating that the model under the current error is the most robust and can adapt to more types of SF errors. To improve inference accuracy, this embodiment modifies the mapping relationship between the embedding table and the SF error based on their characteristics.

[0060] Specifically, in this embodiment, the RRAM calculation unit generates an error matrix by using a first percentage of the error in the low-resistivity state and a second percentage of the error in the high-resistivity state.

[0061] In this embodiment, the first percentage is preferably, but not limited to, 1.75%; the second percentage is preferably, but not limited to, 9.04%.

[0062] In this embodiment, the method further includes: calculating the sum of the minimum absolute deviations of each low-dimensional vector in the low-dimensional vector table, emb_L1_sum; sorting the sum of the minimum absolute deviations, emb_L1_sum, in descending order; and determining a threshold for distinguishing important low-dimensional vectors from unimportant low-dimensional vectors based on the descending order result.

[0063] Among them, top-k and bottom-k are selected as the distinction thresholds based on the descending sort results.

[0064] In this embodiment, when the low-dimensional vector is determined to be an important low-dimensional vector, it is mapped to the row with the least error in the wrong position and the smallest index among the adjacent n rows in the RRAM calculation unit.

[0065] In this embodiment, when the low-dimensional vector is determined to be an unimportant low-dimensional vector, it is mapped to the row with the least error in the wrong position and the smallest index among the adjacent n rows in the RRAM calculation unit.

[0066] In this embodiment, the weights in the model are first recovered and read, and the sum of the L1-norm of each embedding vector in the embedding table is calculated, called emb_L1_sum. Next, emb_L1_sum is sorted in descending order to obtain emb_L1_sum_ds. The top-k and bottom-k (bottom-k) values ​​are selected, called emb_L1_sum_ds_top_k and emb_L1_sum_ds_bot_k, which are the thresholds for distinguishing important and unimportant embedding vectors.

[0067] Then, an error matrix with 1.75% SF0 and 9.04% SF1 and row redundancy is generated to simulate the SF error in RRAMCB. Iterate through emb_L1_sum. When emb_L1_sum[i] is greater than or equal to emb_L1_sum_ds_top_k, the embedding vector emb[i] in the i-th row is an important embedding vector, and it is mapped to the row with the fewest SF1 and the smallest index among the n adjacent rows in RRAMCB. When emb_L1_sum[i] is less than or equal to emb_L1_sum_ds_bot_k, the embedding vector emb[i] in the i-th row is an unimportant embedding vector, and it is mapped to the row with the fewest SF0 and the smallest index among the n adjacent rows in RRAMCB.

[0068] Finally, using different SF errors, the model was inferred and modified multiple times to calculate the average accuracy.

[0069] like Figures 5a to 5b As shown, S0 / S1 represent SF0 / SF1 respectively. Because S0 accounts for a small proportion, the number of S0 vectors is very small, so both S0 and S1 are increased by a factor of 5. The emb_L1_sum is sorted in descending order, and the top-2 and bottom-2 vectors are selected as the most important and least important embedding vectors, respectively, with n = 3. Figure 5a This indicates that the original mapping process resulted in two important embedding vectors being mapped to rows containing more S1, while an unimportant embedding vector was mapped to rows containing more S0, leading to a large error. Figure 5bIn the diagram, the boxes marked with diagonal lines are important low-dimensional vectors, generating an SF matrix with 50% row redundancy, i.e., 6*(1+0.5)=9. The value of emb_L1_sum[1] is 1.18, which is less than emb_L1_sum_ds_bot_2(1.8). Therefore, the embedding vector emb[1] in the first row is an unimportant embedding vector, which is mapped to the row with the fewest SF0s among the three adjacent rows. In the SF matrix [1, 2, 3] rows, the number of SF0s in the first and second rows is 0, which is the fewest, while the index of the first row is the smallest. It is mapped to the first row of the SF error matrix. Then, the embedding vectors in the second and third rows are in the middle. According to the inherent self-compensating property of DLRM, they can be mapped to the corresponding error rows normally. Subsequently, since emb_L1_sum[4] in row 4 is greater than emb_L1_sum_ds_top_2(10.7), emb[4] is an unimportant embedding vector. In rows [4, 5, 6] of the SF matrix, row 5 has the fewest S1s, so it is mapped to row 5. Embedding vectors are mapped to the corresponding rows in the SF matrix in turn. In the row-redundant SF matrix, important embedding vectors are mapped to the row with the fewest SF1s and the smallest index among the three adjacent rows; unimportant embedding vectors are mapped to the row with the fewest SF0s and the smallest index among the three adjacent rows.

[0070] Example 2

[0071] like Figure 6 As shown, this embodiment provides an electronic device 101, which includes a processor 1001 and a memory 1002. The memory 1002 is used to store computer programs. The processor 1001 is used to execute the computer programs stored in the memory 1002, so that the electronic device 101 performs the steps of the RRAM-based deep learning recommendation model fault-tolerant generation method as described in Embodiment 1. Since the specific implementation process of the RRAM-based deep learning recommendation model fault-tolerant generation method has been described in detail in Embodiment 1, it will not be repeated here.

[0072] Processor 1001 is a Central Processing Unit (CPU). Memory 1002 is connected to processor 1001 via a system bus and communicates with it. Memory 1002 stores computer programs, and processor 1001 runs the computer programs to execute the RRAM-based deep learning recommendation model fault-tolerant generation method. Memory 1002 may include Random Access Memory (RAM) and may also include non-volatile memory, such as at least one disk storage device.

[0073] Furthermore, this embodiment also provides a computer-readable storage medium storing a computer program thereon. When executed by the processor 1001, the computer program implements the steps in the RRAM-based deep learning recommendation model fault-tolerant generation method described in Embodiment 1. Embodiment 1 has already provided a detailed description of the RRAM-based deep learning recommendation model fault-tolerant generation method, which will not be repeated here.

[0074] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented using computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0075] In summary, this invention proposes a DLRM architecture based on RRAM. For resistance error (RV), this invention repeatedly trains the model by sensing the error to obtain a more robust model. Based on the importance of weights and errors, and combined with the characteristics of the EL operator, important low-dimensional vectors (embedding vectors) are swapped to small error storage units. Based on weight and SF-aware row redundancy priority mapping: this invention continues to train the model by sensing different stuck-at-the-misplace (SF) errors to obtain a more robust model. Based on the characteristics of weights and SF errors, in the row-redundant SF error matrix, important low-dimensional vectors (embedding vectors) are mapped to the row with the fewest high-resistivity stuck-at-the-misplace errors (SF1) and the smallest index, while unimportant embedding vectors are mapped to the row with the fewest low-resistivity stuck-at-the-misplace errors (SF0) and the smallest index. Therefore, this invention can implement a fault-tolerant method for tightly coupled EL characteristics for RV and SF. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A fault-tolerant generation method for a deep learning recommendation model based on RRAM, characterized by: The application is applied to a DLRM architecture; The DLRM architecture comprises a kernel, an RRAM computing unit, a register of sparse index array base pointers, a register of sparse index arrays, and a memory; the method comprises the following steps: The resistance error is initialized with different variances and random seeds to simulate the resistance error distribution on different RRAMs; under the same variance, different error matrices are used to train the RRAM model to obtain the accuracy of the RRAM model and the average accuracy; the RRAM computing unit generates the error matrix in the form of a first percentage of low-resistance state cards in error position error and a second percentage of high-resistance state cards in error position error; When the average accuracy converges or no longer continues to increase, the RRAM model with the strongest error robustness at the variance is obtained; The variance is adjusted multiple times to obtain the RRAM model with the strongest robustness at each variance; According to the importance of the low-dimensional vector after mapping through the neural network and the resistance distribution, the low-dimensional vector is exchanged and mapped to the memory. 2.The RRAM-based deep learning recommendation model fault-tolerant generation method of claim 1, wherein: The exchanging and mapping of the low-dimensional vector to the memory according to the importance of the low-dimensional vector after mapping through the neural network and the resistance distribution comprises the following steps: The sum of the minimum absolute deviations emb_L1_sum of each low-dimensional vector in the low-dimensional vector table and the sum of the minimum absolute deviations var_L1_sum of the resistance error matrix are calculated respectively; The sum of the minimum absolute deviations emb_L1_sum and the sum of the minimum absolute deviations var_L1_sum are arranged in descending order respectively, and the low-dimensional vectors meeting the preset condition are exchanged and mapped to the memory based on the index. 3.The method of claim 2, wherein: The exchanging and mapping of the low-dimensional vector to the memory based on the index comprises the following steps: The top-k rows of the sum of the minimum absolute deviations emb_L1_sum and the top-k rows of the sum of the minimum absolute deviations var_L1_sum are obtained respectively; If the top-k rows of the sum of the minimum absolute deviations var_L1_sum exist in the index of the top-k rows of the sum of the minimum absolute deviations emb_L1_sum, the low-dimensional vectors meeting the preset condition are exchanged and mapped to the memory. 4.The method of claim 1, wherein: The first percentage is 1.75%, and the second percentage is 9.04%. 5.The RRAM-based deep learning recommendation model fault-tolerant generation method of claim 1, wherein: The importance of the low-dimensional vector is also distinguished: The sum of the minimum absolute deviations emb_L1_sum of each low-dimensional vector in the low-dimensional vector table is calculated; The sum of the minimum absolute deviations emb_L1_sum is arranged in descending order; The distinguishing threshold for distinguishing important low-dimensional vectors and unimportant low-dimensional vectors is determined according to the descending arrangement result.

6. The RRAM-based deep learning recommendation model fault-tolerant generation method according to claim 5, characterized in that: The top-k and bottom-k are selected as the distinguishing threshold according to the descending arrangement result.

7. The RRAM-based deep learning recommendation model fault-tolerant generation method according to claim 5, characterized in that: When the low-dimensional vector is determined to be an important low-dimensional vector, it is mapped to the row with the least error in the high-resistance state card in the error position and the smallest index among the adjacent n rows in the RRAM computing unit.

8. The RRAM-based deep learning recommendation model fault-tolerant generation method according to claim 5 or 7, characterized in that: When the low-dimensional vector is determined to be an unimportant low-dimensional vector, it is mapped to the row with the least error in the low-resistance state card in the error position and the smallest index among the adjacent n rows in the RRAM computing unit.

9. An electronic device, comprising: The application further provides a computer readable storage medium storing a computer program, wherein the computer program is used for implementing the steps of the RRAM-based deep learning recommendation model fault-tolerant generation method according to any one of claims 1 to 8. The application further provides a computer readable storage medium storing a computer program, wherein the computer program is used for implementing the steps of the RRAM-based deep learning recommendation model fault-tolerant generation method according to any one of claims 1 to 8.

Images