A method for detecting appearance defects of semiconductor chips with a wide field of view

Abstract

The present invention belongs to the field of computer vision processing and target detection technology. Specifically, it relates to a method for detecting appearance defects in semiconductor chips with a large field of view. This method, based on stacked multi-scale group convolution YOLOv5, first acquires a large number of large-field-of-view semiconductor chip defect images and divides them into 9 / 16 / 25 equal parts to generate a multi-scale sub-defect image dataset. This dataset is then labeled and partitioned, and the model is trained using the stacked multi-scale group convolution YOLOv5 algorithm. Multi-threaded inference is used to extract sub-defect images. Finally, the sub-defect image detection results are mapped onto a large-field-of-view semiconductor chip image to complete appearance defect detection for large-field-of-view semiconductor chips. The present invention utilizes the SMGC-YOLOv5 algorithm and employs multi-scale lightweight convolution for feature extraction, significantly shortening and improving the model's training time and performance, effectively improving the discriminability of defect feature representation and the accuracy of appearance defect detection for large-field-of-view semiconductor chips.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer vision processing and target detection. Specifically, it provides a method for detecting appearance defects of semiconductor chips with a large field of view. The method is based on stacked multi-scale convolution YOLOv5. Background Art

[0002] During the semiconductor chip manufacturing process, due to the complex technology, environment, and materials involved in each process, a series of appearance defects are inevitable. These defects will affect the performance of semiconductor products to a certain extent. Therefore, semiconductor appearance defect detection is of great significance to improving chip performance.

[0003] The current common visual inspection method is still largely manual, but with the shrinking size of semiconductor chips and the improvement of inspection accuracy, manual inspection is no longer sufficient. Currently, the main automated inspection technologies are electromechanical and optical. However, the measurement equipment used is sophisticated and complex, and its manufacturing is challenging, involving multiple technical fields such as electrical, optical, and photoacoustic technologies. This places high demands on the equipment manufacturer's technical R&D capabilities and the ability to integrate cross-disciplinary technical resources, requiring long-term investment and technical accumulation.

[0004] At each node, chip feature sizes are shrinking, making defects more difficult to detect. Even subtle deviations can impact yield and performance to a certain extent. Compared to traditional surface defect detection technologies, machine vision inspection offers advantages such as non-contact, continuity, cost-effectiveness, and flexibility, providing a new development direction for defect detection. Deep learning models, represented by convolutional neural networks, have been widely researched and applied in the field of computer vision. The high performance of deep learning methods in image classification and object detection can significantly improve the recognition rate of irregular defects, enhancing overall system performance and speed. Summary of the Invention

[0005] The present invention discloses a method for detecting appearance defects of semiconductor chips with a large field of view. The method is based on stacked multi-scale convolution YOLOv5. First, a large number of semiconductor chip defect images with a large field of view are obtained and divided into 9 / 16 / 25 equal parts to generate a multi-scale sub-defect image dataset. Then, the dataset is defect-labeled and divided. A stacked multi-scale convolution YOLOv5 (Stacked Multiscale Group Convolution YOLOv5, SMGC-YOLOv5) algorithm is used for model training. Multi-threaded reasoning of sub-defect maps is utilized. Finally, the sub-defect map detection results are mapped onto a semiconductor chip image with a large field of view to complete the appearance defect detection of semiconductor chips with a large field of view.

[0006] This paper utilizes the multi-level group convolution SMGC-YOLOv5 algorithm and multi-scale lightweight convolution for feature extraction, which greatly shortens and improves the training time and performance of the model, effectively improving the discriminability of defect feature representation and the accuracy of large-field semiconductor chip appearance defect detection. The specific technical solution is as follows:

[0007] A method for detecting appearance defects of semiconductor chips with a large field of view specifically comprises the following steps:

[0008] Step 1: Input a large number of large-field-of-view semiconductor chip appearance images with certain defects;

[0009] Step 2: The semiconductor chip appearance image obtained in step 1 is divided into 9 / 16 / 25 equal parts respectively to form a multi-scale defect image dataset;

[0010] Step 3: Annotate the multi-scale sub-defect images obtained in step 2. Use different color labels and categories to perform a series of defect annotations on the semiconductor chip sub-defect images, and output a txt file corresponding to the annotated sub-defect images, saving the annotation box position information;

[0011] Step 4: After obtaining the dataset labeled in step 3, divide the dataset into a training set and a test set according to a certain ratio.

[0012] Step 5: Use the multi-degree group convolution SMGC-YOLOv5 algorithm to perform end-to-end model training on the multi-scale sub-defect image training set obtained in step 3. During the training process, a parameter adjustment method is used to obtain the optimal model;

[0013] Step 6: Divide the semiconductor chip appearance test image into 9 / 16 / 25 equal parts, respectively. Utilizing multi-threaded processing technology and the optimal model trained in Step 5, all generated multi-scale sub-defect maps are inferred simultaneously to improve inference speed. After the sub-defect map inference is completed, the inference results of the sub-defect map are mapped onto the large-field semiconductor chip image, and the corresponding large-field semiconductor chip appearance image defect inference image is output, thereby completing the semiconductor chip appearance image defect detection.

[0014] Step 7: A large number of large-field-of-view semiconductor chip appearance images with certain defects are processed through the above steps to obtain the trained model and the large image of inference results, realizing end-to-end defect detection with large image input and large image output.

[0015] In a further improvement of the present invention, step three includes the following process:

[0016] Process 1: Defect Annotation: Semantically annotate the acquired multi-scale sub-defect images using self-developed image annotation software. Different defects correspond to different color categories and label categories.

[0017] Process 2: Several detection frames can be marked on a sub-defect image and output to a txt file in a fixed label format. The label information on each sub-defect image will be output to a txt file. The format of each line of the txt file is as follows: label number (class), ratio of the x-coordinate of the center of the marked frame to the x-axis (width) length of the entire image, ratio of the y-coordinate of the center of the marked frame to the y-axis (height) length of the entire image, ratio of the width of the marked frame to the x-axis (width) length of the entire image, ratio of the height of the marked frame to the y-axis (height) length of the entire image.

[0018] A further improvement of the present invention is that the step 5 multi-degree group convolution SMGC-YOLOv5 algorithm is a target detection algorithm, which can be roughly divided into three modules: input end, Backbone backbone network and Head network,

[0019] (1) Input: The network input is a sub-defect image of a semiconductor chip defect image with a large field of view and cut at multiple scales. The sub-defect images at the same scale are of the same size. This module includes image preprocessing and data augmentation modules. Image preprocessing involves scaling the input image to the network input size and performing normalization and other operations. At the same time, data augmentation is used to improve the generalization ability of the model. Based on the existing dataset, the amount of data involved in model training is increased, thereby improving the performance of the model. It includes the following operations: left-right flipping, slice splicing, machine adjustment of color, and random scaling.

[0020] (2) Backbone network: This backbone network is used to extract deep features of defects in semiconductor chip images.

[0021] (3) Head network: The Head is used to output the target detection results. For this multi-level group convolution SMGC-YOLOv5 detection algorithm, the output end has three branches, corresponding to the three different scale defect detection box types of the image to be detected. The YoloHead output size is 80*80*256 for detecting small targets, 40*40*512 for detecting medium targets, and 20*20*1024 for detecting large targets.

[0022] The SMGC_YOLOv5 algorithm uses stacked multi-scale convolutions, adjusting the size of the convolution kernel to achieve multi-scale feature extraction. Without increasing the number of parameters or computational complexity, convolution kernels of different scales can extract multi-scale information, thereby improving the network's limited receptive field and loss of detail during downsampling. Each group of multi-scale convolutions takes the entire input as input and outputs features of a different scale. To minimize computational complexity, group convolutions are performed within each group. The group convolution kernels of each layer have different spatial sizes, and their depth decreases as the number of group convolution kernels increases.

[0023] The number of channels in each group of the multi-scale convolution is different. Assume that the input of the multi-scale convolution contains C i The number of channels, the convolution kernel size of each layer of multi-scale convolution is: K1 2 ,K2 2 ,....K n 2 , the depth is:

[0024]

[0025] The corresponding output feature dimension is C o1 , C o2 ,...,C onA ;

[0026] The number of parameters and computational complexity of multi-scale convolution are as follows:

[0027]

[0028] FLOPs = Para w h

[0029] In the above formula, C o1 +C o2 +...+C on =C o , w and h represent the width and height of the sub-defect map. If a network layer outputs the same number of channels, the number of parameters and computational complexity of that network layer are relatively evenly distributed. Based on the above description, the computational complexity of multi-scale convolution is similar to that of standard convolution.

[0030] In a further improvement of the present invention, step six includes the following process:

[0031] The semiconductor chip inference image is divided into three scales (9, 16, and 25 equal parts). During model inference, multi-threaded processing technology is used to parallelize inference on sub-defect images of different sizes, which can effectively improve model inference efficiency. After inference, the multi-scale sub-defect images of the same original image are mapped one by one. That is, the defect detection box in the sub-image is mapped to the corresponding position in the corresponding semiconductor chip appearance image. In the sub-image of the original image to be inspected, the center position of the defect detection box will be mapped to the original image to be inspected, and the position and size of the defect detection box relative to the sub-image will also be mapped to the original image to be inspected. The specific mapping formula is as follows:

[0032]

[0033] p∈[0,n-1],q∈[0,n-1]

[0034] In the above formula, for an image divided into n equal parts, [p, q] represents the sub-image number, and w and h represent the width and height of the original image. (x i ,y i ) represents the center position of the detection frame relative to the sub-image, (x1, y1) represents the upper left vertex position of the detection frame relative to the sub-image, (X, Y) is mapped to the center position of the detection frame in the original image, (X1, Y1) is mapped to the upper left vertex position of the detection frame in the original image, and (X2, Y2) is mapped to the lower right vertex position of the detection frame in the original image; thereby completing the positioning of the defect detection frame, mapping the detection frames in the multi-scale sub-defect image one by one to the large-field semiconductor chip appearance image, outputting the large image of the detection result, and completing end-to-end defect detection; finally, outputting an original-size large-field semiconductor chip appearance defect detection image, realizing end-to-end defect detection with large image input and large image output.

[0035] Beneficial effects of the present invention: The present invention uses large-field semiconductor chip defects as network input and adopts the stacked multi-scale convolution SMGC-YOLOv5 algorithm to detect semiconductor chip appearance defects. While reducing the amount of model parameters, it greatly shortens the model training and reasoning time, and effectively improves the model performance, effectively improves the discriminability of defect feature representation and the accuracy of large-field semiconductor chip appearance defect detection; in the training and reasoning process, feature extraction is performed on sub-defect images at different scales, multi-threaded reasoning is performed on sub-defect images under multi-dimensionality, and finally the reasoning results of the sub-defect images are mapped to the large image, realizing end-to-end lightweight defect detection with large image input and large image output; compared with other related algorithms, the algorithm proposed in the present invention effectively reduces the amount of model parameters and improves model reasoning efficiency while taking into account network performance. Therefore, the proposed algorithm effectively improves the detection effect and efficiency of semiconductor chip appearance defects under computer vision.

[0036] Specifically:

[0037] (1) The present invention embeds stacked multi-scale convolution into the YOLOv5 semiconductor chip appearance defect detection algorithm, which improves the model detection performance while effectively reducing the number of model parameters.

[0038] (2) The present invention uses sub-defect images of different scales as input for model training, which improves the accuracy of the model in detecting defects of different scales.

[0039] (3) The present invention adopts multi-threaded reasoning of multi-scale sub-defect maps, and simultaneously maps the reasoning results of sub-defect maps at different positions into the large semiconductor chip map, so as to realize end-to-end lightweight defect detection with large map input and large map output. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is the overall flow chart of the present invention.

[0041] Figure 2 This is an example diagram of labeled categories in an embodiment of the present invention.

[0042] Figure 3 It is a principle diagram of the annotation format in an embodiment of the present invention.

[0043] Figure 4 It is a flow chart of the SMGC_YOLOv5 algorithm in an embodiment of the present invention.

[0044] Figure 5 This is a network structure diagram of the SMGC_YOLOv5 algorithm in an embodiment of the present invention.

[0045] Figure 6 Schematic diagram of the group convolution principle in an embodiment of the present invention.

[0046] Figure 7 Schematic diagram of the mapping principle in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to deepen the understanding of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. The embodiments are only used to explain the present invention and do not limit the scope of protection of the present invention.

[0048] like Figure 1 As shown, a method for detecting appearance defects of semiconductor chips with a large field of view includes the following steps:

[0049] Step 1: Input a large number of large-field-of-view semiconductor chip appearance images with certain defects;

[0050] Step 2: The semiconductor chip appearance image obtained in step 1 is divided into 9 / 16 / 25 equal parts respectively to form a multi-scale defect image dataset;

[0051] Step 3: Annotate the multi-scale sub-defect images obtained in step 2. Use different color labels and categories to perform a series of defect annotations on the semiconductor chip sub-defect images, and output a txt file corresponding to the annotated sub-defect images, saving the annotation box position information;

[0052] Step 4: After obtaining the dataset labeled in step 3, divide the dataset into training set and test set according to a certain ratio;

[0053] Step 5: Use the SMGC-YOLOv5 algorithm to perform end-to-end model training on the multi-scale sub-defect image training set obtained in step 3. During the training process, a parameter adjustment method is used to obtain the optimal model;

[0054] Step 6: The semiconductor chip appearance test image is divided into 9, 16, and 25 equal parts, respectively. Using multi-threaded processing technology and the optimal model trained in Step 5, all generated multi-scale sub-defect maps are inferred simultaneously to improve inference speed. After the sub-defect map inference is completed, the inference results of the sub-defect maps are mapped onto the large-field-of-view semiconductor chip image, and the corresponding large-field-of-view semiconductor chip appearance image defect inference image is output, thus completing the semiconductor chip appearance image defect detection.

[0055] Step 7: A large number of large-field-of-view semiconductor chip appearance images with certain defects are processed through the above steps to obtain the trained model and the large image of inference results, realizing end-to-end defect detection with large image input and large image output.

[0056] In this embodiment, step three includes the following process:

[0057] (1) Defect annotation: semantic annotation of the acquired multi-scale sub-defect images. Use the self-developed image annotation software to annotate the multi-scale defect images. Different defects correspond to different color categories and label categories. The annotation examples are as follows: Figure 2 shown.

[0058] (2) Several detection frames can be marked on a sub-defect map and output to a txt file in a fixed label format. The label format is as follows: Figure 3 :

[0059] The label information on each sub-defect image will be output to a txt file. The format of each line in the txt file is:

[0060] The ratio of the x-coordinate of the center of the label number (class) mark box to the length of the x-axis (width) of the entire image;

[0061] The ratio of the y-coordinate of the center of the marked box to the y-axis (height) length of the entire image;

[0062] The ratio of the width of the marker box to the length of the x-axis (width) of the entire image;

[0063] The ratio of the marker box height to the y-axis (height) length of the entire image.

[0064] From the above figure, we can get the labels of the red defect mark box (red category is 0): 0, 0.38, 0.69, 0.37, 0.32.

[0065] In this embodiment, step five includes the following steps:

[0066] The SMGC-YOLOv5 algorithm is a target detection algorithm that can be roughly divided into three modules: input end, Backbone network and Head network. Figure 4 This is the algorithm flow chart, and the specific network structure is shown in the figure Figure 5 .

[0067] (1) Input: The network input is a sub-defect image of a semiconductor chip defect image with a large field of view and cut at multiple scales. The sub-defect images at the same scale are of the same size. This module includes image preprocessing and data augmentation modules. Image preprocessing involves scaling the input image to the network input size and performing normalization and other operations. At the same time, data augmentation is used to improve the generalization ability of the model. Based on the existing dataset, the amount of data involved in model training is increased, thereby improving the performance of the model. It includes the following operations: left-right flipping, slice splicing, machine adjustment of color, and random scaling.

[0068] (2) Backbone network: This backbone network is used to extract the deep features of defects in semiconductor chip images. The specific algorithm network structure is shown in Figure 5 .

[0069] (3) Head network: The Head is used to output the target detection results. For this SMGC-YOLOv5 detection algorithm, the output end has three branches, corresponding to the three different scale defect detection box types of the image to be detected. The YoloHead output size of 80*80*256 is used for detecting small targets, 40*40*512 is used for detecting medium targets, and 20*20*1024 is used for detecting large targets.

[0070] The SMGC_YOLOv5 algorithm uses stacked multi-scale convolutions, adjusting the size of the convolution kernel to achieve multi-scale feature extraction. Without increasing the number of parameters or computational complexity, convolution kernels of different scales can extract multi-scale information, thereby improving the network's limited receptive field and loss of detail during downsampling. Each group of multi-scale convolutions takes the entire input as input and outputs features of a different scale. To minimize computational complexity, group convolutions are performed within each group. The group convolution kernels of each layer have different spatial sizes, and their depth decreases as the number of group convolution kernels increases. Figure 6 Schematic diagram of the principle of multi-scale convolution.

[0071] The number of channels in each group of the multi-scale convolution is different. Assume that the input of the multi-scale convolution contains C i The number of channels, the convolution kernel size of each layer of multi-scale convolution is K1 2 , K2 2 ,…K n 2 , the depth is

[0072]

[0073] The corresponding output feature dimension is C o1 , C o2 ,...,C onA The number of parameters and computational complexity of multi-scale convolution are as follows:

[0074]

[0075] FLOPs = Para w h

[0076] In the above formula, C o1 +C o2 +...+C on =C o , w and h represent the width and height of the sub-defect map. If a network layer outputs the same number of channels, the number of parameters and computational complexity of that network layer are relatively evenly distributed. Based on the above description, the computational complexity of multi-scale convolution is similar to that of standard convolution.

[0077] In this embodiment, step six includes the following steps:

[0078] The semiconductor chip inference image is divided into three scales (9 / 16 / 25 equal parts). During model inference, multi-threaded processing technology is used to parallelize inference on sub-defect images of different sizes, which can effectively improve the model inference efficiency. After the inference is completed, the multi-scale sub-defect images of the same original image are mapped one by one, that is, the defect detection box in the sub-image is mapped to the corresponding position in the corresponding semiconductor chip appearance image. The specific mapping principle diagram is shown in the figure below. Figure 7.

[0079] according to Figure 7 As shown in the figure, in the sub-image of the original image to be inspected, the center position of the defect detection frame will be mapped to the original image to be inspected, and the position and size of the defect detection frame relative to the sub-image will also be mapped to the original image to be inspected. The specific mapping formula is as follows:

[0080]

[0081] p∈[0,n-1],q∈[0,n-1]

[0082] In the above formula, for an image divided into n equal parts, [p, q] represents the sub-image number, and w and h represent the width and height of the original image. (x i ,y i ) represents the center position of the detection frame relative to the sub-image, (x1, y1) represents the top-left vertex position of the detection frame relative to the sub-image, (X, Y) is the position of the detection frame mapped to the center position in the original image, (X1, Y1) is the position of the detection frame mapped to the top-left vertex position in the original image, and (X2, Y2) is the position of the detection frame mapped to the bottom-right vertex position in the original image. This completes the positioning of the defect detection frame, maps the detection frames in the multi-scale sub-defect image one by one to the large-field semiconductor chip appearance image, and outputs the large image of the detection results, completing end-to-end defect detection. Finally, a large-field semiconductor chip appearance defect detection image of the original size is output, achieving end-to-end defect detection with large image input and output.

[0083] The above description is an exemplary embodiment of the present invention and does not limit the scope of patent protection of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present invention.

Claims

1. A method for detecting appearance defects of semiconductor chips with a large field of view, comprising the following steps: Step 1: Input a large number of large-field-of-view semiconductor chip appearance images with certain defects; Step 2: The semiconductor chip appearance image obtained in step 1 is divided into 9 / 16 / 25 equal parts respectively to form a multi-scale defect image dataset; Step 3: Annotate the multi-scale sub-defect images obtained in step 2. Use different color labels and categories to perform a series of defect annotations on the semiconductor chip sub-defect images, and output a txt file corresponding to the annotated sub-defect images, saving the annotation box position information; Step 4: After obtaining the dataset labeled in step 3, divide the dataset into training set and test set according to a certain ratio; Step 5: Use the multi-scale convolution SMGC-YOLOv5 algorithm to perform end-to-end model training on the multi-scale sub-defect image training set obtained in step 3. During the training process, a parameter adjustment method is used to obtain the optimal model; Step 6: Divide the semiconductor chip appearance test image into 9 / 16 / 25 equal parts, respectively. Utilize multi-threaded processing technology and the optimal model trained in step 5 to simultaneously infer all generated multi-scale sub-defect maps to improve inference speed. After the sub-defect map inference is completed, the inference results of the sub-defect maps are mapped onto the large-field semiconductor chip image, and the corresponding large-field semiconductor chip appearance image defect inference image is output, thereby completing the semiconductor chip appearance image defect detection. Step 7: A large number of large-field-of-view semiconductor chip appearance images with certain defects are processed through the above steps to obtain a trained model and a large image of inference results, thereby achieving end-to-end defect detection with large image input and output; The multi-scale convolution SMGC-YOLOv5 algorithm in step 5 is divided into three modules: input end, Backbone network and Head network; (1) Input: This includes image preprocessing and data augmentation modules. Image preprocessing involves scaling the input image to the network input size and performing normalization. Data augmentation is used to improve the generalization capability of the model. Based on the existing dataset, the amount of data involved in model training is increased, thereby improving the performance of the model. This includes the following operations: left-right flipping, piece splicing, machine color adjustment, and random scaling. (2) Backbone network: This backbone network is used to extract deep features of defects in semiconductor chip images; (3) Head network: Head is used to output the target detection results. For this multi-scale convolutional SMGC-YOLOv5 detection algorithm, the output end has three branches, corresponding to the three different scale defect detection box types of the image to be detected. The YoloHead with an output size of 80*80*256 is used to detect small targets, 40*40*512 is used to detect medium targets, and 20*20*1024 is used to detect large targets. In the step 5, the number of channels of each group in the multi-scale convolution is different, and the input of the multi-scale convolution is set to include C i The number of channels, the convolution kernel size of each layer of multi-scale convolution is: K1 2 ,K2 2 ,....K n 2 , the depth is: The corresponding output feature dimension is C o1 , C o2 ,...,C onA ; The number of parameters and computational complexity of multi-scale convolution are as follows: FLOPs = Pard w h Above, middle C o1 +C o2 +...+C on =C o , w and h represent the width and height of the sub-defect map. If the number of channels output by a certain network layer is the same, the parameter quantity and computational complexity of the network layer are more evenly distributed; The specific mapping formula of step 6 is as follows: p∈[0,n-1],q∈[0,n-1] In the above formula, for an image divided into n equal parts, [p, q] represents the sub-image number, w and h represent the width and height of the original image, (x i ,y i ) represents the center position of the detection frame relative to the sub-image, (x1, y1) represents the upper left vertex position of the detection frame relative to the sub-image, (X, Y) is mapped to the center position of the detection frame in the original image, (X1, Y1) is mapped to the upper left vertex position of the detection frame in the original image, and (X2, Y2) is mapped to the lower right vertex position of the detection frame in the original image; thereby completing the positioning of the defect detection frame, mapping the detection frames in the multi-scale sub-defect image one by one to the large-field semiconductor chip appearance image, outputting the large image of the detection result, and completing end-to-end defect detection; finally, outputting an original-size large-field semiconductor chip appearance defect detection image, realizing end-to-end defect detection with large image input and large image output.

2. The method for detecting semiconductor chip appearance defects with a wide field of view according to claim 1, wherein step 3 comprises the following process: Process 1: Defect Annotation: Semantically annotate the acquired multi-scale sub-defect images using self-developed image annotation software. Different defects correspond to different color categories and label categories. Process 2: Mark several detection frames on a sub-defect image and output them to a txt file in a fixed label format. The label information on each sub-defect image will be output to a txt file. The format of each line of the txt file is: label number, ratio of the x-coordinate of the center of the marking frame to the x-axis length of the entire image, ratio of the y-coordinate of the center of the marking frame to the y-axis length of the entire image, ratio of the width of the marking frame to the x-axis length of the entire image, and ratio of the height of the marking frame to the y-axis length of the entire image.

3. According to the large-field semiconductor chip appearance defect detection method according to claim 2, step six includes the following process: the semiconductor chip inference image is divided into three scales: 9 / 16 / 25 equal parts, and multi-threaded processing technology is used to perform parallel inference on sub-defect images of different sizes. After the inference is completed, the multi-scale sub-defect images of the same original image are mapped one by one, that is, the defect detection box in the sub-image is mapped to the corresponding position in the corresponding semiconductor chip appearance large image. In the sub-image of the original image to be detected, the center position of the defect detection box will be mapped to the original image to be detected, and the position and size of the defect detection box relative to the sub-image will also be mapped to the original image to be detected.

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