A non-volatile 3T1R1C storage circuit, correction circuit, DRAM and storage-computing circuit

Abstract

The present invention belongs to the field of integrated circuit technology, and specifically relates to a non-volatile 3T1R1C storage circuit, a correction circuit, a DRAM, and a storage-calculation circuit. The non-volatile 3T1R1C storage circuit includes three N-type transistors M0, M1, and M2, a RRAM (RRAM) called R0, and a capacitor C0. The circuit connections are as follows: the gates of M0, M1, and M2 serve as control terminals for connecting to independent word lines WL_A, WL_B, and WL_C, respectively; the sources of M0 and M1 are connected and connected to a bit line BL; the drain of M1 is connected to the source of M2 and to one end of C0, the other end of C0 being grounded; the drains of M0 and M2 are connected to the TE terminal of R0, and the BE terminal of R0 is connected to the word line SL. The correction circuit is used to resolve the data inversion problem during data recovery in the 3T1R1C storage circuit. The DRAM and storage-calculation circuit are designed using the 3T1R1C storage circuit as the basic storage unit. The present invention solves the problem that DRAM loses data when it is powered off, and the accuracy of multiplication and accumulation operations is easily affected by factors such as bit line voltage changes, drive fluctuations, and device mismatch.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and specifically relates to a non-volatile 3T1R1C storage circuit, a recovery data correction circuit, a DRAM circuit with data backup and recovery functions, and a storage and calculation circuit based on 3T1R1C for implementing multiplication and accumulation operations. Background Art

[0002] In recent years, artificial intelligence (AI) has been applied in many fields and has made significant progress. Convolutional neural networks (CNNs), as an effective machine learning method for implementing AI, have garnered increasing attention. However, the application of CNNs also presents new challenges for circuit and system design. The massive data throughput not only significantly increases processing time and power consumption, but also places higher demands on processor and memory performance.

[0003] Furthermore, to further improve the performance of computing chips used for machine learning tasks, researchers are attempting to innovate traditional computer architecture. Traditional chips utilize the von Neumann architecture, which separates memory from the processor and uses a bus for communication. However, in recent decades, memory performance has lagged far behind processor performance, and communication between the processor and memory is limited by the number of communication interfaces. This makes it difficult to increase data throughput, and the round-trip data transfer consumes significant time and energy, even more than the computation itself. Based on this, researchers have proposed near-memory computing and in-memory computing. Near-memory computing, as the name suggests, involves placing as many processors as possible around the memory, increasing the number of communication interfaces between the processor and memory, and minimizing the communication distance. This improves processing speed to a certain extent, but it still essentially uses the von Neumann architecture, separating data processing and storage. In-memory computing, on the other hand, integrates data processing and storage within memory. It utilizes a fully parallel approach to perform in-memory computations, significantly reducing power consumption and latency.

[0004] For computing in memory (CIM), the most advanced solutions currently fall into the following categories: CIM solutions using volatile or nonvolatile memory; and CIM solutions using current or voltage domains. Standard static random-access memory (SRAM) cells are favored by most CIM designers due to their high speed and ease of integration with arithmetic units. However, their volatility limits their application areas, and leakage power consumption is difficult to eliminate. Current non-volatile memory solutions primarily include resistive random-access memory (RRAM), ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), and phase change random access memory (PCRAM). RRAM offers small footprint, low power consumption, and good compatibility with CMOS processes. When calculating current or voltage domains in memory solutions, the results are typically expressed as bitline current or voltage. However, these calculations suffer from poor precision. Due to factors such as bitline voltage variations, driver fluctuations, and device mismatches, the calculated results often deviate from the ideal value. This limits the CIM architecture to low-precision applications. Summary of the Invention

[0005] To address the problems of existing DRAM chips easily losing data due to power outages when performing in-memory computing tasks, and insufficient calculation accuracy due to factors such as bit line voltage changes, drive fluctuations, and device mismatches when performing multiplication and accumulation operations; the present invention provides a non-volatile 3T1R1C storage circuit, a recovery data correction circuit, a DRAM circuit with data backup and recovery functions, and a storage and calculation circuit based on 3T1R1C for implementing multiplication and accumulation operations, and its corresponding integrated circuit.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] A non-volatile 3T1R1C storage circuit, used as a basic storage unit in large-scale DRAM storage circuits, can back up data before power failure and restore data after power is restored.

[0008] The nonvolatile 3T1R1C storage circuit provided in the present invention includes three N-type transistors M0, M1, and M2, an RRAM called R0, and a capacitor C0. The circuit connection relationship is as follows: the gates of M0, M1, and M2 serve as control terminals for connecting to independent word lines WL_A, WL_B, and WL_C, respectively; the sources of M0 and M1 are connected and connected to the bit line BL; the drain of M1 is connected to the source of M2 and connected to one end of C0, and the other end of C0 is grounded; the drains of M0 and M2 are connected to the TE terminal of R0, and the BE terminal of R0 is connected to the word line SL.

[0009] In this nonvolatile 3T1R1C storage circuit, the charge / discharge state of C0 represents the stored data "1" or "0." Before the circuit is powered off, the C0 data is backed up to R0. During data backup, the low-resistance and high-resistance states of R0 are used to map the stored data "1" or "0," respectively. After the circuit is powered back on, the data backed up in R0 is restored to C0.

[0010] It is particularly important to note that after each power-on data recovery operation in the non-volatile 3T1R1C storage circuit provided by the present invention, the data stored in C0 is the opposite of the original data stored before power failure. To address this circuit characteristic, the present invention can improve it in two ways to avoid data recovery "errors." Specific measures include:

[0011] Solution 1: After each actual power outage and recovery, perform another "active power off" and power on again. This way, the chip will recover twice after each power outage, meaning the stored data is flipped twice, ensuring that the data stored in C0 after power recovery is consistent with the original data stored before the power outage.

[0012] Option 2: Configure a correction circuit for the storage circuit. The correction circuit is implemented through devices such as inverters and selectors, so that when any storage cell is read, the correction circuit can correct the reading result as follows based on the historical number of power failures and recovery times since the last data was written to the storage cell: if the historical number of power failures and recovery times since the last data was written to the storage cell is an odd number, the correction circuit outputs the inverted value of the stored value; if the historical number of power failures and recovery times since the last data was written to the storage cell is an even number, the correction circuit outputs the original value of the stored value.

[0013] The nonvolatile 3T1R1C storage circuit provided by the present invention has the properties of both DRAM and RRAM storage circuits: (1) when using DRAM mode, M0 and M2 are always closed, and R0 is not used; while M1 is activated during reading, writing, and holding; (2) when using RRAM, M1 and M2 are always closed, and C0 is not used; while M0 is activated during reading and writing.

[0014] As a further improvement of the present invention, in the non-volatile 3T1R1C storage circuit, the execution process of the data backup operation is as follows:

[0015] First, the data backup process is performed before power is turned off, during which WL_B remains in a low-level state of 0V. Second, the data backup process is divided into two stages. In the first stage, BL is set to above 1.4V, SL to 0V, and WL_A to 1.8V. At this point, M0 is in the on-state, the voltage drop across the RRAM meets the set operation requirements, and R0 is set to a low-resistance state (LRS). In the second stage, WL_A is set to 0V, SL to 1V, and WL_C to 1.8V. At this point, M0 is off and M2 is on. In the current circuit, if C0 stores the data "1" (a high level), R0's resistance state remains unchanged and remains in the low-resistance state (LRS). If C0 stores the data "0" (a low level), the voltage across R0 meets the reset operation requirements, and R0 is reset to a high-level state (HRS). Finally, through these two stages, the storage state of C0 is transferred to R0.

[0016] As a further improvement of the present invention, in the non-volatile 3T1R1C storage circuit, the execution process of the data recovery operation is as follows:

[0017] First, WL_A remains in a low-level state of 0V throughout the entire data recovery operation. Secondly, the recovery process consists of the following two phases: In the first phase, BL is set to 1V, WL_B is set to 1.8V, M1 is turned on, and C0 is charged to a high level. In the second phase, WL_B is set to 0V, SL is set to 0V, and WL_C is set to 1.8V; M1 is turned off and M2 is turned on. At this time, if R0 is in the high-resistance state (HRS), it is difficult for C0 to discharge through R0, and the high-level state remains, maintaining the data "1". If R0 is in the low-resistance state (LRS), C0 discharges to a low-level state through R0, maintaining the data "0". Finally, through the above two phases, the storage state of R0 is transferred to C0.

[0018] The present invention also includes a recovery data correction circuit, which is applied to the aforementioned non-volatile 3T1R1C storage circuit and is used to correct data "inversion errors" caused by the circuit during each backup and recovery process. The recovery data correction circuit utilizes a 2-to-1 data selector and SA; the 2-to-1 data selector includes two input terminals IN1 and IN2, a selection terminal IN3, and an output terminal OUT. The selection terminal IN3 is used to receive a flag signal SEL that represents the parity attribute of the number of power-off recovery times corresponding to the data currently stored in the non-volatile 3T1R1C storage circuit. The quantized output terminal of the stored data in the non-volatile 3T1R1C storage circuit is connected to SA, and the reference level of SA is set to half of the high level. The output level of SA and the inverse of the output level are selected through SEL, and OUT is the final correction result output.

[0019] In the recovered data correction circuit, assuming that the original storage data of the non-volatile 3T1R1C storage circuit is D, the generation logic of the output terminal OUT is as follows:

[0020]

[0021] The present invention also includes a DRAM circuit with data backup and recovery functions, which includes: a storage array, a bit line group, a word line group, a word line driver, a row decoder, a column decoder, a buffer, a quantization circuit array, and a correction circuit array.

[0022] Among them, the storage array consists of N 2 The same memory cells are arranged in an N×N array, and each memory cell adopts the aforementioned non-volatile 3T1R1C memory circuit.

[0023] The bit line group includes N bit lines BL corresponding to columns of the memory array, and the outputs of all memory cells in the same column of the memory array are connected to the same bit line.

[0024] The wordline group consists of N wordline pairs corresponding to each row of the memory array. Each wordline pair includes four control wordlines: WL_A, WL_B, WL_C, and SL. In the memory array, the gates of M0, M1, and M2 in all memory cells in the same row are connected to WL_A, WL_B, and WL_C in the corresponding row, respectively. The BE terminal of R0 in all memory cells in the same row is connected to wordline SL.

[0025] The word line driver is used to control the opening or closing of the word line WL connected to each memory cell in the memory array when performing data read and write operations. The row decoder is used to control the word line driver module according to the decoding result when performing data read and write operations.

[0026] The column decoder is used to control the opening or closing of the connection between each memory cell column in the memory array when performing data read and write operations; the buffer is used to improve the delay and level loss caused by long wires to ensure correct output.

[0027] The quantization circuit array includes N quantization circuits; each quantization circuit is used to output an analog-to-digital conversion value corresponding to a bit line voltage on one of the bit lines.

[0028] The correction circuit array comprises N restored data correction circuits as described above. Each restored data correction circuit first selects the output of the quantization circuit and its inverse as two targets to be selected during data correction. Then, based on an input flag signal SEL, it selects one of the two targets as the correction result and outputs the correction result as the actual data stored in the corresponding storage unit.

[0029] In a further improvement of the present invention, the DRAM circuit is connected to a peripheral functional circuit, which is used to generate a flag signal SEL required by the correction circuit array. The process of the peripheral functional circuit generating the flag signal is as follows:

[0030] (1) Obtain word line and bit line signals during data reading to determine the selected data storage unit.

[0031] (2) Obtain the historical power-off recovery times m corresponding to the last data write of the current storage data in the current data storage unit.

[0032] (3) Determine the odd or even attribute of the historical power failure recovery times m and generate a corresponding flag signal SEL: when m is an odd number, SEL=1, indicating that the output value of the current quantization circuit needs to be corrected; when m is an even number, SEL=0, indicating that the output value of the current quantization circuit does not need to be corrected.

[0033] The present invention also includes a storage circuit for performing multiplication and accumulation operations based on a 3T1R1C circuit. When used as a storage circuit, this circuit can back up data before power failure and restore data after power is restored. When used as an arithmetic circuit, the storage circuit exhibits robustness against RRAM resistance fluctuations and high linearity, thereby improving the accuracy of multiplication and accumulation results. The storage circuit includes a storage array, a bitline group, a wordline group, a wordline driver, a row decoder, a column decoder, a buffer, a quantization circuit array, a digital shifter, and an accumulator.

[0034] Among them, the storage array consists of N 2 The same memory cells are arranged in an N×N array, and each memory cell adopts the aforementioned non-volatile 3T1R1C storage circuit.

[0035] The bit line group includes N bit lines BL corresponding to columns of the memory array. Outputs of all memory cells in the same column of the memory array are connected to the same bit line.

[0036] The wordline group consists of N wordline pairs corresponding to each row of the memory array. Each wordline pair includes four control wordlines: WL_A, WL_B, WL_C, and SL. In the memory array, the gates of M0, M1, and M2 in all memory cells in the same row are connected to WL_A, WL_B, and WL_C in the corresponding row, respectively. The BE terminals of R0 in all memory cells in the same row are connected to wordline SL.

[0037] The word line driver is used to control the opening or closing of the word line WL connected to each memory cell in the memory array when performing data read and write operations. The row decoder is used to control the word line driver module according to the decoding result when performing data read and write operations.

[0038] The column decoder is used to control the connection between each column of memory cells in the memory array during data read and write operations. The buffer is used to reduce the delay and level loss caused by long wires to ensure correct output.

[0039] The quantization circuit array includes N quantization circuits; each quantization circuit is used to output an analog-to-digital conversion value corresponding to a bit line voltage on one of the bit lines.

[0040] The digital shifter is used to assign different quantization weights to different columns, and the accumulator is used to accumulate the columns assigned with different quantization weights.

[0041] As a further improvement to the present invention, each memory cell in the same column of the memory array of the storage-calculation circuit serves as a basic multiplication execution unit. The cumulative sum of the multiplication results calculated by all memory cells is output to the bitline for quantization and output. In each memory cell, the wordline signal WL_C connected to M2 serves as the first operand of the multiplication operation; the weight W corresponding to the resistance state of R0 serves as the second operand; and the value output by C0 on the bitline BL serves as the product. That is, BL = WL_C × W.

[0042] All memory cells in the same column of the memory array act as execution units for performing single-bit MAC operations. The process of a single-bit MAC operation is as follows:

[0043] S1: Define the weight W corresponding to the resistance state of R0 as follows: HRS represents "0" and LRS represents "1".

[0044] S2: Set BL to 1V and WL_B to 1.8V. At this point, M1 is turned on and all capacitors are charged to "1." One bit of input is applied to WL_C in the form of word line voltage.

[0045] (1) If the input is "1," WL_C is set to 1.8V, and M2 is turned on. At this point, if the RRAM's resistance state is HRS and the weight is "0," the capacitor is unlikely to discharge and remains at Vcap. The output result is "0," meaning 1 × 0 = 0.

[0046] In this state, since the discharge time is short, even if the HRS resistance of the RRAM fluctuates, the voltage fluctuation of Vcap is very small.

[0047] (2) If the input is “1”, the resistance state of the RRAM is LRS, and the weight is “1”, then the capacitor will discharge to the low level 0, and the output operation result is “1”; that is: 1×1=1.

[0048] In this state, even if the LRS resistance of the RRAM fluctuates, the capacitor can still be discharged to zero.

[0049] (3) If the input is “0”, WL_C is set to 0V and M2 is turned off. At this point, regardless of the RRAM resistance state, the capacitor cannot be discharged and the output operation result is “0”, that is, 0×1=0 or 0×0=0.

[0050] S3: Charge is shared across all capacitors in a column through the bit lines, and the bit line potential reflects the simulated accumulation result.

[0051] S4: The analog result is quantized by the Flash ADC circuit and further shifted and accumulated through the digital shifter and adder to obtain the final product-accumulation operation result.

[0052] As a further improvement of the present invention, in the storage-calculation circuit, all storage cells in a plurality of adjacent columns are used as execution units for performing a multi-bit MAC operation. The operation process of the multi-bit MAC operation is as follows:

[0053] First, the multiplication-accumulation operation process in each column is consistent with the process of a single-bit MAC operation.

[0054] Secondly, assuming the N selected operands are arranged in descending order, the partial results obtained from the higher weights account for a larger proportion of the final result. Therefore, the quantization of the partial results obtained from the lower bits of the input does not require high precision. Low-precision quantization can reduce quantization power consumption. After obtaining a single-bit input and N-bit weights, the input is inputted from low to high over N clock cycles. The partial results obtained from the higher bits of the input account for a larger proportion of the final result. Different bit quantization cycles are used; this reduces unnecessary comparisons and power consumption. After quantization, the partial results are shifted and added together to obtain an N-bit output.

[0055] The present invention also includes an integrated circuit, which is formed by encapsulating the aforementioned storage and calculation circuit for implementing multiplication and accumulation operations based on 3T1R1C.

[0056] The technical solution provided by the present invention has the following beneficial effects:

[0057] This invention designs a novel DRAM memory circuit architecture using three N-type transistors, one RRAM, and one capacitor. The three N-type transistors form a π-shaped structure, the capacitor forms the data storage node of the memory cell, and the RRAM acts as a cache node for the data within the memory cell, facilitating data backup before powering off the device and data recovery after powering back on. This enables the invention to provide a 3T1R1C memory circuit that combines the high-speed performance of DRAM with the power-off data retention performance of RRAM, making it a unique non-volatile memory device.

[0058] The present invention incorporates a newly designed 3T1R1C memory circuit into a new large-scale DRAM integrated circuit. This circuit not only reads, writes, and retains data like DRAM, but can even transfer data between DRAM and RRAM before and after power-on, enabling storage and recovery operations. This ensures data non-volatility after power failure. Furthermore, the present invention incorporates the data recovery characteristics of the 3T1R1C memory circuit into two different data correction schemes, improving the circuit's adaptability in various application scenarios.

[0059] The present invention also designs a special memory-arithmetic circuit (CIM) using the designed 3T1R1C storage circuit. The memory-arithmetic circuit can realize a large number of simple logical operations such as addition and multiplication, and can also realize complex logical operations such as MAC (Multiply Accumulate) through charge sharing.

[0060] In particular, the most outstanding contribution of the present invention is that the provided 3T1R1C memory circuit is a new circuit that overcomes the biases of the prior art. The circuit exhibits outstanding resistance to RRAM resistance fluctuations and high linearity, thereby greatly improving the accuracy of calculation results when the circuit performs logical operations and enhancing the circuit's computing performance for data processing tasks such as convolutional neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 This is a circuit diagram of the non-volatile 3T1R1C storage circuit designed in Example 1 of the present invention.

[0062] Figure 2 This is a schematic diagram of the principle of performing data backup operations in a non-volatile 3T1R1C storage circuit. The left part (a) is the basic circuit diagram; the right part (b) is the waveform diagram of each signal during the data backup operation.

[0063] Figure 3 This is a schematic diagram of the principle of performing data recovery operations on a non-volatile 3T1R1C storage circuit. The left part (a) is the basic circuit diagram; the right part (b) is the waveform diagram of each signal during the data backup operation.

[0064] Figure 4 This is a circuit schematic diagram of the restored data correction circuit provided in Example 2 of the present invention.

[0065] Figure 5 This is a logic diagram corresponding to the correction principle of the recovery data correction circuit provided by China in Example 2 of the present invention.

[0066] Figure 6 This is a schematic diagram of the principle structure of a DRAM circuit with data backup and recovery functions provided in Example 3 of the present invention.

[0067] Figure 7 for Figure 6 Circuit diagram of the correction circuit array in the circuit.

[0068] Figure 8 This is a flow chart of generating a flag signal SEL by a peripheral functional circuit in embodiment 3 of the present invention.

[0069] Figure 9 This is a schematic diagram of the principle architecture of a storage circuit for implementing multiplication and accumulation operations based on 3T1R1C provided in Example 4 of the present invention.

[0070] Figure 10 for Figure 9 Circuit diagram of the basic execution unit in the circuit that performs single-bit MAC operations.

[0071] Figure 11 Circuit schematic diagram for performing the multiplication operation of "1×0=0" for the storage unit.

[0072] Figure 12 Circuit schematic for performing a "1×1=1" multiplication operation for a memory cell.

[0073] Figure 13 Circuit schematic diagram for performing a multiplication operation of "0×1=0" for a storage unit.

[0074] Figure 14 Circuit schematic diagram for performing multiplication operation of "0×0=0" for storage unit.

[0075] Figure 15 This is a logic block diagram of the storage-calculation circuit provided in Embodiment 4 of the present invention when performing a weighted 3-bit MAC operation.

[0076] Note: In some of the above circuit diagrams, when there are grayscale differences among the components in the circuit, the dark part of the circuit diagram represents that the device is in the on state at the current stage, and the light gray part represents the device in the off state at the current stage. DETAILED DESCRIPTION

[0077] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0078] Example 1

[0079] This embodiment provides a non-volatile 3T1R1C storage circuit, which serves as a basic storage unit in a large-scale DRAM storage circuit. This storage unit belongs to the DRAM circuit, but has a prominent feature: it can perform data backup before power failure and data recovery after power is restored.

[0080] like Figure 1 As shown, the non-volatile 3T1R1C storage circuit provided in this embodiment includes three N-type transistors M0, M1, and M2, an RRAM called R0, and a capacitor C0; the circuit connection relationship is as follows: the gates of M0, M1, and M2 serve as control terminals for connecting to independent word lines WL_A, WL_B, and WL_C, respectively; the sources of M0 and M1 are connected to each other and to the bit line BL; the drain of M1 is connected to the source of M2 and to one end of C0, and the other end of C0 is grounded; the drains of M0 and M2 are connected to the TE terminal of R0, and the BE terminal of R0 is connected to the word line SL.

[0081] The nonvolatile 3T1R1C storage circuit provided in this embodiment uses three different NMOS transistors to control the signal output paths of the RRAM and capacitor C0, thereby enabling the storage circuit to combine the properties of both DRAM and RRAM. Specifically, when using DRAM mode, M0 and M2 are always off, and R0 is not used; while M1 is activated during reading, writing, and retaining. When using RRAM, M1 and M2 are always off, and C0 is not used; while M0 is activated during reading and writing.

[0082] In the non-volatile 3T1R1C storage circuit provided in this embodiment, the storage data "1" or "0" is represented by the charge / discharge state of C0. Capacitor C0 cannot retain data in the power-off state, so before the circuit is powered off, the switching state of NMOS can be adjusted to back up the C0 data to R0. The low-resistance state and high-resistance state of R0 are used to map the storage data "1" or "0" respectively, so that R0 can achieve data retention in the power-off state, that is, data backup is achieved. Next, when the circuit is powered on again, the NMOS tube can be controlled to conduct, so as to achieve the purpose of restoring the "backed up" data in R0 to C0.

[0083] The ability to perform data backup and data recovery is a key feature and core function of the non-volatile 3T1R1C storage circuit provided in this embodiment. The data backup operation is performed as follows:

[0084] First, the data backup operation is performed before power failure, at which time WL_B is always in a low level state of 0V. Figure 2 As shown in Figure 1, the data backup operation process is divided into two stages: in the first stage, BL is set to above 1.4V, SL is set to 0V, and WL_A is set to 1.8V; at this time, M0 is in the open state; the voltage drop across the RRAM meets the requirements of the set operation; R0 will be set to the low resistance state LRS.

[0085] In the second stage, WL_A is set to 0V, SL is set to 1V, and WL_C is set to 1.8V. At this point, M0 is off and M2 is on. In this circuit, if C0 stores the data "1" corresponding to a high level, the resistance state of R0 will not change and will remain in the low resistance state LRS. If C0 stores the data "0" corresponding to a low level, the voltage on R0 meets the reset operation requirements and R0 will be reset to the high level HRS. Finally, through the above two-stage operation, the storage state of C0 is transferred to R0.

[0086] Accordingly, in the non-volatile 3T1R1C storage circuit, the data recovery operation is performed as follows:

[0087] First, during the entire data recovery operation, WL_A is always in a low level state of 0V. Figure 3 As shown, the recovery operation process includes the following two stages: in the first stage, BL is set to 1V, WL_B is set to 1.8V, M1 is in the on state, and C0 will be charged to a high level.

[0088] In the second stage, WL_B is set to 0V, SL is set to 0V, and WL_C is set to 1.8V; M1 is closed and M2 is opened. At this point, if R0 is in the high-resistance state (HRS), it is difficult for C0 to discharge through R0, and the data remains high, retaining the "1" state. If R0 is in the low-resistance state (LRS), C0 discharges through R0 to a low state, retaining the "0" data. Finally, through these two stages, the stored state of R0 is transferred to C0.

[0089] It is particularly important to note that after each power-on data recovery operation of the non-volatile 3T1R1C storage circuit provided in this embodiment, the data stored in C0 is the opposite of the original data stored before power failure. In view of this circuit characteristic, this embodiment can also adopt two methods to improve this special property to avoid the occurrence of data recovery "errors". Specific measures include:

[0090] Solution 1: After each actual power outage and recovery, perform another "active power off" and power on again. This way, the chip will recover twice after each power outage, meaning the stored data is flipped twice, ensuring that the data stored in C0 after power recovery is consistent with the original data stored before the power outage.

[0091] Solution 2: Configuring a correction circuit for the storage circuit, implemented using components such as inverters and selectors, allows the correction circuit to correct the read result of any memory cell based on the number of power failures and recovery times. If the number of power failures and recovery times is odd, the correction circuit outputs the inverted value of the stored value; if the number of power failures and recovery times is even, the correction circuit outputs the original value.

[0092] Example 2

[0093] This embodiment provides a recovery data correction circuit, which is mainly used in the non-volatile 3T1R1C storage circuit in Example 1, and is used to correct the data "inversion error" caused by the non-volatile 3T1R1C storage circuit during each backup and recovery process. Figure 4 As shown, the recovered data correction circuit utilizes a 2-to-1 data selector and a signal processing unit (SA). The 2-to-1 data selector includes two input terminals, IN1 and IN2, a selector terminal, IN3, and an output terminal, OUT. The selector terminal, IN3, receives a flag signal, SEL, indicating the parity of the power-off recovery times corresponding to the data currently stored in the non-volatile 3T1R1C storage circuit. The quantized output terminal of the stored data in the non-volatile 3T1R1C storage circuit is connected to the signal processing unit (SA). The reference level of the signal processing unit (SA) is set to half a high level. The output level of the signal processing unit (SA) and the inverse of the output level are selected by the signal processing unit (SEL). The final correction result is output as OUT.

[0094] In the recovered data correction circuit, assuming that the original storage data of the non-volatile 3T1R1C storage circuit is D, the generation logic of the output terminal OUT is as follows:

[0095]

[0096] The data recovery correction circuit provided in this embodiment is actually a special circuit designed by using the second solution to solve the data "inversion" problem that occurs during each data recovery process of the non-volatile 3T1R1C storage circuit in embodiment 1. The correction logic of this type of data recovery correction circuit is as follows: Figure 5 As shown, the process includes the following: First, an inverter is used to obtain the original value of the data currently stored in the storage cell, and then the inverter is used to generate the inverted value of the original value of the data. Next, the original value and the inverted value are simultaneously input into the 2-to-1 selector. Finally, a SEL flag signal is used to control the output strategy of the selector:

[0097] (1) When the SEL flag signal reflects that the number of historical power-off recovery times of the data stored in the current storage unit is an odd number, it means that the current value D in the storage unit is now With the original value D original There is an inversion between them. At this time, the selector outputs the current value D of the storage unit. now The inverted value, that is, the original value D original .

[0098] (2) When the SEL flag signal reflects that the number of historical power-off recovery times of the data stored in the current storage unit is an even number, it means that the current value D in the storage unit is now With the original value D original are the same, at this time, the selector outputs the current value of the storage unit D now , that is: original value D original .

[0099] Finally, by using the restored data correction circuit designed by the present invention, the restored data correction circuit in Example 1 can output the correct original value no matter how many times the restored data correction circuit experiences power failure recovery after storing data.

[0100] Specifically, the original embodiment mentioned two methods for preventing errors during the data read process of a non-volatile 3T1R1C memory circuit. This embodiment applies the second method, which does not actually alter the data state of the node corresponding to the memory cell. Instead, it achieves error correction by changing the read logic of the circuit's "data read process." This read logic is called "selective read." That is, if the memory circuit recovers after an odd number of power outages, its inverted value is read; if the memory circuit recovers after an even number of power outages, its original value is read.

[0101] The operating logic of the recovery data correction circuit of the first embodiment and the present embodiment is significantly different. The logic of the first embodiment is that since each memory cell will experience a stored value inversion defect after power failure recovery, an "active power failure data recovery operation" is forcibly performed during each "real power failure data recovery period." This way, after each power failure data recovery in the memory cell causes the current stored data to invert, the active power failure data recovery operation is used to restore the stored data. This ensures that the value read by the data reading circuit is always correct.

[0102] In fact, both Scheme 1 and Scheme 2 can be selected as needed in the non-volatile 3T1R1C storage circuit and its derived functional circuits in Example 1, and can achieve good data de-skew performance. However, their functional implementation requires comprehensive consideration of a series of issues and performance indicators, such as circuit design and operating power consumption, and a reasonable selection should be made based on the relevant performance requirements of specific functional circuits in different scenarios.

[0103] Example 3

[0104] Based on Examples 1 and 2, this embodiment further provides a DRAM circuit with data backup and recovery functions. This DRAM circuit is a large-scale integrated circuit that utilizes the non-volatile 3T1R1C storage circuit of Example 1 as a basic storage unit and employs a restored data correction circuit of Example 2 to selectively correct the stored data read by the output circuit.

[0105] like Figure 6 As shown, the DRAM circuit provided by this embodiment includes: a memory array, a bit line group, a word line group, a word line driver, a row decoder, a column decoder, a buffer, a quantization circuit array, and a correction circuit array.

[0106] Among them, the storage array consists of N 2 The same memory cells are arranged in an N×N array, and each memory cell adopts the non-volatile 3T1R1C memory circuit as in the first embodiment.

[0107] The bit line group includes N bit lines BL corresponding to columns of the memory array, and the outputs of all memory cells in the same column of the memory array are connected to the same bit line.

[0108] The wordline group consists of N wordline pairs corresponding to each row of the memory array. Each wordline pair includes four control wordlines: WL_A, WL_B, WL_C, and SL. In the memory array, the gates of M0, M1, and M2 in all memory cells in the same row are connected to WL_A, WL_B, and WL_C in the corresponding row, respectively. The BE terminal of R0 in all memory cells in the same row is connected to wordline SL.

[0109] The word line driver is used to control the opening or closing of the word line WL connected to each memory cell in the memory array when performing data read and write operations. The row decoder is used to control the word line driver module according to the decoding result when performing data read and write operations.

[0110] The column decoder is used to control the opening or closing of the connection between each memory cell column in the memory array when performing data read and write operations; the buffer is used to improve the delay and level loss caused by long wires to ensure correct output.

[0111] The quantization circuit array includes N quantization circuits; each of the quantization circuits is used to output an analog-to-digital conversion value corresponding to a bit line voltage on one of the bit lines.

[0112] like Figure 7 As shown, the correction circuit array used in this embodiment is composed of N restored data correction circuits of Example 2. When performing data correction, each restored data correction circuit first selects the output of the quantization circuit and its inverted value as two targets to be selected. Then, based on the input flag signal SEL, one value from the two targets is selected as the correction result, and the correction result is output as the real data stored in the corresponding storage unit.

[0113] In the DRAM circuit provided in this embodiment, it is considered that the data stored in different memory cells may be rewritten in different cycles. Therefore, although the number of historical power failure recovery times experienced by each memory cell is consistent, the historical power failure recovery times of the data stored in each memory cell may be inconsistent. Therefore, this embodiment further designs another peripheral circuit of the DRAM circuit. The main function of this peripheral circuit is to determine the historical power failure recovery times corresponding to the data stored in the memory cell currently being read and determine its parity attribute. This facilitates selective correction during the subsequent data reading process.

[0114] Specifically, in the improved solution of this embodiment, the DRAM circuit is connected to a peripheral functional circuit, and the peripheral functional circuit is used to generate the flag signal SEL required by the correction circuit array, such as Figure 8 As shown, the process of the peripheral functional circuit generating the flag signal SEL is as follows:

[0115] (1) Obtain word line and bit line signals during data reading to determine the selected data storage unit.

[0116] (2) Obtain the historical power-off recovery times m corresponding to the writing of the current stored data in the current data storage unit.

[0117] (3) Determine the odd or even attribute of the historical power failure recovery times m and generate a corresponding flag signal SEL: when m is an odd number, SEL=1, indicating that the output value of the current quantization circuit needs to be corrected; when m is an even number, SEL=0, indicating that the output value of the current quantization circuit does not need to be corrected.

[0118] Example 4

[0119] Building on Example 1, this embodiment further provides a storage circuit based on 3T1R1C for implementing multiplication-accumulation operations. When used as a storage circuit, this storage circuit can back up data before power failure and restore data after power is restored. When used as an arithmetic circuit, the storage circuit is well suited for processing multiple complex logical operations, including multiplication-accumulation operations, and is well suited for data operations related to artificial intelligence algorithms such as convolutional neural networks. It also exhibits excellent resistance to RRAM resistance fluctuations and high linearity, thereby improving the accuracy of multiplication-accumulation results.

[0120] like Figure 9 As shown, the storage and calculation circuit provided by this embodiment includes: a storage array, a bit line group, a word line group, a word line driver, a row decoder, a column decoder, a buffer, a quantization circuit array, a digital shifter, and an accumulator.

[0121] Among them, the storage array consists of N 2 The same memory cells are arranged in an N×N array, and each memory cell adopts the non-volatile 3T1R1C memory circuit in Example 1.

[0122] The bit line group includes N bit lines BL corresponding to columns of the memory array. Outputs of all memory cells in the same column of the memory array are connected to the same bit line.

[0123] The wordline group consists of N wordline pairs corresponding to each row of the memory array. Each wordline pair includes four control wordlines: WL_A, WL_B, WL_C, and SL. In the memory array, the gates of M0, M1, and M2 in all memory cells in the same row are connected to WL_A, WL_B, and WL_C in the corresponding row, respectively. The BE terminals of R0 in all memory cells in the same row are connected to wordline SL.

[0124] The word line driver is used to control the opening or closing of the word line WL connected to each memory cell in the memory array when performing data read and write operations. The row decoder is used to control the word line driver module according to the decoding result when performing data read and write operations.

[0125] The column decoder is used to control the connection between each column of memory cells in the memory array during data read and write operations. The buffer is used to reduce the delay and level loss caused by long wires to ensure correct output.

[0126] The quantization circuit array includes N quantization circuits; each quantization circuit is used to output an analog-to-digital conversion value corresponding to a bit line voltage on one of the bit lines.

[0127] The digital shifter is used to assign different quantization weights to different columns, and the accumulator is used to accumulate the columns assigned with different quantization weights.

[0128] In the storage and calculation circuit designed in this embodiment, each storage unit in the same column of the storage array serves as a basic multiplication execution unit, and the cumulative sum of the multiplication results calculated by all storage units will be output to the bit line for quantization and output.

[0129] In each memory cell, the word line signal WL_C connected to M2 serves as the first operand of the multiplication operation; the weight W corresponding to the resistance state of R0 serves as the second operand; and the value output by C0 on the bit line BL serves as the product. That is, BL = WL_C × W. The logical truth table for each memory cell performing the product operation is shown in Table 1 below:

[0130] Table 1: Logical truth table for a storage unit performing a product operation

[0131]

[0132] In this embodiment, if Figure 10 As shown, all memory cells in the same column of the memory array serve as execution units for performing a single-bit MAC operation. The process of a single-bit MAC operation is as follows:

[0133] S1: Define the weight W corresponding to the resistance state of R0 as follows: HRS represents "0" and LRS represents "1".

[0134] S2: Set BL to 1V and WL_B to 1.8V. At this point, M1 is turned on and all capacitors are charged to "1." One bit of input is applied to WL_C in the form of word line voltage.

[0135] (1) Figure 11 As shown in the figure, if the input is "1," WL_C is set to 1.8V, turning M2 on. At this point, if the RRAM's resistance state is HRS and the weight is "0," the capacitor has difficulty discharging and remains at Vcap. The output result is "0," meaning 1 × 0 = 0.

[0136] In this state, since the discharge time is short, even if the HRS resistance of the RRAM fluctuates, the voltage fluctuation of Vcap is very small.

[0137] (2) Figure 12As shown, if the input is "1", the resistance state of the RRAM is LRS, and the weight is "1", then the capacitor will discharge to the low level 0, and the output operation result will be "1"; that is: 1×1=1.

[0138] In this state, even if the LRS resistance of the RRAM fluctuates, the capacitor can still be discharged to zero.

[0139] (3) Figure 13 and Figure 14 As shown in the figure, if the input is "0", WL_C is set to 0V and M2 is turned off. At this time, regardless of the RRAM resistance state, the capacitor cannot be discharged and the output operation result is "0", that is, 0×1=0 or 0×0=0.

[0140] S3: Charge is shared across all capacitors in a column through the bit lines, and the bit line potential reflects the simulated accumulation result.

[0141] S4: The analog result is quantized by the Flash ADC circuit and further shifted and accumulated through the digital shifter and adder to obtain the final product-accumulation operation result.

[0142] In the storage and calculation circuit provided in this embodiment, all the storage cells in multiple adjacent columns are used as execution units for performing multi-bit MAC operations. Taking a 3-bit MAC operation as an example, the operation flow is as follows: Figure 15 The process shown includes the following:

[0143] First, the multiplication-accumulation operation process in each column is consistent with the process of a single-bit MAC operation.

[0144] Secondly, assuming the three selected operands are arranged in descending order, the partial results obtained from the higher weights account for a larger proportion of the final result. Therefore, the quantization of the partial results obtained from the lower bits of the input does not require high precision. Low-precision quantization can reduce quantization power consumption. After obtaining a single-bit input and a 3-bit weight, the input is fed from low to high over three clock cycles. The partial results obtained from the higher bits of the input account for a larger proportion of the final result. Different bit quantization cycles are used; this reduces unnecessary comparisons and power consumption. After quantization, the partial results are shifted and added together, ultimately yielding a 3-bit output.

[0145] The memory circuit provided in this embodiment can be manufactured as a corresponding chip or computing device based on the designed integrated circuit, or integrated into other functional circuits as a corresponding computing module with specific data processing capabilities. Therefore, all final products obtained based on the design concepts of the above embodiments of this invention should be considered as part of the design achievements of this invention.

[0146] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A nonvolatile 3T1R1C storage circuit; characterized in that: As a basic storage unit in a large-scale DRAM storage circuit, the storage unit can perform data backup before power failure and data recovery after power is restored. The non-volatile 3T1R1C storage circuit includes three N-type transistors M0, M1, and M2, a RRAM called R0, and a capacitor C0. The circuit connection relationship is as follows: the gates of M0, M1, and M2 serve as control terminals for connecting to independent word lines WL_A, WL_B, and WL_C, respectively; the sources of M0 and M1 are connected and connected to the bit line BL; the drain of M1 is connected to the source of M2 and connected to one end of C0, the other end of C0 is grounded; the drains of M0 and M2 are connected to the TE terminal of R0, and the BE terminal of R0 is connected to the word line SL; In the non-volatile 3T1R1C storage circuit, the charge / discharge state of C0 represents the stored data "1" or "0". Before the circuit is powered off, the C0 data is backed up to R0. During data backup, the low-resistance state and high-resistance state of R0 are used to map the stored data "1" or "0", respectively. After the circuit is powered on again, the data backed up in R0 is restored to C0. The data stored in C0 after each power-on data recovery operation of the non-volatile 3T1R1C storage circuit is the opposite of the original data stored before the power outage. The data backup operation is divided into two stages: in the first stage, BL is set to above 1.4V, SL is set to 0V, and WL_A is set to 1.8V; M0 is in the open state; R0 is set to the low resistance state LRS; in the second stage, WL_A is set to 0V, SL is set to 1V, and WL_C is set to 1.8V; M0 is in the closed state and M2 is in the open state; at this time, if C0 stores data "1", R0 maintains the low resistance state LRS; if C0 stores data "0", R0 is reset to the high level HRS.

2. The nonvolatile 3T1R1C storage circuit according to claim 1, wherein: The non-volatile 3T1R1C storage circuit has the properties of both DRAM and RRAM storage circuits: when using DRAM mode, M0 and M2 are always closed and R0 is not used; while M1 is activated during reading, writing and retention; when using RRAM, M1 and M2 are always closed and C0 is not used; while M0 is activated during reading and writing.

3. The nonvolatile 3T1R1C storage circuit according to claim 2, wherein: In the non-volatile 3T1R1C storage circuit, the data recovery operation is performed as follows: First, WL_A is always in a low-level state of 0V during the entire data recovery operation. Second, the recovery operation process includes the following two stages: In the first stage, BL is set to 1V, WL_B is set to 1.8V, M1 is in the on state, and C0 will be charged to a high level. In the second stage: WL_B is set to 0V, SL is set to 0V, and WL_C is set to 1.8V; M1 is closed and M2 is opened. At this time, if R0 is in the high-resistance state HRS, then it is difficult for C0 to discharge through R0, and it remains in the high-level state and maintains the data "1". If R0 is in the low-resistance state LRS, then C0 is discharged to the low-level state through R0, maintaining the data "0". Finally, through the above two-stage operations, the storage state of R0 is transferred to C0.

4. A recovery data correction circuit, characterized in that: It is applied to the non-volatile 3T1R1C storage circuit as claimed in any one of claims 1 to 3, and is used to correct the data "inversion error" caused by the circuit during each backup and recovery process; The recovered data correction circuit utilizes a 2-to-1 data selector and SA; the 2-to-1 data selector includes two input terminals IN1 and IN2, a selection terminal IN3, and an output terminal OUT; the selection terminal IN3 is used to receive a flag signal SEL representing the parity attribute of the number of power-off recovery times corresponding to the data currently stored in the non-volatile 3T1R1C storage circuit; the quantized output terminal of the stored data in the non-volatile 3T1R1C storage circuit is connected to SA, the reference level of SA is set to half a high level, the output level of SA and the inverse of the output level are selected by SEL, and OUT is the final correction result output; In the recovered data correction circuit, assuming that the original storage data of the non-volatile 3T1R1C storage circuit is D, the generation logic of the output terminal OUT is as follows:

5. A DRAM circuit with data backup and recovery functions, characterized in that: The DRAM circuit includes: Storage array, which consists of N 2 identical memory cells arranged in an N×N array, each of the memory cells using the nonvolatile 3T1R1C memory circuit according to claim 1; A bit line group includes N bit lines BL corresponding to columns of the memory array, and outputs of all memory cells in the same column of the memory array are connected to the same bit line; A word line group includes N groups of word line pairs corresponding to rows of the memory array, each group of the word line pairs includes four control word lines, namely WL_A, WL_B, WL_C, and SL; in the memory array, the gates of M0, M1, and M2 in all memory cells in the same row are connected to WL_A, WL_B, and WL_C in the corresponding row, respectively; and the BE terminals of R0 in all memory cells in the same row are connected to the word line SL; A word line driver, which is used to control the opening or closing of the word line WL connected to each memory cell in the memory array when performing data read and write operations; A row decoder, which is used to control the word line driver module according to the decoding result when performing data read and write operations; A column decoder, which is used to control the opening or closing of the connection of each memory cell column in the memory array when performing data read and write operations; Buffer, which is used to improve the delay and level loss caused by long wires to ensure correct output; A quantization circuit array comprising N quantization circuits; each of the quantization circuits is configured to output an analog-to-digital conversion value corresponding to a bit line voltage on one of the bit lines; A correction circuit array, comprising N restored data correction circuits as described in claim 4; each restored data correction circuit, when performing data correction, first uses the output of the quantization circuit and its inverted value as two targets to be selected, then selects a value from the two targets to be selected according to an input flag signal SEL as a correction result, and outputs the correction result as real data stored in the corresponding storage unit.

6. The DRAM circuit with data backup and recovery functions according to claim 5, wherein: The DRAM circuit is connected to a peripheral function circuit, which is used to generate a flag signal SEL required by the correction circuit array. The process of generating the flag signal by the peripheral function circuit is as follows: (1) Obtain word line and bit line signals during data reading to determine the selected data storage unit; (2) Obtain the historical power failure recovery times m corresponding to the writing of the current stored data in the current data storage unit; (3) Determine the odd or even attribute of the historical power failure recovery number m, and generate a corresponding flag signal SEL: when m is an odd number, SEL=1, indicating that the output value of the current quantization circuit needs to be corrected; when m is an even number, SEL=0, indicating that the output value of the current quantization circuit does not need to be corrected.

7. A storage circuit for implementing multiplication and accumulation operations based on 3T1R1C, characterized in that: The storage and calculation circuit includes: Storage array, which consists of N 2 identical memory cells arranged in an N×N array, each of the memory cells using the nonvolatile 3T1R1C memory circuit according to claim 1; A bit line group includes N bit lines BL corresponding to columns of the memory array, and outputs of all memory cells in the same column of the memory array are connected to the same bit line; A word line group includes N groups of word line pairs corresponding to rows of the memory array, each group of the word line pairs includes four control word lines, namely WL_A, WL_B, WL_C, and SL; in the memory array, the gates of M0, M1, and M2 in all memory cells in the same row are connected to WL_A, WL_B, and WL_C in the corresponding row, respectively; and the BE terminals of R0 in all memory cells in the same row are connected to the word line SL; A word line driver, which is used to control the opening or closing of the word line WL connected to each memory cell in the memory array when performing data read and write operations; A row decoder, which is used to control the word line driver module according to the decoding result when performing data read and write operations; The column decoder is used to control the opening or closing of the connection between each memory cell column in the memory array when performing data read and write operations; the buffer is used to improve the delay and level loss caused by long wires to ensure correct output; A quantization circuit array comprising N quantization circuits; each of the quantization circuits is configured to output an analog-to-digital conversion value corresponding to a bit line voltage on one of the bit lines; A digital shifter, which is used to assign different quantization weights to different columns; An accumulator, which is used to accumulate columns assigned different quantization weights.

8. The storage-calculation circuit for implementing multiplication-accumulation operations based on 3T1R1C as claimed in claim 7, characterized in that: Each memory cell in the same column of the memory array of the storage-calculation circuit serves as a basic multiplication execution unit. The cumulative sum of the multiplication results calculated by all memory cells is output to the bit line for quantization and output. In each memory cell, the word line signal WL_C connected to M2 serves as the first operand of the multiplication operation; the weight W corresponding to the resistance state of R0 serves as the second operand; and the value output by C0 to the bit line BL serves as the product; that is, BL = WL_C × W. All the memory cells in the same column of the memory array serve as execution units for performing a single-bit MAC operation. The process of the single-bit MAC operation is as follows: S1: Define the weight W corresponding to the resistance state of R0 as follows: HRS represents "0" and LRS represents "1"; S2: Set BL to 1V and WL_B to 1.8V. At this point, M1 is open and all capacitors are charged to "1." The input bit is applied to WL_C in the form of word line voltage. First, if the input is "1", WL_C is set to 1.8V and M2 is turned on. At this time, if the resistance state of the RRAM is HRS and the weight is "0", it is difficult for the capacitor to discharge and it remains at Vcap. At this time, the output operation result is "0", that is, 1×0=0. Second, if the input is "1", the resistance state of the RRAM is LRS, and the weight is "1", then the capacitor will discharge to the low level 0, and the output operation result is "1"; That is: 1×1=1; 3. If the input is "0", WL_C is set to 0V and M2 is turned off. At this time, regardless of the RRAM resistance state, the capacitor cannot be discharged and the output operation result is "0", that is, 0×1=0 or 0×0=0. S3: Charge is shared across all capacitors in a column through the bit lines, and the bit line potential reflects the simulated accumulation result. S4: The analog result is quantized by the Flash ADC circuit and further shifted and accumulated through the digital shifter and adder to obtain the final product-accumulation operation result.

9. The storage-calculation circuit for implementing multiplication-accumulation operations based on 3T1R1C as claimed in claim 8, characterized in that: In the storage-calculation circuit, all storage cells in a plurality of adjacent columns are used as execution units for performing a multi-bit MAC operation. The operation process of the multi-bit MAC operation is as follows: First, the multiplication and accumulation operations in each column are consistent with the process of single-bit MAC operation; Secondly, assume that the selected N operation columns are arranged in descending order by weight; after obtaining a single-bit input and N-bit weight, the input is performed from low to high over N clock cycles; different weights are quantized in different cycles; after quantization, some of the results are shifted and added; finally, an N-bit output is obtained.

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