A long-time storage-oriented flash memory reliability test and prediction method

Abstract

The application discloses a long-time storage-oriented flash memory reliability test and prediction method. The long-time storage-oriented flash memory reliability test method provided by the application can better simulate the reliability decline process of a flash memory chip in a long-time storage scene based on a 3D NAND flash memory reliability mechanism, and the influence of self-repairing effect and threshold voltage jitter on test results is considered. Since the error number of the flash memory chip fluctuates greatly in a short time, the flash memory chip is left for a preset time, so that the accuracy of the test result is improved, and the test result is closer to the actual reliability of the chip. The long-time storage-oriented flash memory reliability prediction method provided by the application establishes a reliability prediction model on the basis of test data of a plurality of different model chips with the same manufacturing process as a benchmark, the model has better generalization ability, and thus the reliability prediction of the flash memory chip under the same manufacturing process is realized.

Description

Technical Field

[0001] This invention belongs to the field of flash memory chips, and more specifically, relates to a method for testing and predicting the reliability of flash memory for long-term storage. Background Technology

[0002] With the development of integrated circuit technology, non-volatile memory (NDRAM) has gradually become the main medium for storing information in electronic devices. NDRAM is a type of memory that can retain information even after power loss. Among NDRAM devices, NAND flash memory is widely used in data storage fields due to its advantages such as low manufacturing cost, large storage capacity, shock and magnetic resistance, fast read / write speed, and non-volatile data. Therefore, testing the reliability of flash memory chips and establishing relevant models is of great significance.

[0003] In recent years, 3D NAND flash memory has gradually replaced 2D NAND flash memory as the mainstream memory in the market. Compared to 2D NAND flash memory, 3D NAND flash memory has a higher storage density and can store more data. However, the data retention problem in 3D NAND flash memory is very serious. The bit error rate increases rapidly in a short period of time during data storage, and the data retention error characteristics are different at different temperatures. Traditional flash memory chip reliability testing methods usually use high-temperature acceleration methods to simulate long-term data retention processes. This method does not consider the error characteristics at the actual target temperature during testing. According to existing research results, the error change curve of 3D NAND flash memory chips during long-term data storage differs from the high-temperature acceleration simulation results. Therefore, when testing 3D NAND flash memory, the high-temperature acceleration method used in traditional flash memory reliability testing may not be able to simulate the real data retention reliability degradation process, making it difficult to obtain accurate test results. Summary of the Invention

[0004] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a flash memory reliability testing and prediction method for long-term storage, thereby solving the technical problem of low accuracy of existing flash memory chip reliability testing methods.

[0005] To achieve the above objectives, according to a first aspect of the present invention, a flash memory reliability testing method for long-term storage is provided, comprising:

[0006] S1, at room temperature, the test memory block of the flash memory chip under test is sequentially erased and programmed, and a read operation is performed after waiting time T0;

[0007] S2, determine whether the number of erase / programming cycles experienced by the tested storage block is less than Cpe. If yes, return to step S1; otherwise, proceed to S3.

[0008] S3, after powering off the flash memory chip under test and placing it at room temperature for time T1, the memory block under test is sequentially erased, programmed, and read, and the read data is saved;

[0009] S4. After waiting for time T2 at temperature K, the tested storage block is read, and the read data is compared with the read data saved in S3 to obtain the data retention error related parameters.

[0010] S5, determine if the total data holding time Ts is less than T3. If yes, return to S4; otherwise, proceed to S6. Where Ts is the time interval between the most recent programming operation and the last read operation.

[0011] S6, determine whether the number of erase / programming cycles experienced by the tested memory block is less than Cto. If yes, return to S1; otherwise, proceed to S7.

[0012] S7. Based on the data retention error related parameters, determine the maximum Ts value corresponding to the number of erase / programm cycles of the flash memory chip under test under the condition of satisfying the preset data retention error, and take it as the time when the chip under test can normally store data at temperature K, so as to obtain the test result of the flash memory chip under test at temperature K.

[0013] According to a second aspect of the present invention, a method for establishing a flash memory reliability prediction model for long-term storage is provided, comprising:

[0014] Test results are obtained for N flash memory chips with the same manufacturing process but different models, as described in the first aspect. At the same time, the erase, programming, and read operation times in steps S1 and S3, the read operation time in step S4, the power consumption and current of each tested chip after the read operation in step S4, and the error-related parameters of each chip's data are used to construct the dataset to be processed for each flash memory chip. Wherein, N is an integer greater than 1.

[0015] From the dataset to be processed of each flash memory chip, parameters whose Pearson correlation coefficients with their corresponding test results meet preset conditions are selected as feature parameters;

[0016] The union of the characteristic parameters corresponding to each flash memory chip is defined as the reliability parameter of each flash memory chip, and the reliability parameters of each flash memory chip and the test results are used as a sample set to obtain N sample sets, which include a training set and a test set.

[0017] Select N-1 sample sets as the target training set, and the remaining sample sets as the target test set. After N different selection combinations, N target sample sets are obtained.

[0018] The reliability prediction model was trained using each target sample set, and the trained reliability prediction model with the smallest prediction error was selected as the target reliability prediction model.

[0019] According to a third aspect of the present invention, a method for predicting the reliability of flash memory for long-term storage is provided, wherein the reliability parameters of the flash memory chip to be predicted are input into a target reliability prediction model established by the method described in the second aspect, and the reliability prediction result of the flash memory chip to be predicted at a temperature K is obtained.

[0020] The reliability prediction result is the time that the flash memory chip to be predicted can normally store data under the preset data retention error conditions.

[0021] The flash memory chip to be predicted is manufactured using the same process as the N flash memory chips.

[0022] According to a fourth aspect of the present invention, a method for predicting the reliability of flash memory for long-term storage is provided, comprising:

[0023] The parameters of the hidden layer of the target reliability prediction model established by the method described in the second aspect are transferred to obtain an updated reliability prediction model, and the updated reliability prediction model is trained using the sample set of chip A.

[0024] The reliability parameters of the flash memory chip A to be predicted are input into the trained updated reliability prediction model to obtain the reliability prediction result;

[0025] The reliability prediction result is the time that the flash memory chip A to be predicted can normally store data under each number of erase / programming cycles, provided that the preset data retention error condition is met.

[0026] The flash memory chip A to be predicted has the same manufacturing process as the N flash memory chips, but different models.

[0027] According to a fifth aspect of the present invention, a computer storage medium is provided, wherein the computer storage medium stores instructions that, when executed on a computer, cause the computer to perform a testing method as described in the first aspect, or a model building method as described in the second aspect, or a prediction method as described in the third aspect, or a prediction method as described in the fourth aspect.

[0028] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0029] The present invention provides a flash memory reliability testing method for long-term storage. Based on the 3D NAND flash memory reliability mechanism design, it can better simulate the reliability degradation process of flash memory chips in long-term storage scenarios. It considers the influence of self-healing effect and threshold voltage jitter on the test results. Since the number of errors of flash memory chips fluctuates greatly in a short period of time, it is left to stand for a preset time to improve the accuracy of the test results and make the test results closer to the actual reliability of the chip.

[0030] The present invention provides a flash memory reliability prediction method for long-term storage. Based on the same manufacturing process, a reliability prediction model is established on the test data of multiple different models of chips with the same manufacturing process. The model has better generalization ability, thereby realizing the reliability prediction of flash memory chips under the same manufacturing process. Attached Figure Description

[0031] Figure 1 This is one of the flowcharts for a flash memory reliability testing method for long-term storage provided in an embodiment of the present invention.

[0032] Figure 2 The second flowchart of a flash memory reliability testing method for long-term storage provided in an embodiment of the present invention.

[0033] Figure 3 A flowchart for programming / erasing loop testing provided in an embodiment of the present invention.

[0034] Figure 4 A flowchart for data retention testing provided in an embodiment of the present invention.

[0035] Figure 5 This is a schematic diagram of the test data combination provided in an embodiment of the present invention.

[0036] Figure 6 A flowchart illustrating the establishment of a flash memory reliability prediction model for long-term storage provided in this embodiment of the invention.

[0037] Figure 7 A flowchart illustrating the establishment of a single reliability model provided in an embodiment of the present invention.

[0038] Figure 8 This is a schematic diagram of the flash memory reliability model structure provided in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0040] This invention provides a flash memory reliability testing method for long-term storage. The method tests the reliability of flash memory during long-term data storage in segments according to the error characteristics of flash memory at different stages of its lifespan. The testing process mainly includes three parts: room temperature programming / erase cycle test, room temperature resting before data retention, and data retention test, including:

[0041] S1, at room temperature (25 degrees), the test memory block of the flash memory chip under test is erased and programmed sequentially, and a read operation is performed after waiting time T0.

[0042] Specifically, S1 includes S11 and S12.

[0043] S11, At room temperature, place the flash memory chip under test in the test equipment, select the test data type, and send the test command; the test equipment performs an erase operation on the memory block under test and collects the erase operation time;

[0044] S12, the test device writes test data to the storage block under test and collects the programming operation time and the number of programming / erase cycles; after waiting for time T0, it performs a read operation on the storage block under test and collects the read operation time.

[0045] Preferably, the test data written to the storage block under test during the programming operation is pseudo-random test data.

[0046] The amount of data to be written to each storage block is determined based on the test requirements. The amount of data must be no less than the minimum write unit size of the storage block and no more than the amount of data that the storage block can store as specified in the datasheet.

[0047] The waiting time T0 in S12 is the read operation delay time. Its purpose is to reduce the impact of storage cell threshold voltage jitter on the read data results, making the acquired parameters more reliable. The waiting time T0 needs to be more than 1 minute.

[0048] When selecting chip storage blocks, if the chip storage density is less than 2M, all storage blocks within the chip are selected as the test object; if the storage density is greater than 2M, 10% of the storage is selected from different locations; the number of storage blocks with odd and even numbers is equal.

[0049] S2, determine whether the number of erase / programming cycles experienced by the tested storage block is less than Cpe. If yes, return to step S1; otherwise, proceed to S3.

[0050] Specifically, the value of Cpe is determined based on the test requirements and must be less than the maximum number of erase / program cycles specified in the datasheet of the flash memory chip under test.

[0051] S3, after powering off the flash memory chip under test and placing it at room temperature for time T1, the memory block under test is sequentially erased, programmed, and read, and the read data is saved.

[0052] Specifically, at room temperature, after the flash memory chip under test is powered off and left for a time T1, the flash memory chip under test is placed in the test equipment, and the memory block under test is sequentially erased / programmed / readed once. The erased / programmed / read operation time is collected, and the read data is saved.

[0053] The latency T1 is the data retention delay time, which is used to reduce the trapped charge generated in the oxide layer of the flash memory cell during erase / program operation and repair oxide layer degradation. The latency T1 needs to be more than 1 hour.

[0054] S4. After waiting for time T2 at temperature K, the tested storage block is read, and the read data is compared with the read data saved in S3 to obtain the data retention error related parameters.

[0055] Specifically, at a temperature K, after the test equipment waits for a time T2, it performs a data reading operation on the memory block under test and collects the reading operation time, power consumption and current of the chip under test; the read data is compared with the data saved in step S3 to statistically analyze the data retention error and obtain the relevant parameters of the data retention error.

[0056] The data retention error-related parameters include at least one of the following: raw error per KB, raw page error, raw error per KB under a read-retry operation, or raw page error.

[0057] Specifically, the test equipment waiting time T2 is the data retention time. The value of the retention time T2 is determined according to the test requirements and must be less than the upper limit of the data retention time specified in the datasheet of the flash memory chip under test.

[0058] Temperature K is the average ambient temperature of the flash memory chip under test during actual application. When the ambient temperature changes significantly during data storage (e.g., the temperature change exceeds 50 degrees), K should be taken as the minimum, lower quartile, median, upper quartile, and maximum value of the ambient temperature distribution for testing and to collect reliability parameters.

[0059] S5, determine if the total data holding time Ts is less than T3. If yes, return to S4; otherwise, proceed to S6. Here, Ts is the time interval between the most recent programming operation and the last read operation.

[0060] Specifically, the total data retention time T3 is the sum of all waiting times T2 during step a08. The value of the total data retention time T3 is determined based on the test requirements and must be less than the upper limit of the data retention time specified in the datasheet of the flash memory chip under test.

[0061] S6, determine whether the number of erase / programming cycles experienced by the tested memory block is less than Cto. If yes, return to S1; otherwise, proceed to S7.

[0062] S7. Based on the data retention error related parameters, determine the maximum Ts value corresponding to the number of erase / programm cycles of the flash memory chip under test under the condition of satisfying the preset data retention error, and take it as the time when the chip under test can normally store data at temperature K, so as to obtain the test result of the flash memory chip under test at temperature K.

[0063] It is understandable that the preset data retention error conditions are set according to test requirements.

[0064] For example, if the number of raw errors per KB is selected as the data retention error related parameter, the preset data retention error conditions are that the number of raw errors per KB cannot exceed 74, Cpe = 100, Cto = 1000, T2 = 12h, and T3 = 120h.

[0065] Then test the flash memory chip:

[0066] Data retention error-related parameters after 100 programming / erase cycles at 12h, 24h, and 36h;

[0067] Data retention error-related parameters after 200 programming / erase cycles for 12h, 24h, 36h, ..., 120h;

[0068] Data retention error-related parameters after 300 programming / erase cycles for 12h, 24h, 36h, ..., 120h;

[0069] Data retention error-related parameters after 400 programming / erase cycles for 12h, 24h, 36h, ..., 120h;

[0070] Data retention error-related parameters after 500 programming / erase cycles for 12h, 24h, 36h, ..., 120h;

[0071] Data retention error-related parameters after 600 programming / erase cycles for 12h, 24h, 36h, ..., 120h;

[0072] Data retention error-related parameters after 700 programming / erase cycles for 12h, 24h, 36h, ..., 120h;

[0073] Data retention error-related parameters after 800 programming / erase cycles for 12h, 24h, 36h, ..., 120h;

[0074] Data retention error-related parameters after 900 programming / erase cycles for 12h, 24h, 36h, ..., 120h;

[0075] Data retention error-related parameters after 1000 programming / erase cycles for 12h, 24h, 36h, ..., 120h.

[0076] If the maximum retention time for a chip with less than 74 original errors per KB is 36 hours during 100 program / erase cycles, then 36 hours is taken as the time the chip can normally store data during 100 program / erase cycles (when the data retention time is less than or equal to 36 hours, the original error per KB is less than 74; when the data retention time is greater than 36 hours, the original error per KB is greater than or equal to 74). If the maximum retention time for a chip with less than 74 original errors per KB is 24 hours during 200 program / erase cycles, then 24 hours is taken as the time the chip can normally store data during 200 program / erase cycles. Similarly, the time for normal data storage during 300, 400, ..., 1000 program / erase cycles is obtained, ultimately yielding the time for normal data storage under the preset data retention error conditions for each number of program / erase cycles.

[0077] The reliability testing method provided by this invention is applicable to all types of flash memory chips.

[0078] The following specific example further illustrates the flash memory reliability testing method for long-term storage provided by this invention.

[0079] Multi-cell 3D NAND flash memory (TLC NAND flash) products manufactured using a certain process were used as the failure prediction target. Figure 1-2 The test steps are as follows: First, at room temperature, place the selected flash memory chip in the test equipment and power on the test equipment. Configure the test parameters, as shown in Table 1.

[0080] Table 1

[0081]

[0082] In this embodiment, the test data used for flash memory reliability testing is pseudo-random test data. The number of erase / programmable cycles Cpe is 100, the total number of erase / programmable cycles Cto is 3000, the waiting time T0 is 1 minute, the flash memory chip power-off placement time T1 is 3 hours, the retention time T2 is 24 hours, the time without erase / programmable execution T3 is 168 hours, the temperature K is 28 degrees Celsius, and the data retention error related parameter is the number of original error bits per KB of data.

[0083] After the test equipment is configured, send the programming / erase cycle test command. The programming / erase cycle test flowchart is as follows: Figure 3 As shown, the specific test steps are as follows:

[0084] 1. The testing equipment performs an erase operation on the memory block under test;

[0085] 2. Check the chip erase operation success flag. If the erase operation is successful, proceed to step 3; otherwise, return to step 1. If step 1 is repeated more than 5 times, the memory block under test is marked as bad and the memory block under test is reselected.

[0086] 3. The test equipment writes test data to the memory block under test;

[0087] 4. Check the chip programming success flag. If the programming operation is successful, proceed to step 5; otherwise, return to step 3. If step 3 is repeated more than 5 times, the memory block under test will be marked as a bad block and the memory block under test will be selected again.

[0088] 5. During the waiting time T0, the test device performs a read operation on the tested storage block and saves the read data Dr;

[0089] 6. Determine whether the number of erase / programming cycles experienced by the tested memory block is less than 100. If the number of programming / erasing cycles is less than 100, repeat steps 1 to 5.

[0090] After completing the programming / erase cycle test, the flash memory chip under test is left unpowered at room temperature for 3 hours. The flash memory chip under test is then placed in the test equipment, and an erase / program / read operation is performed on the test block. The execution time of the erase operation and the number of raw error bits per KB of data in the test block are recorded, and the read data (Dr) is saved. The data retention test then begins; the data retention test flowchart is shown below. Figure 4 As shown, the specific test steps are as follows:

[0091] 1. Place the flash memory chip under test in the testing equipment, adjust the temperature chamber to the target temperature (28 degrees Celsius), and wait for 24 hours.

[0092] 2. The test equipment reads data from the storage block under test, compares the read data with the saved data Dr, and counts the number of errors generated during the data retention period (e.g., the number of raw error bits per KB of data).

[0093] 3. Determine if the time before erasure / programming has not been less than 168 hours. If it is less, repeat steps 1 and 2; otherwise, complete the data retention test.

[0094] The test equipment calculates the cumulative number of erase / programming operations and determines whether the cumulative number of erase / programming operations exceeds 3000. If the cumulative number of erase / programming operations is less than 3000, the programming / erasing cycle test, the data retention pre-temperature resting test, and the data retention test are repeated. Otherwise, the flash memory reliability test is completed, and the maximum retention time for each programming / erasing cycle to meet the preset data retention error conditions is determined, and the test results are obtained.

[0095] This invention provides a method for establishing a flash memory reliability prediction model for long-term storage, comprising:

[0096] Test results for each of the N flash memory chips with the same manufacturing process but different models are obtained by the test method described in any of the above embodiments. At the same time, the erase, programming, and read operation times in steps S1 and S3, the read operation time in step S4, the power consumption and current of each tested chip after the read operation in step S4 are collected, and the error-related parameters of each chip are used to construct the dataset to be processed for each flash memory chip. Wherein, N is an integer greater than 1.

[0097] From the dataset to be processed of each flash memory chip, parameters whose Pearson correlation coefficients with their corresponding test results meet preset conditions are selected as feature parameters;

[0098] The union of the characteristic parameters corresponding to each flash memory chip is defined as the reliability parameter of each flash memory chip, and the reliability parameters of each flash memory chip and the test results are used as a sample set to obtain N sample sets, which include a training set and a test set.

[0099] Select N-1 sample sets as the target training set, and the remaining sample sets as the target test set. After N different selection combinations, N target sample sets are obtained.

[0100] The reliability prediction model was trained using each target sample set, and the trained reliability prediction model with the smallest prediction error was selected as the target reliability prediction model.

[0101] Preferably, the flash memory reliability prediction model is constructed based on functions, support vector machines, neural networks, random forests, decision trees, or KNN.

[0102] Specifically, N different models of flash memory chips under the same manufacturing process are selected for testing and reliability parameters are collected. The test data of a single model of flash memory chip (denoted as Di) are combined to establish N reliability models. The reliability model error is tested, and the reliability model with the smallest error is selected as the target reliability prediction model to predict the reliability of the chip to be predicted.

[0103] Furthermore, embodiments of the present invention provide a flash memory reliability prediction method for long-term storage, comprising:

[0104] The reliability parameters of the flash memory chip to be predicted are input into the target reliability prediction model established using the model building method described in any of the above embodiments, and the reliability prediction result of the flash memory chip to be predicted at temperature K is obtained.

[0105] The reliability prediction result is the time that the flash memory chip to be predicted can normally store data under the preset data retention error conditions.

[0106] The flash memory chip to be predicted is manufactured using the same process as the N flash memory chips.

[0107] Specifically, the N flash memory chips are obtained by sampling, and the sampling rule is: randomly select the chip to be tested from multiple consecutive batches of chip samples, and select no less than 10% of the storage blocks of each chip as the test sample.

[0108] In the data preprocessing stage, taking N=3 (three flash memory chips) as an example, if the characteristic parameters satisfying the preset conditions for the Pearson correlation coefficient between the test results of chip 1 and chip 2 are power consumption and raw errors per KB, and the characteristic parameters satisfying the preset conditions for the Pearson correlation coefficient between the test results of chip 2 and chip 3 are current and raw errors per KB, and the characteristic parameter satisfying the preset conditions for the Pearson correlation coefficient between the test results of chip 3 and chip 3 is the number of raw page errors, then the reliability parameter is the union of the above characteristic parameters, namely: power consumption, raw errors per KB, current, and number of raw page errors. Correspondingly, in the training stage, power consumption, raw errors per KB, current, and number of raw page errors are the inputs, and the test results corresponding to the above reliability parameters are the outputs. By training the flash memory reliability prediction model, the mapping relationship between the inputs and outputs is obtained.

[0109] It is understandable that the parameters and test results in the dataset to be processed for each flash memory chip correspond one-to-one with the number of erase / programming cycles.

[0110] Under the same manufacturing process, the following conditions must be met: same manufacturer, same storage unit structure, same unit process size, same unit composition materials, same array structure, and same programming / erasing / reading method.

[0111] The test data (i.e., the target sample set) is combined as follows: test data from at least two flash memory chip models (denoted as di) are randomly selected and combined to form a training dataset (i.e., the target training dataset) for building a reliability model (i.e., a reliability prediction model), until all test models have been selected. The selected test data should be less than the total amount of data for the selected chip models, and di is a proper subset of Di. The number of chip models included in the combination should be less than the total number of models.

[0112] The process of establishing the reliability model is as follows:

[0113] Step b01: Prepare the datasets needed to build the reliability model and the datasets needed to test the model;

[0114] Step b02: Initialize the modeling program;

[0115] Step b03: The modeling program receives the test data and runs the modeling algorithm, which calculates the reliability model parameters.

[0116] Step b04: The program checks whether the model output error meets the stopping requirements. If it does not meet the requirements, the program adjusts the model parameters. If it does meet the requirements, step b05 is executed.

[0117] Step b05: The program outputs a data reliability model.

[0118] The reliability model can be a data structure that can describe the relationship between input and output, such as a function, support vector machine, neural network, random forest, decision tree, and KNN.

[0119] The target test dataset is: test data dj (j≠i) of chips not selected when building the reliability model, and the intersection with the reliability model training dataset is empty.

[0120] The method for adjusting the reliability model parameters is determined according to the model type. For models that can directly update parameters, the data of the flash memory chip under test is used as the modeling data, and modeling steps b04 to b05 are executed. For models that cannot directly update parameters, the modeling data and the data of the flash memory chip under test are merged as the modeling data, and modeling steps b01 to b05 are executed.

[0121] The target reliability prediction model established by the above method learns the characteristics of different chip models during the training process, has strong generalization ability, and can be applied to the reliability prediction of various chip models under the same manufacturing process.

[0122] Furthermore, for N flash memory chips A with the same manufacturing process but different models from those in the above model establishment method, in order to improve prediction accuracy, the parameters of the above target reliability prediction model can be transferred to obtain an updated reliability prediction model. The updated reliability prediction model is then trained using a sample set of chip A, and the trained updated reliability prediction model is used to predict the reliability of chip A. Based on this, this embodiment of the invention provides a flash memory reliability prediction method for long-term storage, including:

[0123] The parameters of the hidden layer of the target reliability prediction model established using the reliability model establishment method described in any of the above embodiments are transferred to obtain an updated reliability prediction model, and the updated reliability prediction model is trained using the sample set of chip A.

[0124] The reliability parameters of the flash memory chip A to be predicted are input into the trained updated reliability prediction model to obtain the reliability prediction result;

[0125] The reliability prediction result is the time that the flash memory chip A to be predicted can normally store data under each number of erase / programming cycles, provided that the preset data retention error condition is met.

[0126] The flash memory chip A to be predicted has the same manufacturing process as the N flash memory chips, but different models.

[0127] The following example further illustrates the above-mentioned flash memory reliability prediction method for long-term storage.

[0128] Three types of flash memory chips manufactured using the same process were selected. Ten percent of the memory blocks from each chip were randomly selected for reliability testing, and the number of raw errors per KB of the tested memory blocks was collected. The reliability testing procedure is as follows: Figure 1 As shown. The test results for the three flash memory chips are denoted as D1, D2, and D3. Test data d1, d2, and d3 are selected from the test datasets D1, D2, and D3, respectively. Here, di is a proper subset of Di. The test data d1, d2, and d3 are paired to form new datasets as modeling data, as shown in the following combination method. Figure 5 As shown. In this embodiment, the modeling dataset and the corresponding test dataset are as follows:

[0129] 1. Modeling dataset: Dta1 = d1∪d2, Test dataset: Dte1 = d3;

[0130] 2. Modeling dataset: Dta2 = d1∪d3, Test dataset: Dte2 = d2;

[0131] 3. Modeling dataset: Dta3 = d2∪d3, Test dataset: Dte3 = d1.

[0132] In this embodiment, the reliability model establishment process is as follows: Figure 6 As shown. First, a reliability model is built using datasets Dta1, Dta2, and Dta3. The process for building a single model is as follows: Figure 7 As shown. The model type used in this embodiment is a multi-layer artificial neural network, and its structure is as follows. Figure 8 As shown, the artificial neural network consists of an input layer, hidden layers, a softmax layer, and an output layer. There are 10 hidden layers with 50 units per layer, and the activation function is sigmoid. The model input is a reliability parameter, and the output is the time the flash memory chip can normally store data at various erase / program cycles under different temperatures (K).

[0133] The steps for modeling a single reliability model are as follows:

[0134] 1. Initialize the training algorithm;

[0135] 2. Input the modeling data into the artificial neural network, and train the algorithm to calculate the error between the output of the artificial neural network and the actual value;

[0136] 3. The training algorithm adjusts the weights of the artificial neural network;

[0137] 4. Check if the number of epochs has reached 100. If it has, stop training; otherwise, return to step 2.

[0138] 5. Program output reliability model.

[0139] In this embodiment, the error between the artificial neural network output and the actual value in step 2 is the root mean square error, calculated using the following formula:

[0140]

[0141] Where n is the total number of samples, f(x) k ) represents the output of the reliability model, x k As input to the model, y k This is the actual result.

[0142] Input the test dataset into the corresponding reliability model and calculate the reliability model error. The reliability model error is calculated as follows:

[0143]

[0144] Where n is the total number of samples, f(x) k ) represents the output of the reliability model, x k As input to the model, y k For actual results, For all f(x) k The average value of ).

[0145] The reliability model with the smallest error is selected as the target reliability prediction model. Its input layer, softmax layer, and output layer parameters are reset, that is, the parameters of a specified neural network layer are restored to their non-recurrent values ​​(e.g., replaced with random values), while the parameters of the hidden layers are retained. This allows the target reliability prediction model to be transferred to chip A, resulting in an updated reliability prediction model. The test results and reliability parameters of chip A are used as a sample set for training, yielding a more accurate reliability prediction model suitable for chip A. The training algorithm adjusts the parameters of the reliability model after resetting the input layer, softmax layer, and output layer. The specific steps are as follows:

[0146] 1. Test data from flash memory chip A is used as training data to update the reliability model;

[0147] 2. The training algorithm calculates the error between the output of the artificial neural network and the actual value, and adjusts the weights of the artificial neural network accordingly;

[0148] 3. Determine if the error is less than 0.001 or if the number of epochs has reached 1000. If either condition is met, stop training.

[0149] 4. The program outputs the trained and updated reliability model.

[0150] In step 4, the reliability model output by the program is the updated reliability prediction model trained in this embodiment. In this embodiment, the error between the artificial neural network output in step 2 and the actual value is the root mean square error.

[0151] This invention provides a computer storage medium storing instructions that, when executed on a computer, cause the computer to perform a testing method as described in any of the above embodiments, or a prediction method as described in any of the above embodiments.

[0152] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for testing the reliability of flash memory for long-term storage, characterized in that, include: S1, at room temperature, the test memory block of the flash memory chip under test is sequentially erased and programmed, and a read operation is performed after waiting time T0; S2, determine whether the number of erase / programming cycles experienced by the tested storage block is less than Cpe. If yes, return to step S1; otherwise, proceed to S3. S3, after powering off the flash memory chip under test and placing it at room temperature for time T1, the memory block under test is sequentially erased, programmed, and read, and the read data is saved; S4. After waiting for time T2 at temperature K, the tested storage block is read, and the read data is compared with the read data saved in S3 to obtain the data retention error related parameters. S5, determine if the total data holding time Ts is less than T3. If yes, return to S4; otherwise, proceed to S6. Where Ts is the time interval between the most recent programming operation and the last read operation. S6, determine whether the number of erase / programming cycles experienced by the tested memory block is less than Cto. If yes, return to S1; otherwise, proceed to S7. S7. Based on the data retention error related parameters, determine the maximum Ts value corresponding to the number of erase / programm cycles of the flash memory chip under test under the condition of satisfying the preset data retention error, and take it as the time when the flash memory chip under test can normally store data at temperature K, so as to obtain the test result of the flash memory chip under test at temperature K. T0≥1min, T1≥1h.

2. The method as described in claim 1, characterized in that, The data retention error-related parameters include at least one of the following: raw error per KB, raw error per page, raw error per KB under a read-retry operation, or raw error per page.

3. The method as described in claim 1, characterized in that, The test data written to the storage block under test during the programming operation is pseudo-random test data.

4. A method for establishing a flash memory reliability prediction model for long-term storage, characterized in that, include: The method described in any one of claims 1-3 is used to test N flash memory chips with the same manufacturing process but different models to obtain the test results of each chip; at the same time, the erase, programming, and read operation times in steps S1 and S3, the read operation time in step S4, the power consumption and current of each tested chip after the read operation in step S4 are collected, and the error-related parameters of each chip are used to construct the dataset to be processed for each flash memory chip; where N is an integer greater than 1; From the dataset to be processed of each flash memory chip, parameters whose Pearson correlation coefficients with their corresponding test results meet preset conditions are selected as feature parameters; The union of the characteristic parameters corresponding to each flash memory chip is defined as the reliability parameter of each flash memory chip, and the reliability parameters of each flash memory chip and the test results are used as a sample set to obtain N sample sets, which include a training set and a test set. Select N-1 sample sets as the target training set, and the remaining sample sets as the target test set. After N different selection combinations, N target sample sets are obtained. The reliability prediction model was trained using each target sample set, and the trained reliability prediction model with the smallest prediction error was selected as the target reliability prediction model.

5. The method as described in claim 4, characterized in that, The flash memory reliability prediction model is constructed based on functions, support vector machines, neural networks, random forests, decision trees, or KNN.

6. A method for predicting the reliability of flash memory for long-term storage, characterized in that, include: The reliability parameters of the flash memory chip to be predicted are input into the target reliability prediction model established by the method as described in claim 4 or 5, and the reliability prediction result of the flash memory chip to be predicted at temperature K is obtained. The reliability prediction result is the time that the flash memory chip to be predicted can normally store data under the preset data retention error conditions. The flash memory chip to be predicted is manufactured using the same process as the N flash memory chips.

7. A method for predicting the reliability of flash memory for long-term storage, characterized in that, include: The parameters of the hidden layer of the target reliability prediction model established by the method described in claim 4 or 5 are transferred to obtain an updated reliability prediction model, and the updated reliability prediction model is trained using the sample set of chip A. The reliability parameters of the flash memory chip A to be predicted are input into the trained updated reliability prediction model to obtain the reliability prediction result; The reliability prediction result is the time that the flash memory chip A to be predicted can normally store data under each number of erase / programming cycles, provided that the preset data retention error condition is met. The flash memory chip A to be predicted has the same manufacturing process as the N flash memory chips, but different models.

8. A computer storage medium, characterized in that, The computer storage medium stores instructions that, when executed on the computer, cause the computer to perform the testing method as described in any one of claims 1-3, or the model building method as described in any one of claims 4-5, or the prediction method as described in claims 6-7.

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