A method for epitaxial growth of a silicon wafer

Abstract

The application discloses a method for epitaxial growth of a silicon wafer, which comprises the following steps: determining a first heating power in a pre-heating stage before epitaxial growth of the silicon wafer and a second heating power in an epitaxial growth stage of the silicon wafer; heating the silicon wafer to be processed to a preset temperature under the first heating power in the pre-heating stage before epitaxial growth of the silicon wafer; and performing epitaxial growth of the silicon wafer to be processed under the second heating power in the epitaxial growth stage. The method for epitaxial growth of the silicon wafer can ensure that no slip line is generated in the epitaxial wafer during the growth process and that the epitaxial wafer with good resistivity uniformity is obtained.

Description

Technical Field

[0001] This application belongs to the field of silicon wafer technology, specifically relating to a method for epitaxial growth of silicon wafers. Background Technology

[0002] Silicon epitaxial growth is a crucial process in semiconductor chip manufacturing. Under specific conditions, it involves growing a single-crystal silicon layer with uniform resistivity, controllable thickness, and free of COP and oxygen deposits on a polished wafer as a substrate. Methods include vacuum epitaxial deposition, vapor phase epitaxial deposition, and liquid phase epitaxial deposition. Vapor phase epitaxial deposition is the most widely used. In a high-temperature environment, single-crystal silicon is generated by the reaction of silicon source gas and hydrogen and deposited on the silicon wafer surface to obtain the epitaxial layer. Simultaneously, a dopant (B₂H₆ or PH₃) is introduced to dope the epitaxial layer to achieve the desired resistivity.

[0003] The equipment used for silicon epitaxial growth is an epitaxial furnace. After regular preventive maintenance (PM) or bulb replacement, a slip window test is performed on the epitaxial furnace. This involves testing with different inner (center) and outer (outer) power conditions to find a set of conditions that prevent slippage before proceeding with subsequent epitaxial growth. Therefore, the power of the epitaxial furnace is fixed after the slip window test, making it impossible to improve the resistivity uniformity of the epitaxial layer by changing the power. Forcibly changing the furnace power, especially when the temperature difference between the center and edge of the silicon wafer exceeds 10°C, can easily lead to slip lines. Summary of the Invention

[0004] In view of this, the present invention provides a method for epitaxial growth of silicon wafers. The present invention first determines a first heating power that will not generate slip lines before epitaxial growth, and then determines a second heating power that has the best resistivity uniformity based on this first heating power, and uses the second heating power in the epitaxial growth process.

[0005] In a first aspect, the present invention provides a method for epitaxial growth of silicon wafers, comprising:

[0006] The first heating power and the second heating power of the silicon wafer epitaxial growth stage are determined; in the heating stage before silicon wafer epitaxial growth, the silicon wafer to be processed is heated to a preset temperature under the first heating power; in the silicon wafer epitaxial growth stage, the silicon wafer to be processed is subjected to epitaxial growth under the second heating power.

[0007] The determination of the first heating power during the preheating stage before silicon wafer epitaxial growth and the second heating power during silicon wafer epitaxial growth includes:

[0008] A silicon wafer is placed in a reaction chamber, wherein a heating assembly is provided in the reaction chamber, the silicon wafer has a central region and an outer peripheral region, and the heating assembly includes a first heating lamp for heating the central region of the upper surface of the silicon wafer, a second heating lamp for heating the outer peripheral region of the upper surface of the silicon wafer, a third heating lamp for heating the central region of the lower surface of the silicon wafer, and a fourth heating lamp for heating the outer peripheral region of the lower surface of the silicon wafer.

[0009] Adjust the power of the heating component, select different silicon wafers, and heat the different silicon wafers to a preset temperature at different power levels to obtain multiple first silicon wafers; determine the power corresponding to the first silicon wafer that does not produce slip lines among the multiple first silicon wafers as the first heating power;

[0010] A silicon wafer is heated to the preset temperature under the first heating power, and then the power of the heating lamp is adjusted to perform epitaxial growth on different silicon wafers under different power to obtain multiple second silicon wafers; the power corresponding to the second silicon wafer whose resistivity uniformity meets the preset uniformity is determined as the second heating power.

[0011] Furthermore, the first heating power is configured as follows:

[0012] The power of the first heating lamp accounts for 60%-88% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for 12%-24% of the sum of the power of the third heating lamp and the fourth heating lamp.

[0013] Furthermore, the first heating power is configured as follows:

[0014] The power of the first heating lamp accounts for A% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for B% of the sum of the power of the third heating lamp and the fourth heating lamp. A and B satisfy: A is greater than 4B, and B is an integer ranging from 15 to 21.

[0015] Furthermore, A - 4B = 2.

[0016] Furthermore, the sum of the power of the first heating lamp and the second heating lamp is less than the sum of the power of the third heating lamp and the fourth heating lamp.

[0017] Furthermore, the sum of the power of the first heating lamp and the second heating lamp is 42%-46% of the sum of the power of the first heating lamp, the second heating lamp, the third heating lamp, and the fourth heating lamp.

[0018] Furthermore, the second heating power is configured as follows:

[0019] The power of the first heating lamp accounts for 60%-88% of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for 12%-24% of the power of the third heating lamp and the fourth heating lamp.

[0020] Furthermore, the second heating power is configured as follows:

[0021] The power of the first heating lamp accounts for C% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for D% of the sum of the power of the third heating lamp and the fourth heating lamp. C and D satisfy: C is greater than 4D, and D is an integer ranging from 15 to 21.

[0022] Furthermore, C-4D = 2.

[0023] Furthermore, the first heating power is different from the second heating power.

[0024] This invention provides a method for epitaxial growth of silicon wafers. In this method, the power of four heating lamps is adjusted to heat the silicon wafer to a preset temperature at different power levels, resulting in a first silicon wafer. The power used for the first silicon wafer that does not produce slip lines is selected as the first heating power. This first heating power, which prevents slip lines, is used during the pre-epitaxial growth heating stage. After heating the silicon wafer to the preset temperature at the first heating power, the power of the four heating lamps is adjusted to perform epitaxial growth on different silicon wafers at different power levels, resulting in a second silicon wafer. The power used for the second silicon wafer whose resistivity uniformity meets a preset uniformity is selected as the second heating power. This second heating power, which meets the preset uniformity, is used during the epitaxial growth stage. The silicon wafer epitaxial growth method provided in this invention ensures that the epitaxial wafer does not produce slip lines during growth and guarantees an epitaxial wafer with good resistivity uniformity. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the reaction chamber of an epitaxial furnace;

[0026] Figure 2 This is a graph showing the relationship between the resistivity of an epitaxial wafer and its deposition temperature.

[0027] Figure 3 This is a schematic diagram of the resistivity test points;

[0028] Figure label:

[0029] Upper quartz bell jar 1, lower quartz bell jar 2, heating lamp 3, base support rod 4, fixing component 5, silicon wafer support rod 6, mounting component 7, base 8, preheating ring 9. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0032] The following is in conjunction with the appendix Figures 1 to 3 As shown, the material processing method and system provided in this application are described in detail through specific embodiments and application scenarios.

[0033] In a first aspect, the present invention provides a method for epitaxial growth of silicon wafers, comprising:

[0034] The first heating power and the second heating power of the silicon wafer epitaxial growth stage are determined; in the heating stage before silicon wafer epitaxial growth, the silicon wafer to be processed is heated to a preset temperature under the first heating power; in the silicon wafer epitaxial growth stage, the silicon wafer to be processed is subjected to epitaxial growth under the second heating power.

[0035] The determination of the first heating power during the preheating stage before silicon wafer epitaxial growth and the second heating power during silicon wafer epitaxial growth includes:

[0036] A silicon wafer is placed in a reaction chamber, wherein a heating assembly is provided in the reaction chamber. The silicon wafer has a central region and an outer peripheral region. The heating assembly includes a first heating lamp for heating the central region of the upper surface of the silicon wafer, a second heating lamp for heating the outer peripheral region of the upper surface of the silicon wafer, a third heating lamp for heating the central region of the lower surface of the silicon wafer, and a fourth heating lamp for heating the outer peripheral region of the lower surface of the silicon wafer. The power of the heating assembly is adjusted, and different silicon wafers are selected and heated to a preset temperature at different power levels to obtain multiple first silicon wafers. The power corresponding to the first silicon wafer that does not produce slip lines is determined as the first heating power. A silicon wafer is heated to the preset temperature at the first heating power, and then the power of the heating lamps is adjusted to perform epitaxial growth on different silicon wafers at different power levels to obtain multiple second silicon wafers. The power corresponding to the second silicon wafer whose resistivity uniformity meets the preset uniformity is determined as the second heating power.

[0037] First, combine with the appendix Figure 1 This invention introduces the equipment used for silicon wafer growth—the epitaxial furnace. Figure 1 This is a schematic diagram of the epitaxial furnace reaction chamber. It can be seen that the epitaxial furnace includes an upper quartz bell jar 1, a lower quartz bell jar 2, an air inlet, an exhaust outlet, and mounting components 7. The internal structure of the epitaxial furnace includes: a base 8 for placing silicon wafers, a base support rod 4, a fixing component 5, a silicon wafer support rod 6, and a preheating ring 9. The base support rod 4 serves to fix the base 8 and drive its rotation, ensuring uniform epitaxial growth on the substrate. Outside the upper quartz bell jar 1 and the lower quartz bell jar 2, heating lamps 3 are installed to provide reaction energy. The heating lamps 3 provide heat to the reaction through thermal radiation. Generally, the heating lamp 3 can be a halogen lamp, which includes two groups: top and bottom (top being the upper lamp group and bottom being the lower lamp group). Further, each of the top and bottom groups contains two parts acting on the inner and outer regions (inner being the central region and outer being the peripheral region). During power setting, the power of the lamp group in these four regions needs to be set individually. In this invention, to distinguish between the top and bottom groups, and the two parts within each group acting on the inner and outer regions, they are respectively designated as the first heating lamp, the second heating lamp, the third heating lamp, and the fourth heating lamp. Specifically, top inner is the first heating lamp, top outer is the second heating lamp, bottom inner is the third heating lamp, and bottom outer is the fourth heating lamp.

[0038] The resistivity of the epitaxial layer of a silicon wafer is mainly related to the epitaxial growth temperature, such as Figure 2As shown, the higher the epitaxial growth temperature, the lower the resistivity. The resistivity uniformity of the epitaxial wafer is a crucial indicator of the epitaxial layer's performance. Poor resistivity uniformity can cause problems at the customer's end, affecting device yield. Generally, the measurement method for epitaxial layer resistivity uniformity varies depending on customer requirements. It is typically calculated by testing the resistivity values ​​at 5 or 9 points on the silicon wafer. For ease of explanation, we will use the common 9PEE10 method. 9PEE10 is a common resistivity measurement point system. 9P stands for 9 points, meaning one point at the center, four points at R / 2, and four points at the edge. EE10 means edge removal, referring to the outermost point on the silicon wafer, located 10mm from the wafer edge. Figure 3 As shown in the figure. The maximum resistivity value of the 9 test points is denoted as R_max, and the minimum resistivity value is denoted as R_min. The resistivity uniformity is calculated as (R_max-R_min) / (R_max+R_min)x100%.

[0039] The inventors of this invention discovered through research that slip lines are mainly caused by uneven temperature during the pre-epitaxial growth heating process. Therefore, simply changing the power of epitaxial growth will prevent slip lines from forming. Based on this research, the inventors proposed a method for selecting the power of heating lamps for silicon wafer growth. The method includes: placing a silicon wafer in a reaction chamber; wherein heating lamps are provided in the reaction chamber, and the silicon wafer has a central region and an outer peripheral region. The heating lamps include a first heating lamp for heating the central region of the upper surface of the silicon wafer, a second heating lamp for heating the outer peripheral region of the upper surface of the silicon wafer, a third heating lamp for heating the central region of the lower surface of the silicon wafer, and a fourth heating lamp for heating the outer peripheral region of the lower surface of the silicon wafer. The power of the four heating lamps is adjusted to heat the silicon wafer to a preset temperature at different power levels to obtain a first silicon wafer; the power used for the first silicon wafer that does not produce slip lines is selected as the first heating power. This determines the first heating power that will not produce slip lines, and the first heating power is selected during the pre-epitaxial growth heating stage. After heating the silicon wafer to a preset temperature under a first heating power, the power of the four heating lamps is adjusted to perform epitaxial growth on different silicon wafers at different power levels to obtain a second silicon wafer. The power used for the second silicon wafer with resistivity uniformity conforming to a preset uniformity is selected as the second heating power. Thus, the second heating power with resistivity uniformity conforming to the preset uniformity is determined, and this second heating power is used in the epitaxial growth stage. The silicon wafer epitaxial growth method provided in this invention can ensure that the epitaxial wafer does not produce slip lines during the growth process and can also ensure that an epitaxial wafer with good resistivity uniformity is obtained.

[0040] According to some embodiments of the present invention, the first heating power is configured such that the power of the first heating lamp accounts for 60%-88% of the sum of the power of the first heating lamp and the second heating lamp; and the power of the third heating lamp accounts for 12%-24% of the sum of the power of the third heating lamp and the fourth heating lamp.

[0041] According to some embodiments of the present invention, the first heating power is configured such that: the power of the first heating lamp accounts for A% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for B% of the sum of the power of the third heating lamp and the fourth heating lamp, and A and B satisfy: A is greater than 4B, and B is an integer ranging from 15 to 21.

[0042] According to some embodiments of the present invention, A-4B = 2.

[0043] According to some embodiments of the present invention, the sum of the power of the first heating lamp and the second heating lamp is less than the sum of the power of the third heating lamp and the fourth heating lamp.

[0044] According to some embodiments of the present invention, the sum of the power of the first heating lamp and the second heating lamp is 42%-46% of the sum of the power of the first heating lamp, the second heating lamp, the third heating lamp and the fourth heating lamp.

[0045] The inventors of this invention discovered through experiments that the first heating power should satisfy the following relationship: the power of the first heating lamp accounts for 60%-88% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for 12%-24% of the sum of the power of the third heating lamp and the fourth heating lamp. Further, the power of the first heating lamp accounts for A% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for B% of the sum of the power of the third heating lamp and the fourth heating lamp. A and B satisfy: A is greater than 4B, and B is 15-21. More preferably, A-4B = 2, and B is an integer between 15 and 21. For example, if B is 18, then A is 74, meaning the power of the first heating lamp accounts for 74% of the sum of the power of the first and second heating lamps (top inner accounts for 74% of the total top power, top outer accounts for 26% of the total top power); the power of the third heating lamp accounts for 18% of the sum of the power of the third and fourth heating lamps (bottom inner accounts for 18% of the total bottom power, bottom outer accounts for 82% of the total bottom power). Simultaneously, the first heating power also satisfies the following condition: the sum of the power of the first and second heating lamps is 42%-46% of the sum of the power of the first, second, third, and fourth heating lamps. For example, the sum of the power of the first and second heating lamps is 44% of the sum of the power of the first, second, third, and fourth heating lamps (i.e., top power accounts for 44% of the total power).

[0046] According to some embodiments of the present invention, the second heating power is configured such that the power of the first heating lamp accounts for 60%-88% of the power of the first heating lamp and the second heating lamp; and the power of the third heating lamp accounts for 12%-24% of the power of the third heating lamp and the fourth heating lamp.

[0047] According to some embodiments of the present invention, the second heating power is configured such that: the power of the first heating lamp accounts for C% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for D% of the sum of the power of the third heating lamp and the fourth heating lamp, and C and D satisfy: C is greater than 4D, and D is an integer ranging from 15 to 21.

[0048] According to some embodiments of the present invention, C-4D = 2.

[0049] According to some embodiments of the present invention, the first heating power is different from the second heating power.

[0050] The inventors of this invention discovered through experiments that the second heating power should satisfy the following relationship: the power of the first heating lamp accounts for 60%-88% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for 12%-24% of the sum of the power of the third heating lamp and the fourth heating lamp. Further, the power of the first heating lamp accounts for C% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for D% of the sum of the power of the third heating lamp and the fourth heating lamp. C and D satisfy: C is greater than 4D, and D is 15-21. More preferably, C-4D=2, and D is an integer between 15 and 21. For example, if D is 16, then C is 66, meaning the power of the first heating lamp accounts for 66% of the sum of the power of the first heating lamp and the second heating lamp (top inner accounts for 66% of the total top power, and top outer accounts for 34% of the total top power); the power of the third heating lamp accounts for 16% of the sum of the power of the third heating lamp and the fourth heating lamp (bottom inner accounts for 16% of the total bottom power, and bottom outer accounts for 84% of the total bottom power).

[0051] Example 1

[0052] (1) Place the silicon wafer in the reaction chamber of the epitaxial furnace and keep hydrogen gas flowing through it. Perform epitaxial growth using different power distributions. For example, set the first heating power to 56, meaning the bottom power accounts for 56% of the total power, and the top power accounts for 44% of the total power. The top inner and bottom inner regions are 62 / 15, 66 / 16, 70 / 17, 74 / 18, 78 / 19, 82 / 20, and 86 / 21, respectively. After epitaxial growth, confirm the slip. If there are no slip lines for 70 / 17, 74 / 18, and 78 / 19, select the center condition 74 / 18 as the power for baking and heating. That is, the power of the top inner accounts for 74% of the total top power, and 18 means the power of the bottom inner accounts for 18% of the total bottom power. In other words, the sum of the power of the first heating lamp and the second heating lamp is 44% of the sum of the power of the first heating lamp, the second heating lamp, the third heating lamp, and the fourth heating lamp. Meanwhile, the power of the first heating lamp accounts for 74% of the sum of the power of the first and second heating lamps; the power of the third heating lamp accounts for 18% of the sum of the power of the third and fourth heating lamps. Heating for 80 seconds brings the temperature to 1120℃.

[0053] (2) The wafer is baked at 1120℃ for 40 seconds, followed by etching with HCl gas at 1120℃ for 10 seconds. After etching, a purging process is performed, followed by the introduction of SiHCl3 and B2H6 gases for deposition and growth. During this process, different silicon wafers are heated at different power levels, namely 62 / 15, 66 / 16, 70 / 17, 74 / 18, 78 / 19, 82 / 20, and 86 / 21. Wherein, 62 / 15 refers to the power of the first heating lamp being 62% of the sum of the power of the first and second heating lamps; and the power of the third heating lamp being 15% of the sum of the power of the third and fourth heating lamps. 66 / 16 refers to the power of the first heating lamp being 66% of the sum of the power of the first and second heating lamps; and the power of the third heating lamp being 16% of the sum of the power of the third and fourth heating lamps. Similarly, 86 / 21 means that the power of the first heating lamp accounts for 86% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for 21% of the sum of the power of the third heating lamp and the fourth heating lamp. The deposition growth time is 150 seconds. After growth is completed, the wafer is purged, cooled, and its resistivity is tested.

[0054] The power with the best resistivity uniformity was found to be 82 / 20. Therefore, the optimal heating power in this embodiment is 74 / 18, and the optimal heating power during growth is 82 / 20.

[0055] Example 2

[0056] (1) Place the silicon wafer in the reaction chamber of the epitaxial furnace and keep hydrogen gas flowing through it. Perform epitaxial growth using different power distributions. For example, set the first heating power to 56, meaning the bottom power accounts for 56% of the total power, and the top power accounts for 44% of the total power. The top inner and bottom inner regions are 62 / 15, 66 / 16, 70 / 17, 74 / 18, 78 / 19, 82 / 20, and 86 / 21, respectively. After epitaxial growth, check the slip. If there is no slip line in 70 / 17, 74 / 18, 78 / 19, and 82 / 20, select the center condition 76 / 18.5 as the power for baking and heating. That is, the power of the first heating lamp accounts for 78% of the sum of the power of the first and second heating lamps; the power of the third heating lamp accounts for 18.5% of the sum of the power of the third and fourth heating lamps. Heat for 120 seconds to reach a temperature of 1120℃.

[0057] (2) The silicon wafers were baked at 1120°C for 50 seconds, followed by etching with HCl gas at 1110°C for 15 seconds. After etching, the wafers were purged, and then SiHCl3 and B2H6 gases were introduced for deposition and growth. During this process, different silicon wafers were heated at different power levels: 62 / 15, 66 / 16, 70 / 17, 74 / 18, 78 / 19, 82 / 20, and 86 / 21. 62 / 15 refers to the power of the first heating lamp being 62% of the sum of the power of the first and second heating lamps, and the power of the third heating lamp being 15% of the sum of the power of the third and fourth heating lamps. 66 / 16 refers to the power of the first heating lamp being 66% of the sum of the power of the first and second heating lamps, and the power of the third heating lamp being 16% of the sum of the power of the third and fourth heating lamps. Similarly, 86 / 21 means that the power of the first heating lamp accounts for 86% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for 21% of the sum of the power of the third heating lamp and the fourth heating lamp. The deposition growth time is 170 seconds. After growth is completed, the wafer is purged, cooled, and its resistivity is tested.

[0058] The power with the best resistivity uniformity was found to be 72 / 17.5. Therefore, the optimal heating power in this embodiment is 76 / 18.5, and the optimal heating power during growth is 72 / 17.5.

[0059] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for epitaxial growth of silicon wafers, characterized in that, include: The first heating power and the second heating power of the silicon wafer epitaxial growth stage are determined; in the heating stage before silicon wafer epitaxial growth, the silicon wafer to be processed is heated to a preset temperature under the first heating power; in the silicon wafer epitaxial growth stage, the silicon wafer to be processed is subjected to epitaxial growth under the second heating power. The determination of the first heating power during the preheating stage before silicon wafer epitaxial growth and the second heating power during silicon wafer epitaxial growth includes: A silicon wafer is placed in a reaction chamber, wherein a heating assembly is provided in the reaction chamber, the silicon wafer has a central region and an outer peripheral region, and the heating assembly includes a first heating lamp for heating the central region of the upper surface of the silicon wafer, a second heating lamp for heating the outer peripheral region of the upper surface of the silicon wafer, a third heating lamp for heating the central region of the lower surface of the silicon wafer, and a fourth heating lamp for heating the outer peripheral region of the lower surface of the silicon wafer. Adjust the power of the heating component, select different silicon wafers, and heat the different silicon wafers to a preset temperature at different power levels to obtain multiple first silicon wafers; determine the power corresponding to the first silicon wafer that does not produce slip lines among the multiple first silicon wafers as the first heating power; A silicon wafer is heated to the preset temperature under the first heating power, and then the power of the heating lamp is adjusted to perform epitaxial growth on different silicon wafers under different power to obtain multiple second silicon wafers; the power corresponding to the second silicon wafer whose resistivity uniformity meets the preset uniformity is determined as the second heating power; The first heating power is configured such that: the power of the first heating lamp accounts for A% of the sum of the power of the first heating lamp and the second heating lamp; the power of the third heating lamp accounts for B% of the sum of the power of the third heating lamp and the fourth heating lamp. A and B satisfy: A is greater than 4B, and B is an integer ranging from 15 to 21; the sum of the power of the first heating lamp and the second heating lamp is less than the sum of the power of the third heating lamp and the fourth heating lamp.

2. The method according to claim 1, characterized in that, The first heating power is configured as follows: The power of the first heating lamp accounts for 60%-88% of the sum of the power of the first heating lamp and the second heating lamp; The power of the third heating lamp accounts for 12%-24% of the sum of the power of the third heating lamp and the fourth heating lamp.

3. The method according to claim 1, characterized in that, A-4B=2.

4. The method according to claim 1, characterized in that, The sum of the power of the first heating lamp and the second heating lamp is 42%-46% of the sum of the power of the first heating lamp, the second heating lamp, the third heating lamp and the fourth heating lamp.

5. The method according to claim 1, characterized in that, The second heating power is configured as follows: The power of the first heating lamp accounts for 60%-88% of the total power of the first heating lamp and the second heating lamp; The power of the third heating lamp accounts for 12%-24% of the power of the third heating lamp and the fourth heating lamp.

6. The method according to claim 1, characterized in that, The second heating power is configured as follows: The power of the first heating lamp accounts for C% of the sum of the power of the first heating lamp and the second heating lamp. The power of the third heating lamp is D% of the sum of the power of the third heating lamp and the fourth heating lamp. C and D satisfy: C is greater than 4D, and D is an integer ranging from 15 to 21.

7. The method according to claim 6, characterized in that, C-4D=2.

8. The method according to claim 1, characterized in that, The first heating power is different from the second heating power.

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