Method for solving epitaxial slip line problem by optimizing epitaxial pedestal

Abstract

The present application relates to a kind of methods for solving epitaxial slip line problem by optimizing epitaxial pedestal, the wafer epitaxial process technical field, including the following operating steps: first, the wafer epitaxial pedestal pocket with the depth greater than wafer thickness H is opened on epitaxial pedestal.Second, the center groove lower than the size T of wafer epitaxial pedestal pocket outer circle bottom is milled in the center of wafer epitaxial pedestal pocket.Third, then with wafer epitaxial pedestal pocket outer circle bottom as reference, pocket pedestal slope with the inclination C ° is processed, and the transition slope is communicated between pocket pedestal slope and center groove.Fourth, wafer is placed into wafer epitaxial pedestal pocket, in the process of gas deposition CVD epitaxial processing, reduce the radial temperature gradient of wafer in pocket in heating process, solve the problem of narrow epitaxial slip line window, avoid generating slip line.

Description

Technical Field

[0001] This invention relates to the field of wafer epitaxial process technology, and more specifically to a method for solving epitaxial slip line problems by optimizing the epitaxial substrate. Background Technology

[0002] The fundamental principles of chemical vapor deposition (CVD) involve reaction chemistry, thermodynamics, kinetics, transfer mechanisms, film growth phenomena, and reaction engineering. It primarily uses vapors such as metal vapors, volatile metal halides, hydrides, or organometallic compounds as raw materials, undergoing gas-phase thermal decomposition reactions, as well as reactions of two or more elements or compounds, followed by condensation to form materials in various forms. In CVD, the uniformity of the deposited film is extremely important, primarily influenced by the gas distribution within the furnace. CVD is an extremely complex chemical process, and the uniformity of the gas distribution significantly affects the deposition rate, film density, and film uniformity. Generally, uniformity in CVD is difficult to guarantee due to process factors such as gas flow fields. To improve coating uniformity, a graphite disk rotation process is typically employed, achieving stable production.

[0003] [Terminology Explanation]

[0004] CVD: Chemical vapor deposition refers to the method of synthesizing coatings or nanomaterials by reacting chemical gases or vapors on the surface of a substrate. It is the most widely used technology in the semiconductor industry for depositing a variety of materials, including a wide range of insulating materials, most metallic materials, and metal alloys.

[0005] During epitaxial growth, the heating substrate creates a reverse thermal gradient, resulting in a small temperature difference between the front and back sides of the wafer. This causes elastic bending, where the wafer bends into a shallow cup shape until heating ends. When cooled to room temperature, it returns to a flat shape. The range of the bow is approximately 5 to 50 micrometers depending on the temperature gradient. Normally, the warpage value in the wafer does not increase as a result. However, the bow shape causes the edges to no longer contact the substrate itself and become slightly cooler than the center. This radial thermal gradient is released through the formation of slip lines.

[0006] To address these issues, traditional poly tunes typically adjust the temperature compensation in the center region during epitaxial product debugging. However, due to hardware limitations, meeting the temperature window requirements for process debugging without slip lines often requires multiple corrections using traditional poly tunes, resulting in a narrow adjustable window of 3 to 6 degrees Celsius. This also wastes considerable time on window adjustments and leads to unnecessary material (wafer) waste.

[0007] Pocekt: a circular recess on the base of the middle finger in this utility model, one recess being a pocket. Summary of the Invention

[0008] This invention addresses the shortcomings of existing technologies by providing a method to solve the epitaxial slip line problem by optimizing the epitaxial substrate, reducing the radial temperature gradient of the wafer in the pocket during heating, and solving the problem of narrow epitaxial slip line windows.

[0009] The above-mentioned technical problems of the present invention are mainly solved by the following technical solutions:

[0010] A method for solving the epitaxial slip line problem by optimizing the epitaxial base includes the following steps:

[0011] Step 1: Create a wafer epitaxial substrate pocket on the epitaxial substrate with a depth greater than the wafer thickness H.

[0012] Step 2: Mill a central groove in the center of the wafer epitaxial substrate pocket that is lower than the bottom dimension T of the outer ring of the wafer epitaxial substrate pocket.

[0013] Step 3: Next, using the bottom of the outer ring of the wafer epitaxial substrate pocket as a reference, process a pocket base ramp with an inclination angle of C°. The pocket base ramp and the central groove are connected by a transition ramp.

[0014] Step 4: Place the wafer into the wafer epitaxial substrate pocket. During the vapor deposition (CVD) epitaxial process, this reduces the radial temperature gradient change of the wafer in the wafer epitaxial substrate pocket and avoids the formation of slip lines.

[0015] Preferably, the value of H is 0.333±0.03mm.

[0016] Preferably, the value of T is 0.21 mm to 0.23 mm.

[0017] Preferably, the tilt angle C° is between 2° and 2.2°.

[0018] Preferably, the transition slope has a circular ring structure, and the radial width dimension of the transition slope is D, with a value of 0.3 mm.

[0019] The present invention can achieve the following effects:

[0020] This invention provides a method for solving the epitaxial slip line problem by optimizing the epitaxial substrate. Compared with the prior art, it reduces the radial temperature gradient of the wafer in the pocket during the heating process and solves the problem of narrow epitaxial slip line window. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the present invention.

[0022] In the diagram: 1. Central groove; 2. Transition slope; 3. Wafer; 4. Pocket base slope; 5. Wafer epitaxial base pocket; 6. Epitaxial base. Detailed Implementation

[0023] The technical solution of the invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings.

[0024] Example: Figure 1 As shown, a method for solving the epitaxial slip line problem by optimizing the epitaxial base includes the following steps:

[0025] Step 1: Create a wafer epitaxial base pocket 5 on the epitaxial base 6 with a depth greater than the thickness H of the wafer 3. The value of H is 0.333 mm.

[0026] Step 2: Mill a central groove 1 in the center of the wafer epitaxial substrate pocket 5, which is lower than the bottom dimension T of the outer ring of the wafer epitaxial substrate pocket 5. The value of T is 0.22 mm.

[0027] Step 3: Next, using the bottom of the outer ring of the wafer epitaxial substrate pocket 5 as a reference, a pocket base ramp 4 with an inclination angle of C° is machined. The inclination angle C° is 2.1°. The pocket base ramp 4 and the central groove 1 are connected by a transition ramp 2. The transition ramp 2 has a circular ring structure, and the radial width dimension of the transition ramp 2 is D, which is 0.3mm.

[0028] Step 4: Place wafer 3 into wafer epitaxial substrate pocket 5. During the vapor deposition CVD epitaxial process, reduce the radial temperature gradient change of the wafer in wafer epitaxial substrate pocket 5 to avoid slip lines.

[0029] In summary, this method of optimizing the epitaxial substrate to solve the epitaxial slip line problem reduces the radial temperature gradient of the wafer in the pocket during heating, thus solving the problem of narrow epitaxial slip line windows.

[0030] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by those skilled in the art within the scope of the present invention are covered by the patent scope of the present invention.

Claims

1. A method for solving the epitaxial slip line problem by optimizing the epitaxial base, characterized in that... The following steps are included: Step 1: Create a wafer epitaxial base pocket (5) on the epitaxial base (6) with a depth greater than the thickness H of the wafer (3); the value of H is 0.333±0.03mm; Step 2: Mill a central groove (1) in the center of the wafer epitaxial substrate pocket (5) that is lower than the bottom dimension T of the outer ring of the wafer epitaxial substrate pocket (5); the value of T is 0.21 mm to 0.23 mm; Step 3: Next, based on the bottom of the outer ring of the wafer epitaxial base pocket (5), a pocket base ramp (4) with an inclination angle of C° is processed. The value of the inclination angle C° is 2° to 2.2°. The pocket base ramp (4) and the central groove (1) are connected by a transition ramp (2). Step 4: Place the wafer (3) into the wafer epitaxial substrate pocket (5) to reduce the radial temperature gradient change of the wafer in the wafer epitaxial substrate pocket (5) during the vapor deposition CVD epitaxial process and avoid the generation of slip lines.

2. The method for solving the epitaxial slip line problem by optimizing the epitaxial base according to claim 1, characterized in that: The transition slope (2) has a circular structure and the radial width dimension of the transition slope (2) is D, and the value of D is 0.3 mm.

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