Semiconductor device and method of manufacturing the same
By using a third insulating layer for support during the polishing process, the problem of high on-resistance in semiconductor devices was solved, resulting in smaller substrate thickness and lower on-resistance, thus improving the device's conduction performance and heat dissipation efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ARK SEMICON CORP LTD
- Filing Date
- 2022-12-29
- Publication Date
- 2026-07-24
AI Technical Summary
In the existing technology, the on-resistance of semiconductor devices is relatively large, making it difficult to effectively reduce the substrate thickness through traditional polishing methods, resulting in high conduction losses.
By using a third insulating layer as a support during the grinding process, an insulating layer covering the metal part is formed, ensuring that the substrate surface is flush with the metal layer, reducing substrate deformation and breakage, and thus reducing the substrate thickness.
It effectively reduces the on-resistance and parasitic inductance of semiconductor devices, thereby improving the conduction performance and heat dissipation of the devices.
Smart Images
Figure CN116053152B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] The higher the on-resistance (Rdson) of a semiconductor device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), the greater the conduction loss of the semiconductor device. Summary of the Invention
[0003] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate structure, the substrate structure comprising: a printed circuit board (PCB), the PCB comprising a stack having at least one opening, the stack comprising a first insulating layer and a first metal layer stacked along a first direction, at least one die located in the at least one opening, each die comprising a substrate and a first electrode, the substrate having a first surface and a second surface opposite to each other in the first direction, the first electrode located on the first surface, and a second insulating layer filling the at least one opening and covering the second surface and the side of the first insulating layer away from the first metal layer; forming at least one metal portion, the at least one metal portion comprising a first metal portion in contact with the first electrode; forming a third insulating layer covering the at least one metal portion; and, supported by the third insulating layer, performing polishing along the first direction from the side of the second insulating layer away from the third insulating layer, such that the polished second surface and the side of the first metal layer away from the third insulating layer are flush.
[0004] In some embodiments, the grinding stops at the side where the first metal layer contacts the first insulating layer.
[0005] In some embodiments, after the grinding, the thickness of each die is greater than or equal to 10 micrometers and less than or equal to 30 micrometers.
[0006] In some embodiments, after the grinding, the thickness of the substrate is greater than or equal to 5 micrometers and less than 10 micrometers.
[0007] In some embodiments, the thickness of each of the at least one metal part is greater than or equal to 30 micrometers and less than or equal to 300 micrometers.
[0008] In some embodiments, the method further includes: after the grinding, forming a second metal layer electrically coupled to the second surface, the second metal layer serving as a second electrode of at least one die.
[0009] In some embodiments, the at least one metal portion further includes a second metal portion in contact with the first metal layer; the second metal layer is also electrically coupled to the first metal layer to electrically couple the second metal portion.
[0010] In some embodiments, each die further includes a gate located on the first surface; the at least one metal portion further includes a third metal portion in contact with the gate; the first metal portion, the second metal portion, and the third metal portion are spaced apart from each other.
[0011] In some embodiments, the at least one metal portion further includes a second metal portion in contact with the first metal layer, and the method further includes: after the grinding, forming a third metal layer electrically coupled to the second surface on the second surface, wherein the third metal layer is also electrically coupled to the first metal layer to electrically couple the second metal portion, and the third metal layer is spaced apart from the second metal layer and serves as the gate of at least one die.
[0012] In some embodiments, the method further includes removing a portion of the third insulating layer to expose the first metal portion, the second metal portion, and the third metal portion.
[0013] In some embodiments, the at least one die includes a plurality of dies, and the method further includes: locating the PCB according to a cutting mark, and cutting the second insulating layer and the third insulating layer along the first direction to separate the plurality of dies, wherein the cutting mark is an exposed portion of the first metal layer that is not covered by the second metal layer after the grinding.
[0014] In some embodiments, providing the substrate structure includes: fixing the at least one die and the PCB to one side of a fixture; forming a second insulating layer on the same side of the fixture; and removing the fixture to expose the first electrode and the first metal layer.
[0015] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a die including a substrate and a first electrode, the substrate having a first surface and a second surface opposite each other in a first direction, the first electrode being located on the first surface; a first metal layer; a second insulating layer including a first portion located between the die and the first metal layer in a second direction, the second direction being perpendicular to the first direction; and at least one metal portion including a first metal portion in contact with the first electrode; wherein the side of the first metal layer away from the first metal portion in the first direction is flush with the second surface.
[0016] In some embodiments, the side of the second insulating layer away from the first metal portion in the first direction is flush with the second surface.
[0017] In some embodiments, the thickness of the die is greater than or equal to 10 micrometers and less than or equal to 30 micrometers.
[0018] In some embodiments, the thickness of the substrate is greater than or equal to 5 micrometers and less than 10 micrometers.
[0019] In some embodiments, the thickness of each of the at least one metal part is greater than or equal to 30 micrometers and less than or equal to 300 micrometers.
[0020] In some embodiments, the device further includes: a second metal layer located on the second surface and electrically coupled to the second surface, the second metal layer serving as a second electrode of the die.
[0021] In some embodiments, the at least one metal portion further includes a second metal portion in contact with the first metal layer; the second metal layer is also electrically coupled to the first metal layer to electrically couple the second metal portion.
[0022] In some embodiments, the die further includes a gate located on the first surface; the at least one metal portion further includes a third metal portion in contact with the gate; the first metal portion, the second metal portion, and the third metal portion are spaced apart from each other.
[0023] In some embodiments, the at least one metal portion further includes a second metal portion in contact with the first metal layer, and the device further includes: a third metal layer located on the second surface and electrically coupled to the second surface, wherein the third metal layer is also electrically coupled to the first metal layer to electrically couple the second metal portion, and the third metal layer is spaced apart from the second metal layer and serves as the gate of the die.
[0024] In some embodiments, the device further includes a third insulating layer, wherein the first metal portion, the second metal portion, and the third metal portion are spaced apart by the third insulating layer.
[0025] In some embodiments, the device further includes: a fourth metal layer located on the side of the second metal layer away from the third insulating layer; a fifth metal layer located on the side of the first metal portion away from the first electrode; a sixth metal layer located on the side of the second metal portion away from the first metal layer; and a seventh metal layer located on the side of the third metal portion away from the gate.
[0026] In some embodiments, the substrate is made of silicon or silicon carbide.
[0027] According to another aspect of the present disclosure, a battery management system is provided, including the semiconductor device described in any of the above embodiments.
[0028] In the semiconductor device manufacturing method provided in this disclosure, by forming at least one metal portion and forming a third insulating layer covering the at least one metal portion, the third insulating layer can be used as a support during the polishing process, making the second surface of the polished substrate flush with the side of the first metal layer in the PCB away from the third insulating layer. Thus, since the third insulating layer has a certain thickness, it can support the substrate structure during the polishing process, preventing deformation or breakage of the substrate structure. Therefore, this method can effectively reduce the thickness of the polished substrate, thereby effectively reducing the on-resistance of the semiconductor device.
[0029] Furthermore, when the substrate thickness is small, the distance between the first electrode and the other electrode, for example, the first electrode being the source and the other electrode being the drain, is also small, thereby reducing the parasitic inductance between the first electrode and the other electrode.
[0030] Other features, aspects, and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0031] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.
[0032] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:
[0033] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
[0034] Figures 2A-2D These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
[0035] Figures 3A-3H These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to other embodiments of this disclosure;
[0036] Figures 4-7 These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
[0037] Figure 8A This is a top view of a semiconductor device before dicing according to some embodiments of the present disclosure;
[0038] Figures 8B-8CThis is a top view of a diced semiconductor device according to some embodiments of the present disclosure;
[0039] Figure 8D This is a bottom view of a cut semiconductor device according to some embodiments of the present disclosure;
[0040] Figure 9 This is a cross-sectional view after the formation of the third metal layer 1161 in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
[0041] Figure 10 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
[0042] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not necessarily drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation
[0043] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values set forth in these embodiments should be interpreted as exemplary only and not as limiting.
[0044] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.
[0045] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.
[0046] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.
[0047] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0048] The on-resistance of a semiconductor device is positively correlated with the thickness of the substrate in the semiconductor device. That is, the smaller the substrate thickness, the smaller the on-resistance of the semiconductor device. Therefore, in order to obtain a semiconductor device with a smaller on-resistance, the substrate thickness needs to be reduced as much as possible during the manufacturing process of the semiconductor device.
[0049] In related technologies, during the manufacturing process of semiconductor devices, a substrate is first polished using a grinding wheel to reduce its thickness before other components of the semiconductor device are formed. However, since the thinner the substrate is polished, the more easily it deforms, this method cannot effectively reduce the thickness of the polished substrate. For example, it can only reduce the substrate thickness to 36.9 micrometers, resulting in a relatively high on-resistance of the semiconductor device.
[0050] In view of this, the present disclosure proposes the following solution, which can effectively reduce the thickness of the substrate, thereby reducing the on-resistance of the semiconductor device.
[0051] According to one aspect of the embodiments of this disclosure, a method for manufacturing a semiconductor device is provided.
[0052] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this disclosure. For example... Figure 1 As shown, the method for manufacturing a semiconductor device includes steps 102 to 108.
[0053] To facilitate understanding, the following will be combined with Figures 2A-2D right Figure 1 The manufacturing method of the semiconductor device shown will be described. Figures 2A-2D These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.
[0054] In step 102, a substrate structure 1100 is provided.
[0055] Here, as Figure 2AAs shown, the substrate structure 1100 includes a printed circuit board (PCB) 1110. The PCB 1110 includes a stack having at least one opening V1 (two openings V1 are schematically shown in FIG. 2), the stack including a first insulating layer 1111 and a first metal layer 1112 stacked along a first direction Y.
[0056] The substrate structure 1100 also includes at least one die 1120 located in at least one opening V1 (two dies 1120 are schematically shown in FIG2). For example, at least one die 1120 may be located in at least one opening V1 in a one-to-one correspondence. In some embodiments, the die 1120 may be a field effect transistor (FET), such as a MOSFET or a junction field effect transistor (JFET).
[0057] Each die 1120 includes a substrate 1121 and a first electrode E1. The substrate 1121 has a first surface 1122 and a second surface 1123 opposite to each other in a first direction Y, wherein the first electrode E1 is located on the first surface 1122. In some embodiments, the first electrode E1 may be a source or a drain. In some embodiments, the material of the substrate 1121 may be silicon or silicon carbide.
[0058] The substrate structure 1100 further includes a second insulating layer 1130 that fills at least one opening V1. The second insulating layer 1130 covers the second surface 1123 and the side of the first insulating layer 1111 away from the first metal layer 1112. In some embodiments, the material of the second insulating layer 1130 may be a flexible insulating material. For example, the material of the second insulating layer 1130 may be one of epoxy resin adhesive, molding compound, and underfill.
[0059] In step 104, at least one metal part is formed.
[0060] Please see here. Figure 2B At least one metal portion includes a first metal portion 1141 that contacts the first electrode E1. In other embodiments, at least one metal portion may also include other metal portions, which will be further described below.
[0061] In step 106, a third insulating layer 1150 is formed covering at least one metal portion.
[0062] In some embodiments, see Figure 2CThe material of the third insulating layer 1150 can be a flexible insulating material. For example, the material of the third insulating layer 1150 can be one of epoxy resin, molding compound, and underfill adhesive.
[0063] In step 108, with the third insulating layer 1150 as a support, grinding is performed along the first direction Y from the side of the second insulating layer 1130 away from the third insulating layer 1150, so that the ground second surface 1123 and the side of the first metal layer 1112 away from the third insulating layer 1150 are flush.
[0064] In some embodiments, see Figure 2D After grinding is performed with the third insulating layer 1150 as a support, the second insulating layer 1130 and the first insulating layer 1111, located above the first metal layer 1112, are removed. Grinding can be stopped once the first metal layer 1112 is exposed. The thickness of the first metal layer 1112 after grinding can be less than or equal to its thickness before grinding. For example, the thickness of the first metal layer 1112 after grinding can be approximately 15 micrometers.
[0065] In the above embodiments, by forming at least one metal portion and a third insulating layer 1150 covering the at least one metal portion, the third insulating layer 1150 can be used as a support during the polishing process, making the second surface 1123 of the polished substrate 1121 flush with the side of the first metal layer 1112 in the PCB away from the third insulating layer 1150. Thus, since the third insulating layer 1150 has a certain thickness, it can support the substrate structure 1100 during the polishing process, preventing deformation or breakage of the substrate structure 1100. Therefore, this method can effectively reduce the thickness of the polished substrate, thereby effectively reducing the on-resistance of the semiconductor device.
[0066] Furthermore, when the thickness of the substrate 1121 is small, the distance between the first electrode E1 and the other electrode (e.g., the first electrode E1 is the source and the other electrode is the drain) is also small, thereby reducing the parasitic inductance between the first electrode E1 and the other electrode.
[0067] In some embodiments, grinding can stop at the side of the first metal layer 1112 that contacts the first insulating layer 1111. In this case, after grinding, the thickness of each die 1120 is the same as the thickness of the first metal layer 1112. For example, the thickness of the first metal layer 1112 can be set in advance according to the target thickness required for the die 1120, and then grinding can be performed with the first metal layer 1112 as the grinding stop layer, which can more accurately control the thickness of the ground die 1120 to the required target thickness. In this way, the thickness of the ground die can be accurately controlled by setting the thickness of the first metal layer.
[0068] In some embodiments, after polishing, the thickness of each die 1120 can be greater than or equal to 10 micrometers and less than or equal to 30 micrometers. That is, the semiconductor device manufacturing method provided by the embodiments of this disclosure can control the substrate thickness to less than or equal to 30 micrometers, which can further reduce the on-resistance of the semiconductor device compared to the related art which can only make the substrate thickness as small as 36.9 micrometers.
[0069] In some embodiments, after polishing, the thickness of the substrate 1121 can be greater than or equal to 5 micrometers and less than 10 micrometers. That is, the semiconductor device manufacturing method provided in this disclosure can achieve a minimum substrate thickness of 5 micrometers without affecting the function of the die, thereby further reducing the on-resistance of the semiconductor device.
[0070] In some cases, see Figure 3C Each die 1120 may also include a gate G located on the first surface 1122. That is, the electrode located on the first surface 1122 of the substrate 1121 of each die 1120 may include a first electrode E1 and a gate G.
[0071] In other cases, the electrodes located on the first surface 1122 of the substrate 1121 of each die 1120 may consist only of the first electrode E1.
[0072] In some embodiments, after polishing, different processes can be performed depending on the electrode configuration of the first surface 1122 of the substrate 1121 of each die 1120. This will be further explained later.
[0073] The following example uses the electrodes on the first surface 1122 of the substrate 1121 of each die 1120, including the first electrode E1 and the gate G, as an example. Figures 3A-3H The cross-sectional view shown further illustrates the semiconductor manufacturing method provided in the embodiments of this disclosure.
[0074] Please refer to Figures 3A-3E As one implementation of step 102, the substrate structure 1100 can be provided according to the steps shown in S1 to S3 below.
[0075] S1: Secure at least one die 1120 and PCB 1110 to one side of the fastener 1180.
[0076] For example, such as Figure 3A As shown, PCB 1110 is provided first. Figure 3A Two openings V1 on PCB 1110 are schematically shown.
[0077] Then, as Figure 3BAs shown, PCB 1110 is fixed to one side of fastener 1180.
[0078] In some embodiments, the fastener 1180 may be an adhesive tape, such as polyimide (PI) tape.
[0079] After that, as Figure 3C As shown, at least one die 1120 is placed in at least one opening V1, and each die 1120 is also fixed to the side of the fastener 1180 where the PCB 1110 is fixed. Figure 3C Two dies 1120 are schematically shown.
[0080] As one implementation, at least one die 1120 can be placed in at least one opening V1 in a one-to-one correspondence.
[0081] S2: Form a second insulating layer 1130 on one side of the fastener 1180.
[0082] For example, such as Figure 3D As shown, as one implementation, a first fluid material filling at least one opening V1 can be formed on the side of the fastener 1180 where the PCB 1110 and at least one die 1120 are fixed, and the first fluid material can be cured to form a second insulating layer 1130. For example, the first fluid material can be epoxy resin.
[0083] S3: Remove the fastener 1180 to expose the first electrode E1 and the first metal layer 1112.
[0084] For example, such as Figure 3E As shown, after removing the retainer 1180, the side of the first electrode E1 away from the substrate 1121 and the side of the first metal layer 1112 away from the first insulating layer 1111 can be exposed.
[0085] Thus, substrate structure 1100 can be provided.
[0086] It should be understood that in other implementations of step 102, the aforementioned steps may be performed in a different order to provide substrate structure 1100.
[0087] Please refer to Figure 3F After providing the substrate structure 1100, at least one metal portion can be formed.
[0088] In some embodiments, at least one metal portion may include a first metal portion 1141 that is in contact with the first electrode E1.
[0089] In other embodiments, at least one metal portion may include a first metal portion 1141 and a second metal portion 1142 in contact with the first metal layer 1112. The first metal portion 1141 and the second metal portion 1142 are spaced apart.
[0090] In some other embodiments, at least one metal portion may include a first metal portion 1141, a second metal portion 1142, and a third metal portion 1143 that contacts the gate G. The first metal portion 1141, the second metal portion 1142, and the third metal portion 1143 are spaced apart from each other.
[0091] Next, please refer to Figure 3G A third insulating layer 1150 can be formed to cover at least one metal part.
[0092] As one implementation, a second fluid material can be formed to cover at least one metal portion, and the second fluid material can be cured to form a third insulating layer 1150. For example, the second fluid material can be an epoxy resin adhesive. If a second metal portion 1142 and a third metal portion 1143 are also formed, the third insulating layer 1150 can cover the first metal portion 1141, the second metal portion 1142, and the third metal portion 1143.
[0093] Then, with the third insulating layer 1150 as a support, grinding can be performed along the first direction Y from the side of the second insulating layer 1130 away from the third insulating layer 1150, so that the second surface 1123 and the side of the first metal layer 1112 away from the third insulating layer 1150 are flush.
[0094] For example, please refer to Figure 3H The grinding can stop on the side where the first metal layer 1112 contacts the first insulating layer 1111.
[0095] In this way, semiconductor devices with low on-resistance can be manufactured.
[0096] In some embodiments, where at least one die 1120 comprises a plurality of dies 1120, the second insulating layer 1130 and the third insulating layer 1150 can be cut along the first direction Y using the exposed portion 1112a of the first metal layer 1112 after grinding as a cutting mark, thereby separating the plurality of dies 1120. This will be further explained below.
[0097] It should be understood that, where the electrode on the first surface 1122 of the substrate 1121 of each die 1120 includes only the first electrode E1, it can be performed according to... Figures 3A-3H Semiconductor devices are manufactured in a similar manner.
[0098] In some embodiments, the thickness of each metal portion in at least one metal portion is greater than or equal to 30 micrometers and less than or equal to 300 micrometers. This allows for better support of the substrate during the polishing process, more effectively reducing the thickness of the polished substrate, and consequently, more effectively reducing the on-resistance of the die, thereby further reducing the power consumption of the semiconductor device.
[0099] Next, we will first describe, with reference to some embodiments, the different processes that can be performed after polishing when the electrodes on the first surface 1122 of the substrate 1121 of each die 1120 include the first electrode E1 and the gate G.
[0100] Please see Figure 4 , Figure 4 Two dies 1120 are schematically shown. With the electrodes on the first surface 1122 of the substrate 1121 of each die 1120 including a first electrode E1 and a gate G, a second metal layer 1160 electrically coupled to the second surface 1123 can be formed on the second surface 1123 of the substrate 1121 after polishing. Here, the second metal layer 1160 can serve as a second electrode for at least one die 1120. For example, the first electrode E1 can be the source, and the second electrode can be the drain; or, for another example, the first electrode E1 can be the drain, and the second electrode can be the source.
[0101] In some embodiments, at least one metal portion may include a spaced-apart first metal portion 1141 and second metal portion 1142, and the second metal layer 1160 is also electrically coupled to the first metal layer 1112 to electrically couple the second metal portion 1142.
[0102] Then, a portion of the third insulating layer 1150 can be removed to expose the first metal portion 1141 and the second metal portion 1142.
[0103] In other embodiments, please continue to refer to Figure 4 At least one metal portion may include a first metal portion 1141, a second metal portion 1142, and a third metal portion 1143 that contacts the gate G. Furthermore, the first metal portion 1141, the second metal portion 1142, and the third metal portion 1143 are spaced apart from each other. The second metal layer 1160 may also be electrically coupled to the first metal layer 1112 to electrically couple the second metal portion 1142. In this way, the first metal portion 1141 that contacts the first electrode E1, the second metal portion 1142 that is electrically coupled to the second metal layer 1160, and the third metal portion 1143 that contacts the gate G can all be located on the same surface, eliminating the need for re-encapsulation and improving usability.
[0104] Please see below. Figure 5A portion of the third insulating layer 1150 can be removed to expose the first metal portion 1141, the second metal portion 1142, and the third metal portion 1143.
[0105] In some embodiments, the first metal portion 1141, the second metal portion 1142, and the third metal portion 1143 can be formed in the same patterning process, i.e., by patterning the same material layer.
[0106] In some embodiments, see Figure 6 Furthermore, a fourth metal layer 1170, a fifth metal layer 1171, a sixth metal layer 1172, and a seventh metal layer 1173 can also be formed. The fourth metal layer 1170 can be located on the side of the second metal layer 1160 away from the third insulating layer 1150; the fifth metal layer 1171 can be located on the side of the first metal portion 1141 away from the first electrode E1; the sixth metal layer 1172 can be located on the side of the second metal portion 1142 away from the first metal layer 1112; and the seventh metal layer 1173 can be located on the side of the third metal portion 1143 away from the gate G.
[0107] As some implementations, the fourth metal layer 1170, the fifth metal layer 1171, the sixth metal layer 1172, and the seventh metal layer 1173 can be made of the same material, for example, nickel-gold.
[0108] In this way, the manufactured semiconductor device can dissipate heat from both sides through two surfaces opposite each other along the first direction Y, resulting in better heat dissipation.
[0109] In some embodiments, where at least one die 1120 includes a plurality of dies 1120, the PCB 1110 can be positioned according to a cutting mark, and the second insulating layer 1130 and the third insulating layer 1150 can be cut along the first direction Y to separate the plurality of dies 1120, wherein the cutting mark is the exposed portion 1112a of the first metal layer 1112 that is not covered by the second metal layer 1160 after grinding.
[0110] For example, see Figure 6 and Figure 7 The cutting machine tool can position the PCB1110 according to the cutting mark to determine the cutting line, and cut the second insulating layer 1130 and the third insulating layer 1150 along the first direction Y according to the determined cutting line, thereby separating multiple dies 1120. Figure 7 It is along Figure 6 The diagram shows a cross-sectional view of the multiple cores 1120 separated after the cutting line is shown.
[0111] To facilitate understanding, the following will be combined with Figures 8A-8D The above cutting process will be further explained.
[0112] Figure 8A A semiconductor device containing four dies 1120 is schematically illustrated. For example... Figure 8A As shown, the cutting machine tool can position the PCB 1110 according to the cutting mark (i.e., the exposed portion 1112a of the first metal layer 1112) to determine three cutting lines. Then, the second insulating layer 1130 and the third insulating layer 1150 are cut along the first direction Y according to these three cutting lines, thereby separating the four dies 1120. Figures 8A-8D The fourth metal layer 1170, the fifth metal layer 1171, the sixth metal layer 1172, and the seventh metal layer 1173 are not shown. Figure 6 It can be along Figure 8A The cross-sectional view taken from the section line in the diagram.
[0113] Figure 8B According to Figure 8A A top perspective view of a semiconductor device containing a die 1120 after being cut along the dicing line. Figure 8C yes Figure 8B The top view of the semiconductor device shown. Figure 8D yes Figure 8B The semiconductor device shown is viewed from below.
[0114] The following description, in conjunction with some embodiments, illustrates different processes that can be performed after polishing when the electrodes on the first surface 1122 of the substrate 1121 of each die 1120 consist only of the first electrode E1.
[0115] Please see Figure 9 , Figure 9 Two dies 1120 are schematically shown. In the case where the electrode on the first surface 1122 of the substrate 1121 of each die 1120 includes only a first electrode E1, a second metal layer 1160 electrically coupled to the second surface 1123 can be formed after polishing. Here, the second metal layer 1160 can serve as a second electrode for at least one die 1120. For example, the first electrode E1 can be the source, and the second electrode can be the drain; or, for another example, the first electrode E1 can be the drain, and the second electrode can be the source.
[0116] In some embodiments, please continue to see Figure 9At least one metal portion may include a spaced-apart first metal portion 1141 and second metal portion 1142. A third metal layer 1161 electrically coupled to the second surface 1123 may be formed on the second surface 1123. The third metal layer 1161 is also electrically coupled to the first metal layer 1112 to electrically couple the second metal portion 1142. The third metal layer 1161 is spaced apart from the second metal layer 1160 and serves as the gate G of at least one die 1120. In this way, the first metal portion 1141, which is in contact with the first electrode E1, and the second metal portion 1142, which is electrically coupled to the third metal layer 1161 (i.e., the gate G), can be located on the same surface, which is convenient for user use.
[0117] In some embodiments, a portion of the third insulating layer 1150 may be removed to expose the first metal portion 1141 and the second metal portion 1142.
[0118] In some embodiments, the second metal layer 1160 and the third metal layer 1161 may be formed in the same patterning process, i.e., by patterning the same material layer.
[0119] In some embodiments, a fourth metal layer 1170, a fifth metal layer 1171, a sixth metal layer 1172, and an eighth metal layer can be similarly formed. Figure 9 (Not shown). The fourth metal layer 1170 may be located on the side of the second metal layer 1160 away from the third insulating layer 1150; the fifth metal layer 1171 may be located on the side of the first metal portion 1141 away from the first electrode E1; the sixth metal layer 1172 may be located on the side of the second metal portion 1142 away from the first metal layer 1112; and the eighth metal layer may be located on the side of the third metal layer 1161 away from the first metal layer 1112.
[0120] As some implementations, the fourth metal layer 1170, the fifth metal layer 1171, the sixth metal layer 1172 and the eighth metal layer can be made of the same material, for example, nickel gold.
[0121] In this way, the manufactured semiconductor device can dissipate heat from both sides through two surfaces opposite each other along the first direction Y, resulting in better heat dissipation.
[0122] In some embodiments, where at least one die 1120 comprises a plurality of dies 1120, cutting can be performed similarly to the relevant description in the foregoing embodiments to separate the plurality of dies 1120, which will not be repeated here.
[0123] According to another aspect of the embodiments of this disclosure, a semiconductor device is provided. Figure 10 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
[0124] like Figure 10As shown, the semiconductor device 1000 includes a die 1120, a first metal layer 1112, a second insulating layer 1130, and at least one metal portion.
[0125] The die 1120 includes a substrate 1121 and a first electrode E1. The substrate 1121 has a first surface 1122 and a second surface 1123 opposite to each other in a first direction Y, and the first electrode E1 is located on the first surface 1122. In some embodiments, the material of the substrate 1121 may be silicon or silicon carbide.
[0126] The second insulating layer 1130 includes a first portion 1131 located between the die 1120 and the first metal layer 1112 in a second direction, wherein the second direction is perpendicular to the first direction Y. It should be understood that the second insulating layer 1130 also includes other portions besides the first portion 1131, which together surround the die 1120 and the first metal layer 1112.
[0127] At least one metal portion includes a first metal portion 1141 that is in contact with the first electrode E1.
[0128] Here, the second surface 1123 is flush with the side of the first metal layer 1112 that is away from the first metal part 1141 in the first direction Y.
[0129] For example, see Figure 10 The first metal layer 1112 has a third surface 1112b and a fourth surface 1112c opposite to each other in the first direction Y. The distance between the third surface 1112b and the first metal portion 1141 in the first direction Y is greater than the distance between the fourth surface 1112c and the first metal portion 1141 in the first direction Y. That is, the third surface 1112b is the side of the first metal layer 1112 away from the first metal portion 1141 in the first direction Y, and the fourth surface 1112c is the side of the first metal layer 1112 close to the first metal portion 1141 in the first direction Y.
[0130] In some embodiments, the second surface 1123 may also be flush with the side of the second insulating layer 1130 away from the first metal portion 1141 in the first direction Y. In other words, the second surface 1123, the side of the first metal layer 1112 away from the first metal portion 1141, and the side of the second insulating layer 1130 away from the first metal portion 1141 are flush with each other.
[0131] In some embodiments, the thickness of die 1120 can be greater than or equal to 10 micrometers and less than or equal to 30 micrometers. This reduces the on-resistance of the semiconductor device.
[0132] In some embodiments, the thickness of the substrate 1121 can be greater than or equal to 5 micrometers and less than 10 micrometers. This can further reduce the on-resistance of the semiconductor device.
[0133] In some embodiments, the thickness of each metal part in at least one metal part may be greater than or equal to 30 micrometers and less than or equal to 300 micrometers.
[0134] In some embodiments, please continue to see Figure 10 The semiconductor device 1000 may further include a second metal layer 1160 located on and electrically coupled to the second surface 1123, wherein the second metal layer 1160 may serve as the second electrode of the die 1120. For example, the first electrode E1 may be the source and the second electrode may be the drain; or, for another example, the first electrode E1 may be the drain and the second electrode may be the source.
[0135] In some embodiments, at least one metal portion may further include a second metal portion 1142 in contact with the first metal layer 1112. In these embodiments, the second metal layer 1160 may also be electrically coupled to the first metal layer 1112 to electrically couple the second metal portion 1142. This allows the first metal portion 1141 in contact with the first electrode E1 and the second metal portion 1142 electrically coupled to the second metal layer 1160 to be located on the same surface, eliminating the need for re-encapsulation and improving usability.
[0136] In some embodiments, see Figure 9 The semiconductor device 1000 may further include a third metal layer 1161 located on and electrically coupled to the second surface 1123. For example, the third metal layer 1161 may be electrically coupled to a portion of the second surface 1123. The third metal layer 1161 may also be electrically coupled to the first metal layer 1112 to electrically couple to the second metal portion 1142. The third metal layer 1161 is spaced apart from the second metal layer 1160 and may serve as the gate G of the die 1120.
[0137] In other embodiments, please continue to refer to Figure 10 The die 1120 may further include a gate G located on the first surface 1122. At least one metal portion may further include a third metal portion 1143 in contact with the gate G, wherein the first metal portion 1141, the second metal portion 1142, and the third metal portion 1143 are spaced apart from each other. In this way, the first metal portion 1141 in contact with the first electrode E1, the second metal portion 1142 electrically coupled to the second metal layer 1160, and the third metal portion 1143 in contact with the gate G can all be located on the same surface, that is, the first electrode E1, the second electrode, and the gate G of the die 1120 can all be located on the same surface, eliminating the need for repackaging, which is beneficial to the user.
[0138] In some embodiments, the semiconductor device 1000 may further include a third insulating layer 1150, wherein the first metal portion 1141, the second metal portion 1142 and the third metal portion 1143 are spaced apart by the third insulating layer 1150.
[0139] In some embodiments, the semiconductor device 1000 may further include a fourth metal layer 1170, a fifth metal layer 1171, a sixth metal layer 1172, and a seventh metal layer 1173. The fourth metal layer 1170 may be located on the side of the second metal layer 1160 away from the third insulating layer 1150; the fifth metal layer 1171 may be located on the side of the first metal portion 1141 away from the first electrode E1; the sixth metal layer 1172 may be located on the side of the second metal portion 1142 away from the first metal layer 1112; and the seventh metal layer 1173 may be located on the side of the third metal portion 1143 away from the gate G.
[0140] It should be understood that the semiconductor devices provided in this disclosure can be manufactured using the semiconductor device manufacturing method of any of the above embodiments. The beneficial effects and further embodiments of the semiconductor devices provided in this disclosure can be found in the above description of the semiconductor device manufacturing method, and will not be repeated here.
[0141] This disclosure also provides a battery management system (BMS) including a semiconductor device (e.g., semiconductor device 1000) from any of the above embodiments. For example, the BMS may include one or more semiconductor devices 1000 (e.g., two semiconductor devices 1000).
[0142] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.
[0143] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, comprising: A substrate structure (1100) is provided, the substrate structure (1100) comprising: A printed circuit board (PCB) (1110) includes a stack having at least one opening (V1), the stack including a first insulating layer (1111) and a first metal layer (1112) stacked along a first direction (Y). At least one die (1120) is located in the at least one opening (V1), each die (1120) including a substrate (1121) and a first electrode (E1), the substrate (1121) having a first surface (1122) and a second surface (1123) opposite each other in the first direction (Y), the first electrode (E1) being located on the first surface (1122), and The second insulating layer (1130) fills the at least one opening (V1) and covers the second surface (1123) and the side of the first insulating layer (1111) away from the first metal layer (1112); At least one metal portion is formed, the at least one metal portion including a first metal portion (1141) that is in contact with the first electrode (E1). A third insulating layer (1150) is formed to cover the at least one metal portion. Using the third insulating layer (1150) as a support, grinding is performed along the first direction (Y) from the side of the second insulating layer (1130) away from the third insulating layer (1150) so that the ground second surface (1123) and the side of the first metal layer (1112) away from the third insulating layer (1150) are flush.
2. The method according to claim 1, wherein, The grinding stops at the side where the first metal layer (1112) contacts the first insulating layer (1111).
3. The method according to claim 1, wherein, After the grinding, the thickness of each die (1120) is greater than or equal to 10 micrometers and less than or equal to 30 micrometers.
4. The method according to claim 3, wherein, After the grinding, the thickness of the substrate (1121) is greater than or equal to 5 micrometers and less than 10 micrometers.
5. The method according to any one of claims 1-4, wherein, The thickness of each of the at least one metal part is greater than or equal to 30 micrometers and less than or equal to 300 micrometers.
6. The method according to claim 1, further comprising: After the grinding, a second metal layer (1160) electrically coupled to the second surface (1123) is formed on the second surface (1123), and the second metal layer (1160) serves as the second electrode of at least one die (1120).
7. The method according to claim 6, wherein: The at least one metal part further includes a second metal part (1142) in contact with the first metal layer (1112). The second metal layer (1160) is also electrically coupled to the first metal layer (1112) to electrically couple to the second metal part (1142).
8. The method according to claim 7, wherein: Each die (1120) also includes a gate (G) located on the first surface (1122); The at least one metal portion further includes a third metal portion (1143) in contact with the gate (G). The first metal part (1141), the second metal part (1142) and the third metal part (1143) are spaced apart from each other.
9. The method according to claim 6, wherein, The at least one metal portion further includes a second metal portion (1142) in contact with the first metal layer (1112), and the method further includes: After the grinding, a third metal layer (1161) electrically coupled to the second surface (1123) is formed on the second surface (1123), wherein the third metal layer (1161) is also electrically coupled to the first metal layer (1112) to electrically couple to the second metal portion (1142), the third metal layer (1161) is spaced apart from the second metal layer (1160) and serves as the gate (G) of at least one die (1120).
10. The method of claim 8, further comprising: A portion of the third insulating layer (1150) is removed to expose the first metal portion (1141), the second metal portion (1142), and the third metal portion (1143).
11. The method according to claim 6, wherein, The at least one die (1120) includes a plurality of dies (1120), and the method further includes: The PCB (1110) is located according to the cutting mark, and the second insulating layer (1130) and the third insulating layer (1150) are cut along the first direction (Y) to separate the plurality of dies (1120), wherein the cutting mark is the exposed portion (1112a) of the first metal layer (1112) that is not covered by the second metal layer (1160) after the grinding.
12. The method according to claim 1, wherein, The substrate structure (1100) includes: The at least one die (1120) and the PCB (1110) are fixed to one side of the fastener (1180); A second insulating layer (1130) is formed on one side of the fastener (1180). Remove the retainer (1180) to expose the first electrode (E1) and the first metal layer (1112).
13. A semiconductor device, comprising: The die (1120) includes a substrate (1121) and a first electrode (E1), the substrate (1121) having a first surface (1122) and a second surface (1123) opposite each other in a first direction (Y), and the first electrode (E1) is located on the first surface (1122). First metal layer (1112); The second insulating layer (1130) includes a first portion (1131) located in a second direction between the die (1120) and the first metal layer (1112), the second direction being perpendicular to the first direction (Y); At least one metal portion, including a first metal portion (1141) in contact with the first electrode (E1) and a second metal portion (1142) in contact with the first metal layer (1112), wherein, in the second direction, the size of the surface of the first metal portion (1141) in contact with the first electrode (E1) is larger than the size of the surface of the first electrode (E1) in contact with the first metal portion (1141), and the size of the surface of the second metal portion (1142) in contact with the first metal layer (1112) is larger than the size of the surface of the first metal layer (1112) in contact with the second metal portion (1142); and A third insulating layer (1150) is provided, wherein the first metal portion (1141) and the second metal portion (1142) are spaced apart by the third insulating layer (1150); The third insulating layer (1150) covers the at least one metal part during its formation. After the third insulating layer (1150) is formed, it is ground along the first direction (Y) from the side of the second insulating layer (1130) away from the third insulating layer (1150) with the third insulating layer (1150) as a support, so that the side of the first metal layer (1112) away from the first metal part (1141) in the first direction (Y) is flush with the ground second surface (1123), and the side of the second insulating layer (1130) away from the first metal part (1141) in the first direction (Y) is flush with the ground second surface (1123).
14. The device according to claim 13, wherein, The thickness of the die (1120) is greater than or equal to 10 micrometers and less than or equal to 30 micrometers.
15. The device according to claim 14, wherein, The thickness of the substrate (1121) is greater than or equal to 5 micrometers and less than 10 micrometers.
16. The device according to claim 13, wherein, The thickness of each of the at least one metal part is greater than or equal to 30 micrometers and less than or equal to 300 micrometers.
17. The device according to claim 13, further comprising: A second metal layer (1160) is located on the second surface (1123) and electrically coupled to the second surface (1123), and the second metal layer (1160) serves as the second electrode of the die (1120).
18. The device according to claim 17, wherein: The second metal layer (1160) is also electrically coupled to the first metal layer (1112) to electrically couple to the second metal part (1142).
19. The device according to claim 18, wherein: The die (1120) also includes a gate (G) located on the first surface (1122). The at least one metal portion further includes a third metal portion (1143) in contact with the gate (G). The first metal part (1141), the second metal part (1142) and the third metal part (1143) are spaced apart from each other.
20. The device of claim 17, further comprising: A third metal layer (1161) is located on the second surface (1123) and electrically coupled to the second surface (1123). The third metal layer (1161) is also electrically coupled to the first metal layer (1112) to electrically couple to the second metal portion (1142). The third metal layer (1161) is spaced apart from the second metal layer (1160) and serves as the gate (G) of the die (1120).
21. The device according to claim 19, wherein: The first metal portion (1141), the second metal portion (1142), and the third metal portion (1143) are separated by the third insulating layer (1150).
22. The device according to claim 21, further comprising: The fourth metal layer (1170) is located on the side of the second metal layer (1160) away from the third insulating layer (1150); The fifth metal layer (1171) is located on the side of the first metal portion (1141) away from the first electrode (E1); The sixth metal layer (1172) is located on the side of the second metal portion (1142) away from the first metal layer (1112); The seventh metal layer (1173) is located on the side of the third metal portion (1143) away from the gate (G).
23. The device according to any one of claims 13-22, wherein, The substrate (1121) is made of silicon or silicon carbide.