A semiconductor processing defense control method, system, device and storage medium

Abstract

The embodiments of the present disclosure disclose a semiconductor processing defense control method, system, device and storage medium. The method comprises: when the process station is suspended, the current processing process is forcibly ended, and the process state of the lot in the risk station is recorded; when the lot returns to the risk station or enters the non-risk station for reservation, the classification control is performed according to the process state recorded on the wafer. According to the exemplary embodiments of the present disclosure, the processing state of each wafer after confirmation can be recorded when the lot forcibly enters the next station in the case of suspension. The Missing Run or Double Run problem caused by human judgment error and direct reservation is solved, and the LOT forcibly entering the next station is correctly handled by using automatic forced control and disposal process.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a defense control method, system, device and storage medium for semiconductor processing. BACKGROUND

[0002] In the process of semiconductor processing, there are often lots (batch number, wafers are packed in a wafer box in units of 25 pieces, and the batch of 25 wafer groups is a lot) because the machine alarm forces the completion of the current station processing process and then enters the next station. Thus, there may be a situation where all or part of the wafers in a lot are not processed or only part of the wafers are processed. In the face of such a situation, if the historical processing data is not confirmed directly into the next process or returned to the last process (Locate), it is easy to cause Missing Run (missing run) or Double Run (double run), and in severe cases, it causes wafer contamination or reduces the yield. SUMMARY

[0003] Embodiments of the present disclosure provide a defense control method, system, device and storage medium for semiconductor processing to solve or alleviate one or more technical problems in the prior art.

[0004] According to one aspect of the present disclosure, a defense control method for semiconductor processing is provided, comprising:

[0005] When the process station is forced to end the current processing process after a pause operation, the process state of the lot in the risk station is recorded by the wafer;

[0006] When the lot returns to the risk station or enters a non-risk station for reservation, the classification control is controlled according to the process state recorded on the wafer.

[0007] In one possible implementation, the record format of the process state includes one or a combination of risk process number, process node number, pause type, single wafer number and wafer process state.

[0008] In one possible implementation, the risk station is a lot processing station where the pause operation occurs;

[0009] The non-risk station is a lot processing station where the pause operation does not occur.

[0010] In one possible implementation, it comprises:

[0011] When the lot enters a non-process station for reservation, no classification control is performed, and the non-process station includes a measurement station.

[0012] The Lot enters a non-risk site after the processing is completed at the non-process site.

[0013] In a possible implementation, when the Lot returns to the risk site for reservation, the classification control according to the process state recorded on the wafer includes:

[0014] determining whether the wafer has been processed according to the process state recorded on the wafer;

[0015] When it is determined that the wafer has been processed according to the process recorded on the wafer, the Lot enters a special forced unlocking process to perform abnormal processing and controls double running;

[0016] When it is determined that the wafer has not been processed according to the process recorded on the wafer, the Lot enters a normal processing process and clears the record of unprocessed.

[0017] In a possible implementation, when the Lot enters a non-risk site for reservation, the classification control according to the process state recorded on the wafer includes:

[0018] determining whether the wafer has not been processed according to the process state recorded on the wafer;

[0019] When it is determined that the wafer has not been processed according to the process state recorded on the wafer, the Lot enters a special forced unlocking process to perform abnormal processing and controls missing running;

[0020] When it is determined that the wafer has been processed according to the process state recorded on the wafer, the Lot enters a normal processing process and clears the record of processed.

[0021] In a possible implementation, the Lot enters a special forced unlocking process to perform abnormal processing includes:

[0022] triggering a special lock code to lock the Lot;

[0023] performing abnormal processing through a product exception notification form;

[0024] after the abnormal processing is completed, the special lock code is released by the product exception notification form to release the Lot;

[0025] the product exception notification form releases the special lock code while clearing the process state on the wafer.

[0026] According to one aspect of the present disclosure, a defense control system for semiconductor processing is provided, including:

[0027] a recording module configured to record a process state of a Lot in a risk site on a wafer when a current processing process is forcibly ended after a process site is suspended;

[0028] The classification control module is used to classify and control the Lot according to the process status recorded on the wafer when the Lot returns to a risk site or enters a non-risk site for reservation.

[0029] In one possible implementation, the recording format of the process status includes one or more combinations of risk process number, process node number, pause type, single wafer number, and wafer process status.

[0030] In one possible implementation, the risk site is a Lot processing site that has experienced a shutdown.

[0031] The non-risk sites are Lot processing sites that have not experienced any shutdowns.

[0032] In one possible implementation, when the Lot makes an appointment at a non-process station, no classification control or card-based control is performed, and the non-process station includes a measurement station.

[0033] The Lot is processed at a non-process station and then transferred to a non-risk station.

[0034] In one possible implementation, the classification control card module includes:

[0035] The first judgment unit is used to determine whether the wafer has been processed based on the process status recorded on the wafer.

[0036] The first exception handling unit is used to execute exception handling when the Lot enters a special forced unlocking process to control the dual operation of the card when it is determined that the wafer has been processed based on the process recorded on the wafer.

[0037] The first normal processing unit is used to enter the normal processing flow and clear the unprocessed record when it is determined from the process recorded on the wafer.

[0038] In one possible implementation, the classification control card module includes:

[0039] The second judgment unit is used to determine whether the wafer has not been processed based on the process status recorded on the wafer.

[0040] The second exception handling unit is used to execute exception handling and prevent missing operation when the Lot enters a special forced unlocking process to determine that the wafer has not been processed based on the process status recorded on the wafer.

[0041] The second normal processing unit is used to enter the normal processing flow and clear the processed records when the Lot determines that the wafer has been processed based on the process status recorded on the wafer.

[0042] In a possible implementation, the first exception processing unit and the second exception processing unit each include:

[0043] a triggering subunit configured to trigger a special lock code to lock the Lot;

[0044] an executing subunit configured to execute exception processing by a product exception notification sheet;

[0045] a releasing subunit configured to release the special lock code to release the Lot after the exception processing is completed;

[0046] a clearing subunit configured to clear the processing state on the wafer when the product exception notification sheet releases the special lock code.

[0047] According to an aspect of the present disclosure, a defensive control device for semiconductor processing is provided, comprising:

[0048] a processor and a memory;

[0049] The memory is configured to store a computer program, and the processor is configured to invoke the computer program stored in the memory to execute the semiconductor processing defensive control method according to any one of the above aspects.

[0050] According to an aspect of the present disclosure, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. When the computer program is executed by a processor, the processor can execute the semiconductor processing defensive control method according to any one of the above aspects.

[0051] The exemplary embodiments of the present disclosure have the following beneficial effects:

[0052] The problem that the wafer processing state recorded by the manufacturing execution system may not be consistent with the actual wafer processing state when the Lot is processed and the machine has a missed report event is solved;

[0053] The problem that the wafer processing state recorded by the manufacturing execution system may not be consistent with the actual wafer processing state when the Lot is suspended and the user manually processes or adds a process is solved;

[0054] The processing state of each wafer after confirmation can be recorded when the Lot is forced to enter the next station in the case of suspension;

[0055] The problem of Missing Run or Double Run caused by human judgment error when the Lot is reserved is solved, and the LOT forced to enter the next station is correctly processed by using automatic forced control and disposal process.

[0056] The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features and advantages of the application will be apparent from the description that follows. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the application, are given by way of illustration only, and are not by way of limitation. BRIEF DESCRIPTION OF DRAWINGS

[0057] The accompanying drawings are incorporated in and constitute a part of this specification and, together with the description, explain the principles of the disclosure. In the drawings,

[0058] Figure 1 is one of flowcharts of a defense control method of semiconductor processing of the present exemplary embodiment;

[0059] Figure 2 is another of flowcharts of a defense control method of semiconductor processing of the present exemplary embodiment;

[0060] Figure 3 is still another of flowcharts of a defense control method of semiconductor processing of the present exemplary embodiment;

[0061] Figure 4 is still another of flowcharts of a defense control method of semiconductor processing of the present exemplary embodiment;

[0062] Figure 5 is a block diagram of a defense control system of semiconductor processing of the present exemplary embodiment. DETAILED DESCRIPTION

[0063] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example implementations to those skilled in the art. The described features, structures, or characteristics can be combined in one or more implementations. In the following description, numerous specific details are provided to give a thorough understanding of one or more implementations. One skilled in the relevant art will recognize, however, that the implementations can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures have not been described in detail to avoid obscuring the underlying principles of the implementations.

[0064] Furthermore, the accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, as such, a change in the drawings can be represented to help explain the embodiments of the present disclosure.

[0065] The flowcharts shown in the accompanying drawings are only illustrative and do not necessarily include all the steps. For example, some steps can be further divided, and some steps can be combined or partially combined, so that the actual execution order can be changed according to the actual situation.

[0066] The terms "first", "second", and the like in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0067] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or sub-modules does not necessarily have to be limited to those steps or sub-modules clearly listed, but can include other steps or sub-modules that are not clearly listed or inherent to these processes, methods, products or devices.

[0068] Figure 1 is one of the flowcharts of a defense control method for semiconductor processing, as shown in Figure 1 The exemplary embodiments of the present disclosure provide a defense control method for semiconductor processing, comprising:

[0069] When the process station (Process station) is temporarily suspended (Running Hold flag is generated) and the current processing process is forcibly completed (Force Complete), the process status of the lot (a batch of products) in the risk station is recorded through all wafers in the lot; the process status is recorded through the process status to determine whether the lot has been processed;

[0070] When the lot returns to the risk station (Risk station) or enters a non-risk station for reservation, the classification control is performed according to the process status recorded on the wafer.

[0071] It is worth mentioning that wafer manufacturing includes various PD types, which can be generally divided into two types, one is Process, which is used for additive, subtractive and modification processing of wafers, etc.; the other is Measurement, which is used for defect inspection, parameter measurement and electrical property test of wafers, etc.

[0072] For the station of Process, the processing station with Running Hold is defined as a risk station (Risk station), and the processing station without Running Hold is defined as a non-risk station (non-Risk station). That is, the risk station is the Lot processing station with Running Hold, and the non-risk station is the Lot processing station without Running Hold.

[0073] The present exemplary embodiment is applied to the station of Process, and is not applied to the station of measurement and Other (for example, virtual station Dummy Tool). In the present exemplary embodiment, the Lot in the station with Running Hold is defined as a Risk Lot.

[0074] For example, when a lot is forced to complete the current process and enter the next station due to a lot suffering equipment alarm, there may be a problem of no process or only partial process of wafers in the lot. In this example embodiment, when the process station is suspended, the process state of the lot in the risk station is recorded, and then the lot is located backward to the risk station (the station where the lot is processed). This is the first case. Alternatively, the lot enters other process stations different from the risk station, which is the second case. Alternatively, the lot enters non-process stations, such as measurement or other stations, for measurement, which is the third case. In the first and second cases, the lot is processed in the risk station or other process stations different from the risk station. Before processing, it is confirmed whether there is complete processing data. When there is a risk station, a special classification string is used to lock and control the lot. When the lot returns to the risk station or enters non-risk stations for reservation, the classification control is performed according to the process state recorded on the wafer. Then, the product is released only after the special forced unlocking process is performed. In this way, the problem of missing run or double run caused by not confirming the process history and directly moving forward or locating can be avoided when the lot suffers equipment alarm and is forced to complete the current process and enter the next station, resulting in no process or partial process. In addition, the problem of wafer or equipment serious pollution or yield reduction caused by missing run or double run can be avoided.

[0075] It is worth noting that in the third case, when the lot enters non-process stations, such as measurement or other stations, for measurement, no confirmation of complete processing data is performed. That is, the method of classification control according to the process state recorded on the wafer is not applicable to non-process stations.

[0076] Exemplarily, when the current processing process is forcibly ended after the process station is suspended, the record format of the process state recorded by the wafer includes a combination of one or more of a risk process number (Risk Route ID), a process node number (OpeNo), a hold type (HoldType), a single wafer number (SlotNo), and a wafer process state (Wafer Process Status); wherein the wafer process state (Wafer Process Status) includes two types, one is a processed mark (Processed), represented by 00x1, and the other is an un-processed mark (Un-Processed), represented by 00x0;

[0077] For example, the record format of the process state is: Risk Route ID & OpeNo & HoldType & SlotNo & Wafer Process Status: Processed 00x1.

[0078] For example, the record format of the process state is: Risk Route ID & OpeNo & HoldType & SlotNo & Wafer Process Status: Un-Processed 00x0.

[0079] For example, the record format of the process state is: Risk Route ID & OpeNo & Wafer Process Status: Un-Processed 00x0.

[0080] It is worth noting that the above record format of the process state is only an exemplary embodiment, and is not limited to the above record format, and other record formats of the process state should belong to the protection scope of the present embodiment.

[0081] Exemplarily, when the Lot enters a non-process station for reservation, no classification control card control is performed, and the non-process station includes a metrology station.

[0082] The Lot enters a non-risk station after completing processing in the non-process station.

[0083] In the example embodiment, since the process station is a station that makes substantial changes to the wafer, such as additive, subtractive or modification, and the non-process station, such as a measurement station, is a station for defect inspection, parameter measurement or electrical test of the wafer, which does not make substantial changes to the wafer, the embodiment does not perform classification control when the lot enters the non-process station for reservation; after successful reservation in the non-process station, the machine in the measurement station starts, and after completing the reserved measurement project, the lot enters the non-risk station for reservation. It is worth noting that when the lot enters the non-risk station for reservation after the measurement station, it still needs to be controlled according to the process state recorded on the wafer.

[0084] In the example, when the lot enters the non-risk station for reservation, the classification control according to the process state recorded on the wafer includes:

[0085] According to the process state recorded on the wafer, it is judged whether the wafer has been processed or not;

[0086] When it is judged according to the process state recorded on the wafer that the wafer has not been processed, the reservation is not allowed, the lot is controlled to enter the special forced unlocking process to perform abnormal handling, and the missing operation is controlled to avoid the problem that the product is scrapped due to the direct entry into the next station without processing the previous process; for example, when the wafer process state (Wafer Process Status) of the record format of the process state is Un-Processed 00x0, it means that the current wafer has not been processed in the risk station, and further means that the wafer may have a missing processing problem, so the missing operation is checked for this case, and the lot is controlled to enter the special forced unlocking process to perform abnormal handling.

[0087] In the example, the lot enters the special forced unlocking process to perform abnormal handling, which includes:

[0088] Trigger a special hold code (Special Hold Code) to put the lot ONHOLD (hold), so that it cannot enter the process;

[0089] Abnormal handling is performed through a product abnormal notice (PAN);

[0090] After the abnormal handling is completed, the special hold code is released by the product abnormal notice to release the lot;

[0091] The product abnormal notice releases the special hold code while clearing the process state on the wafer.

[0092] It is worth mentioning that the determination and disposal of product abnormalities are recorded through product abnormality notification sheets, and the Hold can be released after confirmation. The general Hold can be directly released in the system operation interface. Since Double or Missing Run can cause more serious product scrapping, a signature process is performed for Double or Missing Run, and then the product is released.

[0093] The exemplary embodiment provides a menu standard interface (without the risk of manual input of error data) that needs to perform abnormal processing through a special forced release process (a process with automatic processing capability) before the product is released. When the release special hold code process is completed, the Process Status recorded on the wafer is cleared.

[0094] When it is determined according to the process status recorded on the wafer that the wafer has been processed, the Lot enters the normal processing flow, and the processed record is cleared. For example, when the wafer process status (Wafer Process Status) in the record format of the process status is Processed 00x1, it indicates that the current wafer has been processed in the risk site, and the wafer does not have the problem of missing processing. Therefore, for this case, the Lot is controlled to enter the normal processing flow, the reservation of the current process site is completed, and the related processed record is cleared to avoid the impact of the processed record on subsequent processing work.

[0095] Exemplarily, the normal processing flow is to reserve the current machine, start the machine, and complete the processing procedure of the reservation.

[0096] In the exemplary embodiment, a menu standard interface is provided, and the product is released after abnormal processing through a special forced release process (a process with automatic processing capability). The menu standard interface provided avoids the risk of manual input of error data. The release special hold code process releases the special identification reserved code, and the Process Status recorded on the wafer is cleared.

[0097] When it is determined according to the process status recorded on the wafer that the wafer has been processed, the Lot enters the normal processing flow, and the processed record is cleared. For example, when the wafer process status (Wafer Process Status) in the record format of the process status is Processed 00x1, it indicates that the current wafer has been processed in the risk site, and the wafer does not have the problem of missing processing. Therefore, for this case, the Lot is controlled to enter the normal processing flow, the reservation of the current process site is completed, and the related processed record is cleared to avoid the impact of the processed record on subsequent processing work.

[0098] For example, when the Lot returns to the Risk site for reservation, the classification control card according to the process state recorded on the wafer includes:

[0099] According to the process state recorded on the wafer, it is judged whether the wafer is processed or not;

[0100] When it is judged according to the process recorded on the wafer that the wafer has been processed, the Lot enters the special forced unlocking process to perform abnormal processing, and controls double run, that is, to avoid the problem of repeated processing of products at a certain site leading to product scrap;

[0101] When it is judged according to the process recorded on the wafer that the wafer has not been processed, the Lot enters the normal processing flow and clears the unprocessed (Un-Processed) record.

[0102] In this embodiment, when the Lot returns to the Risk site for reservation, the wafer in the Risk Lot has a Processed record, and before the product starts to execute (Lot OpeStart), the product is locked (Lot ONHOLD) using the special hold code (Special HoldCode) provided by the user, and double run (Double Run) is controlled.

[0103] If all the wafers in the Risk Lot are unprocessed (Un-Processed) records, the process processing (OpeStart) can be started, and after the process is completed (OpeComp), the unprocessed (Un-Processed) record of the wafer is deleted.

[0104] When it is judged according to the process state recorded on the wafer that part or all of the wafers have been processed, reservation is not allowed, and the Lot is controlled to enter the special forced unlocking process to perform abnormal processing, and double run (Double Run) is controlled; for example, when the wafer process state (Wafer Process Status) of the process state record format is Processed 00x1, it means that the current wafer has been processed in the Risk site, and if it is processed again, it may cause double processing of the wafer and multiple running of the machine, therefore, double run check (Double Run Check) is performed for this case, and the Lot is controlled to enter the special forced unlocking process to perform abnormal processing.

[0105] It is worth mentioning that in the present exemplary embodiment, the special forced unlocking procedure in the step of controlling double running is consistent with the special forced unlocking procedure in the step of controlling missing running, which will not be described herein again.

[0106] It is worth mentioning that when Risk Lot occurs Running Hold again at the Risk site, Force Complete is used to record Process Status again, and the original record is overwritten.

[0107] The present exemplary embodiment solves the problems of missing event reporting of the machine when the lot is in processing and the inconsistency between the MES recorded Wafer Process Status and the actual Wafer Process Status; solves the problem of inconsistency between the MES recorded Wafer Process Status and the actual Wafer Process Status when the lot occurs Running Hold and the user manually offline to supplement the Run; solves the problem of recording and confirming the Process Status of each Wafer when Force OpeComplete occurs when the lot occurs Running Hold; solves the problem of directly reserving DoubleRun or MissingRun due to human judgment error when the lot is reserved, and uses the automatic forced control and disposal procedure to correctly handle the Force OpeComplete lot.

[0108] Figure 2 is a flowchart of a semiconductor processing defense control method according to the present exemplary embodiment; as Figure 2As shown, when wafer processing is performed, first, a machine is reserved, after the reservation is successful, the reserved machine starts processing according to the reservation, when the process site (Process site) is in a running hold state, a product abnormal notification sheet (Trigger PAN) is triggered, when the running hold state occurs, the current processing process is forced to end (Force Complete), and the process status of the lot in the risk site is recorded by the wafer; PE (manufacturing engineer) or EE (equipment engineer) checks the wafer status to ensure that the processing state of the wafer is consistent with the actual situation, and then the lot is located backward to the risk site (the risk site is the lot processing site in the running hold state), or enters other process sites different from the risk site, or enters non-process sites such as measurement or other sites for measurement procedures;

[0109] When the lot is located backward to the risk site, the lock code is manually released, after the lock code is released, the lot can be processed, first, the reservation of the risk site is performed, when the reservation is performed, it is judged whether there is a processed wafer (Processd Wafer), if there is, a special lock code is added to the attribute of the product as a control mark, a double run check is performed, and then a product abnormal notification sheet (PAN) is triggered, the PAN has a menu type mechanism with an automatic processing classification process; otherwise, the machine in the risk site is started, the processing procedure of the reservation is completed, and the measurement site or other site is reserved, since the measurement or other site is not a process site, whether there is complete processing data is not confirmed, the machine in the measurement site or other site is started, after the detection procedure of the reservation is completed, the non-risk site is entered; when the lot enters the non-risk site for reservation, it is judged whether there is an unprocessed wafer (Un-Processd Wafer), if there is, the special hold code (ONHOLD) is performed, a miss run check is performed, and then a PAN (Realease Lot in PAN) is triggered, a menu type mechanism with an automatic processing ability process is provided;

[0110] When a Lot enters a non-risk site, a reservation for the non-risk site is made. During the reservation, it is determined whether there is an unprocessed wafer. If so, ONHOLD (Special Hold Code) is set to perform a Miss Run Check. Then, Trigger PAN (RealeaseLot inPAN) is a menu-driven automated process.

[0111] When a Lot enters a non-Process station, it does not verify whether there is complete processing data. The machine at that measurement station or other stations starts up, completes the scheduled testing procedure, and then enters the non-risk station.

[0112] Figure 3 This is a flowchart of a defense control method for semiconductor processing according to an exemplary embodiment of the present invention; as shown below. Figure 3 As shown, when the machine at the process station starts working (Process OP Start), during the Running Hold phase and Force Complete phase, the Process Status is recorded through the wafer. When Lot Reserve is checked, the Process Status data of risky or non-risky stations is verified. If normal, Release & Open Start are recorded. Otherwise, Double Run or Missing Run is performed to lock and control the process. Forced unlocking process control and automatic handling are implemented. Finally, the PAN process is completed and the product is released, thus releasing the Hold.

[0113] Figure 4 This is a flowchart of a defense control method for semiconductor processing according to an exemplary embodiment of the present invention; as shown below. Figure 4 As shown, process stations are identified. When a process station experiences a Force Complete event, the station is marked as a risk station, and a special classification record controller is used to record the risk information. Process Status data is confirmed at risk stations or non-risk stations, and the product control is forcibly unlocked (with automatic process management and automatic processing capabilities). The product control is released, and normal operation resumes.

[0114] Figure 5 This is a block diagram of a semiconductor fabrication defense control system according to an exemplary embodiment of the present invention. Figure 5 As shown, an exemplary embodiment of this disclosure provides a defense control system for semiconductor processing, including:

[0115] The recording module is configured to record a process state of a lot in a risk station when a current process is forcibly ended after a process station is suspended.

[0116] The classification control carding module is configured to perform classification control carding according to the process state recorded on the wafer when the lot returns to the risk station or enters a non-risk station for reservation.

[0117] Exemplarily, the recording format of the process state includes one or more combinations of a risk process number, a process node number, a suspension type, a single wafer number, and a wafer process state.

[0118] Exemplarily, the risk station is a lot processing station where the suspension occurs.

[0119] The non-risk station is a lot processing station where the suspension does not occur.

[0120] Exemplarily, when the lot enters a non-process station for reservation, no classification control carding is performed, and the non-process station includes a metrology station.

[0121] The lot enters the non-risk station after completing processing in the non-process station.

[0122] Exemplarily, the classification control carding module includes:

[0123] A first judging unit is configured to judge whether the wafer is processed according to the process state recorded on the wafer.

[0124] A first abnormal processing unit is configured to, when it is judged according to the process state recorded on the wafer that the wafer is processed, make the lot enter a special forced unlocking process to perform abnormal processing and control double running.

[0125] A first normal processing unit is configured to, when it is judged according to the process state recorded on the wafer that the wafer is not processed, make the lot enter a normal processing process and clear the record of unprocessed.

[0126] Exemplarily, the classification control carding module includes:

[0127] A second judging unit is configured to judge whether the wafer is not processed according to the process state recorded on the wafer.

[0128] A second abnormal processing unit is configured to, when it is judged according to the process state recorded on the wafer that the wafer is not processed, make the lot enter a special forced unlocking process to perform abnormal processing and control missing running.

[0129] The second normal processing unit is configured to, when it is determined that the wafer has been processed according to the processing state recorded on the wafer, enter the normal processing flow and clear the processed record.

[0130] The first abnormal processing unit and the second abnormal processing unit each include, for example:

[0131] The triggering subunit is configured to trigger a special lock code to lock the lot;

[0132] The execution subunit is configured to execute abnormal processing through a product abnormality notification sheet;

[0133] The release subunit is configured to release the special lock code to release the lot after the abnormal processing is completed;

[0134] The clearing subunit is configured to clear the processing state on the wafer when the product abnormality notification sheet releases the special lock code.

[0135] An exemplary embodiment of the present disclosure provides a defense control device for semiconductor processing, including a processor and a memory; the memory is configured to store a computer program, and the processor is configured to invoke the computer program stored in the memory to execute the above-mentioned defense control method for semiconductor processing.

[0136] An exemplary embodiment of the present disclosure provides a computer readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the processor can execute the above-mentioned defense control method for semiconductor processing.

[0137] In summary, the exemplary embodiments of the present disclosure have a processing ability control method for preventing Double Run and Missing Run of products during process treatment; a classification record controller with a string combination; a control method with a special forced unlocking and automatic processing ability flow; the classification controller can include flow classifications other than Double Run and Missing Run; the special forced unlocking flow has an external communication interface and can automatically execute a menu triggering processing external function.

[0138] The above is only the preferred embodiment of the present disclosure, and the protection scope of the present disclosure is not limited to the above-mentioned embodiments. Any technical solution falling within the idea of the present disclosure belongs to the protection scope of the present disclosure. It should be noted that, for ordinary skilled persons in the art, some improvements and refinements without departing from the principle of the present disclosure should be considered as the protection scope of the present disclosure.

Claims

1. A defense control method for semiconductor processing, characterized in that, include: When the current processing technology is forcibly terminated due to a pause in the process station, the process status of the Lot in the risk station is recorded through the wafer record. When the Lot returns to a risk site or enters a non-risk site to make an appointment, it is classified and controlled according to the process status recorded on the wafer. The risk sites are Lot processing sites that have experienced operational shutdowns. The non-risk sites are Lot processing sites that have not experienced any shutdowns. When a Lot makes an appointment at a non-risk site, it is classified and controlled according to the process status recorded on the wafer, including: Determine whether a wafer has not been processed based on the process status recorded on the wafer; When the process status recorded on the wafer indicates that the wafer has not been processed, the Lot enters a special forced unlocking process to perform exception handling and control the missing operation. When the process status recorded on the wafer indicates that the wafer has been processed, the Lot enters the normal processing flow and clears the processed record.

2. The defense control method for semiconductor processing according to claim 1, characterized in that, The recording format for the process status includes one or more combinations of risk process number, process node number, pause type, single wafer number, and wafer process status.

3. The defense control method for semiconductor processing according to claim 1, characterized in that, include: When the Lot makes an appointment at a non-process station, no classification control or card control is applied. The non-process station includes measurement stations. The Lot is processed at a non-process station and then transferred to a non-risk station.

4. The defense control method for semiconductor processing according to claim 1, characterized in that, When the Lot returns to the risk site to make an appointment, the classification and control based on the process status recorded on the wafer includes: Determine whether a wafer has been processed based on the process status recorded on the wafer; When the process recorded on the wafer indicates that the wafer has been processed, the Lot enters a special forced unlocking process to perform exception handling, thus controlling dual operation. When the process recorded on the wafer indicates that the wafer has not been processed, the Lot enters the normal processing flow and clears the unprocessed record.

5. The defense control method for semiconductor processing according to claim 1 or 4, characterized in that, Lot enters a special forced unlock process and performs exception handling, including: Trigger a special locking code to lock the Lot; Perform exception handling through the product exception notification form; After the exception is handled, the special lock code is released through the product exception notification form to release the Lot; The product anomaly notification releases the special lock code while simultaneously clearing the process status on the wafer.

6. A defense control system for semiconductor processing, characterized in that, include: The recording module is used to record the process status of the Lot in the risk site through the wafer when the current processing technology is forcibly terminated after the process site is suspended. The classification control module is used to classify and control the Lot according to the process status recorded on the wafer when the Lot returns to a risk site or enters a non-risk site for reservation. The risk sites are Lot processing sites that have experienced operational shutdowns. The non-risk sites are Lot processing sites that have not experienced any shutdowns. The classification control card module includes: The first judgment unit is used to determine whether the wafer has been processed based on the process status recorded on the wafer. The first exception handling unit is used to execute exception handling when the Lot enters a special forced unlocking process to control the dual operation of the card when it is determined that the wafer has been processed based on the process recorded on the wafer. The first normal processing unit is used to enter the normal processing flow and clear the unprocessed record when it is determined from the process recorded on the wafer.

7. The defense control system for semiconductor processing according to claim 6, characterized in that, The recording format for the process status includes one or more combinations of risk process number, process node number, pause type, single wafer number, and wafer process status.

8. The defense control system for semiconductor processing according to claim 6, characterized in that, When the Lot makes an appointment at a non-process station, no classification control or card control is applied. The non-process station includes measurement stations. The Lot is processed at a non-process station and then transferred to a non-risk station.

9. The semiconductor processing defense control system according to claim 6 or 8, characterized in that, The classification control card module includes: The second judgment unit is used to determine whether the wafer has not been processed based on the process status recorded on the wafer. The second exception handling unit is used to execute exception handling and prevent missing operation when the Lot enters a special forced unlocking process to determine that the wafer has not been processed based on the process status recorded on the wafer. The second normal processing unit is used to enter the normal processing flow and clear the processed records when the Lot determines that the wafer has been processed based on the process status recorded on the wafer.

10. The defense control system for semiconductor processing according to claim 6, characterized in that, Both the first exception handling unit and the second exception handling unit include: The trigger subunit is used to trigger a special locking code to lock the Lot; The execution subunit is used to perform exception handling based on the product exception notification form. The release subunit is used to release the special lock code to release the Lot after exception handling is completed; The clear sub-unit is used to clear the process status on the wafer when a product exception notification releases a special lock code.

11. A defense control device for semiconductor processing, characterized in that, include: Processor and memory; The memory is used to store computer programs, and the processor calls the computer programs stored in the memory to execute the semiconductor processing defense control method according to any one of claims 1 to 5.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, enables the processor to perform the semiconductor processing defense control method according to any one of claims 1 to 5.

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