Analog-to-digital conversion circuit and analog-to-digital converter

Abstract

This invention provides an analog-to-digital (ADC) conversion circuit and an ADC, relating to the field of integrated circuit technology. A high-order voltage divider coarse quantization module generates two analog voltages corresponding to an M-bit digital code and outputs them to a low-order voltage fine quantization module. The low-order voltage fine quantization module generates two comparison voltages and outputs them to a comparator. The comparator generates a result digital value and outputs it to a SAR LOGIC. The SAR LOGIC generates a new M-bit digital code and a new L-bit digital code, and outputs them to the high-order voltage divider coarse quantization module and the low-order voltage fine quantization module, respectively, until the two comparison voltages generated by the low-order voltage fine quantization module are close enough to meet the resolution requirements, at which point the comparator stops outputting a new result digital value to the SAR LOGIC. This invention reduces the physical area occupied by single resistors and resistor switches, simplifies digital control logic, and facilitates ADC layout. It achieves high-precision conversion, high effective bit depth, and good monotonicity. It further improves the miniaturization operability of the ADC and has high practicality.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an analog-to-digital conversion circuit and an analog-to-digital converter. Background Technology

[0002] Currently, in the classic SAR (Successive Approximation Register) ADC (Analog to Digital Converter) architecture, the DAC (Digital to Analog Converter) module often adopts a traditional resistor voltage divider structure, which requires a large number of switches and resistors, and its digital control logic circuit is complex, affecting its conversion speed.

[0003] The demand for miniaturization in analog-to-digital converters (ADCs) is constantly increasing, with manufacturers and users alike hoping for smaller converters while maintaining higher conversion speeds and accuracy. Taking a 16-bit DAC module as an example, if a simple resistor divider structure is used, the required number of switches and individual resistors is substantial, totaling 65,792 switches and 65,536 individual resistors. Such a large number of resistors and switches inevitably occupies a significant physical area. Furthermore, the control logic based on 65,792 switches is quite complex. Adding to this the shift registers and other circuitry required for ADC conversion further complicates miniaturization.

[0004] Therefore, how to reduce the number of single resistors and switches to reduce the physical area occupied by analog-to-digital converters and reduce the complexity of control logic while ensuring the conversion speed and accuracy of analog-to-digital converters, and further improve the miniaturization of analog-to-digital converters, is an urgent problem to be solved. Summary of the Invention

[0005] In view of the above problems, the present invention proposes an analog-to-digital conversion circuit and an analog-to-digital converter.

[0006] This invention provides an analog-to-digital conversion circuit, which includes: SAR LOGIC, a high-bit coarse quantization module, a low-bit fine quantization module, and a comparator;

[0007] The high-order voltage divider coarse quantization module receives the M-bit digital code output by the SAR LOGIC, divides the voltage to generate two analog voltages corresponding to the M-bit digital code, and outputs them to the low-order fine quantization module.

[0008] The low-order fine quantization module receives two analog voltages, the L-bit digital code output by the SRA LOGIC, and the sampled voltage, generates two comparison voltages, and outputs them to the comparator.

[0009] The comparator receives the two comparison voltages, generates a digital result, and outputs it to the SAR LOGIC.

[0010] The SAR LOGIC receives the result digital value, generates a new M-bit digital code and a new L-bit digital code, and outputs them to the high-bit coarse quantization module and the low-bit fine quantization module, respectively, until the two comparison voltages generated by the low-bit fine quantization module are close to and meet the resolution requirements, at which point the comparator stops outputting the new result digital value to the SAR LOGIC.

[0011] Wherein, the M-bit digital code is the high M-bit digital code in the corresponding target bit, the L-bit digital code is the low L-bit digital code in the corresponding target bit, and the target bit is the number of bits for analog-to-digital conversion by the analog-to-digital conversion circuit. If it is N bits, then N = M + L.

[0012] Of the two comparison voltages, the first comparison voltage corresponds to the result of the digital-to-analog conversion after coarse and fine quantization, and the second comparison voltage corresponds to the result of the amplified sampling voltage.

[0013] Optionally, the high-level voltage divider coarse quantization module includes: a voltage divider submodule and a voltage selection submodule;

[0014] The voltage divider submodule receives the M-bit digital code, generates odd and even voltages, and outputs them to the voltage selection submodule.

[0015] The voltage selection submodule receives the odd voltage and the even voltage, and selects and determines, based on the characteristic bit digital code, whether the first analog voltage is the odd voltage or the even voltage, and selects and determines whether the second analog voltage is the odd voltage or the even voltage.

[0016] Wherein, when the first analog voltage is the odd voltage, the second analog voltage is the even voltage, and vice versa;

[0017] The feature bit code is the least significant bit of the M-bit code.

[0018] Optionally, the voltage divider submodule includes: multiple single resistors, multiple resistor switches, and multiple row switches; the number of the multiple single resistors is determined by M bits;

[0019] The state of the plurality of resistor switches is controlled by the low-order bits of the M-bit digital code;

[0020] The state of the multiple row switches is controlled by the high-order bits of the M-bit digital code;

[0021] Multiple of the single resistors are connected in series in an S-shape between the reference voltage and ground potential;

[0022] The number of rows and columns corresponding to the structure formed by multiple single resistors connected in series in an S-shape is determined by the number of bits of the target bit, and each row is provided with a row switch;

[0023] Each of the multiple single resistors is connected to a resistor switch at both ends, and two adjacent single resistors share a resistor switch.

[0024] Each single resistor is connected to one end of the row switch of the row in which it is located through two resistor switches at its two ends. The other end of the row switch outputs the even voltage and the odd voltage.

[0025] Optionally, the output signal corresponding to the high-order digit code in the M-bit digital code determines the on / off state of each row switch among the multiple row switches;

[0026] The output signal corresponding to the low-order digit code in the M-bit digital code determines the on / off state of each of the multiple resistor switches.

[0027] In this system, the two resistor switches at both ends of each single resistor are controlled by the same signal value and are simultaneously turned on or off.

[0028] The high-order bits of the M-bit digital code are decoded by a high-order decoder to obtain the corresponding output signal.

[0029] The low-order bits of the M-bit digital code are decoded from binary code to the corresponding Gray code, and then decoded by a low-order decoder to obtain the corresponding output signal.

[0030] Optionally, the voltage selection submodule includes: a first selection switch, a second selection switch, a third selection switch, and a fourth selection switch;

[0031] The first terminal of the first selection switch is connected to the first terminal of the third selection switch and receives the dipole voltage;

[0032] The second end of the first selection switch is connected to the first end of the fourth selection switch, and is also connected to the low-level fine quantization module.

[0033] The second terminal of the third selection switch is connected to the second terminal of the second selection switch and is also connected to the low-level fine quantization module.

[0034] The first terminal of the second selector switch is connected to the second terminal of the fourth selector switch and receives the odd voltage;

[0035] The first selection switch, the second selection switch, the third selection switch, and the fourth selection switch are all controlled by the feature bit code.

[0036] Optionally, when the value of the output signal corresponding to the feature bit digital code is 1, the first selection switch and the second selection switch are turned on, the first analog voltage is the odd voltage, and the second analog voltage is the even voltage;

[0037] When the value of the output signal corresponding to the characteristic bit digital code is 0, the third selection switch and the fourth selection switch are turned on, the first analog voltage is the even voltage, and the second analog voltage is the odd voltage.

[0038] Optionally, the low-order fine quantization module includes: an odd / even voltage input submodule, a sampling voltage input submodule, and an amplification submodule;

[0039] The odd / even voltage input submodule includes: multiple PMOS transistors and a first PMOS transistor;

[0040] The sampling voltage input submodule includes: a third PMOS transistor;

[0041] Multiple PMOS transistors are connected in parallel, and their sources are respectively connected to the source of the first PMOS transistor and the source of the third PMOS transistor.

[0042] The drains of the plurality of PMOS transistors are connected to the drain of the first PMOS transistor and the amplification submodule, respectively.

[0043] The gate of each of the plurality of PMOS transistors is connected to two gate switches. The first analog voltage of the two analog voltages is received through one gate switch, and the second analog voltage of the two analog voltages is received through the other gate switch.

[0044] The gate of the first PMOS transistor receives the second analog voltage;

[0045] The source of the third PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the second PMOS transistor receives a bias voltage, and the source of the second PMOS transistor receives a power supply voltage.

[0046] The gate of the third PMOS transistor receives the sampling voltage;

[0047] The drain of the third PMOS transistor is connected to the amplification submodule.

[0048] Optionally, the amplification submodule includes: a fourth PMOS transistor, a fifth PMOS transistor, a first resistor, and a second resistor;

[0049] The source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor.

[0050] The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, and both are connected to ground.

[0051] The drain of the fourth PMOS transistor is connected to the first terminal of the first resistor and outputs the second comparison voltage.

[0052] The source of the fifth PMOS transistor is connected to the drain of the first PMOS transistor and the drains of the plurality of PMOS transistors, respectively.

[0053] The drain of the fifth PMOS transistor is connected to the first terminal of the second resistor and outputs the first comparison voltage;

[0054] The second end of the first resistor and the second end of the second resistor are both connected to the ground terminal.

[0055] Optionally, several operational amplifiers are cascaded between the low-order fine quantization module and the comparator.

[0056] This invention also provides an analog-to-digital converter, which includes: any of the analog-to-digital conversion circuits described above.

[0057] The analog-to-digital conversion circuit provided by this invention includes a high-order coarse quantization module that receives the M-bit digital code output by the SAR LOGIC, divides the voltage to generate two analog voltages corresponding to the M-bit digital code, and outputs them to a low-order fine quantization module; and a low-order fine quantization module that receives the two analog voltages, the L-bit digital code output by the SAR LOGIC, and the sampling voltage, generates two comparison voltages, and outputs them to a comparator.

[0058] The comparator receives two comparison voltages, generates a result digital value, and outputs it to the SAR LOGIC. The SAR LOGIC receives the result digital value, generates a new M-bit digital code and a new L-bit digital code, and outputs them to the high-bit voltage divider coarse quantization module and the low-bit fine quantization module, respectively, until the two comparison voltages generated by the low-bit fine quantization module are close to and meet the resolution requirements, at which point the comparator stops outputting a new result digital value to the SAR LOGIC.

[0059] In the analog-to-digital conversion circuit of this invention, the number of individual resistors is no longer determined by the total number of bits in the digital quantity, but rather by the number of bits used for coarse quantization. For example, in a 16-bit DAC, the number of unit resistors is currently determined by 16 bits, therefore the number of unit resistors is 2. 16 =65536. If the coarse quantization bit depth of this invention is 8 bits, then the number of unit resistors is only 2. 8=256. This undoubtedly greatly reduces the number of individual resistors, and the number of resistor switches is determined by the number of individual resistors. The fewer the number of individual resistors, the fewer the number of resistor switches. This undoubtedly greatly reduces the physical area occupied by individual resistors and resistor switches. Furthermore, due to the reduction in the number of resistor switches, the control logic naturally becomes simpler.

[0060] This invention employs a high-bit coarse quantization module for resistive voltage division in the high M-bit position and a low-bit fine quantization module for the low L-bit position, significantly reducing the number of resistor switches and individual resistors. This reduction in resistor switches simplifies the digital control logic, making the control logic simpler and the analog-to-digital converter (ADC) layout easier. Simultaneously, it achieves high-precision conversion with a high number of effective bits and good monotonicity. This further enhances the miniaturization feasibility of the ADC and makes it highly practical. Attached Figure Description

[0061] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0062] Figure 1 This is a modular schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention;

[0063] Figure 2 This is a schematic diagram of a preferred pressure divider submodule in an embodiment of the present invention;

[0064] Figure 3 This is a schematic diagram of a preferred voltage selection module in an embodiment of the present invention;

[0065] Figure 4 This is a schematic diagram of a preferred low-level fine quantization module in an embodiment of the present invention. Detailed Implementation

[0066] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention, and are merely some embodiments of the present invention, not all embodiments, and are not intended to limit the present invention.

[0067] Reference Figure 1This diagram illustrates a modular schematic of an analog-to-digital conversion circuit according to an embodiment of the present invention. The circuit converts analog quantities into corresponding digital quantities, i.e., performs analog-to-digital conversion. The circuit includes: a SAR LOGIC module, a high-order voltage divider coarse quantization module, a low-order voltage divider fine quantization module, and a comparator.

[0068] Assuming the analog-to-digital converter (ADC) performs analog-to-digital conversion on a target bit N, the M-bit digital code corresponds to the high M bits of the target bit N, and the L-bit digital code corresponds to the low L bits of the target bit N. Then, the high-bit coarse quantization module receives the M-bit digital code output from the SAR LOGIC, divides it to generate two analog voltages V1 and V2 corresponding to the M-bit digital code, and outputs them to the low-bit fine quantization module.

[0069] The low-order fine quantization module receives two analog voltages, an L-bit digital code output from the SRA LOGIC, and the sampled voltage V. IN This generates two comparison voltages and outputs them to the comparator. Figure 1 In the diagram, SH represents the sampling module, used to obtain the sampled voltage V. IN .

[0070] The comparator receives two comparison voltages. Figure 1 V in Chinese OP and V ON This indicates that the resulting digital value Dout is generated and output to SAR LOGIC. The first comparison voltage V is one of the two comparison voltages. ON The second comparison voltage V corresponds to the result of the digital-to-analog conversion after coarse and fine quantization. OP Corresponding sampling voltage V IN The result of magnification.

[0071] The SAR LOGIC receiver comparator sends a digital output, Dout, which generates a new M-bit digital code and a new L-bit digital code. These are then output to the high-bit coarse quantization module and the low-bit fine quantization module, respectively, until the low-bit fine quantization module generates two comparison voltages V. OP and V ON Once the resolution requirement is approached and met, the comparator stops outputting new digital results to SAR LOGIC, and the entire analog-to-digital conversion ends.

[0072] Based on the structure of the analog-to-digital converter circuit described above, the entire analog-to-digital conversion process can be summarized as follows:

[0073] 1) In the shift register ( Figure 1 (Not shown in the image) Input 1 at the input terminal. Shift one position to the right for each bit change. P N-1 =1, P N-2 All values ​​up to P0 are equal to 0.

[0074] 2) SAR's MSB (i.e., D) N-1 The initial value of ) is set to 1, and the remaining bits (D) are set to 1. N-2 All values ​​up to D0 are set to 0.

[0075] 3) The SAR output can be set to 1000...00. Let M+L=N, where the high M bits control the high-bit coarse quantization module to generate two analog voltages V1 and V2, and the low L bits control the low-bit fine quantization module and generate voltage V at its positive input. REF / 2.

[0076] 4) Next, the output of the low-order fine quantization module is amplified by an operational amplifier and converted into two comparison voltages V. OP and V ON The data is sent to the comparator for comparison.

[0077] 5) Sample voltage V IN With V REF Compare / 2. If V IN Greater than V REF / 2, then the comparator output Dout is 1, D N-1 Keep it at 1; if V IN Less than V REF / 2, then the comparator output is 0, D N-1 Change to 0. D N-1 This is the actual MSB of the final digital output code.

[0078] 6) Shift 1 in the shift register one bit to the right, making P... N-2 =1, while the rest of the bits are 0.

[0079] 7) D N-2 Set to 1, D N-3 D0 remains 0, while D N-1 Keep the value obtained from the previous conversion of MSB. At this time, the voltage generated at the positive input of the low-order fine quantization module is V. REF / 4(If D) N-1 =0) or 3V REF / 4(If D) N-1 =1).

[0080] 8) V IN Compare with the voltage generated at the positive input terminal of the low-order fine quantization module. If V IN If the voltage is greater than this, the comparator output Dout will be 1, and D... N-2 Keep it at 1; if V IN If the voltage is less than this, the comparator output Dout is 0, D N-2 Change to 0. D N-2 This is the actual MSB of the final digital output code.

[0081] 9) Repeat the above process until the voltage generated at the positive input terminal of the low-order fine quantization module approaches V. IN Once the resolution requirements are met, the entire analog-to-digital conversion process is complete.

[0082] Based on the above structure and working principle, a new voltage divider circuit was designed. In one possible embodiment, the high-bit voltage divider coarse quantization module includes: a voltage divider submodule and a voltage selection submodule. The voltage divider submodule receives an M-bit digital code, generates odd and even voltages, and outputs them to the voltage selection submodule. The voltage selection submodule receives the odd and even voltages, and, in conjunction with the characteristic bit digital code, determines whether the first analog voltage is odd or even, and whether the second analog voltage is odd or even. Specifically, if the first analog voltage is odd, the second analog voltage is even, and vice versa; that is, if the first analog voltage is even, the second analog voltage is odd. The characteristic bit digital code refers to the least significant bit of the M-bit digital code. For example, in a 16-bit system (N=16), the high M bits and low L bits are each 8 bits, i.e., M=8, L=8, and the digital code corresponding to M is D8~D8. 15 If the digital code corresponding to L is the digital code from D0 to D7, then the characteristic digital code is the digital code of D8.

[0083] Specifically, the voltage divider submodule includes: multiple single resistors, multiple resistor switches, and multiple row switches; the number of single resistors is determined by M bits; the state of the multiple resistor switches is controlled by the low-order bits of the M-bit digital code; the state of the multiple row switches is controlled by the high-order bits of the M-bit digital code. Taking M=8 as an example, the low-order bits of the M-bit digital code can be D8 to D8. 11 The high-order digits in an M-bit code can be D. 12 ~D 15 That is, D8~D 11 The output signal corresponding to the digital code determines the on / off state of each resistor switch in the multiple resistor switches. 12 ~D 15 The output signal corresponding to the digital code determines the on / off state of each row switch among multiple row switches.

[0084] Multiple single resistors are connected in series in an S-shape between the reference voltage and ground potential. The number of rows and columns corresponding to the structure formed by the multiple single resistors connected in series in an S-shape is determined by the number of bits in the target bit. Each row has one row switch. For example, if the number of bits in the target bit is 16, then the structure formed by the multiple single resistors connected in series in an S-shape will have 16 rows and 16 columns, with one row switch in each row, resulting in 16 row switches.

[0085] In a system of multiple single resistors, each resistor is connected to a resistor switch at both ends, with adjacent resistors sharing a single resistor switch. Each single resistor, through its two resistor switches, is connected to one end of a row switch in the row it belongs to. The other end of this row switch outputs an even voltage and an odd voltage. The two resistor switches at each resistor's ends are controlled by the same signal value, simultaneously turning on or off.

[0086] To more clearly explain and illustrate the high-bit coarse quantization module and the low-bit fine quantization module, the following example uses 8 bits of M bits and 6 bits of L bits to illustrate the structural diagrams of the high-bit coarse quantization module and the low-bit fine quantization module. (Refer to...) Figure 2 The diagram shows a preferred voltage divider submodule according to an embodiment of the present invention. Figure 2 It includes: multiple single resistors, multiple resistor switches, a high-order decoder, and a low-order decoder.

[0087] The high-order digit D in the M-bit numeric code 15-12 The corresponding output signal is obtained by decoding through a high-order decoder to control the row switches X0 to X1. 15 The on / off state; the low-order digit D in the M-bit code. 11-8 After decoding the binary code into the corresponding Gray code, a low-order decoder is used to decode the remaining bits to obtain the corresponding output signal, which controls the resistor switch. It should be noted that the low-order digit code D... 11-8 Alternatively, the binary code can be decoded into the corresponding Gray code, but the structure will need to be modified accordingly.

[0088] Since the coarse quantization uses 8 bits, the number of unit resistors is 2. 8 =256, these 256 single resistors are distributed across 16 rows, and after being connected in series, they are connected in an S-shape to the reference voltage ( Figure 2 Chinese V REF ) and grounding potential ( Figure 2 China G ND )between. Figure 2 For the sake of simplicity, the first, second, fifteenth, and sixteenth rows are shown as an example, with the corresponding row switches labeled X1, X2, X14, and X15, respectively.

[0089] Similarly, columns one, two, fifteen, and sixteen are shown as examples. Of the 256 individual resistors, each resistor is connected to a resistor switch at both ends, with adjacent individual resistors sharing a single resistor switch. Based on this design, each row has 16 individual resistors and 17 resistor switches Y0 to Y0. 16 Each single resistor is connected to one end of the row switch of the row containing it via two resistor switches at its two ends. The other end of the row switch is, for example... Figure 2 The left end of the central bank switch X15 outputs a dipole voltage V. EVEN And odd voltage V ODD To voltage selection submodule.

[0090] The high-order decoder generates row selection signals X1 to X16 through the high 4 bits of digital code to control the row switches X1 to X16. 15 The truth table of the row selection signal is shown in the table below, which determines whether the row is on or off.

[0091]

[0092] The low-order decoder generates column selection control signals Y0 to Y4 using the lower 4 bits of digital code. 16 ,Depend on Figure 2 It can be seen that for any single resistor, the resistor switches at both ends must be either on or off simultaneously to select one of the 16 single resistors in that row. Therefore, to simplify the control circuit, the lower four bits of the control signal can be decoded from binary code to the corresponding Gray code, and its truth table is shown in the table below:

[0093]

[0094] As shown in the table above, for any D8-12 digital code, its corresponding output signal will simultaneously turn on two adjacent resistor switches and turn off the remaining resistor switches, so that any single resistor in any row of 16 single resistors can be selected.

[0095] The structure of the voltage divider submodule described above can generate the odd voltage V corresponding to the digital codes D8 to D15 when M=8. ODD Couple voltage V EVEN Then the odd voltage V ODD Couple voltage V EVEN Output to the voltage selection submodule.

[0096] In one possible embodiment, the voltage selection module includes: a first selection switch, a second selection switch, a third selection switch, and a fourth selection switch; a first terminal of the first selection switch is connected to the first terminal of the third selection switch and receives an even voltage; a second terminal of the first selection switch is connected to the first terminal of the fourth selection switch and is connected to a low-order fine-tuning module, outputting an analog voltage to the low-order fine-tuning module; a second terminal of the third selection switch is connected to the second terminal of the second selection switch and is connected to the low-order fine-tuning module, outputting another analog voltage to the low-order fine-tuning module; a first terminal of the second selection switch is connected to the second terminal of the fourth selection switch and receives an odd voltage; wherein the first, second, third, and fourth selection switches are all controlled by the feature bit digital code D8.

[0097] Reference Figure 3 The diagram shows a preferred voltage selection module. The first and second selection switches are both represented by the signal D8 that controls them, while the third and fourth selection switches are both represented by the inverse signal of D8. express.

[0098] Therefore, when the output signal corresponding to the characteristic bit D8 is 1, the first and second selection switches are turned on, and the first analog voltage V1 is an odd voltage V. ODD The second analog voltage V2 is a dipole voltage V EVEN When the output signal corresponding to the feature bit D8 is 0, the third and fourth selection switches are turned on, and the first analog voltage V1 is an even voltage V. EVEN The second analog voltage V2 is the odd voltage V ODD .

[0099] Through the voltage divider submodule and voltage selection submodule described above, 8-bit coarse quantization is achieved, generating the coarse quantization results of first analog voltage V1 and second analog voltage V2. Then, the first analog voltage V1 and second analog voltage V2 are output to the low-bit fine quantization module.

[0100] In one possible embodiment, the low-order fine quantization module includes: a positive input module, a negative input module, and a folding and output module; the positive input module includes: an odd / even voltage input submodule, a sampling voltage input submodule, and an amplification submodule; see reference. Figure 4 The diagram shows a preferred low-level fine-tuning module in an embodiment of the present invention.

[0101] The odd / even voltage input submodule includes: multiple PMOS transistors and a first PMOS transistor M1; the sampling voltage input submodule includes: a third PMOS transistor M3. Multiple PMOS transistors, Figure 4 The dotted box in the middle indicates 10.

[0102] Multiple PMOS transistors are connected in parallel, with their sources connected to the sources of the first PMOS transistor M1 and the third PMOS transistor M3, respectively. The drains of the multiple PMOS transistors are connected to the drain of the first PMOS transistor M1 and the amplification submodule, respectively. The gate of each PMOS transistor is connected to two gate switches, receiving the first analog voltage V1 from two analog voltages through one gate switch and the second analog voltage V2 from two analog voltages through the other gate switch. The gate of the first PMOS transistor receives the second analog voltage V2.

[0103] The source of the third PMOS transistor M3 is connected to the drain of the second PMOS transistor M2. The gate of the second PMOS transistor M2 receives the bias voltage, and the source of the second PMOS transistor M2 receives the power supply voltage. The gate of the third PMOS transistor M3 receives the sampling voltage V.IN The drain of the third PMOS transistor M3 is connected to the amplification submodule.

[0104] The amplification submodule includes: a fourth PMOS transistor M4, a fifth PMOS transistor M5, a first resistor R1, and a second resistor R2. The source of the fourth PMOS transistor M4 is connected to the drain of the third PMOS transistor M3; the gate of the fourth PMOS transistor M4 is connected to the gate of the fifth PMOS transistor M5, and both are connected to ground G. ND connect.

[0105] The drain of the fourth PMOS transistor M4 is connected to the first terminal of the first resistor R1, and outputs the second comparison voltage V. OP The source of the fifth PMOS transistor M5 is connected to the drain of the first PMOS transistor M1 and the drains of the multiple PMOS transistors respectively; the drain of the fifth PMOS transistor M5 is connected to the first terminal of the second resistor R2 and outputs the first comparison voltage V. ON The second terminals of both the first resistor R1 and the second resistor R2 are connected to ground G. ND connect.

[0106] Figure 4 Multiple PMOS transistors are connected in parallel within the dashed box 10. The sources of each PMOS transistor are connected to the source of the first PMOS transistor M1 and the drain of the second PMOS transistor M2, respectively. The drains of all PMOS transistors are connected to the drain of the first PMOS transistor M1. The gate of each PMOS transistor is connected to two gate switches, receiving a first analog voltage V1 through one gate switch and a second analog voltage V2 through the other. Simultaneously, the gate of the first PMOS transistor M1 receives the second analog voltage V2.

[0107] Specifically, since the quantization bit depth is 8 bits (D7 to D0), the area within the dashed box 10 should contain 8 PMOS transistors. For simplicity, only 4 PMOS transistors are shown as an example. Each PMOS transistor has two gate switches, controlled by the digital codes D7 to D0 in the quantization bit depth. Figure 4 Taking the leftmost PMOS transistor within the dashed box 10 as an example: This PMOS transistor corresponds to the least significant bit D0 in the fine-tuning bit set. The first gate switch, one of the two gate switches connected to this PMOS transistor, closes when the least significant bit D0 is 1. Simultaneously, the second gate switch, the other of the two gate switches connected to this PMOS transistor, opens when the least significant bit D0 is 1. At this time, the PMOS transistor receives the first analog voltage V1. In the diagram, D0 represents the controlled condition of the first gate switch; that is, when D0 = 1, the first gate switch is closed, and when D0 = 1, its non-zero value is not specified. Therefore, the second gate switch is turned off.

[0108] Similarly, the first gate switch of the two gate switches connected to the PMOS transistor is open when the least significant bit D0 in the fine-grained bit set is 0. At the same time, the second gate switch of the two gate switches connected to the PMOS transistor is closed when the least significant bit D0 in the fine-grained bit set is 0. The PMOS transistor then receives the second analog voltage V2.

[0109] In this embodiment of the invention, the aspect ratio of the multiple PMOS transistors is determined by the number of bits corresponding to the finer gradation, so as to... Figure 4 Taking the leftmost PMOS transistor within dashed box 10 as an example: this PMOS transistor corresponds to the lowest bit D0 in the refinement bit depth, therefore its width-to-length ratio is W / L. The PMOS transistor immediately to the left of this PMOS transistor corresponds to the second lowest bit D1 in the refinement bit depth, therefore its width-to-length ratio is 2W / L. Similarly, the rightmost PMOS transistor in dashed box 10 corresponds to the highest bit D7 in the refinement bit depth, therefore its width-to-length ratio is 128W / L. The width-to-length ratio of the third PMOS transistor M3 is determined by the number of refinement bits. Since the refinement bit depth is 8 bits, 2... 8 =256, therefore the width-to-length ratio of the third PMOS transistor M3 is 256W / L.

[0110] Based on the current I generated by the odd / even voltage input submodule p The value should be related to the current I generated by the sampling voltage input submodule. n Based on the principle that the values ​​of are equal, we can derive the following formula:

[0111]

[0112]

[0113] in, μ p V is the carrier mobility, Cox is the gate oxide capacitance per unit area, and V is the capacitance per unit area. THP V is the threshold voltage of the PMOS transistor. pi (i = 1, 2, 3, 4, 5, 6, 7, 8) represents the gate voltages of multiple PMOS transistors.

[0114] From this, we can obtain the following formula:

[0115]

[0116]

[0117] Simplify to the following formula:

[0118]

[0119] Among them, g m =2*k*(V x -VBOT -|V THP |).

[0120] And because:

[0121]

[0122] Therefore:

[0123] Therefore, the following formula can be derived:

[0124]

[0125] This completes the function of fine quantification, that is, based on the above. Figure 2 , Figure 3 , Figure 4 The combined effect of the high-bit coarse quantization module and the low-bit fine quantization module, as shown, achieves 16-bit digital-to-analog conversion, taking 8-bit coarse quantization and 8-bit fine quantization as examples.

[0126] In addition, if higher accuracy is required, it is preferable to cascade several operational amplifiers between the low-order fine quantization module and the comparator to improve accuracy.

[0127] The aforementioned low-level fine-tuning module generates and outputs the first comparison voltage V. ON Second comparison voltage V OP After reaching the comparator, the data is compared according to the method described in the aforementioned workflow, and the resulting digital value Dout is output to the SAR LOGIC. Upon receiving this result Dout, the SAR LOGIC generates a new M-bit digital code and a new L-bit digital code, which are then output to the high-bit coarse quantization module and the low-bit fine quantization module, respectively. This process is repeated until the low-bit fine quantization module generates two comparison voltages V... ON and V OP Once the resolution requirement is approached and met, the comparator will stop outputting new digital results to the SAR LOGIC. This completes the entire analog-to-digital conversion process.

[0128] Based on the above analog-to-digital conversion circuit, this embodiment of the invention also provides an analog-to-digital converter, which includes: the analog-to-digital conversion circuit as described above.

[0129] In summary, in the analog-to-digital converter circuit of this invention, the number of individual resistors is no longer determined by the total number of bits in the digital quantity, but by the number of bits used for coarse quantization. For example, in a 16-bit DAC, the number of individual resistors is currently determined by 16 bits, resulting in 2^16 = 65536 individual resistors. However, if the coarse quantization bit depth of this invention is 8 bits, then the number of individual resistors is only 2^8 = 256. This undoubtedly greatly reduces the number of individual resistors. Since the number of resistor switches is determined by the number of individual resistors, fewer individual resistors naturally result in fewer resistor switches. This significantly reduces the physical area occupied by individual resistors and resistor switches, and the control logic becomes simpler due to the reduced number of resistor switches.

[0130] This invention employs a high-bit coarse quantization module for resistive voltage division in the high M-bit position and a low-bit fine quantization module for the low L-bit position, significantly reducing the number of resistor switches and individual resistors. This reduction in resistor switches simplifies the digital control logic, making the control logic simpler and the analog-to-digital converter (ADC) layout easier. Simultaneously, it achieves high-precision conversion with a high number of effective bits and good monotonicity. This further enhances the miniaturization feasibility of the ADC and makes it highly practical.

[0131] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0132] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0133] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. An analog-to-digital converter circuit, characterized in that, The analog-to-digital conversion circuit includes: SAR LOGIC, a high-bit coarse quantization module, a low-bit fine quantization module, and a comparator; The high-order voltage divider coarse quantization module receives the M-bit digital code output by the SAR LOGIC, divides the voltage to generate two analog voltages corresponding to the M-bit digital code, and outputs them to the low-order fine quantization module. The low-order fine quantization module receives two analog voltages, the L-bit digital code output by the SAR LOGIC, and the sampled voltage, generates two comparison voltages, and outputs them to the comparator. The comparator receives the two comparison voltages, generates a digital result, and outputs it to the SAR LOGIC. The SAR LOGIC receives the result digital value, generates a new M-bit digital code and a new L-bit digital code, and outputs them to the high-bit coarse quantization module and the low-bit fine quantization module, respectively, until the two comparison voltages generated by the low-bit fine quantization module are close to and meet the resolution requirements, at which point the comparator stops outputting the new result digital value to the SAR LOGIC. Wherein, the M-bit digital code is the high M-bit digital code in the corresponding target bit, the L-bit digital code is the low L-bit digital code in the corresponding target bit, and the target bit is the number of bits for analog-to-digital conversion by the analog-to-digital conversion circuit. If it is N bits, then N = M + L. Of the two comparison voltages, the first comparison voltage corresponds to the result of the digital-to-analog conversion after coarse and fine quantization, and the second comparison voltage corresponds to the result of the amplified sampling voltage.

2. The analog-to-digital converter circuit according to claim 1, characterized in that, The high-level voltage divider coarse quantization module includes: a voltage divider submodule and a voltage selection submodule; The voltage divider submodule receives the M-bit digital code, generates odd and even voltages, and outputs them to the voltage selection submodule. The voltage selection submodule receives the odd voltage and the even voltage, and selects and determines, based on the characteristic bit digital code, whether the first analog voltage is the odd voltage or the even voltage, and selects and determines whether the second analog voltage is the odd voltage or the even voltage. Wherein, when the first analog voltage is the odd voltage, the second analog voltage is the even voltage, and vice versa; The feature bit code is the least significant bit of the M-bit code.

3. The analog-to-digital converter circuit according to claim 2, characterized in that, The voltage divider submodule includes: multiple single resistors, multiple resistor switches, and multiple row switches; the number of the multiple single resistors is determined by M bits. The state of the plurality of resistor switches is controlled by the low-order bits of the M-bit digital code; The state of the multiple row switches is controlled by the high-order bits of the M-bit digital code; Multiple of the single resistors are connected in series in an S-shape between the reference voltage and ground potential; The number of rows and columns corresponding to the structure formed by multiple single resistors connected in series in an S-shape is determined by the number of bits of the target bit, and each row is provided with a row switch; Each of the multiple single resistors is connected to a resistor switch at both ends, and two adjacent single resistors share a resistor switch. Each single resistor is connected to one end of the row switch of the row in which it is located through two resistor switches at its two ends. The other end of the row switch outputs the even voltage and the odd voltage.

4. The analog-to-digital converter circuit according to claim 3, characterized in that, The output signal corresponding to the high-order digit code in the M-bit digital code determines the on / off state of each row switch among the multiple row switches. The output signal corresponding to the low-order digit code in the M-bit digital code determines the on / off state of each of the multiple resistor switches. In this system, the two resistor switches at both ends of each single resistor are controlled by the same signal value and are simultaneously turned on or off. The high-order bits of the M-bit digital code are decoded by a high-order decoder to obtain the corresponding output signal. The low-order bits of the M-bit digital code are decoded from binary code to the corresponding Gray code, and then decoded by a low-order decoder to obtain the corresponding output signal.

5. The analog-to-digital converter circuit according to claim 2, characterized in that, The voltage selection submodule includes: a first selection switch, a second selection switch, a third selection switch, and a fourth selection switch; The first terminal of the first selection switch is connected to the first terminal of the third selection switch and receives the dipole voltage; The second end of the first selection switch is connected to the first end of the fourth selection switch, and is also connected to the low-level fine quantization module. The second terminal of the third selection switch is connected to the second terminal of the second selection switch and is also connected to the low-level fine quantization module. The first terminal of the second selector switch is connected to the second terminal of the fourth selector switch and receives the odd voltage; The first selection switch, the second selection switch, the third selection switch, and the fourth selection switch are all controlled by the feature bit code.

6. The analog-to-digital converter circuit according to claim 5, characterized in that, When the value of the output signal corresponding to the feature bit digital code is 1, the first selection switch and the second selection switch are turned on, the first analog voltage is the odd voltage, and the second analog voltage is the even voltage; When the value of the output signal corresponding to the characteristic bit digital code is 0, the third selection switch and the fourth selection switch are turned on, the first analog voltage is the even voltage, and the second analog voltage is the odd voltage.

7. The analog-to-digital converter circuit according to claim 1, characterized in that, The low-order fine quantization module includes: an odd-even voltage input submodule, a sampling voltage input submodule, and an amplification submodule; The odd / even voltage input submodule includes: multiple PMOS transistors and a first PMOS transistor; The sampling voltage input submodule includes: a third PMOS transistor; Multiple PMOS transistors are connected in parallel, and their sources are respectively connected to the source of the first PMOS transistor and the source of the third PMOS transistor. The drains of the plurality of PMOS transistors are connected to the drain of the first PMOS transistor and the amplification submodule, respectively. The gate of each of the plurality of PMOS transistors is connected to two gate switches. The first analog voltage of the two analog voltages is received through one gate switch, and the second analog voltage of the two analog voltages is received through the other gate switch. The gate of the first PMOS transistor receives the second analog voltage; The source of the third PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the second PMOS transistor receives a bias voltage, and the source of the second PMOS transistor receives a power supply voltage. The gate of the third PMOS transistor receives the sampling voltage; The drain of the third PMOS transistor is connected to the amplification submodule.

8. The analog-to-digital converter circuit according to claim 7, characterized in that, The amplification submodule includes: a fourth PMOS transistor, a fifth PMOS transistor, a first resistor, and a second resistor; The source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor. The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, and both are connected to ground. The drain of the fourth PMOS transistor is connected to the first terminal of the first resistor and outputs the second comparison voltage. The source of the fifth PMOS transistor is connected to the drain of the first PMOS transistor and the drains of the plurality of PMOS transistors, respectively. The drain of the fifth PMOS transistor is connected to the first terminal of the second resistor and outputs the first comparison voltage; The second end of the first resistor and the second end of the second resistor are both connected to the ground terminal.

9. The analog-to-digital converter circuit according to claim 1, characterized in that, Several operational amplifiers are cascaded between the low-order fine quantization module and the comparator.

10. An analog-to-digital converter, characterized in that, The analog-to-digital converter includes: an analog-to-digital conversion circuit as described in any one of claims 1-9.

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