A chopping timing control method and system for a reference voltage generator of a sigma-delta ADC

Abstract

The present invention relates to a chopping timing control method and system for a reference voltage generator of a sigma-delta ADC, including connecting an output end of the sigma-delta ADC to a first end of an exclusive-NOR operator; connecting an output end of a first timing generator to a second end of the exclusive-NOR operator; an output of the exclusive-NOR operator being a chopping timing control signal; using the chopping timing control signal as a clock signal of the reference voltage generator; and using an output of the reference voltage generator as a reference voltage of the sigma-delta ADC. The present invention avoids the problem of reduced signal-to-noise ratio caused by the intermodulation of the chopping ripple of the amplifier used for the reference voltage and the quantizer data stream; and avoids the residual offset voltage generated by the offset voltage of the amplifier through a second-order modulator.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chopping timing control method and system for a reference voltage generator for a sigma-delta ADC. Background Art

[0002] A low-noise voltage reference is a crucial component of high-precision Sigma Delta analog-to-digital converters (ΣΔADCs). Using an external low-noise reference source in conjunction with a filter capacitor can easily achieve an extremely low-noise reference voltage. This is the most common solution, but it also comes with a higher cost.

[0003] like Figure 1 Using an on-chip reference voltage and a chopper amplifier as the buffer output can significantly reduce system cost. The chopper amplifier modulates the amplifier's low-frequency noise (including low-frequency offset voltage) to near the chopping frequency and its harmonics, ensuring extremely low noise levels within the low-frequency signal bandwidth.

[0004] However, this traditional chopping operation cannot be directly applied to ΣΔADCs. A ΣΔADC feeds the quantizer's output level back to the input integration stage. Depending on whether the output level is high or low, it determines whether the reference voltage is integrated in an anti-phase or non-phase manner. This feedback selection essentially multiplies the quantizer's output signal stream (mathematically, the +1 and -1 signal streams) by the reference voltage, thus creating modulation. However, the ΣΔADC's quantizer output contains quantization noise that has been noise-shaped by the ΣΔADC's modulator. This noise component is no longer white noise, but rather a shaped noise spectrum with higher frequencies exhibiting greater noise components. If a traditional chopper amplifier is used as the reference voltage buffer output stage, noise near the chopping frequency and its harmonics will intermodulate with the high-frequency quantization noise of the quantizer's output data stream. This intermodulation into the low-frequency signal band reduces the signal-to-noise ratio, and therefore the accuracy of the ADC.

[0005] On the other hand, the traditional chopper amplifier timing is also not conducive to second-order or higher-order ΣΔ ADCs. For ΣΔ ADCs of more than second order, the output of the first-stage integrator is used as the input of the second-stage integrator. The traditional chopper timing is directly controlled by a clock with a certain frequency, and the two phases of the clock respectively turn on the two channels of the chopper. In this way, at the end of each chopper period, the contribution of the offset voltage of the amplifier to the output of the first-stage integrator is 0. This is because in the first half cycle of the chopping, the positive-phase offset voltage of the amplifier is stored by the integrator, and at the end of the second half cycle, the negative-phase offset voltage just cancels out the stored positive-phase offset voltage. However, this means that except for the output being 0 at the end of the chopper period, the output of the first-stage integrator is the positive-phase offset voltage value at other times, and this offset voltage will be continuously accumulated by the second-stage integrator without being canceled, and finally is equivalent to the reference voltage with the residual offset voltage of the amplifier superimposed. When the oversampling rate is smaller, the equivalent gain of the first-stage integrator is small, and the equivalent input residual offset voltage is larger.

[0006] Therefore, it is necessary to design a suitable chopper control method to avoid the above problems. Summary of the Invention

[0007] In order to solve the above problems, the present invention provides a chopper timing control method and system for a reference voltage generator of a sigma-delta ADC.

[0008] On the one hand, the present invention provides a chopper timing control method for a reference voltage generator of a sigma-delta ADC, characterized in that: connecting the output end of the sigma-delta ADC to the first end of an exclusive-NOR operator; connecting the output end of a first timing generator to the second end of the exclusive-NOR operator; the output of the exclusive-NOR operator is a chopper timing control signal; using the chopper timing control signal as the clock signal of the reference voltage generator; using the output of the reference voltage generator as the reference voltage of the sigma-delta ADC; wherein, the output signal of the first timing generator is Y[n], n is an integer sequence representing discrete time, and n is a natural number; the Y[n] satisfies: when 4*m*k ≤ n < (4*m + 1)k or (4*m + 3)*k ≤ n < (4*m + 4)k, Y[n] = 1; when (4*m + 1)*k ≤ n < (4*m + 3)k, Y[n] = -1; where m and k are any positive integers.

[0009] Further, the sigma-delta ADC includes at least two stages of integrators.

[0010] Further, the reference voltage generator includes a first chopper and a first amplifier; the chopping timing control signal serves as the clock signal of the first chopper and the bias voltage of the first amplifier; the reference voltage is connected to the first input terminal of the first chopper; the output terminal of the first amplifier is connected to the second input terminal of the first chopper; the first amplifier amplifies the output signal of the first chopper; the output of the first amplifier is the output of the reference voltage generator.

[0011] Further, m = 1 and k = 1.

[0012] Further, when m = 1 and k = 1, the chopping timing control signal is generated by the following structure: a first D flip-flop, a second D flip-flop, a first AND operator, a second AND operator, a first OR operator; the clock signal is connected to the clock terminals of the first D flip-flop and the second D flip-flop; the power-on reset signal is connected to the R terminal of the first D flip-flop and the S terminal of the second D flip-flop; the Qb terminal of the first D flip-flop is connected to the D terminal of the first D flip-flop and the second terminal of the first AND operator; the Q terminal of the first D flip-flop is connected to the first terminal of the second AND operator; the Qb terminal of the second D flip-flop is connected to the second terminal of the second AND operator; the Q terminal of the second D flip-flop is connected to the first terminal of the first AND operator; the output terminals of the first AND operator and the second AND operator are connected to the input terminal of the first OR operator; the Q terminal output of the second D flip-flop is the chopping timing control signal.

[0013] On the other hand, the present invention also discloses a chopping timing control system for a reference voltage generator of a sigma-delta ADC, characterized in that: the system includes a sigma-delta ADC, a chopping timing controller, and a reference voltage generator; the chopping timing controller includes an exclusive-NOR operator; the output terminal of the sigma-delta ADC is connected to the first terminal of the exclusive-NOR operator; the output terminal of a first timing generator is connected to the second terminal of the exclusive-NOR operator; the output of the exclusive-NOR operator is the chopping timing control signal; the chopping timing control signal is used as the clock signal of the reference voltage generator; the output of the reference voltage generator is used as the reference voltage of the sigma-delta ADC; wherein, the output signal of the first timing generator is Y[n], n is an integer sequence representing discrete time, and n is a natural number; the Y[n] satisfies: when 4*m*k ≤ n < (4*m + 1)k or (4*m + 3)*k ≤ n < (4*m + 4)k, Y[n] = 1; when (4*m + 1)*k ≤ n < (4*m + 3)k, Y[n] = -1; where m and k are any positive integers.

[0014] Further, the sigma-delta ADC includes at least two stages of integrators.

[0015] Further, the reference voltage generator includes a first chopper and a first amplifier; the chopping timing control signal serves as the clock signal of the first chopper and the bias voltage of the first amplifier; the reference voltage is connected to the first input terminal of the first chopper; the output terminal of the first amplifier is connected to the second input terminal of the first chopper; the first amplifier amplifies the output signal of the first chopper; the output of the first amplifier is the output of the reference voltage generator.

[0016] Further, m = 1 and k = 1.

[0017] Further, when m = 1 and k = 1, the chopping timing control signal is generated by the following structure: a first D flip-flop, a second D flip-flop, a first AND operator, a second AND operator, a first OR operator; the clock signal is connected to the clock terminals of the first D flip-flop and the second D flip-flop; the power-on reset signal is connected to the R terminal of the first D flip-flop and the S terminal of the second D flip-flop; the Qb terminal of the first D flip-flop is connected to the D terminal of the first D flip-flop and the second terminal of the first AND operator; the Q terminal of the first D flip-flop is connected to the first terminal of the second AND operator; the Qb terminal of the second D flip-flop is connected to the second terminal of the second AND operator; the Q terminal of the second D flip-flop is connected to the first terminal of the first AND operator; the output terminals of the first AND operator and the second AND operator are connected to the input terminal of the first OR operator; the Q terminal output of the second D flip-flop is the chopping timing control signal.

[0018] The technical solution provided by the present invention avoids the problem of signal-to-noise ratio reduction caused by the intermodulation of the chopping ripple (resulting from low-frequency noise including offset voltage) of the amplifier used for the reference voltage and the quantizer data stream; and avoids the residual offset voltage generated by the offset voltage of the amplifier through the second-order modulator. Description of the Drawings

[0019] Figure 1 , the block diagram of the Sigma-Delta ADC of the integrated reference voltage generator in the prior art;

[0020] Figure 2 , the circuit block diagram including the chopping timing controller;

[0021] Figure 3 , a timing controller when m = 1 and k = 1 is selected;

[0022] Figure 4 , Figure 3 The waveform diagram under different Q[n] signals. Detailed implementation manners

[0023] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and not to limit the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present invention without making creative efforts fall within the scope of protection of the present invention.

[0024] Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present invention. For those of ordinary skill in the art, the present invention can also be applied to other similar scenarios based on these drawings without making creative efforts. In addition, it can also be understood that although the efforts made in such a development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed by the present invention, some design, manufacturing or production changes based on the technical content disclosed by the present invention are only conventional technical means and should not be understood that the content disclosed by the present invention is insufficient.

[0025] Referring to "embodiments" in the present invention means that the specific features, structures or characteristics described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art explicitly and implicitly understand that the embodiments described in the present invention can be combined with other embodiments without conflict.

[0026] Unless otherwise defined, the technical terms or scientific terms involved in the present invention should have the ordinary meanings understood by those with ordinary skills in the technical field to which the present invention belongs. The words such as "a", "one", "kind", "the" and the like involved in the present invention do not indicate a limitation in quantity and may represent a single or plural number.

[0027] In the prior art, the traditional solution to solve the intermodulation effect problem is to perform low-pass filtering on the output voltage of the reference voltage generator to filter out the low-frequency noise and low-frequency offset voltage modulated to the vicinity of the chopping and its harmonics. In this way, the noise energy intermodulated to the low frequency is also very small and can be ignored.

[0028] However, the above method requires a relatively high filter cost. By performing a time-domain analysis on the intermodulation effect between chopping noise and Sigma-delta ADC quantization noise, corresponding time-domain solutions can be obtained. The high or low level of the chopping clock respectively determines whether the low-frequency noise of the amplifier is output to the ΣΔADC in-phase or anti-phase, that is, in the frequency domain, the low-frequency noise is modulated to the vicinity of the chopping frequency and its harmonics. In each integration phase, the circuit feeds back the output level of the ΣΔADC quantizer to the input integration stage. According to the high or low of the output level, it determines whether to perform anti-phase integration or in-phase integration on the reference voltage. That is, in each integration phase, whether the noise actually accumulated in the integrator is in-phase or anti-phase is jointly determined by the chopping phase and the output level of the quantizer. If within a certain period of time, the number of in-phase and anti-phase noises accumulated is exactly equal, then the overall contribution of these noises to the ΣΔADC is 0, that is, there is no longer intermodulation noise. However, when the chopping clock is a clock that is not related to the output data of the quantizer, the number of in-phase or anti-phase noises accumulated in the integrator is obviously not necessarily equal, so the contribution of the final noise cannot be canceled.

[0029] The present invention improves the chopping timing to make it follow the change of the quantizer output level. The designed chopping clock modulation algorithm can ensure that within one ADC conversion cycle, the number of in-phase or anti-phase noises accumulated in the input-stage integrator is equal, thereby eliminating the intermodulation noise.

[0030] Although the above algorithm can ensure that the contribution of the low-frequency noise of the reference voltage buffer to the first-stage integrator is 0, it still cannot guarantee that there is no noise contribution to the second-stage integrator. This is because the second-stage integrator accumulates the output signal of the first-stage integrator. For example, assume that one conversion cycle contains 512 integration phases. The first-stage integrator accumulates 256 in-phase offset voltages and 256 anti-phase offset voltages respectively. Although the final output of the first-stage integrator does not contain this offset voltage, the outputs of its first 511 cycles are all in-phase offset voltages, and the total contribution of these voltages to the second-stage integrator is also in-phase, that is, in-phase residual offset voltage is accumulated.

[0031] In order to solve the problems existing in the prior art, in one embodiment, a chopping timing control method for a reference voltage generator of a sigma-delta ADC is disclosed.

[0032] Such as Figure 2As shown, connect the output terminal of the sigma-delta ADC to the first terminal of the exclusive-NOR operator; connect the output terminal of the first timing generator to the second terminal of the exclusive-NOR operator; the output of the exclusive-NOR operator is the chopping timing control signal; use the chopping timing control signal as the clock signal of the reference voltage generator; use the output of the reference voltage generator as the reference voltage of the sigma-delta ADC.

[0033] To ensure that the low-frequency noise (including low-frequency offset voltage) of the reference voltage buffer does not cause errors to the second-stage integrator, the designed timing satisfies the following characteristics:

[0034] Denote the designed timing function for controlling chopping as CH[n], where n is an integer sequence representing discrete time, n≥0. When CH[n] is 1, it means turning on the in-phase channel of the chopper; when CH[n]=-1, it means turning on the anti-phase channel of the chopper. Denote the output data sequence of the quantizer as Q[n]. When Q[n]=1, the integrator performs anti-phase integration on the reference voltage; when Q[n]=-1, the integrator performs in-phase integration on the reference voltage. Y[n] is the product of CH[n] and Q[n]. Design a suitable CH[n] such that the sequence Y[n] satisfies:

[0035] When 4*m*k≤n<(4*m + 1)k or (4*m + 3)*k≤n<(4*m + 4)k, Y[n]=1 (or -1);

[0036] When (4*m + 1)*k≤n<(4*m + 3)k, Y[n]=-1 (or 1);

[0037] where m and k are arbitrary positive integers, and the period of Y[n] is 4*k.

[0038] It can be proved that

[0039]

[0040] That is, at the end of every 4*k cycles, the contribution of the low-frequency noise of the buffer to the outputs of the first-stage integrator and the second-stage integrator is 0.

[0041] The method to implement such CH[n] is as follows: First step, design the desired Y[n] timing generator, where 1 corresponds to digital logic high level and -1 corresponds to digital logic low level; Second step, perform an exclusive-NOR logic operation on Y[n] and Q[n] to obtain CH[n].

[0042] In a further embodiment, the reference voltage generator is a chopping amplifier.

[0043] As Figure 2As shown, the reference voltage generator includes a first chopper and a first amplifier; the chopping timing control signal serves as the clock signal of the first chopper and the clock signal of the internal chopper of the first amplifier; the reference voltage is connected to the first input terminal of the first chopper; the output terminal of the first amplifier is connected to the second input terminal of the first chopper; the first amplifier amplifies the output signal of the first chopper; the output of the first amplifier is the output of the reference voltage generator.

[0044] Preferably, m = 1 and k = 1 are selected. At this time, Y[n] corresponds to a logic sequence of 1001 (or 0110) with a period of 4. Figure 3 It is the specific implementation of the corresponding timing controller. Specifically, it includes:

[0045] A first D flip-flop, a second D flip-flop, a first AND operator, a second AND operator, a first OR operator; the clock signal is connected to the clock terminals of the first D flip-flop and the second D flip-flop; the power-on reset signal is connected to the R terminal of the first D flip-flop and the S terminal of the second D flip-flop; the Qb terminal of the first D flip-flop is connected to the D terminal of the first D flip-flop and the second terminal of the first AND operator; the Q terminal of the first D flip-flop is connected to the first terminal of the second AND operator; the Qb terminal of the second D flip-flop is connected to the second terminal of the second AND operator; the Q terminal of the second D flip-flop is connected to the first terminal of the first AND operator; the output terminals of the first AND operator and the second AND operator are connected to the input terminal of the first OR operator; the Q terminal output of the second D flip-flop is the chopping timing control signal.

[0046] As Figure 4 shown, it is the waveform diagram of the controller under different Q[n] signals.

[0047] In another implementation, as Figure 2As shown in the figure, the present invention also discloses a chopping timing control system for a reference voltage generator of a sigma-delta ADC. The system includes a sigma-delta ADC, a chopping timing controller, and a reference voltage generator. The chopping timing controller includes an exclusive-NOR operator. The output end of the sigma-delta ADC is connected to the first end of the exclusive-NOR operator. The output end of the first timing generator is connected to the second end of the exclusive-NOR operator. The output of the exclusive-NOR operator is a chopping timing control signal. The chopping timing control signal is used as the clock signal of the reference voltage generator. The output of the reference voltage generator is used as the reference voltage of the sigma-delta ADC. Wherein, the output signal of the first timing generator is Y[n], n is an integer sequence representing discrete time, and n is a natural number. The Y[n] satisfies: when 4*m*k ≤ n < (4*m + 1)*k or (4*m + 3)*k ≤ n < (4*m + 4)*k, Y[n] = 1; when (4*m + 1)*k ≤ n < (4*m + 3)*k, Y[n] = -1. Where m and k are any positive integers.

[0048] As Figures 3 - 4 shown, for further optimization of the chopping timing control system for the reference voltage generator of the sigma-delta ADC, its specific principle is the same as that of the aforementioned chopping timing control method for the reference voltage generator of the sigma-delta ADC, and will not be elaborated here. All implementation manners of the aforementioned chopping timing control method for the reference voltage generator of the sigma-delta ADC can be based on Figures 2 - 4 being applied to this embodiment.

[0049] In the description of this specification, the descriptions of terms such as "one embodiment", "some embodiments", "specific embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or instance. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0050] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A chopping timing control method for a reference voltage generator of a sigma-delta ADC, characterized in that: Connect the output terminal of the sigma-delta ADC to the first terminal of the exclusive-NOR operator; Connect the output terminal of the first timing generator to the second terminal of the exclusive-NOR operator; The output of the exclusive-NOR operator is the chopping timing control signal; Use the chopping timing control signal as the clock signal of the reference voltage generator; Use the output of the reference voltage generator as the reference voltage of the sigma-delta ADC; Wherein, the output signal of the first timing generator is Y[n], n is an integer sequence representing discrete time, and n is a natural number; The Y[n] satisfies: When 4*m*k ≤ n < (4*m + 1)*k or (4*m + 3)*k ≤ n < (4*m + 4)*k, Y[n] = 1; when (4*m + 1)*k ≤ n < (4*m + 3)*k, Y[n] = -1; where m and k are any positive integers.

2. The chopping timing control method for the reference voltage generator of the sigma-delta ADC according to claim 1, characterized in that: The sigma-delta ADC includes at least two stages of integrators.

3. The chopping timing control method of the reference voltage generator for sigma-delta ADC according to claim 2, wherein: The reference voltage generator includes a first chopper and a first amplifier; The chopping timing control signal serves as the clock signal of the first chopper and the clock signal of the internal chopper of the first amplifier; The reference voltage is connected to the first input terminal of the first chopper; The output terminal of the first amplifier is connected to the second input terminal of the first chopper; The first amplifier amplifies the output signal of the first chopper; The output of the first amplifier is the output of the reference voltage generator.

4. The chopping timing control method for the reference voltage generator of the sigma-delta ADC according to claim 1, characterized in that: m = 1, k = 1.

5. The chopping timing control method for a reference voltage generator of a sigma-delta ADC according to claim 4, wherein: When m = 1, k = 1, the chopping timing control signal is generated by the following structure: a first D flip-flop, a second D flip-flop, a first AND operator, a second AND operator, a first OR operator; The clock signal is connected to the clock terminals of the first D flip-flop and the second D flip-flop; The power-on reset signal is connected to the R terminal of the first D flip-flop and the S terminal of the second D flip-flop; The Qb terminal of the first D flip-flop is connected to the D terminal of the first D flip-flop and the second terminal of the first AND operator; The Q terminal of the first D flip-flop is connected to the first terminal of the second AND operator; The Qb terminal of the second D flip-flop is connected to the second terminal of the second AND operator; The Q terminal of the second D flip-flop is connected to the first terminal of the first AND operator; The output terminals of the first AND operator and the second AND operator are connected to the input terminal of the first OR operator; The output of the Q terminal of the second D flip-flop is the chopping timing control signal.

6. A chopping timing control system for a reference voltage generator of a sigma-delta ADC, characterized in that: The system includes a sigma-delta ADC, a chopping timing controller, and a reference voltage generator; The chopping timing controller includes an exclusive-NOR operator; The output terminal of the sigma-delta ADC is connected to the first terminal of the exclusive-NOR operator; The output terminal of the first timing generator is connected to the second terminal of the exclusive-NOR operator; The output of the exclusive-NOR operator is the chopping timing control signal; Use the chopping timing control signal as the clock signal of the reference voltage generator; Use the output of the reference voltage generator as the reference voltage of the sigma-delta ADC; Among them, the output signal of the first timing generator is Y[n], where n is an integer sequence representing discrete time and n is a natural number; The Y[n] satisfies: When 4*m*k ≤ n < (4*m + 1)k or (4*m + 3)*k ≤ n < (4*m + 4)k, Y[n] = 1; when (4*m + 1)*k ≤ n < (4*m + 3)k, Y[n] = -1; where m and k are any positive integers.

7. The chopping timing control system of the reference voltage generator for sigma-delta ADC according to claim 6, wherein the sigma-delta ADC includes at least two stages of integrators.

8. The chopping timing control system for the reference voltage generator of the sigma-delta ADC according to claim 7, characterized in that: The reference voltage generator includes a first chopper and a first amplifier; The chopping timing control signal serves as the clock signal of the first chopper and the clock signal of the internal chopper of the first amplifier; The reference voltage is connected to the first input end of the first chopper; The output end of the first amplifier is connected to the second input end of the first chopper; The first amplifier amplifies the output signal of the first chopper; The output of the first amplifier is the output of the reference voltage generator.

9. The chopping timing control system of the reference voltage generator for the sigma-delta ADC according to claim 6, characterized in that: m = 1, k = 1.

10. The chopping timing control system for the reference voltage generator of the sigma-delta ADC according to claim 9, characterized in that: When m = 1 and k = 1, the chopping timing control signal is generated by the following structure: a first D flip-flop, a second D flip-flop, a first AND operator, a second AND operator, a first OR operator; The clock signal is connected to the clock terminals of the first D flip-flop and the second D flip-flop; The power-on reset signal is connected to the R end of the first D flip-flop and the S end of the second D flip-flop; The Qb end of the first D flip-flop is connected to the D end of the first D flip-flop and the second end of the first AND operator; The Q end of the first D flip-flop is connected to the first end of the second AND operator; The Qb end of the second D flip-flop is connected to the second end of the second AND operator; The Q end of the second D flip-flop is connected to the first end of the first AND operator; The output ends of the first AND operator and the second AND operator are connected to the input end of the first OR operator; The Q end output of the second D flip-flop is the chopping timing control signal.

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