Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a trench, a first conductive layer, a second conductive layer, a third conductive layer, a source region and a drain region, a bit line contact, and a storage node contact. The trench is disposed in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on a top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and is electrically connected to the second conductive layer. The source region and the drain region are disposed in the substrate and are disposed on opposite sides of the first conductive layer. The bit line contact is disposed on one of the source region and the drain region, and the storage node contact is disposed on the other of the source region and the drain region.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods for forming them, and particularly to semiconductor structures with word line structures made of materials with different work functions and methods for forming them. Background Technology

[0002] As semiconductor devices miniaturize, memory sizes continue to shrink, leading to the development of buried word line memory devices to increase integration and improve performance. However, the continuous reduction in size increases capacitive coupling between adjacent components or interconnect structures and / or causes leakage current problems, adversely affecting memory performance. Therefore, it is necessary to seek solutions to these problems in the structure and fabrication methods of memory devices. Summary of the Invention

[0003] In view of the above problems, the present invention improves the electrical characteristics of the semiconductor structure by setting up a word line structure with materials of different work functions and adjusting the positions of the materials of different work functions in the word line structure, thereby adjusting the relative positions of the materials with different work functions in the semiconductor structure. For example, a material with a low work function is set at the location where leakage current needs to be avoided, while a material with a high work function is set at the location where conduction current needs to be increased, so as to simultaneously avoid leakage current and increase conduction current.

[0004] The aforementioned semiconductor structure includes: a substrate, a trench, a first conductive layer, a second conductive layer, a third conductive layer, a source region and a drain region, bit line contacts, and storage node contacts. The trench is disposed in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on the top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and is electrically connected to the second conductive layer. The source region and the drain region are disposed in the substrate and are located on opposite sides of the first conductive layer. Bit line contacts are disposed on one of the source region and the drain region, and storage node contacts are disposed on the other of the source region and the drain region.

[0005] The aforementioned method for forming a semiconductor structure includes: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer; forming a sacrificial layer on the second conductive layer; partially removing the sacrificial layer; using the remaining portion of the sacrificial layer as an etching mask to etch the second conductive layer and expose a portion of the second conductive layer; and forming a third conductive layer on the second conductive layer and covering the exposed portion of the second conductive layer. Attached Figure Description

[0006] Figure 1 This is a circuit layout diagram of a semiconductor structure provided according to some embodiments of the present invention.

[0007] Figures 2-8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B and Figure 18 This is a cross-sectional schematic diagram of the formation of a semiconductor structure at various stages, according to some embodiments of the present invention. Figure 11C This is a circuit layout diagram of a semiconductor structure provided according to some embodiments of the present invention.

[0008] Figure 19 This is a cross-sectional schematic diagram of a semiconductor structure provided according to other embodiments of the present invention.

[0009] Explanation of icon numbers:

[0010] 1,2: Semiconductor Structure

[0011] 100:Substrate

[0012] 101: First doped region

[0013] 102: Second doped region

[0014] 110: Isolation Structure

[0015] 111: Gate dielectric layer

[0016] 120: Etching Mask

[0017] 121: First trench

[0018] 122: Second trench

[0019] 130: First Liner

[0020] 140: First conductive layer

[0021] 141: Second Liner

[0022] 150: Second conductive layer

[0023] 160: First dielectric layer

[0024] 161: Sacrificial Layer

[0025] 161a: Part 1

[0026] 161b: Part Two

[0027] 162: Photoresist pattern

[0028] 163: Implantation Process

[0029] 164: Etching Process

[0030] 170: Third conductive layer

[0031] 180: Second dielectric layer

[0032] AA: Active Region

[0033] BC: Bit line contact material

[0034] BL: Bitline

[0035] CC: Storage node contact material

[0036] D1: First Direction

[0037] D2: Second Direction

[0038] P: Current path

[0039] T1: First thickness

[0040] T2: Second thickness

[0041] T3: Third Thickness

[0042] WL: Word Line Detailed Implementation

[0043] Figure 1 This is a schematic diagram of the circuit layout of a semiconductor structure according to some embodiments of the present invention. The semiconductor structure includes: a substrate 100, an isolation structure 110, an active area AA, a bit line BL, a word line WL, a storage node contact CC, and a bit line contact BC.

[0044] In some embodiments, there may be multiple bit lines BL disposed on the substrate 100. Each bit line BL extends along a first direction D1, and adjacent bit lines BL are arranged at a distance in a second direction D2. There may be multiple word lines WL disposed in the substrate 100. Each word line WL extends along the second direction D2, and adjacent word lines WL are arranged at a distance in the first direction D1. The word lines WL may be buried word lines. For example, the gate structure of the word line WL may be lower than the top surface of the substrate 100.

[0045] In some embodiments, an isolation structure 110 may be formed in the substrate 100 to define the extent of the active region AA and to separate adjacent active regions AA from each other. Multiple active regions AA may be formed in the substrate 100. Each active region AA extends generally along a direction having an angle with the first direction D1.

[0046] like Figure 1 As shown, each active region AA spans two word lines WL and one bit line BL. Each active region AA has an overlapping area with its corresponding bit line BL, as well as non-overlapping areas on either side of the overlapping area. Within each active region AA, there are storage node contacts CC in the two aforementioned non-overlapping areas.

[0047] In some embodiments, two storage node contacts CC corresponding to an active region AA are respectively disposed outside two word lines WL passing through this active region AA. The storage node contacts CC may contact a capacitor, and are therefore also referred to as capacitor contacts. The storage node contacts CC are located on the substrate 100, and each storage node contact CC is located between two adjacent bit lines BL and between two adjacent word lines WL.

[0048] In some embodiments, each active region AA has a bit line contact BC at the region overlapping with the corresponding bit line BL. Each bit line BL, as it crosses its corresponding word line WL, can be electrically connected to the corresponding doped region located between two word lines WL using the bit line contact BC, for example, as follows... Figure 18 The first doped region 101 is shown.

[0049] like Figure 1 As shown, the semiconductor structure of the present invention may include memory cells arranged in a 3x2 configuration. An active word line and a passing word line may be respectively disposed on both sides of a target word line in the semiconductor structure of the present invention.

[0050] According to some embodiments of the present invention, Figures 2-8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B and Figure 18 This is a schematic cross-sectional view showing the formation of semiconductor structure 1 at various stages, and Figure 11C This is a schematic diagram of the circuit layout of the provided semiconductor structure. Among them, Figures 2-8 , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A It is provided along such Figure 1 The diagram shows a cross-sectional view of line segment AA', and Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B It is provided along such Figure 1 The diagram shows a cross-sectional view captured by line segment BB'.

[0051] Reference Figure 2 In some embodiments, a substrate 100 is provided, and an isolation structure 110 is formed in the substrate 100.

[0052] Reference Figure 3 A patterned etching mask 120 is formed on the substrate 100. (Refer to...) Figure 4 Continuing from the above, an etching process is performed to form a first trench 121 in the substrate 100 and between the isolation structures 110, and a second trench 122 in the isolation structure 110. In some embodiments, the first trench 121 is used to accommodate subsequently formed active word lines, and the second trench 122 is used to accommodate subsequently formed pass word lines. Because the etching selectivity ratios of the substrate 100 and the isolation structure 110 are different, the first trench 121 and the second trench 122 have different depths. For example, the depth of the first trench 121 is less than the depth of the second trench 122.

[0053] Reference Figure 5 A gate dielectric layer 111 is formed in the first trench 121 and the second trench 122. In some embodiments, the gate dielectric layer 111 may include oxides, nitrides, oxynitrides, high-k materials, or combinations thereof.

[0054] Reference Figure 6 In the first trench and the second trench, a first liner 130 is conformally formed on the gate dielectric layer 111. In some embodiments, the first liner 130 is formed along the top and side surfaces of the etch mask 120 and the surface of the gate dielectric layer 111. In some embodiments, the first liner 130 may be titanium nitride (TiN), tungsten (W), or a combination thereof. Since the first liner 130 is located between the first trench 121 and the subsequently formed first conductive layer, and between the second trench 122 and the subsequently formed first conductive layer, the first liner 130 can serve as a buffer layer to reduce stress concentration, an adhesive layer to enhance adhesion, and / or a diffusion barrier layer to improve the reliability of the subsequently formed semiconductor structure. In some embodiments, the first liner 130 may be omitted.

[0055] In some embodiments, continuing from the above, a first conductive layer 140 is formed on the first substrate 130, and the first conductive layer 140 fills as shown in the figure. Figure 5 The first trench and the second trench are shown. In some embodiments, the first conductive layer 140 may be tungsten. In some embodiments, the first liner 130 and the first conductive layer 140 are formed of the same material. For example, the first liner 130 and the first conductive layer 140 are formed of tungsten.

[0056] Reference Figure 7 The first conductive layer 140 and the first substrate 130 are etched back so that the top surfaces of the first conductive layer 140 and the first substrate 130 are substantially coplanar. In some embodiments, the top surfaces of the first conductive layer 140 and the first substrate 130 are lower than the top surface of the substrate 100 to expose a portion of the side surface of the gate dielectric layer 111. In some embodiments, the depth of the etch-back process can be controlled by the etch-back process parameters, thereby controlling the thickness of the first conductive layer 140.

[0057] Reference Figure 8 A second liner 141 is formed on the first conductive layer 140 and the first liner 130. The materials and processes used to form the second liner 141 may be the same as or different from those used to form the first liner 130. In some embodiments, both the second liner 141 and the first liner 130 are titanium nitride. The first liner 130 and the second liner 141 together surround the first conductive layer 140.

[0058] In some embodiments, a second liner 141 is located between the first conductive layer 140 and a subsequently formed second conductive layer, and also between the first conductive layer 140 and a subsequently formed third conductive layer. In some embodiments, the second liner 141 is continuous and can be formed simultaneously. In some embodiments, the top surface of the second liner 141 is substantially flat. In some embodiments, the second liner 141 is used to improve the adhesion between the second conductive layer and / or the subsequently formed third conductive layer and the first conductive layer 140, thereby improving the reliability of the semiconductor structure. In some embodiments, the second liner 141 may be omitted.

[0059] Reference Figure 9A and Figure 9B A second conductive layer 150 is formed on the top surface of the first conductive layer 140, for example, on the second substrate 141. In some embodiments, the second conductive layer 150 may be polysilicon, either undoped or boron (B) doped. In some embodiments, different concentrations of dopants may be doped into the second conductive layer 150 according to the electrical characteristics required by the semiconductor structure.

[0060] Reference Figure 10A and Figure 10B A first dielectric layer 160 is formed on the second conductive layer 150. The first dielectric layer 160 may include oxides, nitrides, oxynitrides, low-k dielectrics, or combinations thereof. Next, a sacrificial layer 161 is formed on the first dielectric layer 160, and the sacrificial layer 161 may be polysilicon. In some embodiments, the second conductive layer 150, the first dielectric layer 160, and the sacrificial layer 161 may be formed by a deposition process followed by an etching process. In some embodiments, the top surfaces of the second conductive layer 150, the first dielectric layer 160, and the sacrificial layer 161 are substantially flat surfaces.

[0061] Reference Figures 11A to 11C A photoresist pattern 162 is formed on the sacrificial layer 161 to cover a portion of the sacrificial layer 161. For example... Figure 11A and Figure 11B As shown, the photoresist pattern 162 covers the first portion 161a of the sacrificial layer 161 and exposes the second portion 161b of the sacrificial layer 161.

[0062] In some embodiments, the photoresist pattern 162 covers a first portion 161a of the sacrificial layer 161, a portion of the sidewalls of the gate dielectric layer 111, and the sidewalls and top surface of the etching mask 120 located between adjacent first trenches. In other embodiments, the photoresist pattern 162 covers the first portion 161a of the sacrificial layer 161, a portion of the gate dielectric layer 111, and the sidewalls of the etching mask 120 located between adjacent first trenches, but does not cover the top surface of the etching mask 120.

[0063] In some embodiments, where the isolation structure 110 separates the two first trenches 121 in pairs from other pairs of first trenches, i.e., an active region includes a pair of first trenches, the first portions 161a are also provided as a pair, each located in one of the pair of first trenches. In some embodiments, the first portions 161a are located away from the isolation structure 110 and adjacent to the substrate 100 between the pair of first trenches. In some embodiments, the sacrificial layer 161 in the first trench includes a first portion 161a and a second portion 161b of the sacrificial layer 161, however, the sacrificial layer 161 in the second trench is entirely the second portion 161b of the sacrificial layer 161.

[0064] According to some embodiments, Figure 11C A circuit layout diagram of the semiconductor structure is provided. It should be noted that although the bit lines BL, bit line contacts BC, word lines WL, and storage node contacts CC are not yet formed at this stage of the process, for ease of explanation of the relative relationships, as shown below... Figure 11C As shown, the photoresist pattern 162 covers a portion of the subsequently formed adjacent word line WL, that is, as... Figure 11A As shown, the photoresist pattern 162 covers a portion of the sacrificial layer 161. Similarly, as... Figure 11C As shown, the photoresist pattern 162 covers the bit line contact BC that is subsequently formed, i.e. Figure 11A As shown, photoresist pattern 162 covers a portion of substrate 100 between a pair of first trenches.

[0065] Next, after forming the photoresist pattern 162 on the sacrificial layer 161, an ion implantation process 163 is performed on the second portion 161b of the sacrificial layer 161 not covered by the photoresist pattern 162. The aforementioned ion implantation process can change the etch selectivity of the second portion 161b by doping it with a dopant, making the etch selectivity of the first portion 161a greater than that of the second portion 161b. That is, for the same etchant, the etch rate of the first portion 161a is greater than that of the second portion 161b, facilitating the subsequent partial removal of the sacrificial layer 161.

[0066] like Figure 12A and Figure 12B As shown, after performing the implantation process 163, the photoresist pattern 162 is removed.

[0067] like Figure 13A and Figure 13B As shown, a wet etching process is used to remove the first portion 161a of the sacrificial layer 161. In some embodiments, since the sacrificial layer 161 in the second trench belongs to the second portion 161b, the sacrificial layer 161 located in the second trench is not removed.

[0068] In some embodiments, continuing from the above, after removing the first portion 161a of the sacrificial layer 161, an etching process 164 is performed using the second portion 161b of the sacrificial layer 161 remaining on the first dielectric layer 160 as an etching mask. In some embodiments, during the etching process 164, the etching process 164 first removes a portion of the first dielectric layer 160 exposed by the second portion 161b, and since the etching selectivity ratio of the material of the second portion 161b of the sacrificial layer 161 is the same as that of the material of the second conductive layer 150, then a portion of the second conductive layer 150 and the second portion 161b of the sacrificial layer 161 are simultaneously removed until a portion of the second substrate 141 is exposed.

[0069] That is, after the aforementioned implantation process 163, the etching selectivity of the second portion 161b of the sacrificial layer 161 is substantially the same as that of the second conductive layer 150. Therefore, when using the same etching chemicals, the etching rates of the second portion 161b of the sacrificial layer 161 and the second conductive layer 150 are substantially the same. In some embodiments, the materials of the second portion 161b of the sacrificial layer 161 and the second conductive layer 150 are both boron-doped polysilicon. In some embodiments, the thicknesses of the sacrificial layer 161 and the second conductive layer 150 are substantially the same, so that after the etching process 164, the second portion 161b of the sacrificial layer 161 is completely removed and a portion of the second substrate 141 is exposed.

[0070] In another embodiment, the material of the second portion 161b of the sacrificial layer 161 is similar to, but not the same as, the material of the second conductive layer 150. For example, the second portion 161b of the sacrificial layer 161 may be boron-doped polysilicon, while the material of the second conductive layer 150 may be undoped polysilicon. However, by further adjusting the thickness of the sacrificial layer 161 and the second conductive layer 150, it is possible to simultaneously and completely remove the second portion 161b of the sacrificial layer 161 and expose a portion of the second substrate 141.

[0071] In yet another embodiment, such as Figure 11A The photoresist pattern 162 shown covers the second portion 161b of the sacrificial layer 161 and exposes the first portion 161a of the sacrificial layer 161. The first portion 161a of the sacrificial layer 161 is doped using an implantation process 163, resulting in an etch selectivity ratio greater for the first portion 161a than for the second portion 161b. Then, the first portion 161a of the sacrificial layer 161 is removed using an etching process.

[0072] In some embodiments, after etching process 164, the second conductive layer 150 is etched, exposing a portion of the second conductive layer 150 and a portion of the first dielectric layer 160, that is, exposing the side surfaces of the second conductive layer 150 and the first dielectric layer 160. In some embodiments, both the second substrate 141 and the first substrate 130 may be omitted. In embodiments where the second substrate 141 is omitted, after etching process 164, a portion of the first conductive layer 140 is exposed.

[0073] like Figure 14A and Figure 14B As shown, a second portion 161b of the sacrificial layer 161 is removed, exposing a portion of the second liner 141 in the first trench. In some embodiments, the top surface of the first dielectric layer 160 in the first trench is exposed, and the top surface of the first dielectric layer 160 in the second trench is also exposed.

[0074] like Figure 15A and Figure 15B As shown, a third conductive layer 170 is compliantly formed on the first conductive layer 140. For example, the third conductive layer 170 extends along the top and side surfaces of the etch mask 120, the side surface of the gate dielectric layer 111, the top and side surfaces of the first dielectric layer 160, the side surface of the second conductive layer 150, and the top surface of the second substrate 141. In some embodiments, the thickness of the third conductive layer 170 may be adjusted according to the desired thickness of the third conductive layer 170 after etch-back. In some embodiments, the materials and processes used to form the third conductive layer 170 may be the same as or different from those used to form the first conductive layer 140 and / or the second conductive layer 150.

[0075] like Figure 16A and Figure 16B As shown, the third conductive layer 170 is etched back, and a portion of the exposed second substrate 141 is formed to cover the second substrate 141. Therefore, the thickness of the third conductive layer 170 can be controlled by the parameters of the etch-back process. In some embodiments, a pair of third conductive layers 170 are respectively disposed in two adjacent first trenches, and the third conductive layers 170 are located away from the isolation structure 110 and close to the substrate 100 between the two adjacent first trenches. In some embodiments, the third conductive layers 170 are symmetrically arranged.

[0076] In some embodiments, the third conductive layer 170 and the second conductive layer 150 are on the top surface of the first conductive layer 140, and the third conductive layer 170 and the second conductive layer 150 are electrically connected. In some embodiments, the third conductive layer 170 and the second conductive layer 150 are in direct contact. In some embodiments, the bottom surfaces of the second conductive layer 150 and the third conductive layer 170 are in contact with the top surface of the second liner 141, and the top surface of the first conductive layer 140 is in contact with the bottom surface of the second liner 141. In some embodiments, the second liner 141 is omitted, and the first conductive layer 140, the second conductive layer 150, and the third conductive layer 170 are in contact with each other.

[0077] In some embodiments, the bottom surfaces of the second conductive layer 150 and the third conductive layer 170 are substantially coplanar. In some embodiments, a stack including the second conductive layer 150 and the first dielectric layer 160 is formed on the first conductive layer 140, and the stack has a pattern corresponding to a second portion 161b of the sacrificial layer 161 in the first trench.

[0078] In some embodiments, the second conductive layer 150 and the third conductive layer 170 respectively contact opposite sidewalls of the first trench. For example, the second conductive layer 150 contacts one sidewall of the first trench, and the third conductive layer 170 contacts the other sidewall opposite to that sidewall.

[0079] In some embodiments, the first conductive layer 140 has a first thickness T1; the second conductive layer 150 has a second thickness T2; and the third conductive layer 170 has a third thickness T3. In some embodiments, the ratio (T1 / T2) of the first thickness T1 of the first conductive layer 140 to the second thickness T2 of the second conductive layer 150 is 1.67 to 10. When the ratio of the first thickness T1 of the first conductive layer 140 to the second thickness T2 of the second conductive layer 150 is greater than 10, the effect on reducing gate-induced drain leakage (GIDL) is not as expected. When the ratio of the first thickness T1 of the first conductive layer 140 to the second thickness T2 of the second conductive layer 150 is less than 1.67, because the total thickness of the first thickness T1 and the second thickness T2 is limited, it means that the first thickness T1 is small, which will cause the word line WL resistance value to be too high.

[0080] In some embodiments, the ratio (T2 / T3) of the second thickness T2 of the second conductive layer 150 to the third thickness T3 of the third conductive layer 170 is 0.5 to 2. When the ratio of the second thickness T2 of the second conductive layer 150 to the third thickness T3 of the third conductive layer 170 is greater than 2, the effect on increasing the saturation current will be poor; while when the ratio of the second thickness T2 of the second conductive layer 150 to the third thickness T3 of the third conductive layer 170 is less than 0.5, it will have the negative effect of increasing the leakage current of the bit line BL.

[0081] The details of the placement of the first conductive layer 140, the second conductive layer 150, and the third conductive layer 170, which have different work functions, will be described in detail later.

[0082] Reference Figure 17A and Figure 17B This example shows a schematic cross-sectional view of a semiconductor structure in which the top surfaces of the second conductive layer 150 and the third conductive layer 170 are substantially coplanar. In some embodiments, a second dielectric layer 180 is formed on the first dielectric layer 160 and the third conductive layer 170. In some embodiments, the material and process of the second dielectric layer 180 may be the same as or different from the material and process of the first dielectric layer 160.

[0083] Reference Figure 18 Bit line contacts BC are formed between pairs of third conductive layers 170 using etching and deposition processes. That is, the bit line contacts BC are formed in the substrate 100 and between the first trenches. Furthermore, further processes can be performed to form... Figure 1 The bit line BL is shown. Next, storage node contacts CC are formed in the substrate 100 and between the first trench and the adjacent second trench, thereby obtaining the semiconductor structure 1 of the present invention.

[0084] In some embodiments, in an active region AA, the first conductive layer 140, the second conductive layer 150, and the third conductive layer 170 in the first trench together serve as... Figure 1 The gate electrode of the active word line in the word line WL shown. The first conductive layer 140, the second conductive layer 150, and the third conductive layer 170 in the isolation structure 110 together serve as... Figure 1 The gate electrode for transmitting word lines in word line WL is shown.

[0085] In some embodiments, a planarization process may be performed prior to the formation of bit line contacts BC to remove the etch mask 120 and expose the top surface of the substrate 100. In another embodiment, the planarization process may not be performed. For example, the etch mask 120 is left on the substrate 100, and bit line contacts BC and / or storage node contacts CC are formed through the etch mask 120.

[0086] In some embodiments, after forming the bit line contact BC and the storage node contact CC, a first doped region 101 and a second doped region 102 are formed in the substrate 100 by an implantation process. In some embodiments, the first doped region 101 and the second doped region 102 are disposed on opposite sides of the first conductive layer 140. In some embodiments, the first doped region 101 and / or the second doped region 102 may be doped with P-type or N-type dopants as required. In some embodiments, the first doped region 101 and the second doped region 102 are formed in the substrate 100 by an implantation process before forming the bit line contact BC and the storage node contact CC, such as when the substrate 100 is provided. In some embodiments, one of the first doped region 101 and the second doped region 102 serves as a source region, and the other of the first doped region 101 and the second doped region 102 serves as a drain region.

[0087] For ease of explanation, the first doped region 101 is used as the source region, and the second doped region 102 is used as the drain region. The first conductive layer 140, the second conductive layer 150, and the third conductive layer 170 in the first trench are used as... Figure 1 The buried gate structure of the word line WL shown is explained.

[0088] In the semiconductor structure of the present invention, the current path P starts from the first doped region 101, which is the source region, and moves along the outer contour of the first trench to enter the second doped region 102, which is the drain region. Specifically, the current path P starts from the first doped region 101 and moves sequentially along the contours of the substrate 100 near the second dielectric layer 180, near the third conductive layer 170, near the first conductive layer 140, near the second conductive layer 150, near the first dielectric layer 160, and near the second dielectric layer 180 to enter the second doped region 102.

[0089] In some embodiments, the work function of the third conductive layer 170 is greater than that of the second conductive layer 150. For example, the difference between the work function of the third conductive layer 170 and the work function of the second conductive layer 150 is 0.3 to 0.9. The third conductive layer 170 is closer to the bit line contact BC than the second conductive layer 150, thus increasing the conduction current near the bit line contact BC. In this embodiment, since the work function affects the conductivity characteristics at the interface, such as the interface between a metal and a semiconductor, the second conductive layer 150, having a smaller work function, can suppress the flow of electrons to the second conductive layer 150, thereby increasing the conduction current through the third conductive layer 170. Furthermore, since the work function of the second conductive layer 150 near the storage node contact CC is smaller than that of the third conductive layer 170, leakage current near the storage node contact CC can be reduced. For example, this reduces GIDL generated near the second conductive layer 150.

[0090] In some embodiments, the work function of the first conductive layer 140 is greater than the work function of the second conductive layer 150. For example, the difference between the work function of the first conductive layer 140 and the work function of the second conductive layer 150 is 0.3 to 0.7. The first conductive layer 140, with a larger work function, is located deeper in the first trench compared to the second conductive layer 150, thus allowing it to be located further away from the second doped region 102, which serves as the drain region. In other words, the first conductive layer 140, with its larger work function, is located further away from the top surface of the substrate 100, thereby reducing leakage current near the second doped region 102. In this embodiment, since the work function affects the GIDL conductivity at the junction, for example, at the junction between a metal and a semiconductor, the second conductive layer 150, with its smaller work function, can suppress the flow of electrons to the second conductive layer 150, thereby reducing GIDL.

[0091] In other embodiments, besides the work function of the first conductive layer 140 being greater than that of the second conductive layer 150, the work function of the third conductive layer 170 is also greater than that of the first conductive layer 140. For example, the difference between the work function of the first conductive layer 140 and the work function of the third conductive layer 170 is 0.1 to 0.4. This allows for an increase in saturation current without affecting the leakage current of the second doped region 102.

[0092] According to the above embodiments, for example, the work function of titanium nitride is approximately 4.7; the work function of tungsten is approximately 4.52; the work function of tungsten nitride (WN) is approximately 4.6; and the work function of polycrystalline silicon is approximately 4.05. Therefore, in some embodiments, the first substrate 130 may be titanium nitride, the first conductive layer 140 may be tungsten, the second substrate 141 may be titanium nitride, the second conductive layer 150 may be doped or undoped polycrystalline silicon, and the third conductive layer 170 may be titanium nitride. In other embodiments, the first substrate 130 may be titanium nitride, the first conductive layer 140 may be tungsten, the second substrate 141 may be titanium nitride, the second conductive layer 150 may be doped or undoped polycrystalline silicon, and the third conductive layer 170 may be tungsten.

[0093] In other embodiments, the materials of the second conductive layer 150 and the third conductive layer 170 can be selected such that the conductivity of the second conductive layer 150 is less than that of the third conductive layer 170. In this embodiment, it can be further selected such that the conductivity of the third conductive layer 170 and the first conductive layer 140 is greater than that of the second conductive layer 150, thereby increasing the conduction current and reducing the leakage current. In another embodiment, the conductivity of the first conductive layer 140 may be greater than that of the third conductive layer 170.

[0094] In other embodiments, a first doped region 101 is used as the drain region and a second doped region 102 is used as the source region, which similarly reduces the leakage current near the storage node contact CC and increases the on-current near the bit line contact BC.

[0095] In some embodiments, the semiconductor structure 1 provided by the present invention can be referred to as a symmetrical structure with the vertical line passing through the bit line contact BC and the first doped region 101 as the axis of symmetry. In some embodiments, the semiconductor structure 1 provided by the present invention can be referred to as an asymmetrical structure with the boundary line passing through the second conductive layer 150 and the third conductive layer 170 as the axis of symmetry.

[0096] Reference Figure 19 This shows that the top surface of the third conductive layer 170 is substantially higher than the semiconductor structure 2 of the second conductive layer 150. For example... Figure 19 As shown, when the top surface of the third conductive layer 170 is substantially higher than that of the second conductive layer 150, the total length of the current path P is longer, which increases the channel length and thus results in a larger saturation current. In other words, the third thickness T3 of the third conductive layer 170 after the etching process can be adjusted as needed, thereby adjusting the current path length of the semiconductor structure.

[0097] In summary, the semiconductor structure of the present invention includes a buried word line structure formed by a stacked structure of a first conductive layer, a second conductive layer, and a third conductive layer. Furthermore, since the third conductive layer, which is close to the bit line contacts in the semiconductor structure, has a larger work function, the on-state current can be increased; and since the second conductive layer, which is far from the bit line contacts in the semiconductor structure, has a smaller work function, the leakage current can be reduced. For example, gate-induced drain leakage current is reduced. Therefore, a semiconductor structure and its formation method are provided that can overcome the contradiction between refresh time and write recovery time, thereby effectively increasing the on-state current and reducing the leakage current.

[0098] The foregoing summary outlines the components of several embodiments of the present invention, enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art should understand that they can readily use the present invention as a basis for changing, replacing, substituting, and / or modifying other processes and structures to achieve the same purpose and / or the same effect as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: One substrate; A trench is provided in the substrate; A first conductive layer is disposed in the trench; A second conductive layer is disposed on a top surface of the first conductive layer; A third conductive layer is disposed on the top surface of the first conductive layer and is electrically connected to the second conductive layer; A source region and a drain region are disposed in the substrate and on opposite sides of the first conductive layer. A line contact is disposed on one of the source region and the drain region; and A storage node contact is disposed on the other of the source and drain regions; The work function of the first conductive layer and the work function of the third conductive layer are greater than the work function of the second conductive layer. The layer with the higher work function is closer to the bit line contact than the other. The top surface of the third conductive layer is higher than the top surface of the second conductive layer or is coplanar with the top surface of the second conductive layer.

2. The semiconductor structure as described in claim 1, characterized in that, The second conductive layer and the third conductive layer respectively contact the opposite sidewalls of the trench, and the second conductive layer is in contact with the third conductive layer.

3. The semiconductor structure as described in claim 1, characterized in that, The ratio of the thickness of the first conductive layer to the thickness of the second conductive layer is 1.67 to 10.

4. The semiconductor structure as described in claim 1, characterized in that, The ratio of the thickness of the second conductive layer to the thickness of the third conductive layer is 0.5 to 2.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first liner is disposed between the trench and the first conductive layer; A second liner is disposed between the first conductive layer and the second conductive layer, and also between the first conductive layer and the third conductive layer; A first dielectric layer is disposed on the second conductive layer; and A second dielectric layer is disposed on the first dielectric layer and the third conductive layer.

6. A method for forming a semiconductor structure, characterized in that, include: A trench is formed in a substrate; A first conductive layer is formed in the trench; A second conductive layer is formed on the first conductive layer; A sacrificial layer is formed on the second conductive layer; Partially remove the sacrificial layer; The remaining portion of the sacrificial layer is used as an etching mask to etch the second conductive layer and expose a portion of the second conductive layer. as well as A third conductive layer is formed on the second conductive layer and covers the exposed portion of the second conductive layer; A source region and a drain region are disposed in the substrate and on opposite sides of the first conductive layer. A line contact is disposed on one of the source region and the drain region; and A storage node contact is disposed on the other of the source and drain regions; The work function of the first conductive layer and the work function of the third conductive layer are greater than the work function of the second conductive layer. The layer with the higher work function is closer to the bit line contact than the other. The top surface of the third conductive layer is higher than the top surface of the second conductive layer or is coplanar with the top surface of the second conductive layer.

7. The forming method as described in claim 6, characterized in that, Partial removal of the sacrificial layer also includes: A photoresist pattern is formed on the sacrificial layer to cover a portion of the sacrificial layer; An implantation process is performed on the uncovered sacrificial layer; Remove the photoresist pattern and that portion of the sacrificial layer to retain the remaining portion of the sacrificial layer on the second conductive layer.

8. The forming method as described in claim 6, characterized in that, The remaining portion of the sacrificial layer is used as an etching mask to etch the second conductive layer and remove the remaining portion of the sacrificial layer.

9. The forming method as described in claim 6, characterized in that, The thickness of the sacrificial layer is substantially the same as the thickness of the second conductive layer.

10. The forming method as described in claim 6, characterized in that, Also includes: A first dielectric layer is formed on the second conductive layer, and the remaining portion of the sacrificial layer is used as an etching mask to etch a portion of the first dielectric layer and the second conductive layer, thereby exposing the remaining portion of the first dielectric layer and the second conductive layer.

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