A ring-shaped phase change memory cell, a three-dimensional integrated process preparation method and an operating method
By designing a ring-shaped phase-change memory cell and using a three-dimensional integration process, the challenges of high power consumption and three-dimensional integration of phase-change memory were solved, achieving low-current operation, improved durability, and high-density storage, thus optimizing device performance and space utilization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG UNIV OF SCI & TECH
- Filing Date
- 2022-12-30
- Publication Date
- 2026-07-24
AI Technical Summary
Existing phase change memories suffer from high power consumption and high current during the RESET process, which prevents the phase change material from undergoing stable phase transitions. Furthermore, 3D integration faces challenges in terms of process complexity and reliability.
The design incorporates a ring-shaped phase-change memory cell, including a cylindrical heater, a ring-shaped phase-change material layer, and an outer layer. Employing a three-dimensional integration process, the design leverages the advantages of read/write operation separation and high thermal efficiency to reduce reset current and extend device lifespan. The structural design of the central heating rod and the ring-shaped phase-change material layer avoids the application of large currents. Combined with the three-dimensional integration scheme, the design improves integration density and storage capacity.
The RESET current was reduced, the lattice disorder of the phase change material was decreased, the device's durability and storage density were improved, the read/write speed and integration were increased, the device power consumption was reduced, and the space utilization was optimized through three-dimensional stacking technology.
Smart Images
Figure CN116056554B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the memory field of the microelectronics industry, and more specifically, relates to a ring-shaped phase-change memory cell, a three-dimensional integration process fabrication method and an operation method, particularly to a novel cell structure of phase-change memory, a three-dimensional integration process fabrication scheme and a corresponding read / write operation method. Background Technology
[0002] With the development of the information age, the volume of data generated by big data, the Internet, and other technologies across various industries is increasing, placing higher demands on memory. This has highlighted the growing importance of semiconductor memory in the semiconductor industry. Currently, the two mainstream traditional semiconductor memory devices, NAND flash memory and Dynamic Random Access Memory (DRAM), are reaching their physical limits as their size shrinks. The current memory field urgently needs to develop new types of memory with high density, large capacity, high integration density, and fast read / write speeds. Phase-change memory, memristors, and ferroelectric memory are all considered promising candidates for becoming the next generation of mainstream memory due to their respective characteristics. Among them, phase-change memory (PCRAM) has significant advantages such as fast read / write speeds, high erasing / write cycles, compatibility with CMOS processes, and relatively mature manufacturing processes.
[0003] Generally speaking, phase change materials (PCMs) exist in two states: crystalline and amorphous. The amorphous and crystalline states exhibit different optical and electrical properties; the amorphous state exhibits high resistance, while the crystalline state exhibits low resistance, with a difference of several orders of magnitude between the two states. Utilizing this significant difference in resistance and their high stability at room temperature, the high and low resistance states of PCMs can be used to represent information states 0 and 1, respectively, thus enabling information storage.
[0004] During the RESET process of a phase-change memory (PCM), the phase-change cell should first reach its melting temperature Tm within a short time, and then rapidly cool down to achieve the transition from a crystalline to an amorphous state. However, due to the rapid temperature rise during this process, a short-duration voltage pulse with a high peak value is required. According to the power consumption calculation formula... This move will inevitably generate a large amount of power consumption in a short period of time, which is the core issue currently restricting the further development of phase-change memory.
[0005] As application scenarios place increasingly higher demands on memory density, several directions have emerged in high-density memory technology: proportional scaling, multi-value storage, and 3D stacking. For the past thirty years, proportional scaling has been an effective method for reducing chip area. However, with the exponential increase in chip production costs due to process advancements, the cost reduction achieved by proportional scaling cannot compensate for the increased manufacturing costs. Furthermore, proportional scaling and multi-value storage technologies face a series of challenges, including increasing technical difficulty with process node advancements, even approaching physical limits, and declining memory reliability. To achieve higher storage density under current process technology, 3D stacking technology for memory cells is receiving increasing attention from the industry. Phase-change memory (PMQ), as a two-end memory, features a simple structure and ease of 3D stacking. The maturation of the device unit itself ensures the integration and reliability of 3D PMQ. Moreover, the array-level design of 3D integrated PMQ not only overcomes some of the performance and stability shortcomings of PMQ but also achieves further improvements in read / write speed and integration density based on its non-volatility. Summary of the Invention
[0006] Addressing the core issue of high reset current in current phase-change memories (PCMs), this invention provides a novel structural unit and three-dimensional integration fabrication scheme that reduces reset current while extending device lifetime, along with corresponding read / write operation methods. In addition to its low operating voltage, this invention proposes PCMs with advantages such as separate read / write operations and high thermal efficiency, avoiding the application of large currents to the phase-change material. This significantly reduces the probability of factors like lattice disorder preventing the phase-change material from undergoing another phase transition, further improving device durability. Furthermore, a three-dimensional integration scheme is designed based on this ring-shaped device unit, which can significantly improve integration density and storage capacity.
[0007] According to a first aspect of the present invention, a ring-shaped phase change memory cell is provided. The memory cell comprises, from the inside to the outside, a columnar heater, a ring-shaped phase change material layer, and an outer layer along a central axis. The outer layer comprises, from top to bottom, a top insulating layer, a side electrode, and a bottom insulating layer. The upper end and lower end of the memory cell are respectively a top electrode and a bottom electrode. The top electrode covers the upper end of the columnar heater and the ring-shaped phase change material layer, and the bottom electrode covers the lower end of the columnar heater and the ring-shaped phase change material layer.
[0008] Preferably, the material of the columnar heater is titanium nitride, silicon carbide, or tantalum nitride.
[0009] Preferably, the material of the annular phase change material layer is Ge2Sb3Te5, Sb2Te3, or GeTe.
[0010] Preferably, the side electrode is tantalum nitride, tungsten metal, or titanium nitride.
[0011] Preferably, the thickness of the annular phase change material layer is 5-15 nm; and the radius of the columnar heater is 4-6 nm.
[0012] According to another aspect of the present invention, a ring-shaped phase change memory is provided, which is formed by three-dimensionally stacking the ring-shaped phase change memory cells described in any one of the claims.
[0013] According to another aspect of the present invention, a method for fabricating the aforementioned ring-shaped phase-change memory is provided, comprising the following steps:
[0014] (1) A bit line is fabricated on the substrate as the bottom electrode of this column of cells; then a bottom insulating layer is grown on the array plane of the bottom electrode;
[0015] (2) Prepare a readout layer on the bottom insulating layer obtained in step (1); use metal electrochemical etching to create a circular via with a radius equal to the design radius of the device unit;
[0016] (3) Grow columnar side electrodes in the circular vias punched in the readout layer; then grow a top insulating layer in the array plane;
[0017] (4) Using plasma etching on the top insulating layer, through holes are made with a depth corresponding to the design height of the device unit and a radius corresponding to the sum of the radii of the annular phase change material layer and the columnar heater of the device unit, and the holes are made from the top insulating layer to the bottom insulating layer.
[0018] (5) Grow an annular phase change material layer in the through hole punched in step (4); punch a through hole with a radius equal to the radius of the columnar heater in the device unit at the center of the annular phase change material layer, and grow a columnar heater in the punched through hole;
[0019] (6) Prepare the corresponding top electrode at the top insulating layer where the device unit is located in the array as the write line of the layer, and thus obtain the ring phase change memory.
[0020] Preferably, the top electrode prepared in step (6) is used as the bottom electrode of the upper layer array, and then the upper layer array is prepared according to steps (1)-(6) to achieve multi-layer stacking.
[0021] Preferably, the total number of layers in the multi-layer stack is less than or equal to 8.
[0022] According to another aspect of the present invention, an operating method for the aforementioned ring phase-change memory is provided, wherein the vertical bit lines are used as the bottom electrodes of the same column cell, the horizontal write lines are used as the top electrodes of the same row cell, and horizontal read lines are led out at the side electrodes; during a read operation, a read voltage is applied between the bit lines of the corresponding column and the read lines of the corresponding row; during a write operation, a negative half potential of the required write voltage is applied to the bit lines of the corresponding column, and then a positive half potential of the required write voltage is applied to the write lines of the corresponding row.
[0023] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art:
[0024] (1) This invention focuses on reducing RESET current by proposing a novel ring-shaped phase-change memory cell structure from the perspectives of heat dissipation and heating efficiency. Specifically, by embedding a central columnar heating rod layer surrounded by a ring-shaped phase-change material layer, the heating efficiency and energy utilization of the cell structure are improved, thereby reducing RESET current. Based on the device cell design, a three-dimensional integration scheme is used to improve storage density; the corresponding fabrication process and operation methods are also introduced.
[0025] (2) In addition to its low operating voltage, the phase-change memory proposed in this invention also has the advantages of separate read and write operations and high thermal efficiency. Although this increases the processing difficulty of the integration process to some extent, it avoids applying a large current to the phase-change material, thereby greatly reducing the probability of factors such as lattice disorder that prevent the phase-change material from undergoing another phase change, and further improving the durability of the device. In addition, a three-dimensional integration scheme is designed based on this ring-shaped device unit, which can significantly improve the integration degree and storage density.
[0026] (3) The side electrode material used in this invention has low thermal conductivity, which can guide heat to be transferred to the GST layer laterally, improve the thermal efficiency of the device, and reduce the switching current, switching voltage and switching power to a certain extent compared with existing devices, thereby effectively reducing the power consumption of the device.
[0027] (4) The separation of read and write electrodes in this invention can improve the durability of the device. If necessary, the resistance of the device can be detected during RESET and SET operations, thereby better analyzing the operating performance of the device.
[0028] (5) The columnar unit device structure in this invention is conducive to three-dimensional stacking and further integrated processing technology, which can improve the space utilization of the storage array. Attached Figure Description
[0029] Figure 1 The following is a novel ring-shaped phase-change memory device unit structure: (a) is a schematic diagram of the simulated device unit structure design; (b) is a cross-sectional view of the device.
[0030] Figure 2 This is a flowchart of the read / write operation of a novel ring-shaped phase-change storage device.
[0031] Figure 3 This is a graph showing the temperature change over time in the phase transition region when a voltage pulse is applied during simulation.
[0032] Figure 4 The simulation of the RESET process of a novel ring-shaped phase change memory device cell is shown, where (a) to (f) are the phase transition region changes of the device from the initial moment to the final moment when the device completes the phase transition.
[0033] Figure 5 The diagram shows a simulation of the SET process of a novel ring-shaped phase change memory device unit, where (a) to (f) represent the initial moment during the phase change process until the final moment when the device completes the phase change, with each moment interval being 3 seconds.
[0034] Figure 6 The RI curve for the device unit TCAD simulation.
[0035] Figure 7 This is a schematic diagram of the device integration scheme.
[0036] Figure 8 This is a schematic diagram of a three-dimensional stacking scheme for the devices.
[0037] Figure 9 This is a flowchart of the operation process for the three-dimensional integrated array of the device.
[0038] Figure 10 This is a flowchart of the fabrication process for device array integration.
[0039] Figure 11 The diagram shows the fabrication scheme for the device array integration process (the first step is from step a to step k, and after step k, the multi-layer stacking cycle is from step b to step n). Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.
[0041] This invention mainly comprises the following three parts:
[0042] (1) Introduction to the basic structure of the ring-shaped phase change memory device unit. This mainly includes the materials used in each part of the unit and the corresponding RESET, SET, and READ operation methods of the device unit; the phase change process of the device unit is simulated as accurately as possible through the construction of a simulation framework, and the relevant performance advantages of the device are analyzed in combination with the electrothermal simulation results.
[0043] (2) Three-dimensional integration concept and fabrication scheme of ring phase change memory devices. This mainly includes the design scheme of device integration array, ensuring the rationality of the circuit layout in the array when the devices are laid flat in the horizontal direction and stacked in the vertical direction so that the corresponding operation unit in the array can be selected when performing different operations; the method and process of performing corresponding operations after the device array is built; and the process flow required for three-dimensional integration of devices, so as to simplify the device fabrication process and reduce the difficulty and complexity of production and processing as much as possible.
[0044] (3) Optimization strategies for device unit structure to improve device performance. These mainly include the impact of device unit structure size on device performance; the impact of materials used in different structural layers on device performance; and avoiding excessively severe impacts on array system operation caused by thermal crosstalk between units in the three-dimensional stacking design of devices.
[0045] The present invention discloses a structure of a ring phase-change memory cell and a corresponding three-dimensional integration scheme, comprising: a cell structure that separates read and write operations during storage operations and a three-dimensional integration scheme proposed for achieving this separation of read and write operations;
[0046] The unit structure that enables read / write operation separation includes:
[0047] A central columnar heating rod is used to generate Joule heat when the corresponding operating voltage is applied to the upper and lower electrodes and conduct it to the adjacent phase change material layer to achieve phase change.
[0048] A ring-shaped phase change material layer; used to achieve the transformation of the corresponding phase state, i.e., high and low resistance state, when heated, thereby realizing the function of data storage;
[0049] Side electrode layer; used to apply a read voltage between the side electrode and the bottom electrode to read the corresponding state of the phase change material layer, thereby determining the stored data value;
[0050] The three-dimensional integration scheme corresponding to the unit allows adjacent device units on the left and right or front and back of the same layer to share a read line or bit line, and adjacent device units on the top and bottom of adjacent layers to share a write line. This is used to enable the unit structure to accurately perform the corresponding operation on the target unit while saving array space distribution when it is stacked in three dimensions.
[0051] In this invention, the central heating rod, which is wrapped by a ring-shaped phase change material layer, will not energize the GST layer during a write operation, thereby achieving read and write operation separation in the device unit.
[0052] In this invention, the phase change of the annular phase change material layer is not caused by self-heating, but by the thermal conduction effect of the central heating rod.
[0053] In this invention, the side electrode layer connected to the annular phase change material layer is used to apply a corresponding read potential during the read operation to read the state of the phase change material layer.
[0054] In this invention, three lines—read line, write line, and bit line—are drawn out in the circuit for locating and operating the corresponding device units in the array, thereby achieving separation of read and write operations in array operation.
[0055] In this invention, the shared write lines of two adjacent layers in the three-dimensional stack are used to locate the device units in the array and perform the corresponding voltage operations during the write operation.
[0056] Example 1
[0057] This invention relates to a novel annular phase-change memory device cell structure and operation method: Figure 1 Figure (a) shows a schematic diagram of the unit structure design of the simulation device. Figure 1 Figure (b) shows a cross-sectional view of the device. As we can see from the figure, the structure is divided into three layers from the inside to the outside along the central axis: an inner columnar central heater, an outer ring-shaped phase change material, and an outermost insulating layer with embedded electrodes. At the same time, the heating layer and the phase change material layer are covered with a metal electrode at both ends for further integrated module design.
[0058] During the RESET and SET processes, the device unit applies corresponding RESET and SET voltages at the heating layer electrodes, namely the top and bottom electrodes. When reading the device's resistive state, the corresponding READ voltage is applied to the side electrodes between the insulating layers. This achieves read-write separation at the operational level and avoids a series of lattice disorder effects that reduce device durability caused by applying large current to the phase change material. It also benefits from the low thermal conductivity of the side electrode material. Figure 2 The diagram shown is a flowchart of the read / write operation corresponding to this device structure. Figure 2 As shown, during a read operation, the device requires a corresponding read voltage to be applied between the side electrode and the bottom electrode, while the top electrode is left empty; during a write operation, the device requires a corresponding RESET / SET voltage to be applied between the top electrode and the bottom electrode, while the side electrode is left empty.
[0059] Example 2
[0060] Electrothermal simulation and result analysis of the device unit of this invention: PCM TCAD modeling was performed using the multi-state simulation module of Synopsys' Sentaurus tool. To simulate the phase transition process during RESET and SET operations of the ring memory device unit as realistically as possible, this invention achieves this through the following steps:
[0061] (1) Establish a self-consistent electric and thermal model, and add isothermal condition equations and physical field change equations under non-isothermal conditions to the model. This will enable the solution of the corresponding physical field condition parameters and material parameters under conditions of drastic temperature changes.
[0062] (2) The phase transformation of phase change material GST under temperature change is simulated by building the multi-state modeling MSC framework. At the same time, the relevant material properties such as carrier mobility, thermal conductivity and energy band gap are substituted into the above model through the physical interface model PMI, thereby defining different phase states of phase change material.
[0063] (3) Define the phase transformation conditions of the phase change material GST. The crystal growth nucleation model is used in the phase transformation process. The phase transformation rate is also combined with the equation of the reaction rate constant with temperature to display more accurately.
[0064] Figure 3 The figure shown is a graph showing the relationship between the temperature change of the phase transition region caused by applying the corresponding RESET and SET voltage pulses to the phase transition material in the simulation model. It can be seen that the temperature rise and fall range of the phase transition region basically matches the voltage rise and fall range.
[0065] After the model was built and the corresponding parameters were calibrated, the device structure was incorporated into the framework. The device structure model dimensions and materials of each layer used in the simulation experiment were as follows: the internal heater layer was made of titanium nitride with a thickness of 4 nm; the intermediate phase change material layer was made of Ge2Sb3Te5 with a thickness of 5 nm; the external insulating layer was made of silicon dioxide and the side electrode layer was made of tantalum nitride with a thickness of 4 nm each; the device unit height was 15 nm; the side electrode layer divided the insulating layer into three 5 nm high structural layers from top to bottom; the top and bottom electrodes were made of tungsten with a height of 15 nm; and the cross-section was a 15 nm * 15 nm rectangle that completely covered both ends of the phase change material and heater. The simulation used a RESET voltage pulse with an amplitude of 3 V, a rise and fall time of 10 ns, and a duration of 20 ns; and a SET voltage pulse with an amplitude of 1 V, a rise and fall time of 1 ns, and a duration of 50 ns. Figure 4 The diagram shown is a schematic representation of the phase change process during software simulation of the novel phase change storage device structure proposed in this invention. Figure 4 (a) in the diagram represents the moment when the RESET voltage is first applied during the RESET process. Figure 4(a) in Figure 4 The time intervals in (f) are all 3ns. Figure 4 In the figure, (f) represents the moment when the applied RESET voltage pulse reaches its peak value, which is when the device will reach its highest temperature. The legend in the figure is the amorphous state probability distribution factor, which means the probability that the finite element point corresponding to the material is in the amorphous state during the simulation process. It is used to measure whether the phase transformation of the device is sufficient. Figure 5 The figure shown is a graph depicting the temperature variation during simulation of the novel toroidal phase-change memory device. Figure 5 (a) in the diagram represents the moment when the RESET voltage is first applied during the RESET process. Figure 5 (a) in Figure 5 The time intervals in (f) are all 3ns. Figure 5 In the equation (f), the applied RESET voltage pulse reaches its peak value at the same time, and the temperature also reaches its peak value with Tmax = 1660K. Figure 5 The isotherm temperature indicated by the arrow in (e) that is tangent to the boundary between the phase transition region and the side electrode is 888.86 K, which is greater than the melting point Tm = 866 K of the phase transition material GST. This means that the device has completed the phase transition at this point, changing from a low-resistance state to a high-resistance state. The phase transition rate of the device is 12 ns, as shown in the figure. Figure 6 The simulation RI curve for the novel phase-change memory device is shown in the figure. The high and low resistances of the device are 2.38 MΩ and 1.42 kΩ, respectively, the on / off ratio is 1.68 kΩ, and the reset current is only 0.44 mA.
[0066] Example 3
[0067] The present invention relates to a three-dimensional device integration scheme and an array-level operation method for three-dimensional device integration: Since the device unit design has three layers from the inside out—a heater layer, a GST phase-change layer, and an outer layer—and the outer layer also has three layers from top to bottom—an insulating layer, a lateral electrode layer, and another insulating layer—three lines need to be drawn out in the integration design for further array integration: a write line, a read line, and a bit line. Furthermore, voltage operations need to be separated during the read and write processes, using the write line and bit line respectively. The read line and bit line apply corresponding potentials to operate the corresponding device units. Therefore, considering the above points, we adopt the following integration scheme, such as... Figure 7As shown, firstly, the vertical bit lines are used as the bottom electrodes of the same column cell, and the horizontal write lines are used as the top electrodes of the same row cell. Simultaneously, horizontal read lines are led out from the side electrodes. This allows for the identification of corresponding cells within the entire integrated array, enabling the corresponding read and write operations: during a read operation, the corresponding column bit line is given a negative half-voltage, and the corresponding row read line is given a positive half-voltage; similarly, during a write operation, the corresponding column bit line is given a negative half-voltage, and the corresponding row write line is given a positive half-voltage. Furthermore, based on the horizontal cell layout, vertical stacking can also be attempted, significantly reducing the area required for chip design. The stacking approach primarily involves using the first layer's write lines as the second layer's write lines, thus mirroring the entire device cell structure based on the plane containing the first layer's write lines as the plane of symmetry. Then, the second layer's bit lines are used as the third layer's bit lines, mirroring the entire device cell structure again based on the plane containing the second layer's bit lines as the plane of symmetry. Subsequent stacking operations can repeat these steps. Figure 8 As shown, this also enables the integration of devices in three-dimensional space. During read and write operations, the bit lines and read / write lines of the corresponding layers are still used to locate and operate the device cells in the array that need to be operated. The specific three-dimensional integrated array-level operation flowchart is shown below. Figure 9 As shown.
[0068] Example 4
[0069] The fabrication process used for the three-dimensional integration of the device in this invention is as follows: To achieve array-level integration of the device units, the following process is proposed for reference. A detailed process flow diagram is shown below. Figure 10 As shown, the process preparation is as follows: Figure 11As shown, the process in the figure is based on the above-mentioned three-dimensional stacked integration scheme design, and multi-layer fabrication is achieved through cyclic processing. The specific idea is as follows: (1) A bit line is fabricated on the substrate as the bottom electrode of this column of units; (2) On the basis of the bottom electrode fabrication, a silicon dioxide bottom insulating layer is grown on the entire array plane. The thickness of this insulating layer should correspond to the thickness of the outer layer silicon dioxide bottom insulating layer in the device unit; (3) Read lines are fabricated on the bottom insulating layer. The thickness of the read line layer should correspond to the thickness of the outer layer side electrode layer (TaN electrode) in the device unit design; (4) Metal electrochemical etching is used in the read line layer material to create a circular via with a radius equal to the design radius of the device unit; (5) A TaN side electrode is grown in the circular via created in the read line layer. (6) Fill the vias; (7) Grow a silicon dioxide top insulating layer on the entire array plane. The thickness of the insulating layer should correspond to the thickness of the outer silicon dioxide top insulating layer in the device unit; (8) Use plasma etching to create vias on the top insulating layer with a depth corresponding to the device unit design height and a radius corresponding to the sum of the radii of the device's GST phase change layer and heater layer, i.e., drilling from the top insulating layer all the way to the bottom insulating layer; (9) GST phase change material is grown in the drilled vias; (10) A via with a radius equal to the radius of the heater layer in the device unit design is drilled at the center of the phase change material, and the depth also corresponds to the height of the entire device unit; (11) Heater layer material is grown in the drilled vias; (22) Prepare the corresponding top electrode at the corresponding position of the device unit in the array as the write line of that layer. If multiple layers are to be stacked, the write line will be shared with the write line of the next layer; (33) If multiple layers are to be stacked, the top electrode prepared in the previous step can be used as the bottom electrode in (2), and then the steps corresponding to (2) to (11) can be repeated.
[0070] Example 5
[0071] The optimization ideas for the device unit structure design and 3D integration design of this invention are as follows: The heating material used in the entire device design simulation is titanium nitride (mainly because the interlayer thermal resistance between GST and TiN is low, thus facilitating the heating process of the phase change material). GST is used as the phase change material, tantalum nitride is used for the side electrodes (due to its low thermal conductivity, it can significantly increase the proportion of heat diffusion from the phase change material layer during the device phase change process, thereby further reducing the required RESET voltage), silicon dioxide is used as the insulating layer, and both the top and bottom electrodes are tungsten electrode materials. The simulation also revealed the following optimization ideas that can further improve device performance:
[0072] (1) The thickness of GST is best kept between 5-15nm. If the GST layer is too thick, a lot of heat will be dissipated from the bottom electrode and the top electrode during the RESET process, which will increase the minimum voltage required for the RESET process and thus increase the power consumption of the device. If the GST layer is too thin, although it can reduce the power consumption of the device, it will also reduce the high and low resistance window of the device and make the process difficult.
[0073] (2) It is more appropriate to keep the radius of the central heating layer at around 4-6nm, because a thinner heating layer can improve the heating efficiency of the device in the RESET and SET processes, thereby increasing the phase transition speed of the device. However, the improvement in heating efficiency is not significant after the size is less than 4nm. At the same time, too small a size will bring a lot of processing problems, thus affecting the device yield.
[0074] (3) The side electrode material is recommended to be an electrode material with low interlayer thermal resistance and high thermal conductivity. At the same time, the resistivity should not be greater than the resistivity of the low-resistivity state of the phase change material. This can further improve the heating efficiency of the device without affecting the high and low resistance window of the device.
[0075] (4) When operating on a three-dimensional integrated array of devices, thermal crosstalk occurs during the phase transition process of the device cells due to heat loss between the top and bottom electrodes. If the thermal crosstalk is too severe, it will cause phase transitions in adjacent devices in the vertical direction, resulting in the loss or damage of the data stored in the corresponding cells. Therefore, the top and bottom electrodes can be made of materials with higher interlayer thermal resistance to the heatsink layers. In terms of size design, the height can be close to that of the device cells to reduce the interlayer thermal crosstalk effect, while also improving the thermal efficiency of the device itself and reducing the power loss during the phase transition process.
[0076] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A ring-shaped phase-change memory cell, characterized in that, The memory unit consists of a columnar heater, an annular phase change material layer, and an outer layer along the central axis from the inside to the outside. The outer layer consists of a top insulating layer, a side electrode, and a bottom insulating layer from top to bottom. The upper and lower ends of the memory unit are the top electrode and the bottom electrode, respectively. The top electrode covers the upper end of the columnar heater and the annular phase change material layer, and the bottom electrode covers the lower end of the columnar heater and the annular phase change material layer. The columnar heater is made of titanium nitride, silicon carbide, or tantalum nitride. The material of the annular phase change material layer is Ge2Sb3Te5, Sb2Te3, or GeTe; Both the top electrode and the bottom electrode are made of tungsten electrode material.
2. The ring-shaped phase-change memory cell as described in claim 1, characterized in that, The side electrode is tantalum nitride, tungsten metal, or titanium nitride.
3. The ring-shaped phase-change memory cell as described in claim 1, characterized in that, The thickness of the annular phase change material layer is 5-15 nm; the radius of the columnar heater is 4-6 nm.
4. A ring-shaped phase-change memory, characterized in that, It is formed by three-dimensional stacking of the ring-shaped phase change memory cells as described in any one of claims 1-3.
5. The method for fabricating a ring-shaped phase-change memory as described in claim 4, characterized in that, Includes the following steps: (1) A bit line is fabricated on the substrate as the bottom electrode of this column of cells; then a bottom insulating layer is grown on the array plane of the bottom electrode; (2) Prepare a readout layer on the bottom insulating layer obtained in step (1); use metal electrochemical etching to create a circular via with a radius equal to the design radius of the device unit; (3) Grow columnar side electrodes in the circular vias punched in the readout layer; then grow a top insulating layer in the array plane; (4) Using plasma etching on the top insulating layer, through holes are made with a depth corresponding to the design height of the device unit and a radius corresponding to the sum of the radii of the annular phase change material layer and the columnar heater of the device unit, and the holes are made from the top insulating layer to the bottom insulating layer. (5) Grow an annular phase change material layer in the through hole punched in step (4); punch a through hole with a radius equal to the radius of the columnar heater in the device unit at the center of the annular phase change material layer, and grow a columnar heater in the punched through hole; (6) Prepare a corresponding top electrode at the top insulating layer where the device unit is located in the array as the write line of the top insulating layer, thus obtaining a ring phase change memory.
6. The method for fabricating a ring-shaped phase-change memory as described in claim 5, characterized in that, The top electrode prepared in step (6) is used as the bottom electrode of the upper layer array, and then the upper layer array is prepared according to steps (1)-(6) to achieve multi-layer stacking.
7. The method for fabricating a ring-shaped phase-change memory as described in claim 6, characterized in that, The total number of layers in the multi-layer stack is less than or equal to 8.
8. The operation method of the ring phase-change memory as described in claim 4, characterized in that, The vertical bit lines are used as the bottom electrodes of the same column unit, and the horizontal write lines are used as the top electrodes of the same row unit. At the same time, horizontal read lines are led out from the side electrodes. During a read operation, a read voltage is applied between the bit line of the corresponding column and the read line of the corresponding row; during a write operation, half the negative potential of the required write voltage is applied to the bit line of the corresponding column, and then half the positive potential of the required write voltage is applied to the write line of the corresponding row.