Flux tunable qubit architecture for multiplexed qubit control lines

Abstract

A method of multiplexing control lines of a qubit array includes applying a qubit control signal to a single drive line. The qubit control signal is split between a first resonator and a second resonator on the single drive line. A first drive line is operable to control a first qubit, a second tunable qubit, a third qubit, and a fourth tunable qubit. The first qubit is coupled to the second tunable qubit by a first resonator. The third qubit is coupled to the fourth tunable qubit by a second resonator. Variations in amplitude of the qubit control signal are compensated by adjusting a frequency of the second tunable qubit and a frequency of the fourth tunable qubit.

Description

Technical Field

[0001] This disclosure relates generally to superconducting devices, and more specifically to qubit control. Background Technology

[0002] Superconducting quantum computing is the implementation of quantum computers in superconducting electronic circuits. Quantum computing studies the application of quantum phenomena in information processing and communication. Different models of quantum computing exist, with the most popular models including the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states but can be in a quantum superposition of both states. A quantum gate is a generalization of logic gates; however, a quantum gate describes the transformation that one or more qubits will undergo after a gate is applied to them, given their initial states. Different quantum phenomena, such as superposition and entanglement, have no analogues in the world of classical computing and therefore may involve special structures, techniques, and materials. Summary of the Invention

[0003] According to various embodiments, methods and systems for multiplexing control lines of a qubit array are provided. A qubit control signal is applied to a single drive line. This qubit control signal on the single drive line is split between a first resonator and a second resonator, wherein the first drive line is operable to control a first qubit, a second tunable qubit, a third qubit, and a fourth tunable qubit. The first qubit is coupled to the second tunable qubit via the first resonator. The third qubit is coupled to the fourth tunable qubit via the second resonator. Variations in the amplitude of the qubit control signal are compensated by adjusting the frequencies of the second tunable qubit and / or the fourth tunable qubit. Disorder can be, but is not limited to, variations in the frequency of the first qubit and / or variations in the pulse amplitude.

[0004] In one embodiment, the control line is configured to drive a resonator-induced phase (RIP) gate, wherein the first resonator is a RIP resonator and the second resonator is a RIP resonator.

[0005] In one embodiment, calibration of the RIP gate between the first and second qubits is provided by maximizing the gate fidelity while varying the RIP frequency.

[0006] In one embodiment, the second and fourth tunable qubits are flux-tunable ancilla qubits, which are operated to modify the frequency difference between corresponding RIP resonators by changing the frequency shift χ associated with the quantum states on the corresponding RIP resonators of the first and second RIP resonators. The frequency of the RIP resonator can depend on the quantum state, the ancilla qubit, and the data qubit. If both qubits are in the ground state, the frequency of the RIP resonator will not shift. If one or both qubits are in the excited state, the frequency of the RIP resonator will shift by χ.

[0007] The magnitude of the χ shift depends on the frequency difference between the auxiliary qubit and the RIP resonator.

[0008] In one embodiment, the magnitude of the frequency shift χ of the first qubit and the second tunable qubit depends on the frequency difference between the second tunable qubit and the first qubit.

[0009] In one embodiment, a second change in the amplitude of the qubit control signal is compensated by adjusting the frequency of the fourth tunable qubit.

[0010] In one embodiment, the quantum bit control signal is a radio frequency (RF) pulse with a fixed drive amplitude and a fixed frequency.

[0011] In one embodiment, the splitting is performed by a resistive power divider, a reactive power divider, or a multiport coupler.

[0012] In one embodiment, the splitting is performed by a Wilkinson resistive power divider, a Whitworth power divider, or a Delta power divider.

[0013] In one embodiment, error correction for the surface code architecture is performed by cyclically executing at least one of X parity and Z parity checks.

[0014] In one embodiment, the first resonator is detuned to the second resonator. The driving frequency of the qubit control signal is shifted to the same frequency as the gate rate of the first and second tunable qubits and the gate rate of the third and fourth tunable qubits.

[0015] According to an embodiment, the quantum structure includes a first qubit, a second tunable qubit coupled to the first qubit via a first resonator, a third qubit, a fourth tunable qubit coupled to the third qubit via a second resonator, and a fixed drive line coupled to the first and second resonators. The second tunable qubit is configured to be adjusted to compensate for variations in the amplitude of the qubit control signal on the fixed drive line.

[0016] In one embodiment, a control line carries a signal to a resonator to drive a resonator-sensor-phase (RIP) gate. The first resonator is a RIP resonator. The second resonator is a RIP resonator.

[0017] In one embodiment, the second tunable qubit and the fourth tunable qubit are flux-tunable auxiliary qubits configured to modify the quantum state-related frequency shift χ of their respective RIP resonators.

[0018] In one embodiment, modification of χ in at least one of the first or third resonators can be operated to mitigate disturbances in the pulse amplitude of the qubit control signal.

[0019] In one embodiment, the adjustment of the frequency of the fourth tunable qubit can be operated to compensate for a second change in the amplitude of the qubit control signal.

[0020] In one embodiment, the quantum bit control signal is a radio frequency (RF) pulse with a fixed drive amplitude and a fixed frequency.

[0021] In one embodiment, the splitting is performed by a resistive power divider, a reactive power divider, or a multiport coupler.

[0022] In one embodiment, there is an RF divider configured to segment the qubit control signal on a fixed single drive line.

[0023] According to one embodiment, the quantum structure includes a first qubit, a second tunable qubit coupled to the first qubit via a first resonator, a third qubit, a fourth tunable qubit coupled to the third qubit via a second resonator, and a shared drive line coupled to the first and second resonators. The first resonator is detuned from the second resonator. The drive frequency of the qubit control signal is the same as the gate rate of the first and second tunable qubits and the gate rate of the third and fourth tunable qubits. The detuning of the first and second resonators can be achieved by fabricating resonators of different sizes.

[0024] These and other features will become apparent from the following detailed description of illustrative embodiments, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0025] The accompanying drawings are illustrative embodiments. They do not show all embodiments. Other embodiments may be used alternatively or as an alternative. Details that may be obvious or unnecessary may be omitted to save space or for more efficient illustration. Some embodiments may be practiced with additional components or steps and / or without all components or steps shown. When the same number appears in different drawings, it refers to the same or similar parts or steps.

[0026] Figure 1A An example architecture of a quantum computing system conforming to an illustrative embodiment is shown.

[0027] Figure 1B An example graphical representation of the number of wires relative to the size of a logical qubit used in a quantum system, consistent with the illustrative embodiments, is provided.

[0028] Figure 2 The basic elements of a flux-tunable qubit architecture consistent with the illustrative embodiments are shown.

[0029] Figure 3 The illustration shows a version consistent with the illustrative embodiment. Figure 2 An extension of the basic components.

[0030] Figure 4A θ is shown as a function of the change in χ and the change in ε0, respectively. ZZ The changes.

[0031] Figure 4B The change of χ as a function of the change in detuning Δ is shown.

[0032] Figure 5 A conceptual diagram explaining how to tune qubits is provided, consistent with the illustrative embodiments.

[0033] Figure 6A and Figure 6B Several diagrams consistent with the illustrative embodiments are provided, involving the use of RIP frequencies as knobs to multiplex multiple qubits.

[0034] Figure 7 The illustration shows a version consistent with the illustrative embodiment. Figure 6A The example shows the relationship between gate rate and drive frequency.

[0035] Figure 8 An overview of an example architecture with 17 qubits, consistent with the illustrative embodiments, is provided, wherein eight qubits are tunable qubits and nine are fixed qubits.

[0036] Figure 9 A multiplexed RIP bus for driving the first entanglement gate, consistent with the illustrative embodiment, is shown.

[0037] Figure 10 A multiplexed RIP bus for driving the second entanglement gate, consistent with the illustrative embodiment, is shown.

[0038] Figure 11 A multiplexed RIP bus for driving the third entanglement gate, consistent with the illustrative embodiment, is shown.

[0039] Figure 12 A multiplexed RIP bus for driving the fourth entanglement gate, consistent with the illustrative embodiment, is shown.

[0040] Figures 13A to 13D Different methods for performing power division of qubit control signals, consistent with the illustrative embodiments, are provided.

[0041] Figure 14 An illustrative process consistent with the illustrative embodiments is presented, involving the readout of signals from a quantum processor.

[0042] Figure 15 A functional block diagram of a computer hardware platform consistent with the illustrative embodiments is provided, which can be used to implement a specially configured computing device capable of hosting a qubit control engine. Detailed Implementation

[0043] Overview

[0044] In the following detailed explanation, numerous specific details are illustrated by way of examples to provide a thorough understanding of the relevant teachings. However, it should be clear that this teaching can be practiced without such details. In other cases, well-known methods, processes, components, and / or circuits have been described at a relatively high level without detail to avoid unnecessarily obscuring aspects of this teaching.

[0045] In discussing this technique, it may be helpful to describe the different prominent terms. As used in the text, a qubit refers to a quantum bit, and a quantum gate is an operation performed on a qubit, such as controlling the superposition between two qubits.

[0046] As used herein, the resonator-induced phase (RIP) gate is a multi-qubit-wound gate. It allows for high flexibility in qubit frequency, making it suitable for quantum operations in large-scale architectures. A key advantage of the RIP gate is its ability to couple qubits even when they are substantially detuned. Thus, the RIP gate overcomes challenges arising from constraints on the frequency arrangement of these qubits, limitations that could hinder scalability toward larger quantum architectures. The RIP gate is a CZ gate that utilizes strong coupling between qubits and resonators in a quantum system. It can be implemented by applying detuned pulsed microwave drive to a shared bus cavity.

[0047] As used herein, the term C-phase refers to a controlled phase gate, in which the Z-rotation of one qubit is defined by the state of another qubit. ZZ refers to state-dependent qubit interactions that can be used to form a C-phase gate.

[0048] As used in this article, the term flux-tunable refers to devices whose frequency depends on the magnetic flux.

[0049] As used herein, an auxiliary qubit relates to a qubit, which can be used in error correction protocols to store entangled quantum states. In parity circuits, an auxiliary can be used to extract the parity of entangled states. Parity check circuits relate to quantum circuits used for parity checking of the entangled states of data qubits.

[0050] As used in this paper, transmon is a type of superconducting qubit where the charging energy Ec is much smaller than the Josephson energy Ej.

[0051] As used herein, a drive line refers to a qubit control line that carries a signal to a qubit. The term multiplexing includes the meaning of a single control line capable of carrying signals for multiple qubits.

[0052] While the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] Exemplary embodiments are described herein with reference to schematic diagrams of idealized or simplified embodiments (and intermediate structures). Therefore, variations in the shapes of the illustrations are expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the areas shown in the figures are schematic in nature, and their shapes do not necessarily represent the actual shapes of areas of the device and are not limiting in scope.

[0054] It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not restrictive. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0055] As used herein, certain terms are used to indicate what can be considered idealized behavior, such as “lossless,” “superconductor,” “superconducting,” and “absolute zero.” These terms are intended to cover functionality that may not be precisely ideal but is within an acceptable margin for a given application. For example, a certain level of loss or tolerance may be acceptable so that the resulting material and structure can still be referred to by these “idealized” terms.

[0056] This disclosure generally relates to superconducting devices, and more specifically to efficient interaction with lattice arrays comprising multiple qubits. The electromagnetic energy associated with the qubit can be stored in a so-called Josephson junction and in capacitive and inductive elements used to form the qubit. In one example, to read out the qubit state, a microwave signal is applied to a microwave readout cavity coupled to the qubit at the cavity frequency. The emitted (or reflected) microwave signal passes through multiple thermal isolation stages and low-noise amplifiers used to block or reduce noise and improve the signal-to-noise ratio. Alternatively or additionally, the microwave signal (e.g., a pulse) can be used to entangle one or more qubits. Most of the process is performed in a cold environment (e.g., in a low-temperature room temperature), while the microwave signal of the qubit is ultimately measured at room temperature. The amplitude and / or phase of the returned / output microwave signal carry information about the qubit state, such as whether the qubit has shifted to the ground or excited state. The microwave signal carrying quantum information about the qubit state is typically weak (e.g., on the order of a few microwave photons). To measure weak signals using room-temperature electronics (i.e., outside of refrigerated environments), low-noise quantum limiting amplifiers (QLAs) (such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPAs)) can be used as preamplifiers (i.e., the first amplification stage) at the output of the quantum system to amplify the quantum signal while adding a minimum amount of noise specified by quantum mechanics to improve the signal-to-noise ratio of the output chain. In addition to Josephson amplifiers, certain Josephson microwave components using Josephson amplifiers or Josephson mixers (such as Josephson circulators, Josephson isolators, and Josephson mixers) can be used in scalable quantum processors.

[0057] A qubit system may include one or more readout resonators coupled to the qubit. The readout resonator may be a transmission line that includes a capacitive connection to ground on one side and is shorted to ground on the other (as in a quarter-wavelength resonator), or it may have a capacitive connection to ground (as in a half-wavelength resonator), resulting in oscillations within the transmission line, where the resonant frequency of these oscillations is close to the frequency of the qubit. For example, the readout resonator influences pulses from control / measuring instruments at the readout resonator frequency. This pulse is used as a measurement that decoheres with the qubit and collapses it into a "one" or "zero" state, thereby imparting a phase shift to the measurement pulse.

[0058] Coupled resonators, sometimes referred to herein as coupler resonators or RIP buses, can exist between qubits, allowing different qubits to be coupled together to implement quantum logic gates. Coupled resonators are typically structurally similar to readout resonators. However, more complex designs are possible. When a qubit is implemented as a transmon, each side of the coupled resonator is coupled (e.g., capacitively or inductively) to the corresponding qubit by being sufficiently close to it (e.g., its capacitor). Since each side of the coupled resonator has coupling with a correspondingly different qubit, two qubits are coupled together via a coupled resonator (e.g., a RIP bus). In this way, there is interdependence in the states between the coupled qubits, thereby allowing the coupled resonator to control the state of another qubit using the state of one qubit. Entanglement occurs when the interaction between two qubits is such that the states of the two qubits cannot be specified independently but only for the whole system. In this way, the states of two qubits are linked together such that a measurement of one of these qubits causes the state of the other qubit to collapse.

[0059] The ability to include more qubits is significant for the potential to realize quantum computers. Generally, performance increases as temperature decreases, for example by reducing the remaining thermally excited qubit population and reducing the thermal broadening of the transition frequencies of these qubits. Therefore, the lower the temperature, the better the quantum processor.

[0060] It has been determined that improvements to increase the computational power and reliability of quantum computers need to be made along two main dimensions. First, there is the qubit count itself. The more qubits in a quantum processor, the more states can be manipulated and stored in principle. Second is a low error rate, which involves precisely manipulating qubit states and performing sequential operations that provide consistent results rather than just unreliable data. Therefore, to improve the fault tolerance of quantum computers, a large number of physical qubits should be used to store logical qubits. In this way, local information is delocalized, making the quantum computer less susceptible to local errors and the performance of measurements in the eigenbase of the qubits, similar to parity checking in classical computers, thus advancing to more fault-tolerant qubits.

[0061] In one respect, the teachings of this document are based on the applicant's insight that directly applying conventional integrated circuit techniques used for interacting with computing elements to superconducting quantum circuits may be ineffective because the unique challenges presented by quantum circuits are not present in classical computing architectures. Therefore, embodiments of this disclosure are further based on the understanding that the unique problems of quantum circuits have been taken into account when evaluating the suitability of conventional integrated circuit techniques for constructing superconducting quantum circuits, and specifically for the suitability of selected methods and architectures for effective interaction with qubits.

[0062] Example Architecture

[0063] Figure 1A An example architecture 100 of a quantum computing system consistent with the illustrative embodiment is shown. Architecture 100 includes a quantum processor 112, which includes a plurality of qubits 114. The quantum processor 112 is located in a cooling unit 110, which may be a dilution cooler. A dilution cooler is a cryogenic device that provides continuous cooling to temperatures typically between 10 mK and approximately 10 mK. A large portion of the physical volume of architecture 100 is due to the large size of the cooling unit 110. To achieve near-absolute zero temperatures for system operation, the cooling unit 110 may use liquid helium as a coolant.

[0064] A measurement and control unit 130 is located outside the refrigeration unit 110. The measurement and control unit 130 is able to communicate with the quantum processor through an opening 116 (sometimes referred to as the partition of the dilution refrigerator 110), which also forms a hermetically sealed barrier separating the ambient atmospheric pressure from the vacuum pressure of the operating cryostat. A practical challenge in known refrigeration devices that house qubits 114 is that the number of qubits that can be housed in the refrigeration unit is limited by the number of wires between the measurement and control unit 130 and the qubits 114 that are thus measured / controlled.

[0065] As the number of qubits 114 increases, for example to hundreds, thousands, or more, the opening 116 may not be large enough to accommodate all the lines 120 supporting the quantum processor 112 in the dilution cooler 110. In other words, access to the vacuum environment of the dilution cooler 110 is limited by the number of connectors that can be assembled through the partition opening 116. Known architectures (where buses are driven to generate two qubit gates) typically include more than twice the control lines of the cross-resonant gate discussed herein, thus making further scaling impractical.

[0066] Therefore, in one aspect, this paper provides an architecture that substantially reduces the number of lines between the measurement and control unit 130 and the quantum processor 112 housed in a cooled environment. Multiple qubits 114 of the quantum processor 112 can be accessed via multiplexed drive lines, which reduces the number of qubit control lines used for error correction protocols. The concepts discussed herein provide an architecture and method that minimizes the number of drive lines used to control the quantum processor 112. In one aspect, two qubits are coupled together via a resonator. The resonator is driven by an RF pulse that drives a biqubit C-phase gate. One of the two qubits is flux-tunable, which facilitates tuning the frequency of that qubit and aligning that frequency with the radio frequency (RF) pulse driving the biqubit gate.

[0067] As stated above, the teachings of this paper help to substantially reduce the number of wires used for cooling the environment 110 and the measuring and control equipment 130. In this respect, Figure 1B An example graphical representation of the number of wires relative to the size of a logical qubit used in a quantum system, consistent with the illustrative embodiments, is provided. A disadvantage of the architecture that includes drive tuning (e.g., RIP) for the bus is the presence of additional drive lines for each bus. Figure 1B The dashed lines represent the distance from the surface code d. For example, the number of buses at a distance from the surface code d is provided by the following equation:

[0068] Nb uslines =4d 2 -4d

[0069] (Equation 1)

[0070] Therefore, for a 1000-qubit system d~23, the total number of lines is greater than 3000 for conventional systems. In contrast, by using the aids based on the teachings of this paper, although additional lines are provided for tunability, there are only 4 total RIP lines. Figure 1B The middle part is represented by a dotted line.

[0071] In one embodiment, the calculation for multiple RIP lines is based on the size of the logical qubit d. The following expression provides some relationships for the different parameters:

[0072] The number of physical qubits is: N Physical Q =2d 2 -1

[0073] (Equation 2)

[0074] The number of auxiliary qubits is: N Ancilla Q =d ２ -1

[0075] (Equation 3)

[0076] The number of data qubits is: N Data Q =d 2

[0077] (Equation 4)

[0078] The number of bus connections is: N Bus =4d 2 -4d

[0079] (Equation 5)

[0080] There are substantially more bus connections, and each bus includes its own RIP drive line. In this example architecture, the total number of bus connections is reduced to 4. However, the number of auxiliary drive lines increases by a factor of 2. Each auxiliary qubit includes a single qubit RF drive line, and it includes drive lines for flux tuning. There are significantly more bus connections than in the case of auxiliary qubits.

[0081] The number of drive lines after multiplexing is:

[0082] N Drive Lines ==N Data Q +2N Ancilla Q +4 = 3d 2 +2

[0083] (Equation 6)

[0084] Therefore, even after doubling the number of auxiliary lines, there are still fewer driving lines than with one driving line per bus. By using the teachings of this paper, there is one driving line per qubit, in Figure 1B The solid lines represent the lines, which substantially reduces the number of lines in the cooling environment.

[0085] In one respect, the concepts discussed in this paper are scalable because the architecture allows for the partitioning of the RF tuning (sometimes referred to in this paper as the flux pulse or qubit control signal) and the driving of multiple resonators with the same RF tuning. Variations in the RF tuning can be mitigated by adjusting the flux-tunable qubit frequency. These concepts are discussed in more detail below.

[0086] Example basic elements

[0087] See now Figure 2 The figure illustrates the basic elements of a flux-tunable qubit architecture consistent with the illustrative embodiment. Specifically, Figure 2 The fixed-frequency qubit 202 and the tunable auxiliary qubit 204, sometimes referred to as the tunable qubit in this paper, are shown. Figure 2 A fundamental flux-tunable qubit element 206 is also shown, which includes a fixed-frequency qubit Q. d 211 and tunable auxiliary qubit Q tune 213, they are coupled together via a RIP bus 214 having a first frequency f1. First qubit Q d Second tunable quantum bit Q tum Entanglement can be achieved via pulse 220. For example, a fixed-frequency RIP (e.g., radio frequency (RF)) pulse 220 can be transmitted via a RIP bus 214 having a first frequency f1 through a fixed-frequency qubit Q. d (211) and tunable quantum bit Qtune (213) to drive the two-qubit gate. In this way, the first qubit Q d 211 and the second tunable qubit Q tunne 213 can be entangled. The theory of RIP devices can be better understood given the following expression, which assumes that χ is the same for each qubit:

[0088]

[0089] in:

[0090] Δ=ω d -ω r ;

[0091] It is the ZZ rotation rate (i.e., the frequency shift of a qubit, which depends on the state of the other qubit); and

[0092] It is a fixed driving amplitude.

[0093] The applicant has determined that two of these basic elements 206 can be combined to provide a multiplexed basic flux-tunable qubit element 208. Tunable qubit Q tune (e.g., 221 and / or 219) are tunable auxiliary qubits. The RIP pulse frequency and / or fixed frequency qubit Q... d (For example, the frequency change of 209) can be used with a tunable quantum bit Q. tune (For example, 221) to compensate. In other words, the tunable qubit Q can be adjusted. tune To calibrate the gate to a fixed RIP pulse 222.

[0094] In the proposed architecture of the basic flux-tunable element 208 for multiplexing, the flux-tunable qubit Q tune (e.g., 221 and / or 219) can be used to pass through the auxiliary qubit Q tune Flux pulse 222 is applied to 221 and / or 219 to vary χ in Equation 1 above. This tunes the auxiliary qubit Q. tune (For example, 221) to obtain a desired frequency difference between the two qubits. This sequence modifies χ in Equation 1 above and allows for calibration of a fixed drive amplitude. Therefore, any variation in the signal propagating on the fixed drive line 230 (i.e., reaching the first RIP resonator 216 and the second RIP resonator 218) can be controlled by the corresponding tunable qubit Q. tune 221 and / or Q tune219 is used for adjustment. In this way, the amount of entanglement between a qubit (e.g., 209) and its corresponding tunable qubit (e.g., 221) can be controlled.

[0095] Due to Q tune Due to its flux tunability, the basic flux-tunable element 208 of the multiplexer is less sensitive to various types of disturbances. Exemplary disturbances mitigated by the basic flux-tunable element 208 of the multiplexer include RIP driver amplitude. The disorder. Furthermore, the teachings of this paper can mitigate the potential for disruption to the data qubit frequency ω. d and the RIP resonator frequency ω r The disordered manufacturing process.

[0096] Example extensions of basic components

[0097] Now for reference Figure 3 It provides the same as the illustrative embodiments. Figure 2 The basic elements are extended. The basic flux-tunable qubit element 206 and the multiplexed basic flux-tunable qubit element 308 are... Figure 3 This is repeated as a reference to structures that can be extended to provide multiplexing capabilities. More specifically, Figure 3 An example element for a single parity check 306 is shown, which includes a plurality of fixed qubits 322 to 328 coupled to a shared tunable qubit 310. In the structure 306, each fixed-frequency qubit (e.g., 322 to 328) is coupled to the tunable qubit 310 via a RIP bus (sometimes referred to herein as a coupled resonator) having different frequencies (e.g., f1 to f4). For example, qubit Q d 322 is coupled to a frequency f. l RIP bus, quantum bit Q d 324 is coupled to a RIP bus with a second frequency f2, and the quantum bit Q d 326 is coupled to a RIP bus with a third frequency f3; and the quantum bit Q d 328 is coupled to a RIP bus with a fourth frequency f4. In one embodiment, the frequency difference between RIP buses f1 and f4 is 100 MHz or greater.

[0098] The tunable qubit 310 can be sequentially tuned to perform actions with qubit Q d The 322 gate is then retuned to perform operations with qubit Q. d A 324-bit gate is then retuned to perform operations with qubit Q. dGate 328, etc. Although a four-fixed-frequency qubit device is shown by way of example in basic element 306, it will be understood that any number of fixed-frequency qubits can be coupled to a tunable qubit Q. tune Each RIP bus has a different frequency. The basic elements for a single parity check 306 can be extended for multiple parity checks while maintaining a fixed number of RIP buses. Figure 3 An extension of the multiplexing element for the multiple parity check 310 is shown, wherein an additional fixed-frequency qubit Q is added. d 330 and Q d 332 via shared Q tune 352 are included in the array. Fixed-frequency qubits Q d 324 and Q d 328 Both are composed of tunable qubits Q tune 310 and Q tune 352 Both are shared (e.g., accessible). Therefore, multiple qubits with the same qubit frequency can be accessed simultaneously. For example, these qubits coupled to a RIP bus with a first frequency f1 can be accessed simultaneously because they share the same RF line, thereby substantially reducing the number of wires used in a cooled environment. For simplicity and to avoid confusion, six fixed qubits Q are shown in structure 310. d and two tunable qubits Q tune The dot matrix. It should be understood that this article teaches support for dot matrices of any size.

[0099] Example image

[0100] As discussed above, the teachings in this article can alleviate various disorders. Therefore, Figure 4A and Figure 4B This demonstrates how a 40% change in chi can compensate for a 1% change in the RIP pulse amplitude. If the control lines leading to each RIP resonator have slightly different transmission characteristics, each resonator will experience a different amplitude electric field. More specifically, Figure 4A θ is shown as a function of the change in χ and the change in ε0, respectively. ZZ The frequency of the RIP resonator depends on the quantum states of the auxiliary qubit and the data qubit. If both qubits are in the ground state, the frequency of the RIP resonator will not shift. If one or both qubits are in the excited state, the frequency of the RIP resonator will shift by χ. The magnitude of the χ shift depends on the difference in frequency between the auxiliary qubit and the RIP resonator.

[0101] Figure 4BThe change in χ as a function of the detuning change Δ is shown. For example, a detuning change of 30%. For example, frequency detuning of a flux-tunable qubit with a RIP resonator. This change is referenced to detuning (i.e., frequency change). Therefore, Figure 4A and Figure 4B The scope of work has been provided.

[0102] Figure 5 A conceptual diagram consistent with the illustrative embodiments is provided to explain how qubits are tuned. More specifically, graph 500 shows the normalized frequency of the tunable qubit. A RIP pulse 504 is present that can be applied during the tuning phase of the tunable qubit 502, compensating for the disturbances discussed herein, including disturbances from the qubit frequency, resonator, pulse amplitude at splitting, etc. The RIP pulse is applied to perform a two-qubit gate (e.g., to entangle a fixed-frequency qubit with a tunable qubit (e.g., an auxiliary qubit)). Regarding waveform 502, it shows the frequency of the qubit changing over time. While the qubit is tuned to a higher frequency, there is a window where the RIP pulse shown in 504 can be applied to generate entanglement. In practice, the frequency variation of the qubit shown in waveform 502 can be achieved by applying flux to the tunable qubit. Therefore, the dashed line between 502 and 500 illustrates the connection between these frequency variations and flux variations.

[0103] Additional Examples

[0104] Figure 6A and Figure 6B A diagram consistent with the illustrative embodiments is provided, illustrating the use of RIP frequency as a knob to multiplex multiple qubits. Figure 6A The two different RIP resonant buses (i.e., R1 and R2) that connect the qubit Q1 to Q4 are driven using a shared drive line 602. Figure 6B The diagram shows RIP resonators R1 and R2 intentionally detuned to each other. In this way, two resonators 610 can be driven simultaneously. In other words, a two-qubit gate can be applied simultaneously between Q1 and Q2 along with Q3-Q4. In this way, an RF pulse can be applied simultaneously to both RIP resonators, which are located between their frequencies, thereby accelerating phase accumulation.

[0105] This concept can be found in Figure 7 For a better understanding, the illustration shows the gate rate and consistent with the illustrative embodiments. Figure 6A The relationship between the driving frequencies is shown in the example. Curve 702 represents... Figure 6A The qubits Q1 and Q2, represented by curve 704 Figure 6AThe qubits Q3 and Q4. For example, curve 702 represents the gate rate, or entanglement generation rate, between qubits Q1 and Q2, and curve 704 represents the gate rate between qubits Q3 and Q4 as a function of the frequency of the RIP drive applied simultaneously to R1 and R2. Since the gate rate decreases with detuning, the drive frequency can be shifted and the position where the gate rates of Q1 and Q2 are the same as the gate rates of Q3 and Q4 can be found. Figure 7 The value is represented by point 706, which is located at approximately 7.11 GHz.

[0106] As shown in the figure, the ZZ rates as a function of the driving frequency are plotted as R1 at 704 GHz and R2 at 6.2 GHz. Around 6.11 GHz, the gate rates on R1 and R2 are equal. Therefore, two gates can be driven in parallel. It should be noted that if only gates are desired on Q1 and Q2 (instead of Q3 and Q4), the gates can be split into two parts, and an echo sequence can be used to remove the ZZ accumulation on Q3 and Q4. As mentioned earlier, ZZ representation can be used to form C. phasegate The state-dependent qubit interactions. It should be noted that, as used herein, the terms ZZ rate, gate rate, or entanglement generation rate are interchangeable. An attempted 2-qubit operation occurs over a period of time. The reciprocal of the time required to complete the operation is the 'rate' of the operation.

[0107] Example Implementation

[0108] Figure 8 An overview of an example architecture with 17 qubits, consistent with the illustrative embodiments, is provided, eight of which are tunable qubits (marked with Q). a (The qubit representation) and nine are fixed qubits (as noted in the annotation). d (The quantum bit representation). In one embodiment, Figure 8 The architecture can be used in the context of surface code type devices, in which X parity check 802 and Z parity check 804 are performed. For example, X parity check 802 checks the phase, while Z parity check 804 checks the state (e.g., up or down).

[0109] Figure 8 An architecture supporting four separate RIP buses f1 to f4 is shown. All RIP buses with the same frequency can be driven simultaneously during error correction cycles. For this purpose, Figures 9 to 12 The diagram illustrates the different RIP buses activated at different stages (e.g., time periods) during parity checking. More specifically, Figures 9 to 12 A multiplexed RIP bus, consistent with the illustrative embodiment, is shown, driving the first, second, third, and fourth entangled gates respectively. For example, refer to... Figure 9When the first frequency f is generated on the fixed drive line 906 l When the RIP pulse is 904, it can simultaneously drive devices with the same frequency f during the error correction cycle. l All RIP buses. Similarly, in Figure 10 In this process, when a RIP pulse 1004 with a second frequency f2 is generated on a separate fixed drive line 1006, all RIP buses with the same frequency f2 can be driven simultaneously during the error correction cycle. Figure 11 and Figure 12 The operation of driving the third and fourth entanglement gates separately on the multiplexed RIP bus is basically similar to Figure 9 and Figure 10 The operations are described in detail here, and therefore will not be repeated for the sake of brevity. In one embodiment, in the context of performing X parity checks and Z parity checks, Figures 9 to 12 The operations described can be run repeatedly in a loop.

[0110] Example power divider

[0111] As discussed above, the functionality associated with multiplexed RIP drive signals includes splitting the qubit control signal into two or more paths. To this end, Figures 13A to 13D Different methods are provided for performing power segmentation to divide the control signals for qubits. More specifically, Figure 13A A 2-channel Wilkinson power divider is shown; Figure 13B A 3-way Wilkinson power divider is shown; and Figure 13C An N-way Wilkinson power divider is shown. In some embodiments, the power is not divided immediately in the first stage, but rather in progressive stages, such as... Figure 13D As shown.

[0112] Example process

[0113] Given the foregoing overview of the example architecture, it may now be helpful to consider a more advanced discussion of the example process. To this end, Figure 14 An illustrative process related to reading signals from a quantum processor is presented. Process 1400 is shown in a logic flowchart as a set of boxes, representing a series of operations that can be implemented in hardware, software, or a combination thereof. In the context of software, a box represents a computer-executable instruction that performs the operation when executed by one or more processors. Typically, computer-executable instructions may include routines, programs, objects, components, data structures, etc., that perform functions or implement abstract data types. In each process, the order in which the operations are described is not intended to be construed as limiting, and any number of described boxes can be combined and / or executed in parallel in any order to implement the process. For discussion purposes, reference is made to... Figure 2 The architecture of the basic multiplexing element 208 is used to describe this process.

[0114] At box 1402, a qubit control signal 222 is applied to a single drive line 223.

[0115] In block 1404, a qubit control signal is split on a single drive line between a first resonator 216 and a second resonator 218, wherein the single drive line 223 is operable to control a first qubit 209, a second tunable qubit 211, a third qubit 217 and a fourth tunable qubit 219.

[0116] At box 1406, the first qubit 209 is coupled to the second tunable qubit 211 via the first resonator 216.

[0117] In box 1408, the third qubit 217 is coupled to the fourth tunable qubit 219 via the second resonator 218; and

[0118] In box 1410, the amplitude variation of the qubit control signal is compensated by adjusting the frequency of the second tunable qubit 211.

[0119] In one embodiment, at block 1412, further compensation is provided for variations in the amplitude of the qubit control signal by adjusting the frequency of the fourth tunable qubit 219.

[0120] In some embodiments, the process of process 1400 can be repeated cyclically.

[0121] Example computer platform

[0122] As discussed above, functions involving interaction with qubits through measurement and control signals can include measurement and control units, such as... Figure 1A As shown. Figure 15 A functional block diagram of a computer hardware platform 1500 is provided, which can be used to implement a specially configured computing device that can host a qubit control engine 1540. Specifically, Figure 15 A network or host computer platform 1500 is shown that can be used to implement computing devices (such as measurement and control block 130 of Figure 1) with appropriate configurations.

[0123] The computer platform 1500 may include a central processing unit (CPU) 1504, a hard disk drive (HDD) 1506, random access memory (RAM) and / or read-only memory (ROM) 1508, a keyboard 1510, a mouse 1512, a display 1514, and a communication interface 1516, which are connected to the system bus 1502.

[0124] In one embodiment, HDD 1506 has the capability to include a stored program that can perform different processes, such as a qubit control engine 1540, in a manner described herein. The qubit control engine 1540 may have different modules configured to perform different functions. For example, there may be a control module 1542 operable to send control signals to the qubit. There may be a measurement module 1544 operable to perform functions to receive feedback from the qubit discussed herein. There may be a multiplexing module 1548 configured to provide multiplexed control signals discussed herein.

[0125] In one embodiment, Apache can be stored. TM Such programs are used to operate the system as a web server. In one embodiment, HDD 1506 may store an executable application that includes one or more library software modules, such as those for implementing a JVM (Java JVM). TM Java Virtual Machine TM The modules of the runtime environment program.

[0126] in conclusion

[0127] Various embodiments of this teaching have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0128] While the foregoing has described what is considered the best state and / or other instances, it should be understood that various modifications may be made therein, and the subject matter disclosed herein may be implemented in different forms and instances, and the teachings are applicable to many applications, of which only a few have been described herein. The appended claims are intended to claim protection for any and all applications, modifications, and variations that fall within the true scope of this teaching.

[0129] The components, steps, features, purposes, benefits, and advantages discussed herein are illustrative only. They, and the discussions associated with them, are not intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments are necessarily required to include all advantages. Unless otherwise stated, all measurements, values, ratings, locations, amplitudes, sizes, and other specifications set forth in this specification (including in the following claims) are approximate and imprecise. They are intended to have a reasonable range of functionality associated with them and consistent with functionality customary in the art to which they pertain.

[0130] Many other embodiments are also conceived. These include embodiments with fewer, additional, and / or different components, steps, features, purposes, benefits, and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered differently.

[0131] This document describes aspects of the disclosure with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0132] These computer-readable program instructions can be provided to a processor of a suitably configured computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to function in a certain way, such that the computer-readable storage medium storing the instructions includes an article of writing containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0133] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0134] The calling flows, flowcharts, and block diagrams in this document illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to different embodiments of this disclosure. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a non-consecutive order. For example, depending on the functions involved, two consecutively shown blocks may actually execute substantially simultaneously, or these blocks may sometimes execute in reverse order. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0135] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" means only as an example and not as best or optimal. Nothing stated or shown beyond what is immediately stated above is intended or should not be construed as causing any contribution or equivalence to any component, step, feature, object, benefit, advantage, or similarity to the public, whether or not it is stated in the claims.

[0136] It should be understood that the terms and expressions used herein have their general meanings as assigned to the corresponding terms and expressions in the relevant query and field of study, unless otherwise specified herein. Relational terms such as "first" and "second" may be used merely to distinguish one entity or action from another, without necessarily requiring or implying any actual such relationship or order between these entities or actions. The terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element beginning with "a" or "an" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0137] This abstract of disclosure is provided to allow the reader to quickly determine the nature of this technical disclosure. It is submitted under the understanding that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen from the above detailed description, various features are combined in various embodiments for the purpose of simplification. The method of this disclosure should not be construed as reflecting an intention to have more features than expressly recited in each claim of the claimed embodiments. Rather, as reflected in the following claims, the inventive subject matter lies in fewer than all features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

Claims

1. A method for multiplexing the driving lines of a qubit array, comprising: Apply the qubit control signal to a single drive line; The qubit control signal on the single drive line is split between the first resonator and the second resonator, wherein the single drive line is operated to control the first qubit, the second tunable qubit, the third qubit, and the fourth tunable qubit. The first qubit is coupled to the second tunable qubit via the first resonator; The third qubit is coupled to the fourth tunable qubit via the second resonator; as well as The amplitude variation of the qubit control signal is compensated by adjusting the frequency of at least one of the second or fourth tunable qubits.

2. The method according to claim 1, wherein: The drive line is configured to drive a resonator sensing phase RIP gate; The first resonator is a RIP resonator; and The second resonator is a RIP resonator.

3. The method of claim 2, further comprising providing calibration of the RIP gate between the first qubit and the second tunable qubit by maximizing the fidelity of the gate while varying the RIP frequency.

4. The method according to any one of claims 2 to 3, wherein the second tunable qubit and the fourth tunable qubit are flux-tunable auxiliary qubits, the flux-tunable auxiliary qubits being operated to change the frequency shift associated with the quantum state on the corresponding resonators of the first and second resonators. This changes the frequency difference between the corresponding resonators.

5. The method according to claim 4, wherein the frequency shift of the first qubit and the second tunable qubit... The amplitude depends on the frequency difference between the second tunable qubit and the first qubit.

6. The method according to any one of claims 1-3, further comprising compensating for a second change in the amplitude of the qubit control signal by adjusting the frequency of the fourth tunable qubit.

7. The method according to any one of claims 1-3, wherein the quantum bit control signal is a radio frequency (RF) pulse having a fixed drive amplitude and a fixed frequency.

8. The method according to any one of claims 1-3, wherein the splitting is performed by a resistive power divider, a reactive power divider, or a multi-port coupler.

9. The method according to any one of claims 1-3, wherein the splitting is performed by a Wilkinson resistive power divider, a Whitworth power divider, or a Delta power divider.

10. The method according to any one of claims 1-3, further comprising performing error correction for the surface code architecture by cyclically performing at least one of X parity check and Z parity check.

11. The method according to any one of claims 1-3, further comprising: This causes the first resonator to detune from the second resonator; as well as The driving frequency of the qubit control signal is shifted to the same frequency as the gate rates of the first and second tunable qubits and the third and fourth tunable qubits.

12. A quantum structure comprising: First quantum bit; The second tunable qubit is coupled to the first qubit via the first resonator; The third quantum bit; The fourth tunable qubit is coupled to the third qubit via the second resonator; as well as A fixed drive line is coupled to the first resonator and the second resonator, wherein the second tunable qubit is configured to be adjusted to compensate for variations in the amplitude of the qubit control signal of the fixed drive line.

13. The quantum structure according to claim 12, wherein: The drive line carries the signal to the resonator to drive the resonator-sensing phase RIP gate; The first resonator is a RIP resonator; and The second resonator is a RIP resonator.

14. The quantum structure according to any one of claims 12 to 13, wherein, The second tunable qubit and the fourth tunable qubit are configured to modify the quantum state-dependent frequency shift of their respective RIP resonators. Flux-tunable auxiliary qubits.

15. The quantum structure according to claim 14, wherein, Modification of at least one of the first resonator or the third resonator It can be operated to mitigate disturbances in the pulse amplitude of the qubit control signal.

16. The quantum structure according to any one of claims 12 to 13, wherein, The adjustment of the frequency of the fourth tunable qubit is operable to compensate for a second change in the amplitude of the qubit control signal.

17. The quantum structure according to any one of claims 12 to 13, wherein, The quantum bit control signal is a radio frequency (RF) pulse with a fixed driving amplitude and a fixed frequency.

18. The quantum structure according to any one of claims 12 to 13, further comprising an RF divider configured to divide the qubit control signal on the fixed single drive line.

19. The quantum structure according to any one of claims 12 to 13, wherein, The splitting of the qubit control signal on a single drive line is performed by a resistive power divider, a reactive power divider, or a multi-port coupler.

20. A quantum structure comprising: First quantum bit; The second tunable qubit is coupled to the first qubit via the first resonator; The third quantum bit; The fourth tunable qubit is coupled to the third qubit via the second resonator; as well as A shared drive line is coupled to the first resonator and the second resonator, wherein: The first resonator is detuned to the second resonator; as well as The driving frequency of the qubit control signal is the same as the gate rate of the first qubit and the second tunable qubit and the gate rate of the third qubit and the fourth tunable qubit.

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