Semiconductor structure and method of fabricating the same

Abstract

A semiconductor structure and a method for manufacturing the same, the semiconductor structure comprising: a substrate (10) having a plurality of strip-shaped trenches (101) arranged side by side in the substrate; and a heterojunction structure (11) on the bottom wall of the strip-shaped trenches, the side wall of the strip-shaped trenches and the substrate outside the strip-shaped trenches, the heterojunction structure on the bottom wall and the substrate outside the strip-shaped trenches being a polarization region, the heterojunction structure on the side wall being a non-polarization region, and the polarization region having carriers; the heterojunction structure comprising a source region (11a) and a drain region (11b) respectively at two ends of each strip-shaped trench, and a gate region (11c) between the source region and the drain region, the carriers between the source region and the drain region being confined to flow in each polarization region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] As a typical representative of the third generation semiconductor material, the wide band gap semiconductor material III-nitride has excellent characteristics such as wide band gap, high pressure resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterojunction structure, which is very suitable for manufacturing high-temperature, high-frequency and high-power electronic devices.

[0003] For example, the AlGaN / GaN heterojunction structure has a high concentration of two-dimensional electron gas (2DEG) at the AlGaN / GaN interface due to strong spontaneous polarization and piezoelectric polarization, and is widely used in semiconductor structures such as high electron mobility transistors (HEMTs).

[0004] In a planar device, the current flows along the plane in the quantum well formed by the heterojunction structure. Under the condition of reverse bias, the distribution of the electric field is generally non-uniform, and generally a serious electric field concentration will occur at the edge of the gate or the edge of the drain, and the electric field at this place will rapidly increase with the increase of the reverse voltage, and when the critical breakdown field strength is reached, the device is broken down.

[0005] A high breakdown voltage means that the device can work in a larger voltage range, can obtain a higher power density, and has a higher reliability. Therefore, how to improve the breakdown voltage of the device is a problem that electronic device researchers focus on. SUMMARY

[0006] The purpose of the present application is to provide a semiconductor structure and a manufacturing method thereof, and to improve the breakdown voltage.

[0007] To achieve the above-mentioned purpose, the present application provides a semiconductor structure, comprising:

[0008] a substrate, the substrate having a plurality of strip-shaped grooves arranged side by side in the substrate;

[0009] and a heterojunction structure located on the bottom wall of the strip-shaped grooves, the side wall of the strip-shaped grooves and the substrate outside the strip-shaped grooves, the heterojunction structure located on the bottom wall and the substrate outside the strip-shaped grooves is a polarization region, the heterojunction structure located on the side wall is a non-polarization region, and the polarization region has a carrier; the heterojunction structure includes a source region and a drain region located at both ends of each of the strip-shaped grooves, and a gate region located between the source region and the drain region, and the carrier between the source region and the drain region is limited to flow in each of the polarization regions.

[0010] Optionally, the cross section of the strip-shaped trench is rectangular or trapezoidal.

[0011] Optionally, the cross section of the strip-shaped trench is V-shaped, inverted trapezoidal or bowl-shaped.

[0012] Optionally, each of the strip-shaped trenches is directly connected, so that the heterojunction structure at the connection between adjacent strip-shaped trenches is linearly distributed.

[0013] Optionally, the heterojunction structure does not fill the strip-shaped trench.

[0014] Optionally, the heterojunction structure comprises, from bottom to top, a channel layer and a barrier layer.

[0015] Optionally, the heterojunction structure comprises, from bottom to top, a back barrier layer and a channel layer.

[0016] Optionally, the gate region has a gate insulating layer and a gate in sequence, the source region has a source, and the drain region has a drain.

[0017] Optionally, the substrate is a semiconductor substrate.

[0018] Optionally, the substrate comprises, from bottom to top, a semiconductor substrate, a nucleation layer and a buffer layer.

[0019] Another aspect of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0020] providing a substrate, and forming a plurality of strip-shaped trenches arranged side by side in the substrate;

[0021] forming a heterojunction structure on the bottom wall and side wall of the strip-shaped trench and the substrate outside the strip-shaped trench, the heterojunction structure on the bottom wall and the substrate outside the strip-shaped trench being a polarization region, the heterojunction structure on the side wall being a non-polarization region, and the polarization region having carriers; the heterojunction structure comprises a source region and a drain region at both ends of each of the strip-shaped trenches, and a gate region between the source region and the drain region, and the carriers between the source region and the drain region are confined to flow in each of the polarization regions.

[0022] Optionally, in the step of forming a heterojunction structure, the heterojunction structure does not fill the strip-shaped trench.

[0023] Optionally, in the step of forming a heterojunction structure, the heterojunction structure comprises, from bottom to top, a channel layer and a barrier layer.

[0024] Optionally, the heterojunction structure comprises, from bottom to top, a back barrier layer and a channel layer.

[0025] Optionally, the manufacturing method further comprises sequentially forming a gate insulating layer and a gate on the gate region, forming a source on the source region, and forming a drain on the drain region.

[0026] Optionally, the substrate is a semiconductor substrate; before forming the heterojunction structure, the manufacturing method further comprises forming a nucleation layer on the bottom wall and the sidewall of the strip-shaped trench and the semiconductor substrate outside the strip-shaped trench.

[0027] Optionally, the substrate is a semiconductor substrate; before forming the heterojunction structure, the manufacturing method further comprises sequentially forming a nucleation layer and a buffer layer on the bottom wall and the sidewall of the strip-shaped trench and the semiconductor substrate outside the strip-shaped trench.

[0028] Optionally, the substrate comprises, from bottom to top, a semiconductor substrate, a nucleation layer and a buffer layer.

[0029] Compared with the prior art, the present application has the following advantages:

[0030] 1) In a horizontal device, a plurality of strip-shaped trenches are formed in the substrate, and when the heterojunction structure is formed on the substrate, the plane direction of the heterojunction structure on the bottom wall of the strip-shaped trench and the substrate outside the strip-shaped trench is perpendicular to the polarization axis direction, and there is a polarization effect, which can generate carriers, corresponding to a polarization region; the plane direction of the heterojunction structure on the sidewall is substantially parallel to the polarization axis direction, and there is substantially no polarization effect, and no carriers are generated, corresponding to a non-polarization region. In other words, the strip-shaped trenches form alternating polarization regions and non-polarization regions, and the non-polarization regions separate the polarization regions, so that the carriers between the source region and the drain region of the heterojunction structure are limited to flow in each polarization region. Since the strip-shaped polarization regions are limited, the two-dimensional electron gas carriers or two-dimensional hole gas carriers in the heterojunction structure exhibit an approximately one-dimensional transport mode during migration, which can improve the carrier mobility. In addition, the control ability of the gate on the carriers is greatly improved, so that the breakdown voltage of the device can be greatly improved, the leakage problem can be reduced, and the efficiency and linearity of the radio frequency device can be improved.

[0031] 2) In an optional solution, the cross section of the strip-shaped trench is rectangular, trapezoidal, V-shaped, inverted trapezoidal or bowl-shaped. When it is V-shaped, inverted trapezoidal or bowl-shaped, each strip-shaped trench can be directly connected. In other words, the heterojunction structure at the connection between adjacent strip-shaped trenches is linearly distributed.

[0032] 3) In an alternative, the heterojunction structure fills or does not fill the strip-shaped trench. In other words, as long as the interface of the hetero-materials of the heterojunction structure has a section in a plane parallel to the sidewall of the strip-shaped trench, the polarization region can be isolated.

[0033] 4) In an alternative, the heterojunction structure has a gate insulating layer. In other words, the scheme of the present application can be used for a depletion-mode RF MIS device, and can be used for manufacturing, selling or using as a semi-finished product or a finished product. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure of the first embodiment of the present application;

[0035] Figure 2 is a top view of an intermediate structure corresponding to the flow in Figure 1

[0036] Figure 3 is a cross-sectional view along AA line in Figure 2

[0037] Figure 4 is a top view of a semiconductor structure of the first embodiment of the present application;

[0038] Figure 5 is a cross-sectional view along BB line in Figure 4

[0039] Figure 6 is a cross-sectional view along CC line in Figure 4

[0040] Figure 7 is a cross-sectional view of a semiconductor structure of the second embodiment of the present application;

[0041] Figure 8 is a cross-sectional view of an intermediate structure corresponding to the manufacturing of a semiconductor structure in Figure 7

[0042] Figure 9 is a cross-sectional view of a semiconductor structure of the third embodiment of the present application;

[0043] Figure 10 is a cross-sectional view of a semiconductor structure of the fourth embodiment of the present application;

[0044] Figure 11 is a cross-sectional view of a semiconductor structure of the fifth embodiment of the present application;

[0045] Figure 12 is a top view of a semiconductor structure of the sixth embodiment of the present application;

[0046] ​​​​​Figure 13 It is along Figure 12 A sectional view of the DD line in the middle;

[0047] Figure 14 This is a cross-sectional schematic diagram of the semiconductor structure according to the seventh embodiment of the present invention;

[0048] Figure 15 This is a cross-sectional schematic diagram of the semiconductor structure according to the eighth embodiment of the present invention;

[0049] Figure 16 This is a top view schematic diagram of the semiconductor structure according to the ninth embodiment of the present invention;

[0050] Figure 17 It is along Figure 16 A cross-sectional view of the EE line in the diagram;

[0051] Figure 18 It is along Figure 16 A cross-sectional view of the FF line in the diagram;

[0052] Figure 19 This is a cross-sectional schematic diagram of the semiconductor structure according to the tenth embodiment of the present invention.

[0053] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below:

[0054] Substrate 10 Semiconductor substrate 102

[0055] Nucleation layer 103 Buffer layer 104

[0056] Strip-shaped groove 101 Heterogeneous structure 11

[0057] Gate insulating layer 12 Source region 11a

[0058] Drain region 11b Gate region 11c

[0059] Channel layer 111 Barrier layer 112

[0060] Back barrier layer 113 Source 13a

[0061] Drain 13b Gate 13c

[0062] Semiconductor structures 1, 2, 3, 4, 5, 6, 7, 8, 9, 20 Detailed Implementation

[0063] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0064] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention.Figure 2 is a top view structural schematic diagram of the intermediate structure corresponding to the flow in Figure 1 Figure 3 is a sectional view along AA line in Figure 2 Figure 4 is a top view structural schematic diagram of the semiconductor structure of the first embodiment of the present application; Figure 5 is a sectional view along BB line in Figure 4

[0065] Figure 6 is a sectional view along CC line in Figure 4

[0066] First, referring to step S1 in Figure 1 and Figure 2 , a substrate 10 is provided, and a plurality of strip-shaped trenches 101 are formed in the substrate 10. Figure 3

[0067] In this embodiment, the substrate 10 is a semiconductor substrate 102.

[0068] The material of the semiconductor substrate 102 can be sapphire, silicon carbide, silicon, GaN or diamond.

[0069] It should be noted that in the present application, a certain material is represented by a chemical element, but the molar proportion of each chemical element in the material is not limited. For example, in a GaN material, Ga elements and N elements are included, but the molar proportion of Ga elements and N elements is not limited.

[0070] The "plurality" of the plurality of strip-shaped trenches 101 refers to two or more; and the side-by-side arrangement refers to the extension direction of each strip-shaped trench 101 being parallel.

[0071] The cross section of the strip-shaped trench 101 can be rectangular. Correspondingly, the strip-shaped trench 101 can be formed by dry etching or wet etching.

[0072] Next, referring to step S2 in Figure 1 and Figure 4 to Figure 6 , a heterojunction structure 11 is formed on the bottom wall and side wall of the strip-shaped trench 101 and the substrate 10 outside the strip-shaped trench 101, the heterojunction structure 11 on the bottom wall and the substrate 10 outside the strip-shaped trench 101 is a polarization region, the heterojunction structure 11 on the side wall is a non-polarization region, and the polarization region has carriers; the heterojunction structure 11 includes a source region 11a and a drain region 11b located at both ends of each strip-shaped trench 101, respectively, and a gate region 11c located between the source region 11a and the drain region 11b, and the carriers between the source region 11a and the drain region 11b are confined to flow in each polarization region.

[0073] ​​​​​In the embodiment, the heterojunction structure 11 includes, from bottom to top, a channel layer 111 and a barrier layer 112. A two-dimensional electron gas or a two-dimensional hole gas can be formed at the interface between the channel layer 111 and the barrier layer 112. Specifically, a) the channel layer 111 and the barrier layer 112 can each have one layer; or b) the channel layer 111 and the barrier layer 112 can each have multiple layers, and are alternately distributed; or c) one channel layer 111 and two or more barrier layers 112, to meet different functional requirements.

[0074] The channel layer 111 and / or the barrier layer 112 can include a group III nitride material. The material combination of the channel layer 111 and the barrier layer 112 can include GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN.

[0075] The forming process of the channel layer 111 and / or the barrier layer 112 can include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0076] In the grown heterojunction structure 11, the polarization axis (C-axis) direction is parallel to the thickness direction of the substrate 10. Thus, the plane direction of the heterojunction structure 11 on the bottom wall of the strip-shaped trench 101 and the substrate 10 outside the strip-shaped trench 101 is perpendicular to the polarization axis (C-axis) direction, and there is a polarization effect, which can generate carriers, corresponding to a polarization region, and the interface between the channel layer 111 and the barrier layer 112 is a polar surface; the plane direction of the heterojunction structure 11 on the side wall is parallel to the polarization axis (C-axis) direction, and there is no polarization effect, no carrier generation, corresponding to a non-polarization region, and the interface between the channel layer 111 and the barrier layer 112 is a non-polar surface. In other words, the embodiment utilizes the strip-shaped trench 101 to form alternately distributed polarization regions and non-polarization regions, and the non-polarization regions separate the polarization regions.

[0077] In the embodiment, the channel layer 111 and the barrier layer 112 do not fill the strip-shaped trench 101.

[0078] After that, referring to step S3 in Figure 1 and shown in FIG. 12, a gate insulating layer 12 and a gate 13c are formed on the gate region 11c in sequence, a source 13a is formed on the source region 11a, and a drain 13b is formed on the drain region 11b. Figure 4 to Figure 6

[0079] The material of the gate insulating layer 12 can include at least one of SiN, AlO, HfO, MgO, TiO, GaO.

[0080] Specifically, the forming method of the gate insulating layer 12 can include:

[0081] First, an insulating material layer is formed on the whole surface by a physical vapor deposition method or a chemical vapor deposition method.

[0082] In this embodiment, the upper surface of the insulating material layer is uneven, i.e., a thin layer of insulating material is deposited on the whole surface of the heterojunction structure 11.

[0083] After that, the insulating material layer on the source region 11a and the drain region 11b is removed by dry etching or wet etching.

[0084] The forming method of the source 13a, the drain 13b and the gate 13c can include:

[0085] First, a metal layer, such as Ti / Al / Ni / Au, Ni / Au, etc., is formed by sputtering;

[0086] Then, the metal layer in the regions other than the gate region 11c, the source region 11a and the drain region 11b is removed by etching;

[0087] After that, high-temperature annealing is performed to form ohmic contacts between the source 13a and the source region 11a of the heterojunction structure 11 and between the drain 13b and the drain region 11b of the heterojunction structure 11.

[0088] Figure 6 In the embodiment shown, the source 13a and the drain 13b contact the barrier layer 112, and ohmic contacts are formed between the source 13a and the barrier layer 112 and between the drain 13b and the barrier layer 112.

[0089] In some embodiments, N-type ion heavily doped layers can be used to form ohmic contacts between the source 13a and the barrier layer 112 and between the drain 13b and the barrier layer 112. The N-type ion heavily doped layers can enable the source 13a and the source region 11a of the heterojunction structure 11 and the drain 13b and the drain region 11b of the heterojunction structure 11 to directly form ohmic contact layers without high-temperature annealing, and avoid the performance degradation and the reduction of electron migration rate of the heterojunction structure 11 caused by high temperature in the annealing process. ​

[0090] In some embodiments, an N-type ion heavily doped layer can be provided on at least one of the source region 11a and the drain region 11b of the heterojunction structure 11. The source region 11a of the heterojunction structure 11 without the N-type ion heavily doped layer and the source 13a, or the drain region 11b of the heterojunction structure 11 without the N-type ion heavily doped layer can form an ohmic contact layer through high-temperature annealing.

[0091] In the N-type ion heavily doped layer, the N-type ion can be at least one of Si ion, Ge ion, Sn ion, Se ion or Te ion. The doping concentration can be greater than 1E19 / cm3 for different N-type ions. The N-type ion heavily doped layer can be a group III nitride material, such as at least one of GaN, AlGaN or AlInGaN.

[0092] Since the non-polar region separates the polar regions, the carriers between the source region 11a and the drain region 11b of the heterojunction structure 11 are confined to flow within each polar region.

[0093] Referring to Figure 4 to Figure 6 The semiconductor structure 1 of the embodiment includes:

[0094] a substrate 10 having a plurality of strip-shaped grooves 101 arranged side by side in the substrate 10;

[0095] a heterojunction structure 11 located on the bottom wall and the side wall of the strip-shaped grooves 101 and the substrate 10 outside the strip-shaped grooves 101, the heterojunction structure 11 located on the bottom wall and the substrate 10 outside the strip-shaped grooves 101 being a polar region, the heterojunction structure 11 located on the side wall being a non-polar region, and the polar region having carriers; the heterojunction structure 11 includes a source region 11a and a drain region 11b located at both ends of each strip-shaped groove 101, and a gate region 11c located between the source region 11a and the drain region 11b, and the carriers between the source region 11a and the drain region 11b are confined to flow within each polar region;

[0096] and a gate insulating layer 12 and a gate 13c located on the gate region 11c, a source 13a located on the source region 11a, and a drain 13b located on the drain region 11b.

[0097] In the embodiment, the substrate 10 is a semiconductor substrate 102.

[0098] The material of the semiconductor substrate 102 can be sapphire, silicon carbide, silicon, GaN or diamond.

[0099] The plurality of strip-shaped grooves 101 means two or more; and the strip-shaped grooves 101 are arranged side by side, i.e., the extension direction of each strip-shaped groove 101 is parallel.

[0100] The cross section of the strip-shaped groove 101 can be rectangular.

[0101] In the embodiment, the heterojunction structure 11 includes, from bottom to top, a channel layer 111 and a barrier layer 112. A two-dimensional electron gas or a two-dimensional hole gas can be formed at the interface of the channel layer 111 and the barrier layer 112. Specifically, a) the channel layer 111 and the barrier layer 112 can each have one layer; or b) the channel layer 111 and the barrier layer 112 can each have multiple layers, and are alternately distributed; or c) one layer of the channel layer 111 and two or more layers of the barrier layer 112, to meet different functional requirements.

[0102] The channel layer 111 and / or the barrier layer 112 can include a group III nitride material. The material combination of the channel layer 111 and the barrier layer 112 can include GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN.

[0103] The material of the gate insulating layer 12 can include at least one of SiN, AlO, HfO, MgO, TiO, GaO.

[0104] The material of the source 13a and / or the drain 13b and / or the gate 13c can be metal, such as Ti / Al / Ni / Au, Ni / Au, etc.

[0105] As can be seen, the semiconductor structure 1 of the embodiment is a MIS device. The MIS device can be a depletion mode device, i.e., has a normally-on state, and the gate 13c applies a voltage to turn off the conduction between the source 13a and the drain 13b.

[0106] Figure 6 In the illustrated embodiment, the source 13a and the drain 13b are in contact with the barrier layer 112, and ohmic contacts are formed between the source 13a and the barrier layer 112 and between the drain 13b and the barrier layer 112.

[0107] In some embodiments, ohmic contacts can be formed between the source 13a and the barrier layer 112 and between the drain 13b and the barrier layer 112 by using N-type ion heavily doped layers. The N-type ion heavily doped layers can enable the source 13a and the source region 11a of the heterojunction structure 11 and the drain 13b and the drain region 11b of the heterojunction structure 11 to directly form ohmic contact layers without high-temperature annealing, and avoid the performance degradation and the reduction of electron migration rate of the heterojunction structure 11 caused by high temperature in the annealing process.

[0108] In some embodiments, an N-type ion heavily doped layer can also be provided on at least one of the source region 11a and the drain region 11b of the heterojunction structure 11. The source region 11a of the heterojunction structure 11 without the N-type ion heavily doped layer and the source 13a, or the drain region 11b of the heterojunction structure 11 without the N-type ion heavily doped layer can form an ohmic contact layer through high-temperature annealing.

[0109] In the N-type ion heavily doped layer, the N-type ion can be at least one of Si ion, Ge ion, Sn ion, Se ion or Te ion. The doping concentration can be greater than 1E19 / cm3 for different N-type ions. The N-type ion heavily doped layer can be a group III nitride material, such as at least one of GaN, AlGaN or AlInGaN.

[0110] In the semiconductor structure 1 of the present embodiment, due to the confinement of the strip-shaped polarization region, the two-dimensional electron gas carriers or two-dimensional hole gas carriers at the junction of the channel layer 111 and the barrier layer 112 present a nearly one-dimensional transport mode in the migration process, which can improve the carrier mobility. In addition, the control ability of the gate 13c on the carriers can also be greatly improved, so that the breakdown voltage of the device can be greatly improved, and the leakage problem (including the leakage of the gate 13c to the channel layer 111 and the leakage of the channel layer 111 to the substrate 10) can be reduced, and the efficiency and linearity of the radio frequency device can be improved.

[0111] Figure 7 is a schematic diagram of the cross-sectional structure of the semiconductor structure of the second embodiment of the present application; Figure 8 is a schematic diagram of the cross-sectional structure of the semiconductor structure of the second embodiment of the present application; Figure 7 is a schematic diagram of the cross-sectional structure of the intermediate structure corresponding to the semiconductor structure in

[0112] Referring to Figure 7 , the semiconductor structure 2 of the present embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, and the only difference is that the substrate 10 includes a semiconductor substrate 102, a nucleation layer 103 and a buffer layer 104 stacked from bottom to top, and the strip-shaped trench 101 is located in the buffer layer 104.

[0113] The material of the nucleation layer 103 can be, for example, AlN, AlGaN or the like, and the material of the buffer layer 104 can include at least one of AlN, GaN, AlGaN or AlInGaN. The nucleation layer 103 can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 111 in the heterojunction structure 11 (see Figure 7 ) and the semiconductor substrate 102, and the buffer layer 104 can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, and improve the crystal quality.

[0114] In some embodiments, the strip-shaped trenches 101 can also be located in the buffer layer 104, the nucleation layer 103 and the semiconductor substrate 102.

[0115] Correspondingly, the manufacturing method of the semiconductor structure 2 of the second embodiment is substantially the same as the manufacturing method of the semiconductor structure 1 of the first embodiment, and the only difference is that, referring to Figure 8 As shown in the figure, in step S1, the provided substrate 10 includes a semiconductor substrate 102, a nucleation layer 103 and a buffer layer 104 stacked from bottom to top, and a plurality of strip-shaped trenches 101 arranged side by side are formed in the buffer layer 104.

[0116] Figure 9 FIG. 4 is a schematic diagram of the cross-sectional structure of the semiconductor structure of the third embodiment of the present application.

[0117] Correspondingly, the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structures 1 and 2 of the first and second embodiments, and the only difference is that the upper surface of the gate insulating layer 12 is flush. Figure 9 Specifically, for the manufacturing method, in step S3, a thick layer of insulating material can be deposited on the heterojunction structure 11 by physical vapor deposition or chemical vapor deposition, and then planarized by chemical mechanical polishing (CMP).

[0118]

[0119] FIG. 5 is a schematic diagram of the cross-sectional structure of the semiconductor structure of the fourth embodiment of the present application. Figure 10 Correspondingly, the semiconductor structure 4 of the fourth embodiment is substantially the same as the semiconductor structures 1, 2 and 3 of the first, second and third embodiments, and the only difference is that the upper surface of the barrier layer 112 is flush.

[0120] Figure 10 In the present embodiment, the channel layer 111 does not fill the strip-shaped trenches 101, the barrier layer 112 fills the strip-shaped trenches 101, and the interface between the channel layer 111 and the barrier layer 112 has a section parallel to the side wall of the strip-shaped trench 102, so as to isolate the polarization region and limit the polarization region.

[0121] FIG. 6 is a schematic diagram of the cross-sectional structure of the semiconductor structure of the fifth embodiment of the present application.

[0122] Figure 11 Correspondingly, the semiconductor structure 5 of the fifth embodiment is substantially the same as the semiconductor structures 1, 2, 3 and 4 of the first, second, third and fourth embodiments, and the only difference is that the source 13a and the drain 13b contact the channel layer 111, and an ohmic contact is formed between the source 13a and the channel layer 111 and between the drain 13b and the channel layer 111.

[0123] Figure 11

[0124] ​​​Correspondingly, the manufacturing method of the semiconductor structure 5 of the present embodiment five is substantially the same as the manufacturing method of the semiconductor structures 1, 2, 3, 4 of the embodiments one, two, three, four, the only difference is that in step S3, when forming the source 13a on the source region 11a of the heterojunction structure 11 and forming the drain 13b on the drain region 11b, the barrier layer 112 of the source region 11a and the drain region 11b is removed to expose the channel layer 111.

[0125] In some embodiments, the N-type ion heavily doped layer is also used to form the ohmic contact between the source 13a and the channel layer 111 and between the drain 13b and the channel layer 111. The N-type ion heavily doped layer can make the ohmic contact layer between the source 13a and the channel layer 111 and between the drain 13b and the channel layer 111 formed directly without high-temperature annealing.

[0126] In some embodiments, the N-type ion heavily doped layer is used to form the ohmic contact between the source 13a and the channel layer 111 or between the drain 13b and the channel layer 111. The channel layer 111 without the N-type ion heavily doped layer and the source 13a or the channel layer 111 without the N-type ion heavily doped layer and the drain 13b can form the ohmic contact layer through high-temperature annealing.

[0127] Figure 12 is a schematic diagram of the top view structure of the semiconductor structure of the present embodiment six; Figure 13 is a sectional view along the DD line in Figure 12 .

[0128] Referring to Figure 12 and Figure 13 , the semiconductor structure 6 of the present embodiment six is substantially the same as the semiconductor structures 1, 2, 3, 4, 5 of the embodiments one to five, the only difference is that the semiconductor structure 6 is an intermediate semiconductor structure, and the gate insulating layer 12, the gate 13c, the source 13a and the drain 13b are not manufactured.

[0129] Correspondingly, the manufacturing method of the semiconductor structure 6 of the present embodiment six is substantially the same as the manufacturing method of the semiconductor structures 1, 2, 3, 4, 5 of the embodiments one to five, the only difference is that step S3 is omitted.

[0130] In some embodiments, the semiconductor structure 6 as an intermediate semiconductor structure, the gate insulating layer 12, the gate 13c, the source 13a and the drain 13b can be manufactured.

[0131] The semiconductor structure 6 can be produced and sold as a semi-finished product.

[0132] Figure 14 is a schematic diagram of the sectional structure of the semiconductor structure of the present embodiment seven.

[0133] Referring to Figure 14As shown, the semiconductor structure 7 and its fabrication method in this embodiment are largely the same as the semiconductor structures 1, 2, 3, 4, 5, and 6 and their fabrication methods in embodiments one to six, except that the cross-section of the strip trench 101 is V-shaped.

[0134] By controlling the angle α between the slope and the vertical direction, the plane direction of the heterojunction structure 11 located on the sidewall of the slope can be made roughly parallel to the polarization axis (C-axis) direction, with basically no polarization effect and no carrier generation, and can be regarded as a non-polarized region.

[0135] In some embodiments, the cross-section of the strip groove 101 may also be trapezoidal, inverted trapezoidal, or bowl-shaped.

[0136] Figure 15 This is a cross-sectional schematic diagram of the semiconductor structure according to the eighth embodiment of the present invention.

[0137] Reference Figure 15 and Figure 14 As shown, the semiconductor structure 8 and its fabrication method in this embodiment eight are largely the same as the semiconductor structure 7 and its fabrication method in this embodiment seven, except that adjacent V-shaped strip trenches 101 are directly connected. In other words, the heterojunction structures 11 located at the connection of adjacent strip trenches 101 are linearly distributed.

[0138] In some embodiments, adjacent inverted trapezoidal or bowl-shaped grooves 101 may also be directly connected.

[0139] Linear distribution can further confine the strip-shaped polarization region, thereby improving the mobility of two-dimensional electron gas carriers or two-dimensional hole gas carriers in the heterojunction structure 11 during the migration process.

[0140] Figure 16 This is a top view schematic diagram of the semiconductor structure according to the ninth embodiment of the present invention; Figure 17 It is along Figure 16 A cross-sectional view of the EE line in the diagram; Figure 18 It is along Figure 16 A cross-sectional view of the FF line in the diagram.

[0141] Reference Figure 16 to Figure 18 As shown, the semiconductor structure 9 and its fabrication method in this embodiment nine are largely the same as those in embodiments one through eight, namely semiconductor structures 1, 2, 3, 4, 5, 6, 7, and 8 and their fabrication methods, except that the heterojunction structure 11 includes a back barrier layer 113 and a channel layer 111 from bottom to top. A two-dimensional electron gas or a two-dimensional hole gas can be formed at the interface between the back barrier layer 113 and the channel layer 111.

[0142] In one alternative, the back barrier layer 113 is an AlGaN layer and the channel layer 111 is an unintentionally doped GaN layer. In general, GaN-based epitaxial materials grown by MOCVD have a high background electron concentration due to defects such as nitrogen vacancies and oxygen doping, and thus are N-type conductive.

[0143] In other alternatives, the combination of the channel layer 111 and the back barrier layer 113 can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. In addition, instead of having one channel layer 111 and one back barrier layer 113 as shown, the heterojunction structure 11 can also include multiple layers of channel layers 111 and back barrier layers 113 alternately arranged; or one channel layer 111 and two or more back barrier layers 113 to form a multi-barrier structure. Figure 17

[0144] In the embodiment, neither the channel layer 111 nor the back barrier layer 113 fills the strip-shaped trench 101. In some embodiments, the back barrier layer 113 does not fill the strip-shaped trench 101, and the channel layer 111 fills the strip-shaped trench 101. In other words, at least a portion of the interface between the hetero-materials of the heterojunction structure 11 is parallel to the sidewall of the strip-shaped trench, and thus can isolate the polarization region.

[0145] Figure 18 In the embodiment shown, the source 13a and the drain 13b contact the channel layer 111, and ohmic contacts are formed between the source 13a and the channel layer 111 and between the drain 13b and the channel layer 111.

[0146] In some embodiments, the ohmic contacts between the source 13a and the channel layer 111 and between the drain 13b and the channel layer 111 can be formed by N-type ion heavily doped layers. The N-type ion heavily doped layers can allow the source 13a and the source region 11a of the heterojunction structure 11 and the drain 13b and the drain region 11b of the heterojunction structure 11 to form ohmic contact layers directly without high-temperature annealing, and avoid the performance degradation and the reduction of electron mobility of the heterojunction structure 11 caused by high temperature during the annealing process.

[0147] In some embodiments, at least one of the source region 11a and the drain region 11b of the heterojunction structure 11 can have an N-type ion heavily doped layer. The source region 11a of the heterojunction structure 11 without the N-type ion heavily doped layer and the source 13a, or the drain region 11b of the heterojunction structure 11 without the N-type ion heavily doped layer and the drain 13b form ohmic contact layers through high-temperature annealing.

[0148] ​In the N-type ion heavily doped layer, the N-type ion can be at least one of Si ions, Ge ions, Sn ions, Se ions, or Te ions. For different N-type ions, the doping concentration can be greater than 1E19 / cm3. The N-type ion heavily doped layer can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN.

[0149] In some embodiments, the source 13a and the drain 13b may contact the back barrier layer 113, and an ohmic contact may be formed between the source 13a and the back barrier layer 113 and between the drain 13b and the back barrier layer 113.

[0150] Correspondingly, regarding the fabrication method: In step S3, when a source 13a is formed on the source region 11a and a drain 13b is formed on the drain region 11b, the channel layer 111 of the source region 11a and the drain region 11b is removed to expose the back barrier layer 113.

[0151] In some embodiments, ohmic contacts can also be formed between the source 13a and the back barrier layer 113, and between the drain 13b and the back barrier layer 113, using N-type ion heavily doped layers. The N-type ion heavily doped layers enable the formation of ohmic contact layers between the source 13a and the back barrier layer 113, and between the drain 13b and the back barrier layer 113, without the need for high-temperature annealing.

[0152] In some embodiments, an ohmic contact is formed between the source 13a and the back barrier layer 113, or between the drain 13b and the back barrier layer 113, using an N-type ion heavily doped layer. An ohmic contact layer can be formed between the back barrier layer 113 (without an N-type ion heavily doped layer) and the source 13a, or between the back barrier layer 113 (without an N-type ion heavily doped layer) and the drain 13b, through high-temperature annealing.

[0153] Figure 19 This is a cross-sectional schematic diagram of the semiconductor structure according to the tenth embodiment of the present invention.

[0154] Reference Figure 19 As shown, the semiconductor structure 20 of this embodiment is largely the same as the semiconductor structures 1, 2, 3, 4, 5, 6, 7, 8, and 9 of embodiments 1 to 9, except that: the substrate 10 is a semiconductor substrate 102, and the heterojunction structure 11 and the bottom wall, side wall, and semiconductor substrate 102 outside the strip trench 101 have a nucleation layer 103 and a buffer layer 104 from bottom to top.

[0155] Correspondingly, the manufacturing method of the semiconductor structure 20 of the present embodiment 10 is substantially the same as the manufacturing methods of the semiconductor structures 1, 2, 3, 4, 5, 6, 7, 8, 9 of the embodiments 1-9, with the only difference being that in step S2, the nucleation layer 103, the buffer layer 104 and the heterojunction structure 11 are sequentially formed on the bottom wall and the side wall of the strip-shaped trench 101 and the semiconductor substrate 102 outside the strip-shaped trench 101.

[0156] In some embodiments, the heterojunction structure 11 and the semiconductor substrate 102 outside the strip-shaped trench 101 can only have the nucleation layer 103 between them. Correspondingly, in step S2, the nucleation layer 103 and the heterojunction structure 11 are sequentially formed on the bottom wall and the side wall of the strip-shaped trench 101 and the semiconductor substrate 102 outside the strip-shaped trench 101.

[0157] Although the present application has been disclosed as above, it is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate (10) having a plurality of parallel strip-shaped grooves (101) inside; The heterojunction structure (11) is located on the bottom wall and side wall of the strip trench (101) and on the substrate (10) outside the strip trench (101). The heterojunction structure (11) located on the bottom wall and on the substrate (10) outside the strip trench (101) is a polarized region, and the heterojunction structure (11) located on the side wall is a non-polarized region. The polarized region contains charge carriers. The heterojunction structure (11) includes a source region (11a) and a drain region (11b) located at both ends of each strip trench (101) along the length direction, and a gate region (11c) located between the source region (11a) and the drain region (11b). The charge carriers between the source region (11a) and the drain region (11b) are confined to flow within each polarized region.

2. The semiconductor structure according to claim 1, characterized in that, The cross-section of the strip groove (101) is rectangular or trapezoidal.

3. The semiconductor structure according to claim 1, characterized in that, The cross-section of the strip groove (101) is V-shaped, inverted trapezoidal, or bowl-shaped.

4. The semiconductor structure according to claim 3, characterized in that, Each of the strip grooves (101) is directly connected so that the heterojunction structure (11) located at the connection of adjacent strip grooves (101) is linearly distributed.

5. The semiconductor structure according to claim 1, characterized in that, The heterojunction structure (11) does not fill the strip-shaped groove (101).

6. The semiconductor structure according to claim 1, characterized in that, The heterojunction structure (11) includes, from bottom to top: a channel layer (111) and a barrier layer (112), or a back barrier layer (113) and a channel layer (111).

7. The semiconductor structure according to claim 1 or 6, characterized in that, The gate region (11c) has a gate insulating layer (12) and a gate (13c) in sequence, the source region (11a) has a source (13a) and the drain region (11b) has a drain (13b).

8. The semiconductor structure according to claim 1, characterized in that, The substrate (10) is a semiconductor substrate (102); or the substrate (10) includes a semiconductor substrate (102), a nucleation layer (103) and a buffer layer (104) stacked from bottom to top.

9. A method for fabricating a semiconductor structure, characterized in that, include: A substrate (10) is provided, and a plurality of parallel strip-shaped grooves (101) are formed in the substrate (10); A heterojunction structure (11) is formed on the bottom wall, side wall, and substrate (10) outside the strip trench (101). The heterojunction structure (11) on the bottom wall and the substrate (10) outside the strip trench (101) is a polarized region, and the heterojunction structure (11) on the side wall is a non-polarized region. The polarized region contains charge carriers. The heterojunction structure (11) includes a source region (11a) and a drain region (11b) located at both ends of each strip trench (101) along the length direction, and a gate region (11c) located between the source region (11a) and the drain region (11b). The charge carriers between the source region (11a) and the drain region (11b) are confined to flow within each polarized region.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, In the step of forming the heterojunction structure (11), the heterojunction structure (11) does not fill the strip-shaped trench (101).

11. The method for fabricating a semiconductor structure according to claim 9, characterized in that, In the step of forming a heterojunction structure (11), the heterojunction structure (11) includes, from bottom to top: a channel layer (111) and a barrier layer (112), or a back barrier layer (113) and a channel layer (111).

12. The method for fabricating a semiconductor structure according to claim 9 or 11, characterized in that, Also includes: A gate insulating layer (12) and a gate (13c) are sequentially formed on the gate region (11c), a source (13a) is formed on the source region (11a), and a drain (13b) is formed on the drain region (11b).

13. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The substrate (10) is a semiconductor substrate (102); before forming the heterojunction structure (11), the fabrication method further includes: forming a nucleation layer (103) on the bottom wall and side wall of the strip trench (101) and on the semiconductor substrate (102) outside the strip trench (101), or forming a nucleation layer (103) and a buffer layer (104) in sequence; Alternatively, the substrate (10) may include a semiconductor substrate (102), a nucleation layer (103), and a buffer layer (104) stacked from bottom to top.

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