Adaptive Equalizer for a Re-Driver

Abstract

A system (210, 230, 240, 250, 260 and / or 280) for selecting an equalizer setting of an equalizer (210) to equalize a signal received via a communication link. Starting from a first (e.g., minimum) equalizer setting and a threshold voltage VTH,MID near the mid-eye voltage of the equalized output signal, the system estimates the amplitude of the inner eye of the equalized output signal by comparing the equalized output signal with a series of threshold voltages. If the amplitude of the equalized output signal is less than an ideal value, the system dynamically increases the equalizer setting. The system converges quickly to the equalizer setting of the communication link because the system does not use each equalizer setting to compare the output signal at each voltage offset, but only evaluates the equalizer settings required to select the equalizer setting for the communication link and only uses the voltage offsets required to evaluate each equalizer setting.

Description

Background Art

[0001] The Universal Serial Bus (USB) interface is one of the most popular computer interfaces. Since its inception, each released USB standard has supported increasing throughput. The USB 1.x standard released in 1998 supported data rates of 1.5 to 12 megabits per second (Mbps). USB 3.2 supports two channels, each with a throughput of 10 gigabits per second (Gbps) on a single interface. However, high-speed USB signals suffer increased signal integrity degradation on long printed circuit board (PCB) traces and USB cables. Insertion loss is the most common problem, which is the loss of signal power caused by any medium in the signal path.

[0002] Other simplex buses (such as High-Definition Multimedia Interface (HDMI), Peripheral Component Interconnect Express (PCIe), etc.) have similar problems with signal integrity degradation. In addition to long traces and cable connections, signals may also be subject to signal integrity degradation due to cross connectors and capacitive lines.

[0003] To improve signal quality, systems typically include a re-driver that improves the signal quality of the transmitted and received signals, enabling the system to maintain signal integrity at higher data rates and longer traces and cables. Summary of the Invention

[0004] A system for selecting equalizer settings to equalize a signal received via a communication link. Starting from a first equalizer setting (e.g., the minimum equalizer setting of the equalizer) and a threshold voltage near the mid-eye voltage of the equalized output signal, the system determines a baseline number indicative of the number of times the equalized output signal crosses the threshold voltage during a predetermined time interval. The system collects information sufficient to estimate the amplitude of the inner eye of the equalized output signal by increasing the voltage offset from the mid-eye voltage. If the amplitude of the equalized output signal is less than an ideal value, the system dynamically increases the equalizer setting.

[0005] By comparing the equalized output signal with a plurality of voltage offsets using a plurality of equalizer settings, the system is able to select the equalizer settings for each newly established communication link (e.g., during link training). Also, the process performed by the system is more efficient than prior art processes because it does not use each equalizer setting to compare the equalized output signal at each voltage offset. Instead, the system only evaluates the equalizer settings required to select the communication link settings and only uses the voltage offsets required to evaluate each of these equalizer settings. By using this efficient process, the controller quickly converges on the equalizer settings to equalize the signal received via the communication link by determining whether the output signal is over-equalized, whether the equalizer is set to the maximum equalizer setting, or whether the eye of the equalized output signal at the equalizer setting is fully open. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a detailed description of various examples, reference will now be made to the accompanying drawings, in which:

[0007] Figure 1A is an eye diagram illustrating signal loss of a USB signal as the data rate increases.

[0008] Figure 1B is an eye diagram illustrating signal loss of a USB signal as the cable length increases.

[0009] Figure 1C is a block diagram illustrating a USB re-driver.

[0010] Figure 2 is a block diagram of a system for determining equalizer settings to equalize a signal received via a communication link according to an illustrative embodiment.

[0011] Figure 3 is a block diagram of a divider and counter according to an illustrative embodiment.

[0012] Figure 4A is a waveform of an example equalized output signal using a first equalizer setting.

[0013] Figure 4B is using a second equalizer setting Figure 4A of an example equalized output signal waveform.

[0014] Figure 5A is an example cumulative distribution function of a USB channel.

[0015] Figure 5B is shorter than the USB channel for generating Figure 5A of an example cumulative distribution function of a USB channel of an example cumulative distribution function.

[0016] Figure 6is a flowchart illustrating a novel process for effectively selecting equalizer settings to equalize a signal received via a communication link according to an illustrative embodiment.

[0017] Figure 7 illustrates the execution according to an illustrative embodiment Figure 6 of the process Figure 2 of how a system according to an illustrative embodiment can more effectively select Figure 5A equalizer settings for an example channel than prior art systems. Detailed Description

[0018] Figure 1A is an eye diagram (e.g., voltage versus time plot) illustrating signal loss of a USB signal (on a 36-inch printed circuit board trace) as the data rate increases. At 250 Mbps, eye 101 is very clean / open, indicating very little signal loss. As the speed increases to 2 Gbps, eye 101 experiences degradation. At 4 Gbps, eye 101 is almost closed, resulting in a significant bit error. Finally, at 6 Gbps, eye 101 is completely closed and the system will not be able to correctly decode data without any signal conditioning.

[0019] Similarly, a USB signal experiences higher signal degradation over longer cable (or printed circuit board trace) lengths. Figure 1B is an eye diagram illustrating signal loss of a 10 Gbps USB signal as the cable length increases. On a 1 meter (m) cable, eye 101 is very clean / open, indicating very little signal loss. As the cable length increases to 5 m, eye 101 begins to close and when the cable length increases to 10 m, the eye is completely closed.

[0020] Figure 1C is a block diagram illustrating a re-driver 150 coupled to a USB controller 110 and a USB port 190. As Figure 1C shown, re-driver 150 improves the signal quality of transmitted signal 120 and received signal 180 such that the system can maintain signal integrity at higher data rates and over longer traces and cables. To improve the quality of transmitted signal 120, re-driver 150 changes the shape of transmitted signal 120 to generate transmitted signal 122, which will be easier to recover after it has attenuated due to cross-channel propagation.

[0021] To improve the quality of the received signal 180, the re-driver 150 may include an equalizer that compensates for attenuation that occurs during transmission by amplifying the received signal 180 and generating an equalized output signal 182. For receive equalization, it is desirable to apply an appropriate amount of equalization. Applying too small a gain (under-equalization) may prevent the signal from being correctly recovered. At the same time, amplifying the received signal 180 by more than the amount by which the received signal 180 was attenuated will over-equalize the received signal, which can interfere with the receiver's ability to recover data. For example, over-equalization may cause the bit transition amplitude to be too large, which may cause compliance issues with system specifications for logic high and logic low tolerances and may cause separation of the rising and falling edges (commonly referred to as "double-band"), which may interfere with the receiver's ability to correctly detect the frequency or maintain the correct phase relationship with the input data.

[0022] The optimal amount of equalization that maximizes signal quality depends on several factors, including the data rate and channel characteristics (e.g., trace and cable length). Accordingly, the re-driver 150 may perform receive equalization using an adaptive equalizer and select an equalizer setting for each newly established communication link. When a new communication link is established, the device may participate in a link training process during which the re-driver 150 may select an equalizer setting for the newly established communication link.

[0023] U.S. Patent No. 10,038,577 (the entire content of which is incorporated herein by reference) describes a system for selecting an equalizer setting to equalize the received signal 180. The system of U.S. Patent No. 10,038,577 determines a preferred equalizer setting by comparing the output signal of the equalizer at each equalizer setting with each of a number of predetermined threshold voltages. By comparing the equalized output signal at each equalizer setting with each predetermined threshold voltage, the system of U.S. Patent No. 10,038,577 is ultimately able to select an equalizer setting for a newly established communication link. However, during link training, the equalizer setting must be selected quickly to minimize the impact on other link training processes. At the same time, the system described in U.S. Patent No. 10,038,577 is inefficient and may therefore not be able to select the equalizer setting quickly enough to minimize the impact on other link training processes.

[0024] The present system performs a more efficient process for selecting an equalizer setting to equalize a signal received via a communication link. Instead of taking each equalizer setting and comparing each equalized output signal with each threshold voltage, the system only evaluates the equalizer settings required to select an equalizer setting for the communication link and only uses the threshold voltages required to evaluate each of these equalizer settings.

[0025] Figure 2is a block diagram of an example system 200 for selecting equalizer settings to equalize a signal received via a communication link according to an illustrative embodiment. As Figure 2 shown, in some embodiments, system 200 may be implemented in a re-driver 150, a USB controller 110, and / or a USB port 190, and system 200 includes an equalizer 210, a comparator 230, a divider 240, a counter 250, a controller 260, and a digital-to-analog converter (DAC) 280. In Figure 2 an example, controller 260 includes a processing unit 262, a memory 264, and a program timer 268. Equalizer 210 receives a digital input signal RXIN and outputs an equalized output signal. (As shown in FIG. 1, for example, equalizer 210 may receive received signal 180 from USB port 190 and output equalized output signal 182.) Equalizer 210 is an adaptive equalizer having a plurality of preset configurations (referred to herein as "equalizer settings") that control the equalization function employed by equalizer 210. As Figure 2 shown, controller 260 is coupled to equalizer 210, enabling controller 260 to set the active equalizer setting EQ of equalizer 210. Controller 260 is also coupled to the analog input of DAC 280, which enables controller 260 to specify a threshold voltage V TH . For example, DAC 280 may be configured to output a plurality of predetermined threshold voltages V TH in response to one of a plurality of predetermined multi-bit control signals from controller 260. Thus, controller 260 may be configured to output one of the plurality of predetermined threshold voltages V TH to comparator 230 by outputting the predetermined multi-bit control signal associated with the selected threshold voltage V TH to DAC 280.

[0026] Comparator 230 includes a first input (e.g., non-inverting input) coupled to the output of equalizer 210 and a second input (e.g., inverting input) coupled to the analog output of DAC 280, enabling comparator 230 to compare the instantaneous voltage output by equalizer 210 with the threshold voltage V TH specified by controller 260. For example, in Figure 2 an example, the output of equalizer 210 is coupled to the positive input of comparator 230, and the analog output of DAC 280 is coupled to the negative input of comparator 230. Thus, in this embodiment, when the instantaneous voltage output by equalizer 210 is greater than the threshold voltage V TH specified by controller 260, the output of comparator 230 is high, and when the instantaneous voltage output by equalizer 210 is less than the threshold voltage V TH specified by controller 260, the output of comparator 230 is low. Thus, inFigure 2 In an example, whenever the instantaneous voltage of the equalized output signal rises above the threshold voltage V TH of the voltage, the comparator 230 outputs a rising signal edge. In other embodiments, the input of the comparator 230 can be inverted such that when the instantaneous voltage output by the equalizer 210 is less than the threshold voltage V TH specified by the controller 260, the output of the comparator 230 is high, and when the instantaneous voltage output by the equalizer 210 is greater than the threshold voltage V TH specified by the controller 260, the output of the comparator 230 is low. In those embodiments, whenever the instantaneous voltage of the equalized output signal drops below the threshold voltage V TH of the voltage, the comparator 230 outputs a rising signal edge, and whenever the instantaneous voltage of the equalized output signal rises above the threshold voltage V TH of the voltage, the comparator 230 outputs a falling signal edge.

[0027] The counter 250 is a digital counter that stores a binary increment value indicating the number of times the instantaneous voltage of the equalized output signal rises above the threshold voltage V TH specified by the controller 260. Since the output of the comparator 230 can have a higher frequency than the operating frequency of the counter 250, the comparator 230 can be coupled to the counter 250 via a divider 240. For example, in Figure 2 an example, the output of the comparator 230 is coupled to the counter 250 via a divider 240, and the divider divides the input of the comparator 230 by outputting one signal edge for every N signal edges output by the comparator 230. In one example, N is eight, and the divider 240 outputs one signal edge for every eight signal edges output by the comparator. Thus, Figure 2 the counter 250 counts the rising signal edges output by the comparator 230 (each indicating that the equalized output signal has risen to cross the threshold voltage V TH ), as divided by the divider 240. (In other embodiments, the output of the comparator 230 can be coupled to the counter 250 without an intermediate divider 240. Additionally, in other embodiments, the counter 250 can be configured to count the falling signal edges output by the comparator 230 or the divider 240 or both the rising and falling signal edges output by the comparator 230 or the divider 240.)

[0028] In Figure 2 an example, the controller 260 is coupled to the counter 250, enabling the controller 260 to read the value stored in the counter 250 and output control signals to the counter 250 to start, pause, or reset the counting. As described below with reference to Figure 3As described, for example, the controller 260 may assert an enable count signal to cause the counter 250 to start counting the signal output by the comparator 230 (in some embodiments, divided by the divider 240) until the controller 260 de-asserts the enable count signal. In other embodiments, the controller 260 may assert a separate disable or pause count signal.

[0029] The programmed timer 268 defines a predetermined time interval during which the counter 250 counts the number of times the equalized output signal from the equalizer 210 rises and crosses the selected threshold voltage V TH (as detected by the comparator 230 and, in some embodiments, divided by the divider 240).

[0030] The predetermined time interval is long enough for the system 200 to compare the equalized output signal of the equalizer 210 with the selected threshold voltage V over multiple cycles of the equalizer 210. TH In some embodiments, the predetermined time interval may be constant. In other embodiments, the predetermined time interval may be selected, for example, by the controller 260 based on the frequency of the equalized output signal of the equalizer 210. For example, for a higher frequency output signal from the equalizer 210, the predetermined time interval may be shorter, and for a lower frequency output signal from the equalizer 210, the predetermined time interval may be longer, such that the system 200 can compare the equalized output signal of the equalizer 210 with the selected threshold voltage V in a similar number of cycles TH regardless of the frequency of the output signal.

[0031] The controller 260 may comprise any hardware device suitably configured to perform the functions described herein. In some embodiments, for example, the controller 260 may be a hardware state machine configured to perform the functions described herein. In Figure 2 embodiments, the controller 260 comprises a processing unit 262 (e.g., a microprocessor, microcomputer, microcontroller, and / or processor implemented on an integrated circuit chip) and a memory 264 storing instructions (e.g., a non-transitory computer-readable storage medium, volatile memory, and / or non-volatile memory) that, when executed by the processing unit 262, cause the processing unit 262 to perform the functions herein.

[0032] As mentioned above, equalizer 210 is configured to amplify a signal received from another device via a communication link (e.g., USB, HDMI, PCIe, etc.). Equalizer 210 can be a continuous-time linear equalizer (CTLE), a decision feedback equalizer (DFE), a feed-forward equalizer (FFE), or any other suitable type of equalizer. Equalizer 210 has a plurality of equalizer settings that control the equalization function employed by equalizer 210. For example, equalizer 210 can include 16 equalizer settings, herein referred to as "equalizer setting 0" through "equalizer setting 15". These equalizer settings can include a minimum equalizer setting (equalizer setting 0), which, from the plurality of equalizer settings, causes equalizer 210 to perform a minimum amount of signal equalization and introduce the least amount of signal gain. In this example, the plurality of equalizer settings can incrementally increase from equalizer setting 0 to equalizer setting 15, where each incrementally larger equalizer setting performs a greater amount of signal equalization and introduces more signal gain. Finally, the plurality of equalizer settings can include a maximum equalizer setting (in this example, equalizer setting 15), which, from the plurality of equalizer settings, causes equalizer 210 to perform the highest amount of signal equalization and introduce the highest amount of signal gain.

[0033] Equalizer 210 amplifies the signal received via the communication link to compensate for the attenuation that occurs along the stacked communication link. Since the amount of attenuation for each communication link is different, the optimal amount of equalization to compensate for the attenuation is different for each communication link. The amount of equalization performed by equalizer 210 depends on the equalizer settings of equalizer 210. Thus, the equalizer setting selected to equalize the signal received via each communication link is different for each communication link. Accordingly, during link training for a newly established communication link, system 200 enables controller 260 to perform a calibration process to select the equalizer settings of equalizer 210 for equalizing the signal received via the newly established communication link.

[0034] During link training, each device generates and transmits a training pattern specified by the relevant communication standard (e.g., USB, HDMI, PCIe, etc.). For example, during USB link training, the USB system-on-chip (SOC) of the host generates and transmits a training pattern to the USB device, and the USB SOC of the USB device generates and transmits a training pattern to the host. During link training, equalizer 210 receives the training pattern generated by the device at the other end of the communication link and attenuated in the course of the communication link. Equalizer 210 equalizes the attenuated training pattern according to the active equalizer setting EQ of equalizer 210 and outputs an equalized output signal.

[0035] To select an equalizer setting to equalize a signal received via a newly established communication link, system 200 enables controller 260 to evaluate each equalizer setting of equalizer 210 by dynamically setting the active equalizer setting EQ of equalizer 210 and estimating the amplitude of the eye diagram of the equalized output signal generated using each equalizer setting. To estimate the amplitude of the eye diagram of each equalized output signal, system 200 enables controller 260 to output a series of threshold voltages V TH to comparator 230 and use counter 250 to count a number indicative of the number of times each equalized output signal rises to cross each threshold voltage V TH . Additionally, process 600 for selecting an equalizer setting for a newly established communication link performed by controller 260 is more efficient than conventional methods. Instead of adopting each equalizer setting and comparing each equalized output signal with each threshold voltage V TH , system 200 only evaluates the equalizer settings required to select an equalizer setting for the communication link and only uses the threshold voltages V TH required to evaluate each of these equalizer settings. As described below with reference to Figure 6 and 7 , if the number of crossings of the equalized output signal with threshold voltage V TH is less than a baseline number, then controller 260 increases the active equalizer setting EQ of equalizer 210 and estimates the amplitude of the eye diagram of the equalized output signal generated using the increased equalizer setting. By using this efficient process 600, controller 260 quickly selects an equalizer setting to equalize a signal received via a newly established communication link by determining whether the output signal is over-equalized, whether equalizer 210 is set to the maximum equalizer setting, or whether the eye of the equalized output signal generated using one of the equalizer settings is fully open.

[0036] Figure 3 is a block diagram of divider 240 and counter 250 according to an illustrative embodiment. Divider 240 can be any circuit that outputs one signal edge for every N signal edges output by comparator 230. Divider 240 can include, for example, n flip-flops 341, each of which outputs one signal edge for every two received signal edges. In those embodiments, the divider divides the signal edge by N, where N = 2 n . For example, in the instance of Figure 3 , divider 240 includes three flip-flops 341 that together divide the signal edge output by comparator 230 by 2 3 or 8.

[0037] In Figure 3In an example, the counter 250 includes a synchronizer 351, a ripple counter 356, and a synchronous counter 358. The synchronizer 351 can be any digital circuit configured to convert a signal received by the counter 250 into the clock domain of the counter 250, enabling the counter 250 to capture asynchronous signals without introducing metastable faults. In Figure 3 In an example, the divider 240 is coupled to the synchronizer 351 via the comp_hits signal line, and the controller 260 is coupled to the synchronizer 351 via the enable_counting signal line. The synchronizer 351 receives a signal from the divider 240, including an instantaneous voltage of the equalized output signal of the equalizer 210 and a threshold voltage V specified by the controller 260 TH crossing rising signal edges. When the signal line asserts the enable counting signal, the synchronizer 351 outputs a signal in response to each signal received from the divider 240. When the enable counting signal from the controller 260 is deasserted, the synchronizer 351 ignores any additional signals from the comparator 230.

[0038] In Figure 3 In an example, the synchronizer 351 includes two flip-flop synchronizers 352, which include a first flip-flop 352a and a second flip-flop 352b. The second flip-flop 352b (e.g., via the Q-bar output) is coupled to a first AND gate 353, the first AND gate 353 is coupled to a latch 354, and the latch 354 is coupled to a second AND gate 355. (As will be appreciated by those of ordinary skill in the art, in other embodiments, the synchronizer 351 can be implemented using any of a number of alternative configurations.) The divider 240 is coupled to the clock input of the two flip-flop synchronizers 352 via the comp_hits signal line. The controller 260 is coupled to the data input (D) of the first flip-flop 352a of the two flip-flop synchronizers 352 via the enable_counting signal line. When the enable_counting signal is asserted, the two flip-flop synchronizers 352 output a copy of the enable signal synchronized with the comp_hits signal in response to the signal edges received via the comp_hits line. When the enable_counting signal and the synchronous copy are asserted, the first AND gate 353 outputs a constant enable. Whenever the signal output by the divider 240 via the comp_hits signal line is low, the latch 354 latches the output of the first AND gate 353. When the output of the latch 354 is high, the second AND gate 354 outputs a comp_hits pulse. Thus, the synchronizer 351 converts the signals output by the divider 240 into the clock domain of the counter 250 and provides those signals to the ripple counter 356.

[0039] In Figure 3In an example, synchronizer 351 is coupled to ripple counter 356, and ripple counter 356 is coupled to synchronous counter 358. Controller 260 is coupled to ripple counter 356 and synchronous counter 358 via the hit_counts signal line and the reset_counter signal line. To keep up with the frequency of the output signal from divider 240, ripple counter 356 is a fast enough counter. At the same time, synchronous counter 358 counts and resets the number of times the ripple counter 356 counts beyond its maximum count value. (In other embodiments, the functions of ripple counter 356 and synchronous counter 358 may be performed by a single counter that is fast enough to keep up with the frequency of the output signal from comparator 230 or divider 240 and includes a sufficient number of bits to count the number of times the threshold voltage V TH has been crossed.) In Figure 3 the example, ripple counter 356 is a 4-bit counter implemented by four flip-flops 3570 to 3573, and synchronous counter 358 is a 28-bit counter using twenty-eight flip-flops 3574 to 357 31 and twenty-six AND gates 3596 to 359 31 implemented. (In other embodiments, ripple counter 356 and / or synchronous counter 358 may store any number of bits.) In Figure 3 the example, the 4-bit ripple counter 356 counts from its reset state 0000 to its maximum count value 1111, at which time the output of the not-Q (also known as Q-bar) of flip-flop 3573 outputs a signal to the 28-bit synchronous counter 358 to increment its count value by 1. In Figure 3 the example, the 4-bit ripple counter 356 and the 28-bit synchronous counter 358 generate a 32-bit count value that is output to controller 260 via the Q outputs of flip-flops 3570 to 3573 via the hit_counts signal line. Then, ripple counter 356 and synchronous counter 358 reset their count values in response to a signal received from controller 260 via the reset_counter signal line.

[0040] In Figures 2 to 3 the example, counter 250 is configured to count the number of rising signal edges when the equalized output signal rises above a selected threshold voltage V TH of voltage, each of the rising signal edges being output by comparator 230 (and in some embodiments, divided by divider 240). However, in other embodiments, counter 250 may compare the equalized output signal voltage with the selected threshold voltage V THThe total number of crossings (in some embodiments, as divided by divider 240) is counted regardless of whether the voltage of the equalized output signal is increasing or decreasing. In those embodiments, for example, comparator 250 may be configured to count the total number of rising and falling signal edges output by comparator 230 or divider 240.

[0041] Figure 4A 4 is an example waveform of the equalized output signal 401 output by the equalizer 210 using the first equalizer setting. The horizontal axis represents time, and the vertical axis represents voltage (where each gray scale represents a different threshold voltage THR0 to THR14). Figure 4A As shown in FIG. 4 , the equalized output signal 401 is at a voltage V MID At the same time, in the above described Figure 2 In the example of FIG. 2 , the controller 260 is configured to output a plurality of predetermined threshold voltages V to the comparator 250. TH Each of the fifteen threshold voltages (e.g., from THR0 to THR14) (by outputting each of a plurality of predetermined control signals to DAC 280). The threshold voltages (e.g., THR0 to THR14) may be a range of discrete voltage levels uniformly (or non-uniformly) distributed between a desired minimum voltage level THR0 and a desired maximum voltage level THR14 of the equalized output signal output by equalizer 210. In those embodiments, the threshold voltage V output by controller 260 TH The number can be an odd number, and the median threshold voltage V TH (eg, THR7) may be at or near the mid-eye voltage V of the equalized output signal 401. MID In other embodiments, the number of threshold voltages may be an even number, for example, at or near the mid-eye voltage V MID The two threshold voltages V TH .

[0042] Using counter 250, controller 260 can then determine whether the eye of the equalized output signal is open by counting the number of times (“hits”) that the instantaneous voltage of the equalized output signal 401 increases to a voltage greater than each of the specified threshold voltages THR0 to THR14 during a predetermined time interval. To serve as a baseline, controller 260 counts the closest eye voltage V MID The threshold voltage V TH (This article refers to the middle eye threshold voltage V TH,MID ) is counted. Figure 4A As shown in , for example, the controller 260 may output a threshold voltage THR7 and count the number of times the voltage of the equalized output signal 401 increases to a voltage greater than the threshold voltage THR7 during a predetermined time interval implemented by the programming timer 268.Figure 4A In the example shown, the equalized output signal 401 rises and crosses the threshold voltage THR7 six times (HITS = 6).

[0043] Then, the controller 260 can select a threshold voltage V TH,MID that is incrementally greater than the middle eye threshold voltage V TH (e.g., THR8), and count the number of times the voltage of the output signal 401 increases to a voltage greater than the selected threshold voltage THR8 within the same predetermined time interval. In Figure 4A the example shown, the rising equalized output signal 401 crosses the threshold voltage THR8 six times again (HITS = 6). The controller 260 can also select a threshold voltage V TH,MID that is incrementally less than the middle eye threshold voltage V TH (e.g., THR6), and count the number of times the voltage of the equalized output signal 401 increases and crosses the selected threshold voltage THR6 (six times in this example).

[0044] As Figure 4A shown, by selecting the threshold voltages THR8 and THR6 that are greater than and less than the middle eye threshold voltage V TH,MID , the system 200 increases the voltage offset V TH,MID from the middle eye threshold current V OFFSET . Then, the system 200 can incrementally increase the voltage offset V OFFSET (e.g., by selecting the threshold voltages THR9 and THR5, and then selecting the threshold voltages THR10 and THR4), and count the number of hits at each of the selected threshold voltages V TH .

[0045] By increasing the voltage offset V OFFSET and counting the number of hits at the selected threshold voltage V TH , the controller 260 can estimate the amplitude of the inner eye of the equalized output signal 401 for the active equalizer setting EQ. If the number of hits at the selected voltage offset V OFFSET equals the baseline number of hits at the middle eye threshold voltage V TH,MID , then the eye of the equalized output signal 401 is considered "open". When the voltage offset V OFFSET is further increased to the threshold voltage V TH , the amplitude of the inner eye of the equalized output signal 401 becomes evident, where the number of hits drops below the baseline number of hits at the middle eye threshold voltage V TH,MID (and the eye of the equalized output signal is considered "closed"). For the example equalizer setting illustrated in Figure 4A , when the voltage offset VOFFSET When increased to threshold voltages THR9 and THR5, the number of hits drops below the baseline (in this example, 6 hits).

[0046] After estimating the amplitude of the estimated equalized output signal 401 as shown in Figure 4A , the controller 260 may increase the active equalizer setting EQ of the equalizer 210 and determine whether the newly specified equalizer setting increases the amplitude of the equalized output signal 401 (e.g., as shown in Figure 4B ).

[0047] Figure 4B is the waveform of an example equalized output signal 401 output by the equalizer 210 using a second equalizer setting. Again, the number of hits (in this example, 6) at the mid-eye threshold voltage V TH,MID (in this example, the threshold voltage THR7) can be used as a baseline. Then, the controller 260 may repeatedly increase the voltage offset V OFFSET , and count the number of hits at the threshold voltage V TH , where the threshold voltage V TH is incrementally greater than and incrementally less than the mid-eye threshold voltage V MID,TH . In the example shown in Figure 4B , the equalized output signal 401 rises and crosses each of the threshold voltages THR3 to THR11 six times. When the voltage offset V OFFSET is further increased to the threshold voltages THR13 and THR2, the number of hits only drops (in this example, drops to 5).

[0048] In some examples, there may be error conditions (e.g., data path offset, clock frequency instability, comparator metastability, etc.) such that the number of hits at the selected voltage offset V OFFSET does not indicate the amplitude of the inner eye of the equalized output signal. If such error conditions persist, then the number of hits cannot be used reliably to evaluate the equalizer settings. However, if such error conditions exist, then the equalized output signal 401 is unlikely to have a reasonable symmetric shape around the mid-eye voltage V MID . Thus, by counting the number of hits at voltage offsets V TH,MID that are greater than and less than the mid-eye threshold voltage V OFFSET , the controller 260 can ensure that there are no error conditions (and ensure that the number of hits can be reliably used to evaluate each equalizer setting) by confirming that the equalized output signal 401 has a reasonable symmetric shape around the mid-eye voltage V MID .

[0049] By using the mid-eye threshold voltage V TH,MIDUsing the number of hits at [location] as a baseline, the controller 260 can also quickly determine whether the output signal is over - equalized. If the output signal is over - equalized, then using the voltage offset V OFFSET the number of hits for at least one of OFFSET will be higher than the baseline, while using the other voltage offset V OFFSET the number of hits will be equal to or lower than the baseline. Thus, if the number of hits at voltage offset V TH,MID is greater than the number of hits at the middle - eye threshold voltage V

[0050] By viewing the full cumulative distribution function showing the number of hits at each threshold voltage V TH for each of the equalizer settings of the equalizer 210, the selection of the equalizer setting to equalize the signal received via the communication link can be best illustrated.

[0051] Figure 5A is the example cumulative distribution for the first USB channel. The horizontal axis represents the threshold voltage V TH and the vertical axis represents the number of hits (e.g., the number of times the instantaneous voltage of the equalized output signal output by the comparator 210 crosses the threshold voltage V TH ). The full cumulative distribution shows the number of hits at each threshold voltage V TH for each equalizer setting (e.g., equalizer setting 0 to equalizer setting 15).

[0052] At Figure 5A the example cumulative distribution, the number of hits recorded at the middle - eye threshold voltage V TH,MID (in this example, the threshold voltage THR7) can be used as a baseline. Using equalizer setting 0 (EQ = 0), when the voltage offset V OFFSET first increases to the threshold voltages THR6 and THR8, the number of hits drops below the baseline. The same is true for equalizer setting 1 (EQ = 1). However, further increasing the equalizer setting increases the amplitude of the output signal and causes the output signal to record the baseline number of hits using increasingly large voltage offsets V OFFSET . For example, using equalizer setting 9 (EQ = 9), when the voltage offset V OFFSET increases all the way to the threshold voltages THR2 and THR12, the equalized output signal maintains the baseline number of hits. The number of hits recorded using equalizer setting 9 does not drop below the baseline until the voltage offset V OFFSET is further increased to the threshold voltages THR1 and THR13.

[0053] As Figure 5AAs shown, increasing the equalizer setting to equalizer setting 10 (EQ = 10) does not meaningfully improve the equalized output signal because the equalized output signal still does not record the number of baseline hits at the threshold voltages THR1 and THR13. At the same time, at equalizer setting 11 (EQ = 11), Figure 5A the output signal shown in TH,MID is over-equalized, and thus, the number of hits recorded at the threshold voltages THR1 and THR13 is greater than the number of baseline hits at the middle-eye threshold voltage V

[0054] The equalizer setting selected to equalize the signal received via the communication link is the lowest equalizer setting of equalizer 210 that keeps the equalized output signal at the highest voltage offset V OFFSET at the number of baseline hits. The lowest equalizer setting is the setting of the equalizer settings from equalizer 210 where equalizer 210 performs the least amount of signal equalization and results in the least amount of gain. Thus, equalizer setting 9 is the equalizer setting for equalizing the signal received via the USB channel used to generate Figure 5A the example cumulative distribution function shown in OFFSET because using equalizer setting 9 keeps the equalized output signal at the number of baseline hits at voltage offset V OFFSET at the threshold voltages THR2 and THR12. Further increasing the active equalizer setting to equalizer setting 10 will not cause the equalized output signal to keep the number of baseline hits at a higher voltage offset V

[0055] As mentioned above, the equalizer setting for equalizing the signal received via each communication link depends on many factors, including the channel length.

[0056] Figure 5B is an example cumulative distribution function of a second USB channel that is shorter than the first USB channel for which the example cumulative distribution function shown in Figure 5A is generated. As Figure 5B shown, the equalizer for equalizing the signal received via the second USB channel is equalizer setting 0 (EQ = 0) because the equalized output signal keeps the number of baseline hits (recorded at the middle-eye threshold voltage V TH,MID , which is also the threshold voltage THR7 in this example) at voltage offset V OFFSET at the threshold voltages THR2 and THR13. At the same time, increasing the equalizer setting to equalizer setting 1 (EQ = 1) will over-equalize the output signal, and thus, using the voltage offset V OFFSET at the threshold voltages THR1 and THR12 causes the number of hits recorded by the output signal to exceed the baseline.

[0057] As described above, the number of "hits" may be equal to the number of times the instantaneous voltage of the equalized output signal rises above the selected threshold voltage V TH during a predetermined time interval. However, as described above, in some embodiments, the counter 250 may count signal edges indicating that the equalized output signal has dropped below the selected threshold voltage V TH or (in the case of all signal edges indicating that the equalized output signal has crossed the selected threshold voltage V TH in either direction). Meanwhile, in the Figure 2 example, the divider 240 divides the output of the comparator 230 by (in this example, by 8) and outputs the divided output of the comparator 230 to the counter 250. Thus, the number of "hits" recorded by the system 200 may indicate - but not necessarily be equal to - the number of times the equalized output signal crosses (rising, falling, or both) the selected threshold voltage V TH during a predetermined time interval.

[0058] In addition, as described above, the controller 260 compares the number of hits at various threshold voltages V TH to determine whether the eye of the equalized output signal is open or closed, whether there is an error condition, or whether the output signal is over-equalized. For example, if the number of hits at the voltage offset V OFFSET is equal to the baseline number of hits at the mid-eye threshold voltage V TH,MID , then the eye of the equalized output signal is considered "open". However, if the eye of the equalized output signal is open, the number of hits at the voltage offset V OFFSET may be slightly lower or higher than the baseline. Thus, if the two hits (above and below the mid-eye threshold voltage V OFFSET ) at the selected voltage offset V TH,MID are both within a predetermined margin of the baseline, then the controller 260 may determine that the eye of the equalized output signal is open. By extension, if either hit (above or below the mid-eye threshold voltage V OFFSET ) at the selected voltage offset V TH,MID is less than the baseline by an amount equal to or greater than the predetermined margin, then the controller 260 may determine that the eye of the equalized output signal is closed. In addition, if either hit (above or below the mid-eye threshold voltage V OFFSET ) at the selected voltage offset V TH,MID is greater than the baseline by an amount equal to or greater than the predetermined margin, then the controller 260 may determine that the output signal is over-equalized. A similar predetermined margin may be used when determining whether there is an error condition. The predetermined margin may be a percentage of the baseline, an integer, etc.

[0059] Over sufficient time, the equalizer settings for each newly established communication link can be selected by generating a full cumulative distribution function such as those shown in Figure 5A and 5B . For example, the system described in U.S. Patent No. 10,038,577 effectively generates a full cumulative distribution function by comparing the output signal of the equalizer at each equalizer setting with each predetermined threshold voltage. However, as mentioned above, it is desirable to select the equalizer settings as quickly as possible in order to minimize the impact on other link training processes. At the same time, the full cumulative distribution function contains more information than is required to select an equalizer setting to equalize the signal received via the communication link.

[0060] Briefly referring back to Figure 5A , using equalizer setting 0 (EQ = 0), the number of hits at threshold voltages THR6 and THR8 is below the baseline by more than a predetermined margin. Therefore, there is no need to use equalizer setting 0 to further increase the voltage offset V OFFSET . It can be assumed that at a threshold voltage V MID further from the center eye voltage V TH , the number of hits will further decrease. Instead, the controller 260 can increase the equalizer setting to equalizer setting 1 and determine whether the number of hits at threshold voltages THR6 and THR8 increases. Similarly, after determining that the number of hits using equalizer setting 0 at threshold voltages THR6 and THR8 is below the baseline and deciding to increase the active equalizer setting to equalizer setting 1, there is no need to reset the threshold voltage to THR7 and count the number of hits at the center eye threshold voltage V TH,MID using equalizer setting 1. Instead, the controller 260 can maintain the selected voltage offset V OFFSET (in this example, the selected threshold voltages THR6 and THR8) and increase the active equalizer setting EQ until the number of hits equals the baseline. Then, the controller 260 can maintain increasing the active equalizer setting EQ and incrementally increase the voltage offset V OFFSET until the voltage offset V OFFSET reaches its limit (e.g., the voltage offset V Figure 5A and 5B to the threshold voltages THR0 and THR14 of OFFSET ), the active equalizer setting EQ is the maximum equalizer setting of the equalizer 210, or the active equalizer setting EQ overequalizes the output signal.

[0061] Figure 6is a flowchart illustrating a novel process 600 for effectively selecting equalizer settings to equalize a signal received via a communication link according to the illustrated embodiments. Process 600 may be performed by system 200, such as during link training, to identify equalizer settings for equalizer 210 to equalize a signal received via a newly established communication link. During process 600, equalizer 210 receives a training pattern and outputs an equalized output signal.

[0062] At step 602, the active equalizer setting EQ of equalizer 210 is set to a first equalizer setting. In an embodiment, the first equalizer setting is the minimum equalizer setting of equalizer 210. As described above, the minimum equalizer setting is an equalizer setting from a plurality of equalizer settings that causes equalizer 210 to perform a minimum amount of signal equalization and introduce a minimum amount of signal gain. As described above, the active equalizer setting EQ of equalizer 210 may be set by controller 260.

[0063] At step 604, an indication of the first equalizer setting is stored as a variable (e.g., "SAVED_EQ"). The variable may be stored by controller 260 (e.g., stored in memory 264). As described below, process 600 is recursive, and the variable may be updated whenever step 654 is performed during the recursive process 600 to reflect the active equalizer setting EQ of equalizer 210. When process 600 ends, the variable reflects the equalizer setting of equalizer 210 that is selected to equalize a signal received via the communication link as determined using process 600. Although the variable is referred to below as SAVED_EQ, one of ordinary skill in the art will recognize that any variable name may be used.

[0064] At step 606, the mid-eye voltage V MID of the equalized output signal output by equalizer 210 (e.g., when equalizer 210 is set to equalizer setting 0) is output. TH,MID For example, controller 260 may select the threshold voltage V TH from a plurality of predetermined threshold voltages V MID that is closest to the mid-eye voltage V TH of the equalized output signal output by equalizer 210. In the example shown in FIGS. 4 and 5, for example, the mid-eye threshold voltage V TH,MID is threshold voltage THR7. Controller 260 may then output the mid-eye threshold voltage V TH,MID to comparator 230. For example, controller 260 may output a control signal associated with the mid-eye threshold voltage V TH,MID to DAC 280, causing DAC 280 to output the mid-eye threshold voltage V TH,MID to comparator 230.

[0065] In step 610, the number of baseline hits at the mid-eye threshold voltage V TH,MID is recorded. For example, comparator 230 may compare the equalized output signal output by equalizer 210 with the mid-eye threshold voltage V TH,MID output by controller 260 (via DAC 280) during a predetermined time interval. The number of baseline hits may be a number indicating the number of times the equalized output signal crosses the mid-eye threshold voltage V TH,MID , as determined by comparator 230, divided by divider 240, and counted by counter 250.

[0066] In step 620, the voltage offset V OFFSET is incrementally increased. For example, controller 260 may select the lowest threshold voltage V TH greater than the mid-eye threshold voltage V TH,MID and the highest threshold voltage V TH less than the mid-eye threshold voltage V TH,MID from a plurality of predetermined threshold voltages V TH (in the example embodiments of FIGS. 4 and 5, for example, threshold voltages THR6 and THR8). Again, those threshold voltages V TH may be selected by controller 260 and output by controller 260 (via DAC280) to comparator 230.

[0067] In step 622, the number of hits greater than the mid-eye threshold voltage V OFFSET at the selected voltage offset V TH,MID is recorded. In step 624, the number of hits less than the mid-eye threshold voltage V OFFSET at the selected voltage offset V TH,MID is recorded. Again, the number of hits may be a number indicating the number of times the equalized output signal crosses each threshold voltage V OFFSET at the selected voltage offset V TH (e.g., determined by comparator 230, divided by divider 240, and counted by counter 250). Controller 260 may store the number of hits (recorded in steps 622 and 624) at the selected voltage offset V OFFSET relative to the baseline (determined in step 610). Recording the number of hits relative to the baseline reduces the number of gates (or, for example, the amount of memory) required to store the hits, which reduces the die size (and the power required) of system 200.

[0068] Process 600 may include determining in step 630 whether an error condition exists. For example, controller 260 may compare the number of hits greater than the mid-eye threshold voltage V OFFSET at the selected voltage offset V TH,MIDThe number of hits (recorded in step 622) is related to the voltage offset V OFFSET is less than the middle eye threshold voltage V TH,MID The number of hits (recorded in step 624). If there is no error condition, then the equalized output signal will be reasonably symmetrical and at the selected voltage offset V OFFSET is greater than the middle eye threshold voltage V TH,MID The number of hits will be equal to (or have a predetermined margin to) the selected voltage offset V OFFSET is less than the middle eye threshold voltage V TH,MID Therefore, the controller 260 can compare the selected voltage offset V OFFSET The two hit numbers at are compared with the baseline, and if one is greater than the baseline (e.g., an amount equal to or greater than a predetermined margin) and the other is less than the baseline (e.g., an amount equal to or greater than a predetermined margin), then it is determined that an error condition exists.

[0069] If an error condition is detected (step 630: yes), then it may be determined in step 632 whether a continuous error condition has been detected. When an error condition is detected for the first time (step 632: no), the controller 260 may store an error condition status indicating that an error condition has been detected, and the process 600 may return to steps 622 and 624 so that the selected voltage offset V may be re-recorded. OFFSET . Whenever there is no error condition (step 630: No), the controller 260 may clear the error condition state. However, if a continuous error condition is detected in step 630 before the error condition state is cleared (step 632: Yes), then the process 600 may end. As described below with respect to some example embodiments, when the process 600 ends, the controller 260 may select the equalizer setting indicated by the stored variable SAVED_EQ. If there is no error condition (step 630: No), then the process 600 proceeds to step 640.

[0070] In step 640, it is determined whether the equalized output signal is over-equalized. For example, the controller 260 may determine whether the equalized output signal is over-equalized by comparing the selected voltage offset V OFFSET is greater than the middle eye threshold voltage V TH,MID (recorded in step 622) and is less than the middle eye threshold voltage V TH,MID The number of hits (recorded in step 624) and the middle eye threshold voltage V TH,MID The number of baseline hits at (recorded in step 610) is used to determine whether the equalized output signal is over-equalized. OFFSET Any hit number at (either greater than or less than the middle eye threshold voltage V TH,MID)Greater than the baseline (or an amount greater than the baseline equal to or greater than a predetermined margin), then the controller 260 may determine that the equalized output signal is over - equalized (step 640: Yes). If the equalized output signal of the equalizer 210 is over - equalized (step 640: Yes), then the process 600 ends. In those examples, in some example embodiments, the controller 260 may select the equalizer settings indicated by the stored variable SAVED_EQ as the equalizer settings of the equalizer 210 to equalize the signal received via the communication link.

[0071] If the equalized output signal is not over - equalized (step 640: No), then at step 650 it is determined whether the eye of the equalized output signal is open. For example, the controller 260 may compare the number of hits greater than and less than the middle eye threshold voltage V OFFSET at the selected voltage offset V TH,MID (recorded at steps 622 and 624) with the baseline number of hits (recorded at step 610). If the number of hits at both greater than and less than the middle eye threshold voltage V OFFSET at the selected voltage offset V TH,MID is equal to (or within a predetermined margin) the baseline number of hits, then the controller 260 may determine that the eye of the equalized output signal is open (step 650: Yes).

[0072] Whenever it is determined that the eye of the equalized output signal is open (step 650: Yes), the variable SAVED_EQ may be updated at step 654 to reflect the active equalizer settings EQ of the equalizer 210. For example, the controller 260 may update the variable SAVED_EQ (e.g., stored in the memory 264) to be equal to the active equalizer settings EQ of the equalizer 210 set by the controller 260. Since the process 600 is recursive, the active equalizer settings EQ of the equalizer 210 may be set to the first equalizer settings (e.g., the minimum equalizer settings) at step 602, and then, as described below, may be increased at step 680 (repeatedly in some examples).

[0073] If the eye of the equalized output signal is open (step 650: Yes), then at step 658 it is determined whether the selected voltage offset V OFFSET is at the maximum setting. As described above, for example, the controller 260 may be configured to output (via the DAC 280) each of a plurality of predetermined threshold voltages V TH (e.g., threshold voltages THR0 to THR14) to the comparator 230. In those examples, if the selected voltage offset V OFFSET is such that the controller 260 has output the lowest predetermined threshold voltage V TH (e.g., threshold voltage THR0) and the highest predetermined threshold voltage V TH(e.g., threshold voltage THR14), then the controller 260 may determine the selected voltage offset V OFFSET is at the maximum setting.

[0074] If the eye of the equalized output signal is open (step 650: yes), and the selected voltage offset V OFFSET is at the maximum setting (step 658: yes), then process 600 ends. In those examples, the controller 260 may select the equalizer setting indicated by the stored variable SAVED_EQ as the equalizer setting of the equalizer 210 to equalize the signal received via the communication link.

[0075] If the eye of the equalized output signal is open (step 650: yes), and the selected voltage offset V OFFSET is not at the maximum setting (step 658: no), then process 600 returns to step 620, and the voltage offset V OFFSET is increased again. Again, as described above, the controller 260 may be configured to output (via the DAC 280) to the comparator 230 multiple predetermined threshold voltages V TH (e.g., threshold voltages THR0 to THR14). In those examples, the controller 260 may increase the voltage offset V TH by selecting a predetermined threshold voltage V TH that is incrementally greater than the larger of two previously selected predetermined threshold voltages V TH and a predetermined threshold voltage V TH that is incrementally less than the smaller of two previously selected predetermined threshold voltages V OFFSET .

[0076] Returning to step 650, it may be determined that the eye of the equalized output signal is not open (step 650: no). For example, the controller 260 may compare the number of hits (recorded in steps 622 and 624) at the selected voltage offset V OFFSET that are greater than and less than the mid-eye threshold voltage V TH,MID with the baseline number of hits (recorded in step 610), and if either number of hits (either greater than or less than the mid-eye threshold voltage V OFFSET ) at the selected voltage offset V TH,MID is less than the baseline number of hits (or less than the amount by which the baseline number of hits equals or exceeds a predetermined margin), then it may be determined that the eye of the equalized output signal is not open (step 650: no).

[0077] If the eye of the equalized output signal is not open (step 650: No), then it can be determined in step 670 whether the active equalizer setting EQ of the equalizer 210 is the maximum equalizer setting of the equalizer 210. As described above, for example, the equalizer 210 can have multiple equalizer settings, and the maximum equalizer setting can be the equalizer setting from the multiple equalizer settings that causes the equalizer 210 to perform the highest amount of signal equalization and introduce the highest amount of signal gain.

[0078] If the eye of the equalized output signal is not open (step 650: No), but the active equalizer setting EQ is the maximum equalizer setting of the equalizer 210 (step 670: Yes), then the process 600 ends. In those examples, the controller 260 can select the equalizer setting indicated by the stored variable SAVED_EQ as the equalizer setting of the equalizer 210 to equalize the signal received via the communication link.

[0079] If the eye of the equalized output signal is not open (step 650: No), and the active equalizer setting EQ is not the maximum equalizer setting of the equalizer 210 (step 670: No), then in step 680, increase the active equalizer setting EQ of the equalizer 210. For example, the controller 260 can identify the lowest equalizer setting greater than the active equalizer setting EQ from the multiple equalizer settings of the equalizer 210 and set the active equalizer setting of the equalizer 210 to the identified equalizer setting. Different from when generating the full cumulative distribution function as shown in Figure 5A and 5B which requires recording hits at each voltage offset V with each equalizer setting EQ, once it is determined during the process 600 that the eye of the equalized output signal is not open (step 650: No), the process 600 does not require repeatedly increasing the voltage offset V OFFSET (step 620), such that hits can be recorded at each voltage offset V OFFSET (steps 622 and 624) with the active equalizer setting EQ. Instead, because it can be assumed that the number of hits at a higher voltage offset V OFFSET will not be higher than the number of hits at the selected voltage offset V OFFSET , let alone equal to the baseline, so in step 680, increase the active equalizer setting EQ of the equalizer 210 without recording hits at each voltage offset V OFFSET with the equalizer setting. OFFSET

[0080] After increasing the active equalizer setting EQ in step 680, the process 600 returns to step 622, where, with the newly increased active equalizer setting EQ of the equalizer 210, at a voltage greater than the middle eye threshold voltage V TH,MID (step 622) and less than the middle eye threshold voltage VTH,MID (Step 624)'s selected voltage offset V OFFSET Record the number of hits at. Again, different from when as Figure 5A and 5B When generating the full cumulative distribution function as shown, which requires recording hits for each equalizer setting at each voltage offset V OFFSET If during process 600 the voltage offset V OFFSET has increased (Step 620) and the active equalizer setting EQ of the equalizer has increased (Step 680), then process 600 does not require recording the number of hits at the lower voltage offset V OFFSET Instead, after increasing the equalizer setting in Step 680, process 600 starts at Step 622 with the same voltage offset V OFFSET previously selected for the previous equalizer setting (because the eye height at the higher equalizer setting is expected to match or exceed the eye height at all lower equalizer settings).

[0081] Process 600 is recursive. If the eye of the equalized output signal is open (Step 650: Yes), then update the variable SAVED_EQ (Step 654), and increase the voltage offset V OFFSET (Step 620) until the eye of the equalized output signal is no longer open (Step 650: No), or until the maximum voltage offset V OFFSET (Step 658: Yes) has been selected. If the eye of the equalized output signal is not open (Step 650: No), then increase the active equalizer setting EQ of equalizer 210 (Step 680) until the eye of the equalized output signal is open (Step 650: Yes), until the active equalizer setting EQ is the maximum equalizer setting of equalizer 210 (Step 670: Yes), or until the output signal is over - equalized (Step 640: Yes).

[0082] As described above, for each communication link, system 200 can identify the equalizer setting to equalize the signal received via the communication link by dynamically changing the active equalizer setting EQ of equalizer 210 and using comparator 230 to compare the equalized signals output by equalizer 210 at a series of voltage offsets V OFFSET Record the number of hits at. Again, different from when as

[0083] Figure 7 Is an example of how system 200 executing process 600 selects the equalizer setting to equalize the signal received via Figure 5A The instance USB channel while collecting fewer data points (in this instance, 35 data points) than the full cumulative distribution function shown in Figure 5A Figure.

[0084] As Figure 7As shown, the eye threshold voltage V in the record can be set by using the first equalizer setting (e.g., the minimum equalizer setting, equalizer setting 0). TH,MID (In this example, the threshold voltage THR7) The number of hits is used to establish a baseline for determining the eye of the equalized output signal. Then the voltage offset V OFFSET is increased to the threshold voltages THR6 and THR8. Because the number of hits at the selected voltage offset V OFFSET is less than the baseline by more than a predetermined margin, the active equalizer setting EQ is increased without using the equalizer setting 0 at the higher voltage offset V OFFSET to determine the number of hits until an active equalizer setting EQ (in this example, equalizer setting 2) is identified where the number of hits at the increasing voltage offset V OFFSET (to the threshold voltages THR6 and THR8) is within the predetermined margin of the baseline.

[0085] Because the eye of the equalized output signal opens at the selected voltage offset V OFFSET (to the threshold voltages THR6 and THR8), the active equalizer setting (EQ = 2) is stored as the variable SAVED_EQ, and the voltage offset V OFFSET is increased to the threshold voltages THR5 and THR9. Because the number of hits is less than the baseline by more than a predetermined margin, the active equalizer setting EQ is increased to equalizer setting 3, and then to equalizer setting 4, at which time the active equalizer setting (EQ = 4) is stored as the variable SAVED_EQ, and the voltage offset V OFFSET is increased to the threshold voltages THR4 and THR10, where the eye of the equalized output signal closes until the active equalizer setting EQ is increased to equalizer setting 6, at which time the active equalizer setting (EQ = 6) is stored as the variable SAVED_EQ, and the voltage offset V OFFSET is increased to the threshold voltages THR3 and THR11. Again, the number of hits at the increasing voltage offset V OFFSET (to the threshold voltages THR3 and THR11) remains less than the baseline by more than a predetermined margin until the active equalizer setting EQ is increased to equalizer setting 7, at which time the active equalizer setting (EQ = 7) is stored as the variable SAVED_EQ, and the voltage offset V OFFSET is increased to the threshold voltages THR2 and THR12, where the eye of the equalized output signal closes until the active equalizer setting EQ is increased to equalizer setting 9.

[0086] Using equalizer setting 9, at the selected voltage offset V OFFSET (to the threshold voltages THR2 and THR12), the eye of the equalized output signal opens. Therefore, the active equalizer setting (EQ = 9) is stored as the variable SAVED_EQ, and the voltage offset V OFFSETIncreased to threshold voltages THR1 and THR13. Using equalizer setting 9, at the increased voltage offset V OFFSET (to threshold voltages THR2 and THR12), the number of hits is less than the baseline and greater than a predetermined margin. Therefore, the active equalizer setting EQ is then increased to equalizer setting 10. However, using equalizer setting 10, at the selected voltage offset V OFFSET (to threshold voltages THR2 and THR12), the number of hits remains less than the baseline and greater than a predetermined margin. Therefore, the active equalizer setting EQ is increased again to equalizer setting 11. However, using equalizer setting 11, equalizer 210 over - equalizes the output signal, and at the selected voltage offset V OFFSET (to threshold voltages THR2 and THR12), the number of hits is greater than the baseline and greater than a predetermined margin. Since the output signal of equalizer 210 is over - equalized, process 600 ends.

[0087] The equalizer setting (in this example, equalizer setting 9) stored as variable SAVED_EQ at the end of process 600 is selected as the equalizer setting to equalize the signal received via the communication link. As described above, the selected equalizer setting is the lowest equalizer setting of equalizer 210 that keeps the equalized output signal open at the highest voltage offset V OFFSET . For the example USB channel of Figure 5A , the selected equalizer setting is equalizer setting 9. As shown in Figure 7 and described above, system 200 that executes process 600 can select the equalizer setting more effectively than prior - art methods, which compare the output signal of the equalizer at each equalizer setting with each threshold voltage to generate a full cumulative distribution function as shown in Figure 5A .

[0088] For example, process 600 can be executed during the USB 3.2 Polling.RxEQ phase of link training. Process 600 enables controller 260 to quickly converge on an equalizer setting to equalize the signal received via the communication link, which is an important consideration for USB link training. Although in an example where the equalizer range is 0 to 15, the offset range is 1 to 7, and the hit - count duration is 3 μs, the full cumulative distribution function may take approximately 720 microseconds (μs), system 200 that executes process 600 can select the equalizer setting in approximately 186 μs. Process 600 can also be used to select an equalizer setting to equalize the signal received via other communication links (e.g., HDMI, PCIe, etc.).

[0089] In this description, the term "coupled" may encompass a connection, communication, or signal path that implements a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, if an intermediate component C does not change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C such that device B is controlled by device A via the control signal generated by device A.

[0090] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0091] As used herein, the terms "terminal", "node", "interconnect", "pin", and "lead" may be used interchangeably. Unless explicitly stated to the contrary, these terms generally refer to the interconnections or terminals between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0092] A circuit or device described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources, for example, by an end user and / or a third party at the time of manufacture or after the time of manufacture to form the described structure.

[0093] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this description. Unless otherwise stated, "about", "approximately", or "substantially" before a value means + / - 10% of that value.

[0094] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A system for selecting an equalizer setting of an equalizer to equalize a signal received via a communication link, the equalizer receiving an input signal and generating an equalized output signal having an eye and an eye voltage at the center of the eye according to an active equalizer setting, the system comprising: A comparator coupled to the equalizer and configured to compare an instantaneous voltage of the equalized output signal with a threshold voltage and output a signal indicating a crossing of the instantaneous voltage of the equalized output signal with the threshold voltage; A counter coupled to the comparator and configured to output a hit count indicating the number of times the instantaneous voltage of the equalized output signal crosses the threshold voltage during a predetermined time interval; And A controller coupled to the counter and the equalizer and configured to: Set the active equalizer setting of the equalizer to a first equalizer setting; Select, from a plurality of predetermined threshold voltages, the threshold voltage closest to the eye voltage at the center of the equalized output signal; Store the hit count at the threshold voltage closest to the eye voltage at the center of the eye as a baseline; Increase a voltage offset by selecting, from the plurality of predetermined threshold voltages, a threshold voltage incrementally greater than or incrementally less than the eye voltage at the center of the equalized output signal; Further increase the voltage offset in response to a determination that the hit count at the selected threshold voltage is within a predetermined margin of the baseline; And Increase the active equalizer setting of the equalizer in response to a determination that the hit count at the selected threshold voltage is less than the baseline by an amount equal to or greater than the predetermined margin.

2. The system according to claim 1, wherein the controller is further configured to repeatedly increase the voltage offset in response to each determination that the hit count at the selected threshold voltage is within the predetermined margin of the baseline.

3. The system according to claim 2, wherein the controller is further configured to repeatedly increase the active equalizer setting of the equalizer in response to each determination that the hit count at the selected threshold voltage is less than the baseline by an amount equal to or greater than the predetermined margin.

4. The system according to claim 3, wherein the controller is configured to determine whether the equalized output signal of the equalizer is over-equalized by determining whether the hit count at the selected threshold voltage is greater than the baseline by an amount equal to or greater than the predetermined margin.

5. The system according to claim 4, wherein the controller is further configured to: Store an indication of the active equalizer setting and increase the voltage offset in response to each determination that the hit count at the selected threshold voltage is within the predetermined margin of the baseline; and In response to a determination that the selected threshold voltage is the highest or lowest threshold voltage among the plurality of predetermined threshold voltages, select the stored equalizer setting, the active equalizer setting being the maximum equalizer setting of the equalizer, and the number of hits at the selected threshold voltage being less than the amount by which the baseline is equal to or greater than the predetermined margin, or the equalized output signal of the equalizer being over-equalized.

6. The system of claim 5, wherein the selected equalizer setting is the lowest equalizer setting of the equalizer, and wherein the number of hits is within the predetermined margin of the baseline at the highest voltage offset.

7. The system of claim 1, wherein the controller is configured to: Increase the voltage offset by selecting two threshold voltages from the plurality of predetermined threshold voltages that are incrementally greater than and incrementally less than the middle eye voltage; In response to a determination that the number of hits at both of the selected threshold voltages is within the predetermined margin of the baseline, repeatedly increase the voltage offset by selecting the two threshold voltages from the plurality of predetermined threshold voltages that are incrementally greater than and incrementally less than the selected threshold voltage; and In response to a determination that any one of the number of hits at any one of the selected threshold voltages is less than the amount by which the baseline is equal to or greater than the predetermined margin, repeatedly increase the active equalizer setting of the equalizer.

8. The system of claim 7, wherein the controller is configured to determine whether the equalized output signal of the equalizer is over-equalized by determining whether any one of the number of hits at any one of the selected threshold voltages is greater than the amount by which the baseline is equal to or greater than the predetermined margin.

9. The system of claim 8, wherein the controller is further configured to: Store an indication of the active equalizer setting and increase the voltage offset in response to each determination that the number of hits at both of the selected threshold voltages is within the predetermined margin of the baseline; In response to a determination that the selected threshold voltage is the highest or lowest threshold voltage among the plurality of predetermined threshold voltages, select the stored equalizer setting, the active equalizer setting being the maximum equalizer setting of the equalizer, and any one of the number of hits at any one of the selected threshold voltages being less than the amount by which the baseline is equal to or greater than the predetermined margin, or the equalized output signal of the equalizer being over-equalized.

10. The system of claim 1, wherein the controller is configured to select the threshold voltage by outputting a digital control signal to a digital-to-analog converter that outputs an analog voltage to the comparator.

11. A method for selecting an equalizer setting of an equalizer to equalize a signal received via a communication link, the equalizer being operable to receive an input signal and generate an equalized output signal having an eye and a middle eye voltage according to an active equalizer setting, the method comprising: Setting the active equalizer setting of the equalizer to a first equalizer setting; Select the threshold voltage closest to the middle eye voltage of the equalized output signal from a plurality of predetermined threshold voltages; Compare the instantaneous voltage of the equalized output signal with the selected threshold voltage; Store a baseline hit count indicative of the number of times the instantaneous voltage of the equalized output signal crosses the threshold voltage closest to the middle eye voltage of the equalized output signal during a predetermined time interval; Increase the voltage offset by selecting a threshold voltage incrementally greater than or incrementally less than the middle eye voltage of the equalized output signal from the plurality of predetermined threshold voltages; Record a hit count indicative of the number of times the instantaneous voltage of the equalized output signal crosses the selected threshold voltage during the predetermined time interval; In response to a determination that the hit count at the selected threshold voltage is within a predetermined margin of the baseline hit count, further increase the voltage offset; and In response to a determination that the hit count at the selected threshold voltage is less than the baseline hit count by an amount equal to or greater than the predetermined margin, increase the active equalizer setting of the equalizer.

12. The method of claim 11, further comprising: Repeatedly increase the voltage offset in response to each determination that the hit count at the selected threshold voltage is within the predetermined margin of the baseline hit count.

13. The method of claim 12, further comprising: Repeatedly increase the active equalizer setting of the equalizer in response to each determination that the hit count at the selected threshold voltage is less than the baseline hit count by an amount equal to or greater than the predetermined margin.

14. The method of claim 13, further comprising: Determine whether the output signal of the equalizer is over-equalized by determining whether the hit count at the selected threshold voltage is greater than the baseline hit count by an amount equal to or greater than the predetermined margin.

15. The method of claim 14, further comprising: Store an indication of the active equalizer setting and increase the voltage offset in response to each determination that the hit count at the selected threshold voltage is within the predetermined margin of the baseline hit count; and In response to a determination that the selected threshold voltage is the highest or lowest threshold voltage among the plurality of predetermined threshold voltages, select the stored equalizer setting, the active equalizer setting being the maximum equalizer setting of the equalizer, and the hit count at the selected threshold voltage being less than the baseline hit count by an amount equal to or greater than the predetermined margin, or the equalized output signal of the equalizer being over-equalized.

16. The method of claim 15, wherein the selected equalizer setting is the lowest equalizer setting of the equalizer, and wherein the hit count is within the predetermined margin of the baseline hit count at the highest voltage offset.

17. The method of claim 11, comprising: Increase the voltage offset by selecting two threshold voltages incrementally greater than and incrementally less than the middle eye voltage from the plurality of predetermined threshold voltages; and In response to a determination that both of the hit counts at the selected threshold voltage are within the predetermined margin of the baseline hit count, the voltage offset is repeatedly increased by selecting two threshold voltages that are incrementally greater than and incrementally less than the selected threshold voltage from the plurality of predetermined threshold voltages; and in response to a determination that any one of the hit counts at any one of the selected threshold voltages is less than the baseline hit count by an amount equal to or greater than the predetermined margin, the active equalizer setting of the equalizer is repeatedly increased.

18. The method according to claim 17, further comprising: determining that the equalized output signal of the equalizer is over-equalized by determining whether any one of the hit counts at any one of the selected threshold voltages is greater than the baseline hit count by an amount equal to or greater than the predetermined margin.

19. The method according to claim 18, further comprising: storing an indication of the active equalizer setting and increasing the voltage offset in response to each determination that both of the hit counts at the selected threshold voltage are within the predetermined margin of the baseline hit count; selecting the stored equalizer setting in response to a determination that the selected threshold voltage is the highest or lowest threshold voltage among the plurality of predetermined threshold voltages, the active equalizer setting being the maximum equalizer setting of the equalizer, and any one of the hit counts at any one of the selected threshold voltages is less than the baseline hit count by an amount equal to or greater than the predetermined margin, or the equalized output signal of the equalizer is over-equalized.

20. A system for selecting an equalizer setting of an equalizer to equalize a signal received via a communication link, the equalizer receiving an input signal and generating an equalized output signal having an eye and an eye voltage in the middle according to an active equalizer setting, the system comprising: a comparator coupled to the equalizer and configured to compare an instantaneous voltage of the equalized output signal with a threshold voltage and output a signal indicating a crossing of the instantaneous voltage of the equalized output signal and the threshold voltage; a counter coupled to the comparator and configured to output a hit count indicating the number of times the instantaneous voltage of the equalized output signal crosses the threshold voltage during a predetermined time interval; and a controller coupled between the equalizer and the counter and configured to: set the active equalizer setting of the equalizer to a first equalizer setting; select, from a plurality of predetermined threshold voltages, the threshold voltage closest to the eye voltage in the middle of the equalized output signal; store the hit count at the threshold voltage closest to the eye voltage in the middle as a baseline; increase a voltage offset by selecting two threshold voltages that are incrementally greater than and incrementally less than the eye voltage in the middle of the equalized output signal from the plurality of predetermined threshold voltages; repeatedly store an indication of the active equalizer setting and increase the voltage offset in response to each determination that both of the hit counts at the selected threshold voltage are within the predetermined margin of the baseline; In response to each determination that any number of hits at any one of the selected threshold voltages is less than the baseline by an amount equal to or greater than the predetermined margin, repeatedly increase the active equalizer setting of the equalizer; If any number of hits at any one of the selected threshold voltages is greater than the baseline by an amount equal to or greater than the predetermined margin, then determine that the equalized output signal of the equalizer is over-equalized; and In response to the determination that the selected threshold voltage is the highest or lowest threshold voltage among the plurality of predetermined threshold voltages, select the stored equalizer setting, the active equalizer setting is the maximum equalizer setting of the equalizer, and any number of hits at any one of the selected threshold voltages is less than the baseline by an amount equal to or greater than the predetermined margin, or the equalized output signal of the equalizer is over-equalized.

Images