Solid-state imaging device and imaging device

Abstract

The present application enables to obtain a dynamic range even in low illumination. A solid-state imaging device (200) includes: a plurality of detection pixels (300) each outputting a luminance variation of incident light; a detection circuit (305) outputting an event signal in accordance with the luminance variation output from each detection pixel; and a first common line (3101) connecting the plurality of detection pixels to each other, wherein each detection pixel includes: a photoelectric conversion element (311); a logarithmic conversion circuit (312, 313) converting a photoelectric current flowing from the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photoelectric current; a first circuit (340) outputting the luminance variation of the incident light incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit; a first transistor (317) connected between the photoelectric conversion element and the logarithmic conversion circuit; and a second transistor (318) connected between the photoelectric conversion element and the first common line, and the detection circuit includes a second circuit (500) outputting the event signal based on the luminance variation output from each detection pixel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a solid-state imaging device and an imaging device. BACKGROUND

[0002] Conventional technologies related to imaging devices and the like have used a synchronous solid-state imaging device that captures image data (frames) in synchronization with a synchronization signal such as a vertical synchronization signal. Such a typical synchronous solid-state imaging device is only able to acquire image data at every synchronization signal period (for example, 1 / 60 seconds), making it difficult to handle faster processing when required in fields related to transportation, robots, and the like. To address this problem, an asynchronous solid-state imaging device has been proposed that detects, as an address event, an event in which the amount of change in the luminance of a pixel exceeds a threshold value for each pixel address (for example, refer to Patent Literature 1). A solid-state imaging device that detects an address event for each pixel in this way is also referred to as an event-based vision sensor (EVS) or a dynamic vision sensor (DVS).

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: JP 5244587 B2 SUMMARY

[0006] PROBLEMS

[0007] In the above-described asynchronous solid-state imaging device, the transistor constituting the address event detection circuit operates in the subthreshold region, and thus, the dynamic range under low illumination greatly depends on the SN ratio, which is the ratio of the photocurrent (S) to the thermal noise (N) in the transistor. In particular, when performed in line with the trend toward miniaturization and high resolution, pixel micromachining will cause a reduction in the photocurrent per pixel, resulting in degradation of the SN ratio under low illumination and a narrower dynamic range. This can cause problems such as a decrease in the sensitivity of address event occurrence and an increase in detection errors.

[0008] In view of this, the present disclosure proposes a solid-state imaging device and an imaging device that are able to obtain a dynamic range even under low illumination.

[0009] SOLUTION TO PROBLEM

[0010] To address the above concerns, a solid-state imaging device according to an aspect of the present disclosure includes a plurality of detection pixels each outputting a change in luminance of incident light, a detection circuit outputting an event signal based on the change in luminance output from each of the detection pixels, and a first common line connecting the plurality of detection pixels to each other, wherein each of the detection pixels includes a photoelectric conversion element, a logarithmic conversion circuit converting a photoelectric current flowing from the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photoelectric current, a first circuit outputting the change in luminance of incident light on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit, a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit, and a second transistor connected between the photoelectric conversion element and the first common line, and the detection circuit includes a second circuit outputting the event signal based on the change in luminance output from each of the detection pixels. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram showing a configuration example of an imaging device according to the first embodiment.

[0012] Figure 2 is a diagram depicting an example of a stacked structure of a solid-state imaging device according to the first embodiment.

[0013] Figure 3 is an example of a plan view of a light-receiving chip according to the first embodiment.

[0014] Figure 4 is an example of a plan view of a detection chip according to the first embodiment.

[0015] Figure 5 is an example of a plan view of an address event detection section according to the first embodiment.

[0016] Figure 6 is a circuit diagram describing a configuration example of a logarithmic response section according to the first embodiment.

[0017] Figure 7 is a circuit diagram depicting another configuration example of a logarithmic response section according to the first embodiment.

[0018] Figure 8 is a block diagram showing a configuration example of a detection block according to the first embodiment.

[0019] Figure 9 is a circuit diagram depicting a configuration example of a differentiator according to the first embodiment.

[0020] Figure 10 is a circuit diagram describing a configuration example of a comparison section according to the first embodiment.

[0021] Figure 11 is a circuit diagram depicting a configuration example of a differentiator, a selector, and a comparator according to the first embodiment.

[0022] Figure 12 is a timing chart showing an example of control of a row drive circuit according to the first embodiment.

[0023] Figure 13 is a block diagram depicting a configuration example of a detection pixel and a detection circuit according to the first embodiment.

[0024] Figure 14 is a flowchart depicting an example of operation of a solid-state imaging device according to the first embodiment.

[0025] Figure 15 is a block diagram showing a configuration example of a detection pixel and a detection circuit according to the first embodiment of the present technology.

[0026] Figure 16 is a timing chart depicting an example of control of a row drive circuit in the modified example of the first embodiment of the present technology.

[0027] Figure 17 is a circuit diagram showing a schematic configuration example of a sharing block according to the first embodiment.

[0028] Figure 18 is a plan view depicting a layout example of a sharing block according to the first embodiment.

[0029] Figure 19 is a timing chart showing an example of control of a switching transistor in a high-resolution mode and a merging mode according to the first embodiment.

[0030] Figure 20 is a flowchart describing an example of operation of an imaging device according to the first embodiment.

[0031] Figure 21 is a circuit diagram showing a schematic configuration example of a sharing block according to the second embodiment.

[0032] Figure 22 is a plan view depicting a layout example of a sharing block according to the second embodiment.

[0033] Figure 23 is a timing chart showing an example of control of a switching transistor in a high-resolution mode and a merging mode according to the second embodiment.

[0034] Figure 24 is a circuit diagram depicting a schematic configuration example of a sharing block according to the third embodiment.

[0035] Figure 25is a timing chart showing exemplary control of the switching transistor in the high-resolution mode and the merging mode according to the third embodiment.

[0036] Figure 26 is a circuit diagram showing an exemplary configuration example of a sharing block according to the fourth embodiment.

[0037] Figure 27 is a circuit diagram showing an exemplary configuration example of a sharing block according to a modification of the fourth embodiment.

[0038] Figure 28 is a circuit diagram showing an exemplary configuration example of a readout circuit according to the fourth embodiment.

[0039] Figure 29 is an example of a plan view of a detection chip according to the fourth embodiment.

[0040] Figure 30 is a flowchart showing an example of operation for performing switching between the target detection mode and the gray-scale image readout mode according to the fourth embodiment.

[0041] Figure 31 is a circuit diagram showing an exemplary configuration example of a sharing block according to the fifth embodiment.

[0042] Figure 32 is a circuit diagram showing an exemplary configuration example of a sharing block according to a modification of the fifth embodiment.

[0043] Figure 33 is an example of a plan view of a detection chip according to the sixth embodiment.

[0044] Figure 34 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0045] Figure 35 is a diagram for assisting in explaining an installation position of a vehicle exterior information detection unit and an imaging section. DETAILED DESCRIPTION

[0046] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In each of the following embodiments, the same components are denoted by the same reference symbols, and repetitive description will be omitted.

[0047] The present disclosure will be described in the following order.

[0048] 1. First Embodiment

[0049] 1.1 Configuration Example of Imaging Device

[0050] 1.2 Configuration Example of Solid-state Imaging Device

[0051] 1.3 Configuration example of logarithmic response section

[0052] 1.3.1 Modified example of logarithmic response section

[0053] 1.4 Configuration example of detection block

[0054] 1.4.1 Configuration example of differentiator, selector, and comparator

[0055] 1.5 Control example of row drive circuit

[0056] 1.6 Configuration example of detection pixel and detection circuit

[0057] 1.6.1 Operation example of solid-state imaging device

[0058] 1.7 Modified example of detection pixel and detection circuit

[0059] 1.7.1 Control example of row drive circuit according to modified example

[0060] 1.8 Configuration example of shared block

[0061] 1.9 Layout example of shared block

[0062] 1.10 Operation example

[0063] 1.10.1 Timing chart

[0064] 1.10.2 Flowchart

[0065] 1.11 Effects and advantages

[0066] 2. Second embodiment

[0067] 2.1 Configuration example of shared block

[0068] 2.2 Layout example of shared block

[0069] 2.3 Operation example (timing chart)

[0070] 2.4 Effects and advantages

[0071] 3. Third embodiment

[0072] 3.1 Configuration example of shared block

[0073] 3.2 Operation example (timing chart)

[0074] 3.3 Effects and advantages

[0075] 4. Fourth embodiment

[0076] 4.1 Configuration example of shared block

[0077] 4.1.1 Modified example of shared block

[0078] 4.2 Example of readout circuit configuration

[0079] 4.3 Example of Detection Chip Configuration

[0080] 4.4 Operation Example

[0081] 4.5 Functions and Effects

[0082] 5. Fifth Implementation Method

[0083] 5.1 Configuration Example of Shared Blocks

[0084] 5.1.1 Variations of shared blocks

[0085] 5.2 Operation Example

[0086] 6. Sixth Implementation Method

[0087] 7. Examples of application to moving objects

[0088] 1. First Implementation Method

[0089] First, the first embodiment will be described in detail with reference to the accompanying drawings.

[0090] 1.1 Example of Imaging Device Configuration

[0091] Figure 1 This is a block diagram illustrating an example configuration of an imaging apparatus 100 according to a first embodiment of the present disclosure. The imaging apparatus 100 includes an optical unit 110, a solid-state imaging device 200, a recording unit 120, and a control unit 130. Examples of the imaging apparatus 100 are assumed to include devices such as cameras mounted on industrial robots and vehicle-mounted cameras.

[0092] The optical unit 110 converges the incident light and guides the converged light to the solid-state imaging device 200. The solid-state imaging device 200 photoelectrically converts the incident light to generate image data. The solid-state imaging device 200 performs predetermined signal processing (such as image recognition processing) on ​​the generated image data and outputs the processed data to the recording unit 120 via the signal line 209.

[0093] For example, the recording unit 120 includes a device such as flash memory, and records data output from the solid-state imaging device 200 and data output from the control unit 130.

[0094] For example, the control unit 130 includes an information processing device such as an application processor, and controls the solid-state imaging device 200 to output image data.

[0095] 1.2 Configuration Example of Solid State Imaging Device

[0096] (Example of a layered structure)

[0097] Figure 2 This is a diagram illustrating an example of the stacked structure of a solid-state imaging device 200 according to this embodiment. The solid-state imaging device 200 includes a detection chip 202 and a light-receiving chip 201 stacked on the detection chip 202. These chips are electrically connected to each other via connection portions such as vias. In addition to vias, Cu-Cu bonding or bumps can be used for connection. For example, the light-receiving chip 201 may be an example of the first chip in the claim, and the detection chip 202 may be an example of the second chip in the claim.

[0098] (Layout example of an optical receiver chip)

[0099] Figure 3 This is an example of a plan view of the optical receiver chip 201 according to this embodiment. The optical receiver chip 201 includes an optical receiver section 220 and through-hole arrangement sections 211, 212 and 213.

[0100] Through-hole arrangement portions 211, 212, and 213 are portions that arrange through-holes connected to the detection chip 202. The light receiving portion 220 is the location where a plurality of shared blocks 221 are arranged in a two-dimensional grid pattern.

[0101] In each shared block 221, one or more logarithmic response units 310 are arranged. For example, for each shared block 221, four logarithmic response units 310 are arranged in a 2-row × 2-column pattern. These four logarithmic response units 310 share the circuitry on the detection chip 202. Details of the shared circuitry will be described below. The number of logarithmic response units 310 in the shared block 221 is not limited to four. Furthermore, some or all of the circuitry configuration in each logarithmic response unit 310, excluding the photoelectric conversion element 311, can be arranged on the detection chip 202 side.

[0102] The logarithmic response unit 310 converts the photocurrent flowing from the photoelectric conversion element 311 into a voltage signal corresponding to the logarithmic value of the photocurrent. A pixel address, including a row address and a column address, is assigned to each logarithmic response unit 310. It should be noted that, for example, the pixels in this disclosure may have a configuration based on the photoelectric conversion element 311 described below, and the pixels in this embodiment may have a configuration corresponding to the detection pixel 300 described below.

[0103] (Layout example of a detection chip)

[0104] Figure 4This is an example of a plan view of the detection chip 202 according to this embodiment. The detection chip 202 includes via arrangement portions 231, 232 and 233, a signal processing circuit 240, a row driving circuit 251, a column driving circuit 252 and an address event detection unit 260. The via arrangement portions 231, 232 and 233 are portions in which vias connected to the optical receiving chip 201 are arranged.

[0105] Address event detection unit 260 detects the presence or absence of address events in each logarithmic response unit 310 and generates a detection signal indicating the detection result.

[0106] The row drive circuit 251 selects the row address and causes the address event detection unit 260 to output a detection signal corresponding to the row address.

[0107] The column drive circuit 252 selects the column address and causes the address event detection unit 260 to output a detection signal corresponding to the column address.

[0108] The signal processing circuit 240 performs predetermined signal processing on the detection signal output from the address event detection unit 260. The signal processing circuit 240 arranges the detection signal as pixel signals into a two-dimensional lattice pattern and generates image data with 2 bits of information for each pixel. The signal processing circuit 240 then performs signal processing such as image recognition processing on the image data.

[0109] (Layout example of a detection chip)

[0110] Figure 5 This is an example of a plan view of the address event detection unit 260 according to this embodiment. The address event detection unit 260 is a unit in which a plurality of detection blocks 320 are arranged. Detection blocks 320 are arranged on the optical receiver chip 201 for each shared block 221. When the number of shared blocks 221 is N (N is an integer), N detection blocks 320 are arranged. Each detection block 320 is connected to the corresponding shared block 221.

[0111] 1.3 Example of Logarithmic Response Unit Configuration

[0112] Figure 6This is a circuit diagram illustrating a basic configuration example of the logarithmic response unit according to this embodiment. The logarithmic response unit 310 includes a photoelectric conversion element 311, n-channel metal-oxide-semiconductor (nMOS) transistors 312 and 313, and a p-channel MOS (pMOS) transistor 314. The two nMOS transistors 312 and 313, for example, constitute a logarithmic conversion circuit that converts the photocurrent flowing from the photoelectric conversion element 311 into a voltage signal corresponding to the logarithmic value of the photocurrent. Furthermore, the pMOS transistor 314 operates as a load MOS transistor for the logarithmic conversion circuit. Note that, for example, the photoelectric conversion element 311 and the nMOS transistors 312 and 313 may be arranged on the photoreceiving chip 201, while the pMOS transistor 314 may be arranged on the detection chip 202.

[0113] Regarding nMOS transistor 312, its source is connected to the cathode of photoelectric conversion element 311, and its drain is connected to the power supply terminal. pMOS transistor 314 and nMOS transistor 313 are connected in series between the power supply terminal and the ground terminal. Furthermore, the junction of pMOS transistor 314 and nMOS transistor 313 is connected to the gate of nMOS transistor 312 and the input terminal of detection block 320. Additionally, a predetermined bias voltage Vbias1 is applied to the gate of pMOS transistor 314.

[0114] The drains of nMOS transistors 312 and 313 are connected to the power supply side, and such a circuit is called a source follower. The two source followers connected in a ring convert the photocurrent from the photoelectric conversion element 311 into a voltage signal corresponding to the logarithm. In addition, pMOS transistor 314 supplies a constant current to nMOS transistor 313.

[0115] In addition, the ground of the optical receiver chip 201 and the ground of the detection chip 202 are isolated from each other to prevent interference.

[0116] 1.3.1 Variation of the logarithmic response unit

[0117] although Figure 6 This is an example of the configuration of the logarithmic response section 310 of the source follower type, but the configuration of this section is not limited to this example. Figure 7 This is a circuit diagram illustrating a basic configuration example of the logarithmic response unit according to a modified example of this embodiment. For example... Figure 7 As shown, for example, the logarithmic response unit 310A has a configuration known as a gain boost circuit configuration, relative to... Figure 6The source follower circuit configuration shown includes an additional nMOS transistor 315 connected in series between nMOS transistor 312 and the power supply line, and an additional nMOS transistor 316 connected in series between nMOS transistor 313 and pMOS transistor 314. The four nMOS transistors 312, 313, 315, and 316, for example, constitute a logarithmic converter circuit that converts the photocurrent flowing from photoelectric conversion element 311 into a voltage signal corresponding to the logarithmic value of the photocurrent.

[0118] In this way, even when using a gain boost type logarithmic response unit 310A, the photocurrent from the photoelectric conversion element 311 can be converted into a voltage signal corresponding to the logarithm of the charge.

[0119] 1.4 Configuration Example of Detection Block

[0120] Figure 8 This is a block diagram illustrating an example configuration of the detection block 320 according to this embodiment. The detection block 320 includes a plurality of buffers 330, a plurality of differentiators 340, a selection unit 400, a comparison unit 500, and a transmission circuit 360. The buffers 330 and differentiators 340 are arranged for each logarithmic response unit 310 in the shared block 221. For example, when the number of logarithmic response units 310 in the shared block 221 is four, four buffers 330 and four differentiators 340 are arranged.

[0121] The buffer 330 outputs the voltage signal from the corresponding logarithmic response unit 310 to the differentiator 340. The buffer 330 can improve the driving force used to drive subsequent stages. In addition, the buffer 330 can ensure isolation from noise associated with switching operations in subsequent stages.

[0122] Differentiator 340 obtains the change in voltage signal, that is, the change in brightness of light incident on photoelectric conversion element 311, as a differential signal. Differentiator 340 receives the voltage signal from the corresponding logarithmic response unit 310 through buffer 330 and obtains the change in voltage signal by differentiation. Subsequently, differentiator 340 supplies the differential signal to selection unit 400. The m-th differential signal Sin (m is an integer from 1 to M) in detection block 320 is defined as Simn. Differentiator 340 may correspond to, for example, the first circuit in claim 1.

[0123] The selection unit 400 selects one of M differential signals based on the selection signal from the line drive circuit 251. The selection unit 400 includes selectors 410 and 420.

[0124] M differential signals Sin are input to selector 410. Selector 410 selects one of these differential signals Sin according to a selection signal and supplies the selected differential signal Sin as Sout+ to comparator 500. M differential signals Sin are also input to selector 420. Selector 420 selects one of these differential signals Sin according to a selection signal and provides the selected differential signal Sin to comparator 500 as Sout-.

[0125] The comparison unit 500 compares the differential signal (i.e., the amount of change) selected by the selection unit 400 with a predetermined threshold. The comparison unit 500 provides a signal representing the comparison result as a detection signal to the transmission circuit 360. For example, the comparison unit 500 may correspond to the second circuit in the claim.

[0126] The transmission circuit 360 transmits the detection signal to the signal processing circuit 240 based on the column drive signal from the column drive circuit 252.

[0127] (Example of differentiator configuration)

[0128] Figure 9 This is a circuit diagram illustrating an example configuration of the differentiator 340 according to this embodiment. The differentiator 340 includes capacitors 341 and 343, an inverter 342, and a switch 344.

[0129] One end of capacitor 341 is connected to the output terminal of buffer 330, and the other end is connected to the input terminal of inverter 342. Capacitor 343 is connected in parallel to inverter 342. Switch 344 opens and closes the path connected to the end of capacitor 343 according to the row drive signal.

[0130] Inverter 342 inverts the voltage signal input through capacitor 341. Inverter 342 outputs the inverted signal to selection unit 400.

[0131] When switch 344 is turned on, the voltage signal V init The input is given to the buffer 330 side of capacitor 341, making the opposite side a virtual ground terminal. For convenience, assume the potential of the virtual ground terminal is zero. At this time, when the capacitance of capacitor 341 is C1, the accumulated potential Q in capacitor 341... init This is expressed by the following formula (1). On the other hand, since the two ends of capacitor 343 are short-circuited, the stored charge is 0.

[0132] Q init =C1×V init (1)

[0133] Next, assuming switch 344 is open, the voltage on the buffer 330 side of capacitor 341 becomes voltage V. afterThe charge Q stored in capacitor 341 after It is represented by the following formula (2).

[0134] Q after =C1×V after (2)

[0135] On the other hand, when the output voltage is V out At that time, the charge Q2 accumulated in capacitor 343 is represented by the following formula (3).

[0136] Q2=-C2×V out (3)

[0137] At this time, since the total charge of capacitors 341 and 343 does not change, the following formula (4) holds true.

[0138] Q init =Q after +Q2(4)

[0139] When equations (1) to (3) are replaced by equation (4), the result can be converted into equation (5).

[0140] V out =-(C1 / C2)×(V) after -V init (5)

[0141] Equation (5) represents the subtraction operation of the voltage signal, where the gain of the subtraction result is C1 / C2. Since maximum gain is generally desirable, it is preferable to design C1 to be large and C2 to be small. On the other hand, an excessively small C2 will increase kTC noise and lead to a deterioration in noise characteristics. Therefore, the reduction in the capacitance of C2 is limited to the noise tolerance range. Furthermore, since a differentiator 340 is provided for each pixel, capacitors C1 and C2 have area limitations. Taking these into consideration, for example, C1 is set to a value of 20 to 200 Fetofarads (fF), and C2 is set to a value of 1 to 20 Fetofarads (fF).

[0142] (Comparison section configuration example)

[0143] Figure 10 This is a circuit diagram showing an example configuration of the comparison unit 500 according to this embodiment. The comparison unit 500 includes comparators 510 and 520.

[0144] Comparator 510 compares the differential signal Sout+ from selector 410 with a predetermined upper threshold Vrefp. Comparator 510 provides the comparison result to transmission circuit 360 as a detection signal DET+. The detection signal DET+ indicates the presence or absence of an on / off event. Here, an on / off event indicates an event where the change in brightness exceeds the predetermined upper threshold.

[0145] Comparator 520 compares the differential signal Sout- from selector 420 with a lower threshold Vrefn that is below the upper threshold Vrefp. Comparator 520 provides the comparison result to transmission circuit 360 as a detection signal DET-. The detection signal DET- indicates the presence or absence of a disconnect event. Here, a disconnect event represents an event where the change in brightness is less than a predetermined lower threshold. It should be noted that although comparator 500 detects the presence or absence of both an on and off event, it may also detect only one of the on and off events.

[0146] It should be noted that, for example, comparator 510 may be an example of the first comparator described in the claims, and comparator 520 may be an example of the second comparator described in the claims. For example, the upper threshold may be an example of the first threshold described in the claims, and the lower threshold may be an example of the second threshold described in the claims.

[0147] 1.4.1 Configuration examples of differentiators, selectors, and comparators

[0148] Figure 11 This is a circuit diagram illustrating an example configuration of the differentiator 340, selector 410, and comparator 510 in the detection block 320 according to this embodiment.

[0149] Differentiator 340 includes capacitors 341 and 343, pMOS transistors 345 and 346, and nMOS transistor 347. PMOS transistors 345 and 347 are connected in series between a power supply terminal and a ground terminal, with pMOS transistor 345 as the power supply side. Capacitor 341 is inserted between the gate of pMOS transistor 345 / nMOS transistor 347 and a buffer 330. The connection point of pMOS transistors 345 and 347 is connected to selector 410. With this connection configuration, pMOS transistors 345 and 347 function as inverter 342.

[0150] Furthermore, capacitor 341 and pMOS transistor 345 are connected in parallel between the junction of pMOS transistor 346 and nMOS transistor 347 and capacitor 343. pMOS transistor 346 serves as switch 344.

[0151] In addition, the selector 410 is provided with a plurality of pMOS transistors 411. A pMOS transistor 411 is arranged for each differentiator 340.

[0152] pMOS transistors 411 are inserted between the corresponding differentiator 340 and comparator 510. Furthermore, a selection signal SEL is individually input to the gate of each of the M pMOS transistors 411. The selection signal SEL of the first pMOS transistor 411 is called SELm. Through these selection signals SEL, the row drive circuit 251 can control the conduction of one of the M pMOS transistors 411 and the blocking of the remaining others. Additionally, the differential signal Sout+ is output to comparator 510 as a selection signal through the pMOS transistor 411 in the on state. Note that the circuit configuration of selector 420 is similar to that of selector 410.

[0153] Comparator 510 includes a pMOS transistor 511 and an nMOS transistor 512. The pMOS transistor 511 and nMOS transistor 512 are connected in series between a power supply terminal and a ground terminal. Furthermore, the differential signal Sout+ is input to the gate of the pMOS transistor 511, while the upper threshold voltage Vrefp is input to the gate of the nMOS transistor 512. The detection signal DET+ is output from the junction of the pMOS transistor 511 and the nMOS transistor 512. Note that the circuit configuration of comparator 520 is similar to that of comparator 510.

[0154] It should be noted that the circuit configurations of the differentiator 340, selector 410, and comparator 510 are not limited to... Figure 11 The examples described herein, provided they have reference value. Figure 8 The described function is sufficient. For example, nMOS transistors and pMOS transistors are interchangeable.

[0155] 1.5 Example of control for drive circuit

[0156] Figure 12 This is a timing diagram illustrating an example of the control of the row drive circuit 251 according to this embodiment. At time T0, the row drive circuit 251 selects the first row via the row drive signal L1 and drives the differentiator 340 of the selected row. The row drive signal L1 initializes the capacitor 343 in the differentiator 340 of the first row. Furthermore, the row drive circuit 251 selects the upper left of the 2-row × 2-column pattern in the shared block 221 via the selection signal SEL1 for a certain time period and drives the selection unit 400. Through this driver, the presence or absence of address events is detected in the odd-numbered columns of the first row.

[0157] Next, at time T1, the row drive circuit 251 drives the differentiator 340 of the first row again via the row drive signal L1. Furthermore, the row drive circuit 251 selects the upper right corner of the 2-row × 2-column pattern in the shared block 221 for a certain time period via the selection signal SEL2. Therefore, the presence or absence of address events is detected in the even-numbered columns of the first row.

[0158] At time T2, the row drive circuit 251 drives the differentiator 340 in the second row via the row drive signal L2. The row drive signal L2 initializes the capacitor 343 in the differentiator 340 in the second row. Furthermore, the row drive circuit 251 selects the lower left of the 2-row × 2-column pattern in the shared block 221 via the selection signal SEL3 for a certain period of time. This driver detects the presence or absence of address events in the odd-numbered columns of the second row.

[0159] Subsequently, at time T3, the row drive circuit 251 drives the differentiator 340 in the second row again via the row drive signal L2. Furthermore, the row drive circuit 251 selects the lower right corner of the 2-row × 2-column pattern in the shared block 221 for a certain time period via the selection signal SEL4. Therefore, the presence or absence of address events is detected in the even-numbered columns of the second row.

[0160] Subsequently, similarly, the row driving circuit 251 sequentially selects the rows where the logarithmic response units 310 are arranged, and drives the selected rows via row driving signals. Furthermore, whenever a row is selected, the row driving circuit 251 sequentially selects each detection pixel 300 in the shared block 221 of the selected row via a selection signal. For example, in the case where the detection pixels 300 of a 2-row × 2-column pattern are arranged in the shared block 221, each time a row is selected, the odd-numbered columns and even-numbered columns in that row are selected sequentially.

[0161] It should be noted that the row drive circuit 251 can also sequentially select rows in which the shared block 221 is arranged (in other words, two rows having the logarithmic response unit 310). In this case, each time a row is selected, four detection pixels in the shared block 221 of that row are selected sequentially.

[0162] 1.6 Example of Pixel and Circuit Detection Configuration

[0163] Figure 13 This is a block diagram illustrating an example configuration of the detection pixel 300 and the detection circuit 305 according to this embodiment. In the detection block 320, which is shared by multiple logarithmic response units 310 in the shared block 221, a circuit including a selection unit 400, a comparison unit 500, and a transmission circuit 360 is defined as the detection circuit 305. Furthermore, a circuit including a logarithmic response unit 310, a buffer 330, and a differentiator 340 is defined as the detection pixel 300. As shown, the detection circuit 305 is shared by multiple detection pixels 300.

[0164] Each of the multiple detection pixels 300 sharing the detection circuit 305 generates a voltage signal corresponding to the logarithmic value of the photocurrent. Subsequently, each of the detection pixels 300 outputs a differential signal Sin, indicating the amount of change in the voltage signal, to the detection circuit 305 according to the row drive signal. In each detection pixel 300, the logarithmic response unit 310 generates a voltage signal corresponding to the logarithmic value, while the differentiator 340 generates a differential signal.

[0165] Selection signals such as selection signals SEL1 and SEL2 are commonly input to selectors 410 and 420 in detection circuit 305. Detection circuit 305 selects the differential signal (i.e., change amount) of the detection pixel indicated by the selection signal from a plurality of detection pixels 300 and detects whether the change amount exceeds a predetermined threshold. Detection circuit 305 then transmits the detection signal to signal processing circuit 240 according to a column drive signal. In detection circuit 305, the differential signal is selected by selection unit 400 and compared with a threshold by comparison unit 500. Furthermore, the detection signal is transmitted by transmission circuit 360.

[0166] Here, in a typical DVS, the comparator 500 and transmission circuit 360 are arranged together with the logarithmic response unit 310, buffer 330, and differentiator 340 for each detected pixel. Conversely, in the above configuration where the detection circuit 305, including the comparator 500 and transmission circuit 360, is shared by multiple detected pixels 300, the circuit size of the solid-state imaging device 200 can be reduced compared to a case where the detection circuit is not shared. This facilitates the micro-manufacturing of pixels.

[0167] When a stacked structure is specifically employed, using a conventional configuration without a shared detection circuit 305 results in a larger circuit size for the detection chip 202 compared to the light receiver chip 201. Under this structure, the pixel density is limited by the circuitry on the detection chip 202, making it difficult to achieve pixel microfabrication. However, by using a configuration where multiple detection pixels 300 share the detection circuit 305, the circuit size of the detection chip 202 can be reduced, facilitating pixel microfabrication.

[0168] Although a buffer 330 is arranged for each detected pixel 300, the configuration is not limited to this configuration, and the buffer 330 may also be omitted.

[0169] Furthermore, although the photoelectric conversion element 311 and nMOS transistors 312 and 313 of the logarithmic response unit 310 are arranged on the light receiving chip 201, and the pMOS transistor 314 and subsequent transistors are arranged on the detection chip 202, the configuration is not limited to this example. For example, the photoelectric conversion element 311 may be arranged solely on the light receiving chip 201, and other devices may be arranged on the detection chip 202. Alternatively, the logarithmic response unit 310 may be arranged solely on the light receiving chip 201, and the buffer 330 and subsequent devices may be arranged on the detection chip 202. Still alternatively, the logarithmic response unit 310 and the buffer 330 may be arranged on the light receiving chip 201, while the differentiator 340 and subsequent devices may be arranged on the detection chip 202. Furthermore, the logarithmic response unit 310, the buffer 330, and the differentiator 340 may be arranged on the light receiving chip 201, and the detection circuit 305 and subsequent circuitry may be arranged on the detection chip 202. Alternatively, the portion up to the selection unit 400 can be arranged on the optical receiving chip 201, while the comparison unit 500 and subsequent components can be arranged on the detection chip 202.

[0170] 1.6.1 Operational Example of a Solid-State Imaging Device

[0171] Figure 14 This is a flowchart illustrating an example of the operation of the solid-state imaging apparatus 200 according to this embodiment. For example, operation begins at a timed interval for the execution of a predetermined application used to detect the presence or absence of an address event.

[0172] The row driving circuit 251 selects one of the rows (step S901). The row driving circuit 251 selects and drives one of the detection pixels 300 in each shared block 221 of the selected row (step S902). The detection circuit 305 detects whether an address event exists in the selected detection pixel 300 (step S903). After step S903, the solid-state imaging device 200 repeats step S901 and subsequent steps.

[0173] In this way, this embodiment has a configuration in which the detection circuit 305 for detecting the presence or absence of an address event is shared by multiple detection pixels 300, thereby reducing the circuit size compared to a case where the detection circuit 305 is not shared. This facilitates the micro-manufacturing of the detection pixels 300.

[0174] 1.7 Modified Examples of Detection Pixels and Detection Circuits

[0175] In the first embodiment described above, the solid-state imaging device 200 selects each of the detection pixels 300 one by one, and simultaneously detects both the on and off events of the detection pixels. Alternatively, the solid-state imaging device 200 may select two detection pixels, detect the on event of one detection pixel, and detect the off event of the other detection pixel. The solid-state imaging device 200 according to a variation of the first embodiment differs from the first embodiment in that it detects the on event of one of the two detection pixels and the off event of the other detection pixel.

[0176] Figure 15 This is a block diagram illustrating an example configuration of the detection pixel 300 and detection circuit 305 according to a variant of this embodiment. The detection circuit 305 according to the variant of the first embodiment differs from the detection circuit 305 of the first embodiment in that, for example, a selection signal SEL1p or selection signal SEL2p is input to selector 410, while a selection signal SEL1n or selection signal SEL2n is input to selector 420. In the variant of the first embodiment, two detection pixels 300 are selected, and selector 410 selects a differential signal based on selection signals SEL1p, SEL2p, etc. Simultaneously, selector 420 selects another differential signal based on selection signals SEL1n, SEL2n, etc.

[0177] 1.7.1 Control Example of Horizontal Drive Circuit Based on Modified Example

[0178] Figure 16 This is a timing diagram illustrating an example of the control of the line drive circuit 251 in a variant of this embodiment. At times T0 to T2, it is assumed that two pixels are selected: the detection pixel 300 that outputs the differential signal Sin1 and the detection pixel 300 that outputs the differential signal Sin2. At times T0 to T1, the line drive circuit 251 sets the selection signals SEL1p and SEL2n to high level and sets the selection signals SEL2p and SEL1n to low level. Using this setting, an on event is detected for the pixel corresponding to the differential signal Sin1, and an off event is detected for the pixel corresponding to the differential signal Sin2.

[0179] Next, between time T1 and T2, the row drive circuit 251 sets the selection signals SEL1p and SEL2n to low level and sets the selection signals SEL2p and SEL1n to high level. Using this setting, an on event is detected for the pixel corresponding to the differential signal Sin2, and an off event is detected for the pixel corresponding to the differential signal Sin1.

[0180] In this way, according to a variation of this embodiment, since an on event is detected for one of the two detection pixels and an off event is detected for the other detection pixel, on events and off events can be detected simultaneously and in parallel in space.

[0181] 1.8 Configuration Example of Shared Blocks

[0182] Next, more specific configuration examples of each shared block 221 described above will be described in detail with reference to the accompanying drawings. For example, the following description uses... Figure 7 The gain boost type logarithmic response unit 310A shown is a logarithmic response unit 310. However, this configuration is not limited to this example, and various circuits that generate voltage signals based on the logarithm of the photocurrent can be used, such as... Figure 6 The source follower type logarithmic response unit 310 is shown. Furthermore, the following describes an exemplary case using one of the shared blocks 221, comprising a total of four logarithmic response units 310A in a 2-row × 2-column pattern. However, the configuration is not limited to this example, and each shared block 221 may include one, two, or more logarithmic response units 310A.

[0183] Figure 17 This is a circuit diagram illustrating a schematic configuration example of the shared block according to this embodiment. For example... Figure 17 As shown, each shared block 221 includes four logarithmic response units 310A1 to 310A4. Each of the logarithmic response units 310A1 to 310A4 (hereinafter referred to as logarithmic response unit 310An when not distinguished from each other) has two switching transistors 317 and 318 added thereto. Figure 6 The configuration of the basic configuration of the logarithmic response unit 310A described herein. Each of the two switching transistors 317 and 318 may be an nMOS transistor or a pMOS transistor. For example, switching transistor 317 may be an example of the first transistor in the claim, and switching transistor 318 may be an example of the second transistor in the claim.

[0184] The switching transistor 317 is connected, for example, between the cathode of the photoelectric conversion element 311, the drain of the nMOS transistor 312, and the gate of the nMOS transistor 313, and controls the inflow of photocurrent from the photoelectric conversion element 311 into the logarithmic conversion circuit.

[0185] A switching transistor 318 is connected between, for example, the cathode of a photoelectric conversion element 311 and a common line 3101. The common line 3101 is connected via the switching transistor 318 to the cathode of the photoelectric conversion element 311 included in all logarithmic response units 310An in the same shared block 221. For example, the common line 3101 may be an example of the first common line in the claim.

[0186] In the above configuration, by turning on the switching transistors 318 in two or more logarithmic response units 310An included in the shared block 221, turning on the switching transistors 317 of one of the two or more logarithmic response units 310An (referred to as logarithmic response unit 310A1), and turning off the switching transistors 317 of the other logarithmic response units 310An, the photocurrent flowing out of the photoelectric conversion element 311 of the logarithmic response unit 310A1 and the photocurrent flowing out of the photoelectric conversion element 311 of the logarithmic response unit 310An where the switching transistor 317 is turned off can be concentrated into the logarithmic conversion circuit of the logarithmic response unit 310A1. That is, the photocurrent flowing out of the photoelectric conversion element 311 of the logarithmic response unit 310An where the switching transistor 317 is turned off and the switching transistor 318 is turned on can be collected into the logarithmic conversion circuit of the logarithmic response unit 310An where both the switching transistors 317 and 318 are turned on.

[0187] In this way, by employing a configuration that can converge the photocurrent flowing from multiple photoelectric conversion elements 311 into a single logarithmic conversion circuit, a larger photocurrent can be obtained, resulting in an expanded dynamic range in photocurrent detection. This allows for a sufficiently wide dynamic range even under conditions such as low illumination.

[0188] On the other hand, when sufficient illumination can be obtained, by turning off the switching transistor 318 and turning on the switching transistor 317 in all or a sufficient number of logarithmic response units 310An, all or a sufficient number of logarithmic response units 310An can be allowed to operate as an address event detection pixel, resulting in the realization of high-resolution address event detection, reduction of operating power, etc.

[0189] 1.9 Layout example of shared blocks

[0190] Next, it will be described in Figure 17 The layout example of shared block 221 described in the document. Figure 18 This is a plan view illustrating an example layout of the shared blocks according to this embodiment. For ease of explanation, Figure 18 A schematic layout example of the device formation surface side of the semiconductor substrate on which the photoelectric conversion element 311 is formed is described, as well as a schematic layout example of a portion of the wiring layer formed on the device formation surface of the substrate. Furthermore, for clarity, Figure 18 The arrangement of nMOS transistors 312, 313, 315, and 316, as well as switching transistors 317 and 318, is depicted by the position of their gate electrodes. Figure 18 The outline of the current path formed in the merging mode described below is further shown by thick arrows.

[0191] In this embodiment, there are at least two definitions for a pixel. In one definition, a pixel is a pixel on a layout formed by repeating patterns in the design of the light receiving unit 220, and in another definition, a pixel is a pixel on a circuit that operates as a detection pixel 300. Each pixel on the circuit includes a logarithmic response unit 310An. In the following description, pixels on the layout are referred to as layout pixels, and pixels on the circuit are referred to as circuit pixels. Furthermore, since the configuration of the detection pixels 300 arranged in the light receiving unit 220 is all or part of the logarithmic response units 310An, the logarithmic response units 310An are described here as circuit pixels.

[0192] (Layout pixels)

[0193] like Figure 18 As shown, one of the layout pixels 10 is arranged in a pixel region of the light receiving chip 201, which is divided by pixel isolation portions 12 extending in the row and column directions. Each layout pixel 10 includes: a photoelectric conversion element 311 arranged substantially at the center; and a plurality of nMOS transistors 312, 313, 315, and 316 arranged along the outer periphery of the pixel region, in other words, arranged from at least two directions ( Figure 18 The three directions of the photoelectric conversion element 311; switching transistors 317 and 318; and contact 314c are used to form a connection with the pMOS transistor 314 disposed on the side of the detection chip 202.

[0194] exist Figure 18 In the layout example shown, for example, in Figure 17 In each logarithmic response unit 310An shown, nMOS transistors 312 and 315 in the left column are arranged to the left of the photoelectric conversion element 311, and nMOS transistors 313 and 316 in the right column are arranged to the right of the photoelectric conversion element 311. Furthermore, for example, two switching transistors 317 and 318 are arranged above or below the photoelectric conversion element 311. Thus, by employing a highly symmetrical layout in which the photoelectric conversion element 311 is sandwiched between two nMOS transistors, manufacturing process accuracy and yield can be improved.

[0195] Furthermore, for example, two switching transistors 317 and 318 are arranged below the photoelectric conversion element 311 in the odd-numbered rows and above the photoelectric conversion element 311 in the even-numbered rows. That is, the layout pixels 10 in the even-numbered rows have a layout obtained by vertically reversing the layout pixels 10 in the odd-numbered rows. By adopting this layout, the pattern of one layout pixel 10 can be used for all layout pixels 10, which facilitates the layout design of the light receiving section 220.

[0196] Furthermore, by arranging the layout pixels 10 in a layout in which odd and even rows are vertically reversed, the switching transistors 317 and 318 constituting the logarithmic response section 310An of the shared block 221 can be close to each other, which makes it convenient to realize the layout design of the shared line 3101 and reduce the wiring length of the shared line 3101.

[0197] (Circuit pixels)

[0198] On the other hand, in this circuit, the photoelectric conversion element 311 in the specific layout pixel 10, the two nMOS transistors 312 and 315 arranged to the left of the photoelectric conversion element 311, and the two nMOS transistors 313 and 316 arranged to the right of the photoelectric conversion element 311 constitute a circuit pixel (here, logarithmic response section 310An) in the layout pixel (here, logarithmic response section 310An) in the layout. That is, in the circuit pixel (here, logarithmic response section 310An) in the layout, the logarithmic conversion circuit including four nMOS transistors 312, 313, 315 and 316 is configured to be arranged across the pixel isolation section 12.

[0199] By configuring the logarithmic conversion circuit in the logarithmic response section 310An between adjacent layout pixels 10 in this way, the wiring length of the logarithmic conversion circuit—that is, the wiring length connecting the nMOS transistors 312, 313, 315, and 316 constituting the logarithmic conversion circuit—can be reduced while maintaining the symmetry of the layout pixels 10. This allows for a reduction in the time constant formed by the wiring constituting the logarithmic conversion circuit, resulting in an improved response speed of the logarithmic conversion circuit.

[0200] 1.10 Operation Example

[0201] Next, an operational example of the imaging apparatus 100 according to this embodiment will be described. As described above, in this embodiment, by controlling the on / off state of switching transistors 317 and 318, it is possible to switch between two modes: a mode in which one logarithmic response unit 310 (which may be logarithmic response unit 310A) operates as a pixel (hereinafter referred to as high-resolution mode) and a mode in which two or more logarithmic response units 310 in the shared block 221 operate as a pixel (hereinafter referred to as merging mode). Furthermore, it is also possible to implement a mode in which some shared blocks 221 are driven in high-resolution mode and the remaining shared blocks 221 are driven in merging mode (hereinafter referred to as ROI mode). For example, the merging mode and ROI mode may be examples of the first mode in the claims, the high-resolution mode may be an example of the second mode in the claims, the segmentation mode may be an example of the third mode in the claims, and the ROI mode may be an example of the fourth mode in the claims.

[0202] 1.10.1 Timing Diagram

[0203] Figure 19 This is a timing diagram illustrating exemplary control of the switching transistors in high-resolution mode and merging mode according to this embodiment. (As shown...) Figure 19 As shown, in the high-resolution mode illustrated in sections T10 to T11, in each logarithmic response section 310A1 to 310A4, the switching transistor 317 is turned on and the switching transistor 318 is turned off. This results in a current path forming the photocurrent flowing from the photoelectric conversion element 311 of each logarithmic response section 310A1 to 310A4 into its own logarithmic conversion circuit.

[0204] Conversely, in the combined mode shown in sections T11 to T12, both switching transistors 317 and 318 of the logarithmic response section 310A1 are turned on. On the other hand, in the logarithmic response sections 310A2 to 310A4, switching transistor 317 is turned off, while switching transistor 318 is turned on. This results in a current path forming the current flowing from the photoelectric conversion element 311 of each logarithmic response section 310A1 to 310A4 into the logarithmic conversion circuit of the logarithmic response section 310A1.

[0205] 1.10.2 Flowchart

[0206] Next, an operational example of the imaging device 100 will be described. Figure 20 This is a flowchart illustrating an operational example of the imaging apparatus of this embodiment. It is a flowchart illustrating an operational example of switching between a mode operating in a pixel-merging mode (hereinafter referred to as full-pixel combination mode), a mode operating in a high-resolution mode (hereinafter referred to as full-pixel high-resolution mode), and a ROI mode. This description will describe the control unit 130 (see reference 130) in the imaging apparatus 100. Figure 1 This is an exemplary case of controlling the operating mode of the solid-state imaging device 200. However, the control of the operating mode is not limited to this example, and the signal processing circuitry 240 in the solid-state imaging device 200 can be configured to control the operating mode. Furthermore, Figure 20 The operation described herein can be terminated, for example, by interrupting the control unit 130 or the solid-state imaging device 200.

[0207] like Figure 20 As shown, in this operation, after activation, the control unit 130 sets the operating mode of the solid-state imaging device 200 to full-pixel combination mode (step S101). In full-pixel combination mode, as described above, all shared blocks 221 of the light receiving unit 220 are driven in combination mode. In this case, for example, in Figure 17In the example shown, the switching transistors 317 of all logarithmic response units 310A1 to 310A4 in each shared block 221 are turned on, the switching transistor 318 of logarithmic response unit 310A1 is turned on, and the switching transistors 318 of logarithmic response units 310A2 to 310A4 are turned off. This results in a current path forming from the photocurrent flowing out of the photoelectric conversion element 311 of all logarithmic response units 310A1 to 310A4 into the logarithmic conversion circuit of logarithmic response unit 310A1.

[0208] Next, the control unit 130 determines whether a subject is detected in the full-pixel combination mode (step S102), and continues in the full-pixel combination mode until a subject is detected (step S102 is "No"). For example, object detection determination can be performed based on conditions such as whether an address event (on event and / or off event) has been detected in any shared block, or whether the area where an address event has been detected has a certain area or number of pixels (e.g., a preset threshold or more). Object detection does not need to be determined in one frame, but can be determined in several consecutive frames. Note that a frame can be, for example, image data that includes address information (which may include timestamps) of pixels on which address events have been detected within a predetermined time period. Furthermore, object detection can be performed through processing such as object recognition on image data.

[0209] When an object has been detected (yes in step S102), the control unit 130 determines, for example, whether the detected object is a wide-range object, or whether the detected object is multiple objects, etc. (step S103). It should be noted that, for example, a wide range can be a range that is greater than or equal to the area occupied by the light receiving unit 220 (e.g., 20% of the area or the number of pixels, etc.).

[0210] When the detected object is not a wide-range object ("No" in step S103), for example, the control unit 130 sets the operation mode of the solid-state imaging device 200 to ROI mode (step S104). ROI mode is, for example, a mode that drives a part of the area containing the subject detected in the light receiving unit 220 in high-resolution mode and drives other areas in combination mode.

[0211] Next, the control unit 130 determines whether an object has been detected (step S105). If no subject is detected (step S105 is "No"), the control unit 130 returns the process to step S101 and restarts setting the full pixel combination mode for the solid-state imaging device 200. When an object is detected (yes in step S105), the control unit 130 determines, for example, similar to step S103, whether the detected object is a wide-range object, whether the detected object is multiple objects, etc. (step S106). When the detected object is not a wide-range object (no in step S106), the control unit 130 returns the process to step S105 to continue the ROI mode.

[0212] When a wide range of objects is detected in step S103 or S106 ("Yes" in steps S103 / S106), for example, the control unit 130 sets the operating mode of the solid-state imaging device 200 to full-pixel high-resolution mode (step S107). As described above, full-pixel high-resolution mode is a mode in which all shared blocks 221 of the light receiving unit 220 are driven in high-resolution mode. In this case, for example, in Figure 17 In the example shown, the switching transistors 317 of all logarithmic response units 310A1 to 310A4 in each shared block 221 are turned off, and the switching transistors 318 are turned on. This results in separate current paths forming the photocurrent flowing from the photoelectric conversion element 311 of each logarithmic response unit 310A1 to 310A4 into its own logarithmic conversion circuit.

[0213] Next, the control unit 130 determines whether an object has been detected (step S108). If no subject is detected (step S108 is "No"), the control unit 130 returns the process to step S101 and restarts setting the solid-state imaging device 200 to full-pixel combination mode. When an object is detected (step S108 is "Yes"), similar to step S103, the control unit 130 determines, for example, whether the detected object is a wide-range object or whether the detected object is multiple objects (step S109). When the detected object is a wide-range object (step S109 is "Yes"), the control unit 130 returns the process to step S108 to continue in full-pixel high-resolution mode. Conversely, when the detected object is neither a wide-range object nor multiple objects (step S109 is "No"), the control unit 130 proceeds to step S104, sets the solid-state imaging device 200's operation mode to ROI mode, and performs subsequent operations.

[0214] 1.11 Functions and Effects

[0215] As described above, according to this embodiment, by concentrating the photocurrent flowing from multiple photoelectric conversion elements 311 into a logarithmic conversion circuit structure, a larger photocurrent can be obtained, thereby expanding the dynamic range in photocurrent detection. This allows for a sufficiently wide dynamic range even under conditions such as low illumination.

[0216] On the other hand, when sufficient illumination can be obtained, by turning off the switching transistor 318 and turning on the switching transistor 317 in all or a sufficient number of logarithmic response units 310An, all or a sufficient number of logarithmic response units 310An can be allowed to operate as an address event detection pixel, resulting in the realization of high-resolution address event detection, reduction of operating power, etc.

[0217] Furthermore, in the segmented mode, the constant conduction of the switching transistor 318 sharing the logarithmic response units 310An (e.g., all logarithmic response units 310An in the shared block 221) allows for a constant current path from each logarithmic response unit 310A2 to 310An to the logarithmic conversion circuit of the logarithmic response unit 310A1. This enables multiple detection pixels 300 to share a single logarithmic conversion circuit, without including charge storage sections such as floating diffusion regions, as in the case of CMOS image sensors.

[0218] 2. Second Implementation Method

[0219] Next, the second embodiment will be described in detail with reference to the accompanying drawings. In this embodiment, the first embodiment will be described by way of example. Figure 17 Another configuration of the shared block 221 described.

[0220] In the first embodiment, as referenced Figure 17 and Figure 18 As described, the photocurrent flowing out of the photoelectric conversion elements 311 of the logarithmic response units 310A2 to 310A4 (where the switching transistor 318 is off in combined mode) flows through the common line 3101, then through the switching transistor 317 of the logarithmic response unit 310A1, the cathode of the photoelectric conversion element 311, and through the switching transistor 318, so as to flow into the logarithmic conversion circuit of the logarithmic response unit 310A1. Therefore, in the first embodiment, it is necessary to implement a potential design from the switching transistor 317 of the logarithmic response unit 310A1 through the cathode of the photoelectric conversion element 311 to the switching transistor 318, so that the photocurrent flowing out of the photoelectric conversion elements 311 of the logarithmic response units 310A2 to 310A4 flows smoothly into the logarithmic conversion circuit of the logarithmic response unit 310A1. Therefore, in the second embodiment, a shared block that can greatly relax the limitations on possible designs will be described by example.

[0221] The configuration and operation of the imaging device and solid-state imaging device according to this embodiment can be similar to the configuration and operation of the imaging device 100 and solid-state imaging device 200 according to the first embodiment described above, and therefore, a detailed description will be omitted here. However, in this embodiment, the shared block 221 according to the first embodiment is replaced by the shared block 621 described below.

[0222] 2.1 Configuration Example of Shared Blocks

[0223] Figure 21 This is a circuit diagram illustrating a schematic configuration example of the shared block according to this embodiment. The logarithmic response unit 310Bn in the following examples is based on... Figure 7 The example shown is a logarithmic response section 310A of a gain boost type. However, the configuration is not limited to this; for example, a logarithmic response section 310B with various circuits based on generating a voltage signal corresponding to the logarithm of the photocurrent may also be permitted, such as in... Figure 6 The example illustrates a source follower type logarithmic response unit 310. Further, the following describes an exemplary case using a shared block 621 comprising a total of four logarithmic response units 310Bn in a 2-row × 2-column pattern. However, the configuration is not limited to this example, and each shared block 621 may include one, two, or more logarithmic response units 310Bn.

[0224] like Figure 21 As shown, the logarithmic response units 310B1 to 310B4 according to this embodiment (in this specification, when the logarithmic response units 310B1 to 310B4 are not distinguished, they are referred to by reference numeral 310Bn) all have a switching transistor 319 further incorporated similar to that in the first embodiment. Figure 17 The logarithmic response unit 310An is configured as described. Switching transistor 319 is connected, for example, to the drain of switching transistor 318, and to, for example, the drain of switching transistor 317, the source of nMOS transistor 312, and the gate of nMOS transistor 313. For example, switching transistor 319 may be an example of the third transistor in the claim. Furthermore, for example, the node connecting the drain of switching transistor 317, the source of nMOS transistor 312, and the gate of nMOS transistor 313 to each other may be an example of the second node in the claim, and the drain of switching transistor 318 may be an example of the second node in the claim.

[0225] 2.2 Layout Example of Shared Blocks

[0226] Next, we will describe Figure 21 The layout example of shared block 621 described in the document. Figure 22 This is a plan view illustrating an example layout of the shared blocks according to this embodiment. For ease of explanation, Figure 22A schematic layout example of the device formation surface side of the semiconductor substrate on which the photoelectric conversion element 311 is formed is depicted, as well as a schematic layout example of a portion of the wiring layer formed on the device formation surface of the substrate. Furthermore, for clarity, Figure 22 The arrangement of the gate electrode positions of nMOS transistors 312, 313, 315 and 316 and switching transistors 317 to 319 is shown. Figure 22 The outlines of the current paths formed in the merging mode described below are further illustrated by thick arrows. For example, nMOS transistor 312 may be an example of the fourth transistor in the claim, nMOS transistor 313 may be an example of the fifth transistor in the claim, nMOS transistor 315 may be an example of the sixth transistor in the claim, and nMOS transistor 316 may be an example of the seventh transistor in the claim.

[0227] like Figure 22 As shown, each layout pixel 20 according to this embodiment has a configuration in which a switching transistor 319 is added to the same side of a switching transistor 317, the switching transistor 317 being disposed relative to the photoelectric conversion element 311, a configuration similar to that in the first embodiment. Figure 18 The layout of pixel 10 is described. By adopting this layout, the wiring from the common line 3101 to the switching transistor 319 can be reduced.

[0228] 2.3 Operation Example (Sequence Diagram)

[0229] Next, an operational example of the logarithmic response unit 310Bn will be described. Figure 23 This is a timing diagram illustrating exemplary control of the switching transistors in high-resolution mode and merging mode according to this embodiment. (As shown...) Figure 23 As shown, in the high-resolution mode illustrated in sections T20 to T21, in each logarithmic response section 310B1 to 310B4, switching transistors 317 and 319 are turned off, and switching transistor 318 is turned on. This results in a current path forming the photocurrent flowing from the photoelectric conversion element 311 of each logarithmic response section 310B1 to 310B4 into its own logarithmic conversion circuit.

[0230] On the other hand, in the combined mode shown in parts T21 to T22, switching transistor 317 of logarithmic response unit 310B1 is turned on, switching transistor 318 is turned off, and switching transistor 319 is turned on. On the other hand, in logarithmic response units 310B2 to 310B4, switching transistor 317 is turned off, switching transistor 318 is turned on, and switching transistor 319 is turned off. This results in a current path forming from the photocurrent flowing out of the photoelectric conversion element 311 of each logarithmic response unit 310B1 to 310B4 into the logarithmic conversion circuit of logarithmic response unit 310B1.

[0231] 2.4 Functions and Effects

[0232] As described above, according to this embodiment, in the combined mode, a current path can be formed in which the photocurrent flowing through the common line 3101 flows into the logarithmic conversion circuit of the logarithmic response unit 310B1 via the switching transistor 319, without passing through the switching transistor 318 of the logarithmic response unit 310B1, the cathode of the photoelectric conversion element 311, or the switching transistor 317. This allows for a significant relaxation of limitations on potential designs ranging from switching transistor 318 to switching transistor 317.

[0233] Since other configurations, operations, and effects may be similar to those in the above embodiments, detailed descriptions will be omitted here.

[0234] 3. Third Implementation Method

[0235] Next, the third embodiment will be described in detail with reference to the accompanying drawings. In this embodiment, the first embodiment will be described by way of example. Figure 17 Another configuration of the shared block 221 described.

[0236] The configuration and operation of the imaging device and solid-state imaging device according to this embodiment can be similar to the configuration and operation of the imaging device 100 and solid-state imaging device 200 according to the first embodiment described above, and therefore, a detailed description will be omitted here. However, in this embodiment, the shared block 221 according to the first embodiment is replaced by the shared block 721 described below.

[0237] 3.1 Configuration Example of Shared Blocks

[0238] Figure 24 This is a circuit diagram illustrating a schematic configuration example of the shared block according to this embodiment. The logarithmic response unit 310Cn in the following example is based on... Figure 7 The example shown is a logarithmic response section 310A of a gain boost type. However, the configuration is not limited to this; for example, various circuits that generate a voltage signal corresponding to the logarithm of the photocurrent may also be allowed to have a logarithmic response section 310B, such as in... Figure 6 The example illustrates a source follower type logarithmic response unit 310. Furthermore, the following describes an exemplary case where one of the shared blocks 721 includes a total of four logarithmic response units 310Cn in a 2-row × 2-column pattern. However, the configuration is not limited to this example, and each shared block 721 may include one, two, or more logarithmic response units 310Cn.

[0239] like Figure 24As shown, the logarithmic response units 310C1 to 310C4 according to this embodiment (in this specification, when the logarithmic response units 310C1 to 310C4 are not distinguished, they are referred to by reference numeral 310Cn) each have a reference from the second embodiment. Figure 21 The configuration of the switching transistor 319 is omitted in the similar configuration of the described logarithmic response unit 310Bn. Furthermore, in the logarithmic response unit 310Cn, the drain of the switching transistor 317 is connected to the source of the nMOS transistor 312, the source is connected to the gate of the nMOS transistor 313 and the cathode of the photoelectric conversion element 311, and the drain of the switching transistor 318 is connected to the source of the switching transistor 317, the gate of the nMOS transistor 313 and the cathode of the photoelectric conversion element 311.

[0240] 3.2 Operation Example (Sequence Diagram)

[0241] Next, an operational example of the logarithmic response unit 310Cn will be described. Figure 25 This is a timing diagram illustrating exemplary control of the switching transistors in high-resolution mode and merging mode according to this embodiment. (As shown...) Figure 25 As shown, in the high-resolution mode illustrated in sections T30 to T31, in each logarithmic response section 310C1 to 310B4, the switching transistor 317 is turned on and the switching transistor 318 is turned off. This results in a current path forming the photocurrent flowing from the photoelectric conversion element 311 of each logarithmic response section 310C1 to 310C4 into its own logarithmic conversion circuit.

[0242] Conversely, in the combined mode described in sections T31 to T32, both switching transistors 317 and 318 of the logarithmic response section 310C1 are turned on. On the other hand, in the logarithmic response sections 310C2 to 310C4, switching transistor 317 is turned off, while switching transistor 318 is turned on. This results in a current path forming the current flowing from the photoelectric conversion element 311 of each logarithmic response section 310C1 to 310C4 into the logarithmic conversion circuit of the logarithmic response section 310C1.

[0243] 3.3 Functions and Effects

[0244] As described above, according to this embodiment, for example, compared to the second embodiment, since the switching transistor 319 can be omitted, the area occupied by the logarithmic response unit 310Cn in the pixel region can be reduced. This allows the area of ​​the light-receiving surface of the photoelectric conversion element 311 to be increased, resulting in improved sensitivity and extended dynamic range of the solid-state imaging device 200. Furthermore, omitting the switching transistor 319 allows for a further reduction in drive current.

[0245] Since other configurations, operations, and effects may be similar to those in the above embodiments, detailed descriptions will be omitted here.

[0246] 4. Fourth Implementation Method

[0247] The above embodiments are exemplary configurations in which the solid-state imaging device 200 outputs frame data (corresponding to image data) including detection signals indicating the presence or absence of address events for each pixel. Conversely, the fourth embodiment will be described by example, relating to a configuration in which the solid-state imaging device 200, in addition to image data including detection signals for each pixel, may also output image data including pixel signals based on the exposure of each pixel (hereinafter also referred to as grayscale image data).

[0248] The configuration and operation of the imaging device and solid-state imaging device according to this embodiment can be similar to the configuration and operation of the imaging device 100 and solid-state imaging device 200 according to the first embodiment described above, and therefore, detailed description will be omitted here. However, in this embodiment, the shared block 221 according to the first embodiment is replaced by the shared block 821 described below, and the detection chip 202 is replaced by the detection chip 802 described below.

[0249] 4.1 Configuration Example of Shared Blocks

[0250] Figure 26 This is a circuit diagram illustrating a schematic configuration example of a shared block according to this embodiment. The shared block 821 illustrated below is based on... Figure 17 The example shown is shared block 221. However, the configuration is not limited to this; for example, shared block 821 may be based on shared block 621 according to the second embodiment or shared block 721 according to the third embodiment.

[0251] like Figure 26 As shown, the shared block 821 according to this embodiment has a readout circuit 370 for reading pixel signals, similar to the reference circuit in the first embodiment. Figure 17 The configuration of the described shared block 221 is connected to the configuration of the shared line 3101.

[0252] 4.1.1 Variations of shared blocks

[0253] Furthermore, for example, the shared block 821 according to this embodiment may also be based on a reference in the second embodiment. Figure 21 The described shared block 621 is used to form this. Similarly, in this case, as... Figure 27 As shown, shared block 821 has a similar design to reference 821. Figure 21 The configuration of the described shared block 621 includes a readout circuit 370 for reading pixel signals connected to a common line 3101.

[0254] 4.2 Example of readout circuit configuration

[0255] Figure 28 This is a circuit diagram illustrating a schematic configuration example of the readout circuit according to this embodiment. For example... Figure 28 As shown, the readout circuit 370 according to this embodiment includes a reset transistor 373, an amplification transistor 375, and a selection transistor 376.

[0256] The readout circuit 370 operates together with the photoelectric conversion element 311 and the switching transistor 318 of the logarithmic response unit 310An to serve as a grayscale pixel 810 that generates a pixel signal corresponding to the amount of received light. That is, in this embodiment, the switching transistor 318 of each logarithmic response unit 310An also serves as a transmission transistor in the grayscale pixel 810. Furthermore, the node where the drain of the switching transistor 318, the source of the reset transistor 373, and the gate of the amplification transistor 375 are connected serves as a floating diffusion region (FD) 374 with a current-to-voltage conversion function (i.e., the function of converting accumulated charge into a voltage corresponding to the amount of charge).

[0257] For example, the drain of reset transistor 373 and the drain of amplification transistor 375 are connected to the power supply voltage VDD. However, for example, the drain of reset transistor 373 may be connected to a reset voltage different from the power supply voltage VDD. The source of amplification transistor 375 is connected to the drain of selection transistor 376, and the source of selection transistor 376 is connected to the vertical signal line VSL for inputting analog pixel signals to the column analog-to-digital converter (column ADC) 270 described below.

[0258] When a pixel signal is read, a high-level transmission signal TRG is applied from the row drive circuit 251 to the gate of the switching transistor 318. This turns on the switching transistor 318, causing the charge accumulated in the cathode of the photoelectric conversion element 311 to be transferred through the switching transistor 318 to the floating diffusion region 374. As a result, a pixel signal with a voltage value corresponding to the amount of charge accumulated in the floating diffusion region 374 appears at the source of the amplifying transistor 375. Subsequently, by setting the selection signal SEL applied from the row drive circuit 251 to the gate of the selection transistor 376 to a high level, the pixel signal appearing at the source of the amplifying transistor 375 appears in the vertical signal line VSL.

[0259] Furthermore, when the charge accumulated in the floating diffusion region 374 is released to reset the floating diffusion region 374, a high-level reset signal RST is applied from the row drive circuit 251 to the gate of the reset transistor 373. This allows the charge accumulated in the floating diffusion region 374 to be released to the power supply side through the reset transistor 373 (FD reset). At this time, the charge accumulated in the cathode of the photoelectric conversion element 311 can also be released to the power supply side by turning on the switching transistor 318 during the same cycle (PD reset).

[0260] In each shared block 821, the number of photoelectric conversion elements 311 simultaneously connected to the readout circuit 370 when reading grayscale image data, i.e., the number of switching transistors 318 (transfer transistors) turned on during the same time period, is not limited to one and can be multiple. For example, when reading high-resolution grayscale image data in each shared block 821, the switching transistors 318 can be connected to the readout circuit 370 in a time-division sequence, and when reading is performed under low illumination or other conditions with an expanded dynamic range (in combination), two or more switching transistors 318 can be turned on during the same time period.

[0261] 4.3 Example of Detection Chip Configuration

[0262] Figure 29 This is an example of a plan view of the detection chip according to this embodiment. The detection chip 802 according to this embodiment has a configuration in which a column ADC 270 for reading the analog pixel signal output from the grayscale pixel 810 as a digital pixel signal is added, similar to the one referenced in the first embodiment. Figure 4 The configuration of the detection chip 202 is described.

[0263] Under the control of the row drive circuit 251, each grayscale pixel 810 causes an analog pixel signal to appear on the vertical signal line VSL, thereby supplying the analog pixel signal to the column ADC 270. The column ADC 270 includes, for example, an AD converter for each vertical signal line VSL, and performs analog-to-digital (AD) conversion on the analog pixel signal input via each vertical signal line VSL. Subsequently, the column ADC 270 provides the digital signal, which has undergone AD conversion, to the signal processing circuit 240. The signal processing circuit 240 performs predetermined image processing on the image data including the digital signal. It should be noted that the column ADC 270 may include, for example, correlated double sampling (CDS) circuitry and may reduce kTC noise included in the digital pixel signal.

[0264] 4.4 Operation Example

[0265] For example, when an address event is detected in any detection pixel 300, grayscale image data can be read out by reading pixel signals from all grayscale pixels 810, or by reading pixel signals from grayscale pixels 810 belonging to the region where the address event was detected (in other words, the region where the object was detected by detection pixel 300). Figure 30 An example of switching between the target detection mode and the grayscale image reading mode according to this embodiment during operation is described. This description will describe the control unit 130 (see reference 130) in the imaging apparatus 100. Figure 1 This is an exemplary case of controlling the operating mode of the solid-state imaging device 200. However, the control of the operating mode is not limited to this example, and the signal processing circuitry 240 in the solid-state imaging device 200 can be configured to control the operating mode. Furthermore, Figure 30 The operation described herein can be terminated, for example, by interrupting the operation of the control unit 130 or the solid-state imaging device 200.

[0266] like Figure 30 As shown, in this operation, after activation, the control unit 130 sets the target detection mode to, for example, the operating mode of the solid-state imaging device 200 (step S201). The object detection mode is the operating mode that detects the occurrence of address events, and can be, for example, the mode described in the first embodiment. Figure 20 The described operation mode.

[0267] Next, the control unit 130 determines whether a target has been detected in the target detection mode (step S202), and continues in the address event detection mode until a target is detected (no in step S202). For example, the object detection determination may be similar to that in the first embodiment. Figure 20 The operations described in steps S102, S105 and S108.

[0268] If an object has been detected (Yes in step S202), the control unit 130 specifies the region where the object has been detected based on the frame data output from the solid-state imaging device 200 (step S203). Note that the region where the object has been detected can be, for example, a region that includes pixels where an on-time event (or off-time event) has been detected.

[0269] Next, the control unit 130 instructs the solid-state imaging device 200 to read pixel signals from the region where the object has been detected (step S204). Through this operation, the solid-state imaging device 200 outputs grayscale image data including pixel signals read from grayscale pixels 810 belonging to the region where the object has been detected.

[0270] 4.5 Functions and Effects

[0271] As described above, according to this embodiment, not only can object detection be performed based on the presence or absence of address events, but grayscale image data of the region or all pixels of the detected object can also be acquired.

[0272] Since other configurations, operations, and effects may be similar to those in the above embodiments, detailed descriptions will be omitted here.

[0273] 5. Fifth Implementation Method

[0274] The fourth embodiment described above is an exemplary configuration in which the readout circuit 370 is connected to the common line 3101 in a configuration capable of reading grayscale image data other than subject detection. In contrast, in the fifth embodiment, the case where the readout circuit 370 is connected to a different common line than the common line 3101 will be described by example.

[0275] The configuration and operation of the imaging device and solid-state imaging device according to this embodiment can be similar to the configuration and operation of the imaging device 100 and solid-state imaging device 200 according to the fourth embodiment described above, and therefore, a detailed description will be omitted here. However, in this embodiment, the shared block 821 according to the fourth embodiment is replaced by the shared block 921 described below.

[0276] 5.1 Configuration Example of Shared Blocks

[0277] Figure 31 This is a circuit diagram illustrating a schematic configuration example of a shared block according to this embodiment. The shared block 921 in the following example is based on... Figure 17 The example shown is shared block 221. However, the configuration is not limited to this; for example, shared block 921 may also be based on shared block 621 according to the second embodiment or shared block 721 according to the third embodiment.

[0278] like Figure 31 As shown, the shared block 921 according to this embodiment has a configuration in which the cathodes of the photoelectric conversion elements 311 in two or more or all logarithmic response units 310An are connected by a common line 3102, which is different from the reference line in the first embodiment. Figure 17 The shared block 221 described is configured with a common line 3101. The readout circuit 370 is connected to the common line 3102. Furthermore, a switching transistor 377, also serving as a transfer transistor, is disposed between the readout circuit 370 and the photoelectric conversion element 311 of each logarithmic response unit 310An, and the connection between the photoelectric conversion element 311 and the readout circuit 370 is controlled by the switching transistor 377. For example, the common line 3102 may be an example of the second common line in the claims.

[0279] 5.1.1 Variations of shared blocks

[0280] Furthermore, for example, the shared block 921 according to this embodiment can also be based on the reference in the second embodiment. Figure 21 The described shared block 621 is formed. Even in this case, as Figure 32 As shown, shared block 921 has the same characteristics as the reference. Figure 21 The shared block 621 described has a similar configuration, in which the cathodes of the photoelectric conversion elements 311 in two or more or all logarithmic response units 310An are connected by a common line 3102, the readout circuit 370 is connected to the common line 3102, and the switching transistor 377 is disposed between the readout circuit 370 and the photoelectric conversion elements 311 of each logarithmic response unit 310An.

[0281] 5.2 Operation Example

[0282] In the above configuration, when reading pixel signals from grayscale pixels including the readout circuit 370, all switching transistors 317 and 318 of the logarithmic response units 310A are turned off, and the switching transistors 377 corresponding to individual grayscale pixels of the logarithmic response unit 310A are connected to the readout circuit 370 in a time-division sequence. However, during cell division, when reading is performed with an extended dynamic range under low illumination or the like, two or more switching transistors 318 are turned on during the same time period, thereby achieving reading with an extended dynamic range.

[0283] 6. Sixth Implementation Method

[0284] The above-described implementation is an exemplary case where a synchronous EVS, which does not require arbitration for requests to read detection signals output from each shared block 221, is applied to a solid-state imaging device 200. However, this configuration is not limited to such an example. For example, as in Figure 33 The solid-state imaging apparatus described herein may also allow the application of an asynchronous EVS including a line arbitrator 280, which arbitrates the requests output from each line of the address event detection unit 260 and determines the order of reading the detection signals. It should be noted that... Figure 33 The detection chip 1002 in the solid-state imaging apparatus according to this embodiment is depicted.

[0285] In this way, even when using asynchronous EVS, similar to the implementation described above, the photocurrent flowing from multiple photoelectric conversion elements 311 can be concentrated into a single logarithmic conversion circuit, resulting in a larger photocurrent. Consequently, the dynamic range of photocurrent detection is expanded, achieving a sufficiently wide dynamic range even under conditions such as low illumination.

[0286] On the other hand, when sufficient illumination can be obtained, by turning off the switching transistor 318 and turning on the switching transistor 317 in all or a sufficient number of logarithmic response units 310An, etc., all or a sufficient number of logarithmic response units 310An, etc. can be operated as an address event detection pixel, resulting in high-resolution address event detection, reduced operating power, etc.

[0287] Since other configurations, operations, and effects may be similar to those in the above embodiments, detailed descriptions will be omitted here.

[0288] 7. Examples of application to moving objects

[0289] The technology disclosed herein (the Technology) can be applied to a variety of products. The Technology disclosed herein can be applied to devices mounted on any moving object, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, aircraft, drones, ships, and robots.

[0290] Figure 34 This is a block diagram illustrating an example configuration of a vehicle control system as an example of a mobile body control system to which the technology according to embodiments of the present disclosure can be applied.

[0291] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 34 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle external information detection unit 12030, a vehicle internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as examples of the functional structure of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0292] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for drive force generating devices (such as internal combustion engines, drive motors, etc.) that generate drive force for the vehicle, drive force transmission mechanisms that transmit drive force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate braking force for the vehicle.

[0293] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches, which are alternatives to buttons, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0294] The vehicle external information detection unit 12030 detects information outside the vehicle, including information from the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle external information detection unit 12030. The vehicle external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. In addition, the vehicle external information detection unit 12030 can also perform processing based on the received images, such as detecting people, vehicles, obstacles, signs, text on the road surface, etc., or detecting their distances.

[0295] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0296] The vehicle interior information detection unit 12040 detects information about the vehicle interior. The vehicle interior information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the vehicle interior information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is drowsy.

[0297] The microcomputer 12051 can calculate control target values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, following driving based on following distance, maintaining vehicle speed, collision warning, lane departure warning, etc.

[0298] In addition, the microcomputer 12051 controls the drive force generating device, steering mechanism, braking device, etc., based on information about the outside or inside of the vehicle obtained by the vehicle external information detection unit 12030 or the vehicle internal information detection unit 12040, and can perform cooperative control for autonomous driving, which enables the vehicle to drive automatically without relying on the driver's operation.

[0299] Additionally, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the outside of the vehicle obtained by the vehicle external information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam based on the position of the vehicle in front or oncoming vehicle detected by the vehicle external information detection unit 12030.

[0300] The audio / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information. Figure 35 In the example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. For example, display unit 12062 may include at least one of an on-board display and a head-up display.

[0301] Figure 35 This is a schematic diagram illustrating an example of the mounting position of the imaging unit 12031.

[0302] exist Figure 35 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0303] Imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, installed on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, as well as on the upper part of the windshield inside the vehicle. Imaging unit 12101 installed on the front nose inside the vehicle and imaging unit 12105 installed on the upper part of the windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 installed on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 installed on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0304] Incidentally, Figure 35 An example of the imaging range of imaging units 12101 to 12104 is described. Imaging range 12111 represents the imaging range of imaging unit 12101 installed at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 installed at the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 installed at the rear bumper or rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by overlaying image data captured by imaging units 12101 to 12104.

[0305] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0306] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed relative to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the vehicle ahead. This nearest three-dimensional object specifically exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can preset a following distance to stay behind the vehicle ahead and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Thus, coordinated control for autonomous driving, enabling the vehicle to drive automatically without relying on driver operation, is possible.

[0307] For example, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0308] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. The microcomputer 12051 can identify a pedestrian, for example, by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the audio / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The audio / image output unit 12052 can also control the display unit 12062 so that an icon representing the pedestrian is displayed at a desired location.

[0309] Examples of vehicle control systems to which the technology according to this disclosure is applicable have been described above. The technology according to this disclosure can be appropriately applied to the imaging unit 12031 in the above configuration. Specifically, Figure 1 The imaging device 100 can be applied to the imaging unit 12031. By applying the technology according to this disclosure to the imaging unit 12031, pixel miniaturization and higher visibility in captured images can be achieved, thereby reducing driver fatigue.

[0310] It should be noted that the above embodiments describe examples for embodying the present technology; therefore, the matters in the embodiments correspond to the matters in the specified claims of the present invention. Similarly, the matters in the claims that specify the present invention correspond to the matters in the embodiments of the present technology that are represented by the same names as the matters specifying the present invention. However, the present technology is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the scope and spirit of the present technology.

[0311] The effects described in this specification are merely examples, and therefore, other effects may exist, not limited to the exemplary effects.

[0312] It should be noted that this technology may also have the following configurations. (1)

[0314] A solid-state imaging device, comprising:

[0315] Multiple detection pixels, each of which outputs the brightness change of the incident light;

[0316] The detection circuit outputs an event signal based on the brightness change output from each detected pixel; and

[0317] A first common line connects the plurality of detected pixels to each other.

[0318] Each detected pixel includes:

[0319] Photoelectric conversion element;

[0320] The logarithmic conversion circuit converts the photocurrent flowing from the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent.

[0321] The first circuit outputs the brightness change of the incident light incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit;

[0322] A first transistor is connected between the photoelectric conversion element and the logarithmic conversion circuit; and

[0323] The second transistor is connected between the photoelectric conversion element and the first common line, and

[0324] The detection circuit includes a second circuit that outputs the event signal based on the brightness change output from each of the detected pixels. (2)

[0326] According to the solid-state imaging device described in (1),

[0327] Each detection pixel also includes:

[0328] A third transistor is connected between a first node and a second node, the first node being configured to connect the first transistor and the logarithmic conversion circuit to each other, and the second node being configured to connect the second transistor and the first common line to each other. (3)

[0330] According to the solid-state imaging device of (1), wherein the second transistor is connected between the first common line and the node, the node being configured to connect the photoelectric conversion element and the first transistor to each other. (4)

[0332] The solid-state imaging apparatus according to any one of (1) to (3) further includes a readout circuit connected to a first common line and generating a pixel signal having a voltage value corresponding to the charge accumulated in the photoelectric conversion element. (5)

[0334] According to the solid-state imaging device described in (4),

[0335] The readout circuit includes:

[0336] A reset transistor is connected between the first common line and the power line; and

[0337] An amplifying transistor, the gate of which is connected to the first common line. (6)

[0339] The solid-state imaging apparatus according to any one of (1) to (3) further comprises:

[0340] A second common line connects the plurality of detection pixels to each other;

[0341] Multiple fourth transistors are connected between the photoelectric conversion element in each of the detection pixels and the second common line; and

[0342] The readout circuit is connected to the second common line and generates a pixel signal having a voltage value corresponding to the charge accumulated in the photoelectric conversion element. (7)

[0344] According to the solid-state imaging device described in (6),

[0345] The readout circuit includes:

[0346] The reset transistor is connected between the second common line and the power line; and

[0347] An amplifying transistor, the gate of which is connected to the second common line. (8)

[0349] According to any one of (1) to (7), the solid-state imaging device,

[0350] Each of the detected pixels further includes:

[0351] The differentiator generates a differential signal representing the amount of the converted voltage signal output from the logarithmic conversion circuit. (9)

[0353] According to the solid-state imaging device described in (8),

[0354] The detection circuit includes:

[0355] The selection unit selects one of the differential signals output from each of the detected pixels; and

[0356] The comparator outputs the event signal based on the differential signal. (10)

[0358] According to the solid-state imaging device described in (9),

[0359] The comparator includes:

[0360] A first comparator detects that the voltage value of the differential signal exceeds a first threshold and outputs the event signal; and

[0361] The second comparator detects that the voltage value of the differential signal has dropped below a second threshold, which is lower than the voltage level of the first threshold, and outputs the event signal. (11)

[0363] The solid-state imaging device according to any one of (1) to (10) includes

[0364] Multiple detection circuits,

[0365] Each of the detection circuits is configured to output a request to read the detection signal from the detection circuit when an address event is detected in at least one of the plurality of detection pixels.

[0366] The solid-state imaging device further includes an arbitrator configured to arbitrate the request output from at least one of the plurality of detection circuits and determine the readout order of the detection signals of the detection circuits that have output the request. (12)

[0368] The solid-state imaging apparatus according to any one of (1) to (11) further comprises: a first chip including a light receiving section having a plurality of logarithmic response sections arranged in a two-dimensional lattice pattern, each of the plurality of logarithmic response sections including a photoelectric conversion element, a logarithmic conversion circuit, a first transistor, and a second transistor. (13)

[0370] According to the solid-state imaging device described in (12),

[0371] The logarithmic conversion circuit includes:

[0372] A fourth transistor, the source of which is connected to the first transistor; and

[0373] A fifth transistor, the gate of which is connected to the source of the fourth transistor and the source of which is grounded, and

[0374] The gate of the fourth transistor is connected to the drain of the fifth transistor. (14)

[0376] According to the solid-state imaging device described in (13),

[0377] The logarithmic conversion circuit includes:

[0378] A sixth transistor, the source of which is connected to the drain of the fourth transistor, and the drain of which is connected to a power supply line; and

[0379] A seventh transistor, the gate of which is connected to the drain of the fourth transistor, and the source of which is connected to the drain of the fifth transistor, and

[0380] The gate of the sixth transistor is connected to the drain of the seventh transistor. (15)

[0382] According to the solid-state imaging device described in (12),

[0383] The light receiving portion further includes pixel isolation portions extending in a lattice pattern, and

[0384] Each of the logarithmic response units is disposed in each pixel region of a two-dimensional lattice pattern divided by pixel isolation units. (16)

[0386] According to the solid-state imaging device described in (15),

[0387] The first transistor, the second transistor, at least two transistors different from the first transistor or the second transistor, and the photoelectric conversion element are arranged in the pixel region.

[0388] The at least two transistors are disposed in the pixel region at a position spanning the photoelectric conversion element, and

[0389] The logarithmic conversion circuit is composed of at least one of the at least two transistors used in each of the two adjacent pixel regions. (17)

[0391] The solid-state imaging apparatus according to any one of (12) to (16) further includes

[0392] The second chip, on which multiple detection circuits are arranged, is further divided into two chips.

[0393] The first chip and the second chip constitute a single stacked chip. (18)

[0395] An imaging device, comprising:

[0396] The solid-state imaging device according to any one of (1) to (17); and

[0397] The control unit controls the solid-state imaging device. (19)

[0399] According to the imaging device described in (18),

[0400] The solid-state imaging device includes multiple shared blocks, each of which includes the multiple detection pixels.

[0401] The control unit switches the operating mode of the solid-state imaging device to either the first mode or the second mode.

[0402] A first mode is a mode in which transistor on / off is executed in at least one of the plurality of shared blocks, the transistor on / off being configured to cause the first transistor and the second transistor in one of the plurality of detection pixels to be turned on in a detection image, the first transistor in at least another detection image in the plurality of detection pixels to be turned off, and the second transistor to be turned on.

[0403] The second mode is a mode in which transistor on / off is performed in all of the plurality of shared blocks, wherein the transistor on / off is configured to perform such that the first transistor of each of the plurality of detection pixels is turned on and the second transistor is turned off. (20)

[0405] According to the imaging device described in (19),

[0406] The first mode includes:

[0407] The third and fourth modes,

[0408] The third mode is a mode in which transistor on / off is executed in all of the plurality of shared blocks, wherein the transistor on / off is configured to cause the first transistor and the second transistor in one of the plurality of detection pixels to be turned on, the first transistor in at least one of the plurality of detection pixels in another detection image to be turned off, and the second transistor to be turned on.

[0409] The fourth mode is a mode in which transistors are turned on / off in a portion of the plurality of shared blocks and in the remaining shared blocks among the plurality of shared blocks.

[0410] When executed within a portion of the plurality of shared blocks, the transistor on / off state of the fourth mode is configured to cause the first and second transistors in one of the plurality of detected pixels to be turned on, the first transistor in at least one of the other detected pixels to be turned off, and the second transistor to be turned on.

[0411] When executed in the remaining shared blocks among the plurality of shared blocks, the transistor on / off state of the fourth mode is configured to cause the first transistor of each of the plurality of detected pixels to be turned on and the second transistor to be turned off, and

[0412] The control unit switches the operating mode of the solid-state imaging device to one of the second to the fourth modes.

[0413] Reference number list

[0414] 10, 20 layout pixels

[0415] 12-pixel isolation section

[0416] 100 Imaging Device

[0417] 110 Optics Department

[0418] 120 Recording Department

[0419] 130 Control Department

[0420] 200 Solid-State Imaging Device

[0421] 201 Optical Receiver Chip

[0422] 202, 802, 1002 detection chips

[0423] 211, 212, 213, 231, 232, 233 through-hole arrangement section

[0424] 220 optical receiver

[0425] Shared blocks 221, 621, 721, 821, and 921

[0426] 240 Signal Processing Circuit

[0427] 251-line drive circuit

[0428] 252-column drive circuit

[0429] 260 Address Event Detection Department

[0430] 270 ADCs

[0431] 280-line arbitrator

[0432] 300 detection pixels

[0433] 305 detection circuit

[0434] Logarithmic response units of 310, 310A, 310An, 310Bn, and 310Cn

[0435] 311 photoelectric conversion element

[0436] 312, 313, 315, 316, 512 nMOS transistors

[0437] 314, 411, 511 pMOS transistors

[0438] 314c contact

[0439] 317 to 319, 377 switching transistors

[0440] 320 Detection Module

[0441] 330 buffer

[0442] 340 Differentiator

[0443] 341 and 343 capacitors

[0444] 342 Inverter

[0445] 344 Switch

[0446] 360° transmission circuit

[0447] 370 Readout Circuit

[0448] 373 Reset Transistor

[0449] 374 Floating Diffusion Region

[0450] 375 Amplifying Transistor

[0451] 376 Select Transistor

[0452] 400 Selection Department

[0453] 410, 420 selectors

[0454] 500 Comparative Section

[0455] 510 and 520 comparators

[0456] 3101 and 3102 share a line

Claims

1. A solid-state imaging device, comprising: Multiple detection pixels, each of which outputs the brightness change of the incident light; The detection circuit outputs an event signal based on the brightness change output from each detected pixel; A first common line connects the plurality of detection pixels to each other; A second common line connects the plurality of detection pixels to each other; as well as The readout circuit is connected to the second common line. The readout circuit includes: The reset transistor is connected between the second common line and the power line; and An amplifying transistor, the gate of which is connected to the second common line. Each detected pixel includes: Photoelectric conversion element; The logarithmic conversion circuit converts the photocurrent flowing from the photoelectric conversion element into a voltage signal corresponding to the logarithmic value of the photocurrent. The first circuit outputs the brightness change of the incident light incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit; A first transistor is connected between the photoelectric conversion element and the logarithmic conversion circuit; and The second transistor is connected between the photoelectric conversion element and the first common line, and The detection circuit includes a second circuit that outputs the event signal based on the brightness change output from each of the detected pixels.

2. The solid-state imaging device according to claim 1, in, Each detected pixel also includes: A third transistor is connected between a first node and a second node, the first node being configured to connect the first transistor and the logarithmic conversion circuit to each other, and the second node being configured to connect the second transistor and the first common line to each other.

3. The solid-state imaging apparatus of claim 1, wherein the second transistor is connected between the first common line and node, the node being configured to connect the photoelectric conversion element and the first transistor to each other.

4. The solid-state imaging device according to claim 1, further comprising: The readout circuit is connected to the first common line and generates a pixel signal having a voltage value corresponding to the charge accumulated in the photoelectric conversion element.

5. The solid-state imaging device according to claim 4, in, The readout circuit includes: A reset transistor is connected between the first common line and the power line; and An amplifying transistor, the gate of which is connected to the first common line.

6. The solid-state imaging device according to claim 1, further comprising: Multiple fourth transistors are connected between the photoelectric conversion element in each of the detection pixels and the second common line; as well as The readout circuit generates a pixel signal having a voltage value corresponding to the charge accumulated in the photoelectric conversion element.

7. The solid-state imaging device according to claim 1, in, Each of the detected pixels also includes: The differentiator generates a differential signal representing the amount of the converted voltage signal output from the logarithmic conversion circuit.

8. The solid-state imaging device according to claim 7, in, The detection circuit includes: The selection unit selects one of the differential signals output from each of the detected pixels; and The comparator outputs the event signal based on the differential signal.

9. The solid-state imaging device according to claim 8, in, The comparator includes: A first comparator detects that the voltage value of the differential signal exceeds a first threshold and outputs the event signal; and The second comparator detects that the voltage value of the differential signal has dropped below a second threshold, which is lower than the voltage level of the first threshold, and outputs the event signal.

10. The solid-state imaging device according to claim 1, comprising: Multiple detection circuits, Each of the detection circuits is configured to output a request to read the detection signal from the detection circuit when an address event is detected in at least one of the plurality of detection pixels. An arbitrator configured to determine the readout order of the detection signals of the detection circuits that have output the request by arbitrating the request output from at least one of the plurality of detection circuits.

11. The solid-state imaging device according to claim 1, further comprising: The first chip includes a light receiver having a plurality of logarithmic response units arranged in a two-dimensional lattice pattern, each of the plurality of logarithmic response units including a photoelectric conversion element, a logarithmic conversion circuit, a first transistor, and a second transistor.

12. The solid-state imaging device according to claim 11, in, The logarithmic conversion circuit includes: A fourth transistor, the source of which is connected to the first transistor; and A fifth transistor, the gate of which is connected to the source of the fourth transistor and the source of which is grounded, and The gate of the fourth transistor is connected to the drain of the fifth transistor.

13. The solid-state imaging device according to claim 12, in, The logarithmic conversion circuit includes: A sixth transistor, the source of which is connected to the drain of the fourth transistor, and the drain of which is connected to a power supply line; and A seventh transistor, the gate of which is connected to the drain of the fourth transistor, and the source of which is connected to the drain of the fifth transistor. The gate of the sixth transistor is connected to the drain of the seventh transistor.

14. The solid-state imaging device according to claim 11, in, The light receiving portion further includes pixel isolation portions extending in a lattice pattern, and Each of the logarithmic response units is disposed in each pixel region of a two-dimensional lattice pattern divided by pixel isolation units.

15. The solid-state imaging device according to claim 14, in, The first transistor, the second transistor, at least two transistors different from the first transistor or the second transistor, and the photoelectric conversion element are arranged in the pixel region. The at least two transistors are disposed in the pixel region at a position spanning the photoelectric conversion element, and The logarithmic conversion circuit is constructed by using at least one of the at least two transistors in each of two adjacent pixel regions.

16. The solid-state imaging apparatus according to claim 11, further comprising: The second chip, on which multiple detection circuits are arranged, is further divided into two chips. The first chip and the second chip constitute a single stacked chip.

17. An imaging device, comprising: The solid-state imaging device according to claim 1; as well as The control unit controls the solid-state imaging device.

18. The imaging apparatus according to claim 17, in, The solid-state imaging device includes multiple shared blocks, and the multiple shared blocks include the multiple detection pixels, and The control unit switches the operating mode of the solid-state imaging device to either the first mode or the second mode. The first mode is a mode in which transistor on / off is executed in at least one of the plurality of shared blocks, the transistor on / off being configured to cause the first transistor and the second transistor in one of the plurality of detection pixels to be turned on in a detection image, the first transistor in at least another detection image in the plurality of detection pixels to be turned off, and the second transistor to be turned on. The second mode is a mode in which transistor on / off is performed in all of the plurality of shared blocks, wherein the transistor on / off is configured to perform such that the first transistor of each of the plurality of detection pixels is turned on and the second transistor is turned off.

19. The imaging apparatus according to claim 18, in, The first mode includes: The third and fourth modes, The third mode is a mode in which transistor on / off is executed in all of the plurality of shared blocks, wherein the transistor on / off is configured to cause the first transistor and the second transistor in one of the plurality of detection pixels to be turned on, the first transistor in at least one of the plurality of detection pixels in another detection image to be turned off, and the second transistor to be turned on. The fourth mode is a mode in which transistors are turned on / off in a portion of the plurality of shared blocks and in the remaining shared blocks among the plurality of shared blocks. When executed within a portion of the plurality of shared blocks, the transistor on / off state of the fourth mode is configured to cause the first and second transistors in one of the plurality of detected pixels to be turned on, the first transistor in at least one of the other detected pixels to be turned off, and the second transistor to be turned on. When executed in the remaining shared blocks among the plurality of shared blocks, the transistor on / off state of the fourth mode is configured to cause the first transistor of each of the plurality of detected pixels to be turned on and the second transistor to be turned off, and The control unit switches the operating mode of the solid-state imaging device to one of the second to the fourth modes.

Images