Voltage regulating circuit and electronic device

Abstract

The present disclosure provides a voltage adjustment circuit and an electronic device, belonging to the technical field of power supply control systems, wherein the voltage adjustment circuit includes: a first sampling circuit, a first operation subcircuit, a second sampling circuit, a second operation subcircuit, a logic control module, a driving subcircuit and a voltage regulation subcircuit. The voltage adjustment circuit provided by the present disclosure adds a bypass working mode on the basis of the traditional BOOST architecture, and can achieve output following input changes when the input voltage is close to the output voltage and the input voltage is greater than the output voltage without adding additional electronic components at the topological level, thereby widening the input voltage range of the circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of power supply control systems, and in particular relates to a voltage regulating circuit and an electronic device. Background Art

[0002] As people's requirements for the size, battery life, processing speed and other aspects of consumer electronic products increase, power management chips, as the heart of portable electronic products, show a development trend of smaller and smaller size, higher conversion efficiency and more frequent transient conversion. Among them, switching power supplies have gradually become the first choice for power management chips due to their advantages such as high conversion efficiency and simple circuit structure. DC / DC converters are voltage converters that transform input voltage and effectively output fixed voltage. DC / DC converters are divided into three categories: boost DC / DC converters, buck DC / DC converters and buck-boost DC / DC converters. Taking the BOOST type DC / DC converter as an example, the traditional BOOST architecture can only achieve boost output, that is, the output voltage is greater than the input voltage. Therefore, when the input voltage is greater than the preset value of the output voltage, the circuit cannot work normally. Therefore, the input voltage range limits the application scenario of the traditional BOOST architecture. However, in actual applications, the BOOST load requirements include working conditions where the input voltage is greater than the output voltage, so the conventional BOOST architecture cannot cover this application scenario. Summary of the invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a voltage regulating circuit and an electronic device.

[0004] In a first aspect, an embodiment of the present disclosure provides a voltage adjustment circuit, comprising:

[0005] A first sampling circuit is configured to sample the output voltage to generate a first feedback voltage, and output the first feedback voltage to a first operation sub-circuit;

[0006] a first operation subcircuit, configured to compare the first feedback voltage with a reference voltage, obtain a first comparison result through comparison, generate a first control signal according to the first comparison result and a preset algorithm, and output the first control signal to a logic control module;

[0007] A second sampling circuit is configured to sample the input voltage to generate a second feedback voltage, and output the second feedback voltage to a second operation sub-circuit;

[0008] a second operation subcircuit, configured to compare the second feedback voltage with a reference voltage, obtain a second comparison result through comparison, generate a second control signal according to the second comparison result, and output the second control signal to a logic control module;

[0009] a logic control module, configured to determine a first working mode or a second working mode according to the second control signal, configured to output a third control signal generated by a logic operation according to the first control signal and a clock signal in the first working mode, and output the third control signal to the driving sub-circuit, and configured to output a fourth control signal generated by a logic operation according to the second control signal in the second working mode, and output the fourth control signal to the driving sub-circuit;

[0010] a driving subcircuit, configured to generate a first driving signal according to the third control signal, or to generate a second driving signal according to the fourth control signal, so as to drive the voltage regulating subcircuit;

[0011] The voltage regulating subcircuit is configured to regulate the input voltage according to the first driving signal or the second driving signal to generate the output voltage.

[0012] In some embodiments, the logic control module includes a pattern recognition subcircuit and a logic control subcircuit; the pattern recognition subcircuit is configured to determine whether the operating mode of the voltage adjustment circuit is the first operating mode or the second operating mode according to the second control signal; the logic control subcircuit is configured to output the third control signal or the fourth control signal to the driving subcircuit according to the recognition result of the pattern recognition subcircuit.

[0013] In some embodiments, the third control signal includes a first control sub-signal and a second control sub-signal, the driving sub-circuit includes a first driving sub-circuit and a second driving sub-circuit, and the first driving signal includes a first driving sub-signal and a second driving sub-signal; the first driving sub-circuit is configured to generate a first driving sub-signal according to the first control sub-signal, and the second driving sub-circuit is configured to generate a second driving sub-signal according to the second control sub-signal.

[0014] In some embodiments, the first control sub-signal and the second control sub-signal are dead-zone complementary signals.

[0015] In some embodiments, the first sampling circuit includes a first voltage-dividing resistor and a second voltage-dividing resistor; the first end of the first voltage-dividing resistor is electrically connected to the output voltage end, the second end of the first voltage-dividing resistor is electrically connected to the first end of the second voltage-dividing resistor and the second end of the first operation subcircuit, and the second end of the second voltage-dividing resistor is electrically connected to the first reference voltage end; and / or,

[0016] The second sampling circuit includes a third voltage-dividing resistor and a fourth voltage-dividing resistor; the first end of the third voltage-dividing resistor is electrically connected to the input voltage end, the second end of the third voltage-dividing resistor is electrically connected to the first end of the fourth voltage-dividing resistor and the second end of the second operation subcircuit, and the second end of the fourth voltage-dividing resistor is electrically connected to the first reference voltage end.

[0017] In some embodiments, when the first sampling circuit includes the first voltage-dividing resistor and the second voltage-dividing resistor, and the second sampling circuit includes the third voltage-dividing resistor and the fourth voltage-dividing resistor, the ratio of the first voltage-dividing resistor to the second voltage-dividing resistor is M1, the ratio of the third voltage-dividing resistor to the fourth voltage-dividing resistor is M2, and M1=M2.

[0018] In some embodiments, a ratio M1 of the first voltage-dividing resistor to the second voltage-dividing resistor and a ratio M2 of the third voltage-dividing resistor to the fourth voltage-dividing resistor both match the code value.

[0019] In some embodiments, the first operation subcircuit includes an error amplifier and a first comparator; the non-inverting input terminal of the error amplifier is electrically connected to the first sampling circuit, the inverting input terminal of the error amplifier is electrically connected to the reference voltage terminal, the output terminal of the error amplifier is electrically connected to the inverting input terminal of the first comparator, the non-inverting input terminal of the first comparator is configured to receive a sawtooth wave signal, and the output terminal of the first comparator is electrically connected to the logic control module.

[0020] In some embodiments, the first operation subcircuit includes a second comparator; the non-inverting input terminal of the second comparator is electrically connected to the first sampling circuit, the inverting input terminal of the second comparator is electrically connected to the reference voltage terminal, and the output terminal of the second comparator is electrically connected to the logic control module.

[0021] In some embodiments, the second operation subcircuit includes a bypass comparator; the non-inverting input terminal of the bypass comparator is electrically connected to the reference voltage terminal, the inverting input terminal of the bypass comparator is electrically connected to the second sampling circuit, and the output terminal of the bypass comparator is electrically connected to the logic control module.

[0022] In some embodiments, the voltage regulation subcircuit includes an inductor, a first transistor, a second transistor and a load capacitor; the first end of the inductor is electrically connected to the input voltage end, the second end of the inductor is electrically connected to the first end of the first transistor and the first end of the second transistor, the second end of the first transistor is electrically connected to the second reference voltage end, the control end of the first transistor is electrically connected to the driving subcircuit, the second end of the second transistor is electrically connected to the first end of the load capacitor, and the control end of the second transistor is electrically connected to the driving subcircuit.

[0023] In a second aspect, an embodiment of the present disclosure further provides an electronic device, which includes the voltage adjustment circuit described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of a traditional voltage regulation circuit structure;

[0025] Figure 2 is a schematic diagram of an exemplary voltage adjustment circuit structure;

[0026] Figure 3 A schematic diagram of a voltage adjustment circuit structure provided by an embodiment of the present disclosure;

[0027] Figure 4 for Figure 3 Mode switching waveform of medium voltage regulation circuit;

[0028] Figure 5 for Figure 3 Schematic diagram of hysteresis output in bypass mode of medium voltage regulation circuit;

[0029] Figure 6 A schematic diagram of another voltage adjustment circuit structure provided in an embodiment of the present disclosure.

[0030] The figures are marked as follows: 1. first sampling circuit; Vout, output voltage; Vfb_vout, first feedback voltage; Vref, reference voltage; 2. first operation subcircuit; K1, first control signal; 3. logic control module; 4. second sampling circuit; Vin, input voltage; Vfb_vin, second feedback voltage; 5. second operation subcircuit; K2, second control signal; CLK, clock signal; 6. driving subcircuit; 7. voltage regulation subcircuit; K31, first control subsignal; K32, second control subsignal; 61, first driving subcircuit Circuit; 62, second driving sub-circuit; RFB1, first voltage-dividing resistor; RFB2, second voltage-dividing resistor; RFB3, third voltage-dividing resistor; RFB4, fourth voltage-dividing resistor; EA, error amplifier; CMP1, first comparator; STW, sawtooth wave signal; CMP2, second comparator; CMP3, bypass comparator; L, inductor; LS, first transistor; HS1, second transistor; Cout, load capacitor; HS2, superposition transistor; Vbias, bias voltage; Vs, output voltage setting value; Voffset, final hysteresis voltage. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0034] The inventors found that, taking the BOOST type DC / DC converter as an example, the traditional BOOST architecture can only achieve boost output, that is, the output voltage Vout is greater than the input voltage Vin. Therefore, when the input voltage Vin is greater than the output voltage preset value Vs, the circuit cannot work normally. Therefore, the input voltage Vin range limits the application scenarios of the traditional BOOST architecture. Figure 1 FIG. 1 is a schematic diagram of a conventional voltage regulation circuit structure. Figure 1As shown, the voltage adjustment circuit includes a first sampling circuit 1, a first operation subcircuit 2, a logic control module 3, a driving subcircuit 6 and a voltage regulation subcircuit 7; wherein the first sampling circuit 1 is configured to sample the output voltage Vout to generate a first feedback voltage Vfb_vout, and output the first feedback voltage Vfb_vout to the first operation subcircuit 2; the first operation subcircuit 2 is configured to compare the first feedback voltage Vfb_vout with the reference voltage Vref, obtain a first comparison result through comparison, generate a first control signal K1 according to the first comparison result and a preset algorithm, and output the first control signal K1 to the logic control module 3; the logic control module 3 is configured to output a third control signal generated by logic operation according to the first control signal K1 and the clock signal CLK, and output the third control signal to the driving subcircuit 6; the driving subcircuit 6 is configured to generate a first drive signal according to the third control signal to drive the voltage regulation subcircuit 7; the voltage regulation subcircuit 7 is configured to regulate the input voltage Vin according to the first drive signal to generate the output voltage Vout.

[0035] Specifically, Figure 1 As shown, the first sampling circuit 1 includes a first voltage-dividing resistor RFB1 and a second voltage-dividing resistor RFB2, the first operation subcircuit 2 includes an error amplifier EA and a first comparator CMP1, and the voltage regulation subcircuit 7 includes an inductor L, a first transistor LS, a second transistor HS1 and a load capacitor Cout; the first end of the first voltage-dividing resistor RFB1 is electrically connected to the output voltage Vout end, the second end of the first voltage-dividing resistor RFB1 and the first end of the second voltage-dividing resistor RFB2 and the in-phase input end of the error amplifier EA are all electrically connected, and the second end of the second voltage-dividing resistor RFB2 is electrically connected to the first reference voltage end; the inverting input end of the error amplifier EA is electrically connected to the reference voltage Vref end, The output end of the error amplifier EA is electrically connected to the inverting input end of the first comparator CMP1, the non-inverting input end of the first comparator CMP1 is configured to receive the sawtooth wave signal STW, and the output end of the first comparator CMP1 is electrically connected to the logic control module 3; the first end of the inductor L is electrically connected to the input voltage Vin end, the second end of the inductor L is electrically connected to the first end of the first transistor LS and the first end of the second transistor HS1, the second end of the first transistor LS is electrically connected to the second reference voltage end, the control end of the first transistor LS is electrically connected to the driving sub-circuit 6, the second end of the second transistor HS1 is electrically connected to the first end of the load capacitor Cout, and the control end of the second transistor HS1 is electrically connected to the driving sub-circuit 6.

[0036] As Figure 1Taking the voltage adjustment circuit shown in the figure as an example, as a traditional BOOST architecture, it can only achieve boost output. D represents the conduction duty cycle of the first transistor LS. When the system is in a continuous conduction state, according to the volt-second balance principle, the relationship between the output voltage Vout and the input voltage Vin satisfies the following conditions:

[0037]

[0038] Among them, due to the restrictions on the minimum on-time and the maximum on-time, 0<D<1, it can be achieved that Vout is always greater than Vin, that is, the output voltage Vout is greater than the input voltage Vin. However, when the input voltage Vin is greater than the preset output voltage Vs under the BOOST architecture, the BOOST circuit cannot work normally, resulting in the input voltage Vin range limiting the application scenarios of the traditional BOOST architecture.

[0039] However, in actual applications, the BOOST load requirements include the working condition that the input voltage Vin is greater than the output voltage Vout, so the conventional BOOST architecture cannot cover this application scenario. Figure 1 The traditional BOOST architecture shown is used as an example to power a low-dropout regulator (LDO) for detailed description.

[0040] It should be noted that LDO is a linear regulator with a low voltage difference between input and output voltage Vout. There are two basic forms of linear regulators: series regulator and shunt regulator. LDO is a series regulator, which is located between the power supply and the load. It adjusts the resistance of the variable resistor according to the change of input voltage Vin or output current to keep the output voltage Vout stable. When the LDO output is fixed, as long as its supply voltage is greater than the voltage difference voltage of its output value, stable power supply can be achieved.

[0041] Specifically, for example, if the LDO output voltage Vout is 3.3V, assuming that its voltage difference is 50mV, then its supply voltage only needs to be greater than 3.35V for the LDO to work properly, that is, the BOOST circuit output voltage Vout is greater than 3.35V, and the LDO can work properly. If the device withstands a voltage of 5V, the LDO input voltage Vin ranges from 3.35 to 5V, which is equivalent to the BOOST circuit output voltage Vout range. In order for the LDO to obtain the highest conversion efficiency, the voltage difference between its input voltage Vin and output voltage Vout should be as small as possible, that is, the output voltage Vout of the BOOST circuit is optimally 3.35V, so the BOOST circuit output voltage preset value Vs is set to 3.35V. Assuming that in the application scenario, the power supply voltage of the BOOST circuit is 2.9~5V, and the minimum on-time limit is not considered, then when the power supply voltage of the BOOST circuit is 2.9~3.35V, the output voltage Vout of the BOOST circuit can be boosted to 3.35V. When the power supply voltage of the BOOST circuit is greater than 3.35V, the BOOST circuit cannot work normally, which causes the subsequent LDO to fail to work normally, that is, the input voltage Vin range is 2.9~3.35V when the BOOST circuit works normally. However, in fact, when the LDO input voltage Vin range is 3.35~5V, it can also work normally. Therefore, the traditional BOOST architecture limits the input voltage Vin range and limits the application scenarios.

[0042] Since the traditional BOOST architecture can only achieve boost output, it cannot work properly when the input voltage Vin is greater than the output voltage Vout, thus limiting its input voltage Vin range and limiting its application scenarios. Based on this, additional buck function can be achieved by superimposing a freewheeling tube on the traditional BOOST architecture. Figure 2 is a schematic diagram of an exemplary voltage adjustment circuit structure, such as Figure 2 As shown, in the voltage regulating circuit, a second transistor HS1 is added to the voltage regulating sub-circuit 7 to achieve a voltage reduction function.

[0043] Specifically, Figure 2 As shown, in the voltage regulating subcircuit 7 in the voltage regulating circuit, a second transistor HS1 is superimposed on the original second transistor HS1. For ease of description and understanding, the superimposed second transistor HS1 is referred to as superimposed transistor HS2 below to distinguish it from the original second transistor HS1. Figure 2 The voltage regulation circuit shown is compared with the Figure 1 The voltage regulation circuit shown in the figure is different only in that there is an additional superposition transistor HS2. Figure 2In the voltage regulation circuit shown, the voltage regulation subcircuit 7 includes an inductor L, a first transistor LS, a superimposed transistor HS2, a second transistor HS1 and a load capacitor Cout; the first end of the inductor L is electrically connected to the input voltage Vin end, the second end of the inductor L is electrically connected to the first end of the first transistor LS and the first end of the superimposed transistor HS2, the second end of the first transistor LS is electrically connected to the second reference voltage end, the control end of the first transistor LS is electrically connected to the driving subcircuit 6, the second end of the superimposed transistor HS2 is electrically connected to the first end of the second transistor HS1, the control end of the superimposed transistor HS2 is electrically connected to the bias voltage Vbias end, the second end of the second transistor HS1 is electrically connected to the first end of the load capacitor Cout, and the control end of the second transistor HS1 is electrically connected to the driving subcircuit 6. Among them, the control end of the superimposed transistor HS2 is connected to the bias voltage Vbias. Taking the superimposed transistor HS2 as a P-type transistor as an example, when its gate-source voltage is fixed, its on-current is fixed, which can also be understood as the on-impedance of the superimposed transistor HS2 is fixed. In this case, the superimposed transistor HS2 is not fully turned on after being connected to the fixed bias voltage Vbias, and is equivalent to an active resistor. When a fixed current flows through the active resistor, a voltage drop can be formed. In this voltage adjustment circuit, when the input voltage Vin is higher than the output voltage setting value Vs, the node LX is selected for observation. In fact, the voltage Vlx of the node LX is equal to the output voltage Vout plus the voltage drop of the active resistor equivalent to the superimposed transistor HS2, and the voltage drop of the second transistor HS1 in the fully turned-on state. From the outside of the BOOST circuit, it can be achieved that when the input voltage Vin is greater than the output voltage preset value Vs, the circuit can still work normally.

[0044] like Figure 2 Although the voltage adjustment circuit shown in the figure can realize normal operation when the input voltage Vin is greater than the preset output voltage Vs, the introduction of the superimposed transistor HS2 is equivalent to the introduction of a resistor, which introduces a fixed loss. Therefore, the voltage drop mode will cause a large voltage difference between the input voltage Vin and the output voltage Vout, which ultimately leads to a low overall conversion efficiency of the circuit. Specifically, the electric power P = I 2 R, electrical work W (or electrical energy consumed) is W = I 2 RT, now there is an extra resistor in the circuit, it will have a heat loss, and the resistor will lose a part of the power consumption, which cannot be avoided in this circuit structure. Therefore, the second transistor HS1 (freewheeling tube) is superimposed to achieve voltage reduction so that the BOOST circuit can output normally. Although it can achieve normal operation when the input voltage Vin is greater than the preset output voltage Vs, the input voltage Vin range is widened, but there is a fixed loss, which reduces the conversion efficiency.

[0045] In view of this, the embodiment of the present disclosure provides a voltage adjustment circuit, which adds a bypass (BYPASS) mode control on the basis of the traditional BOOST architecture. Under the premise of not adding additional electronic components at the topological level, it can achieve that when the circuit input voltage Vin is close to the output voltage preset value Vs, and the input voltage Vin is greater than the output voltage preset value Vs, the output voltage Vout can follow the input voltage Vin to change, thereby widening the circuit input voltage Vin working range, so that it can be applied to more application scenarios; at the same time, compared with the conventional topological structure of BOOST step-down (for example, Figure 2 The voltage adjustment circuit shown in the figure has the advantages of lower voltage difference between the output voltage Vout and the input voltage Vin and higher circuit conversion efficiency; in addition, the voltage adjustment circuit provided by the embodiment of the present disclosure has simple control, low detection complexity and higher reliability.

[0046] It should be noted that the voltage adjustment circuit mentioned in the embodiments of the present disclosure may be various topology circuits of a switching power supply. For ease of description and understanding, the voltage adjustment circuit in the present disclosure is specifically described using a BOOST circuit as an example.

[0047] In the first aspect, the technical solution adopted to solve the above technical problem is a voltage adjustment circuit. Figure 3 A schematic diagram of a voltage adjustment circuit structure provided by an embodiment of the present disclosure is shown in FIG. Figure 3As shown, the voltage adjustment circuit includes: a first sampling circuit 1, a first operation subcircuit 2, a second sampling circuit 4, a second operation subcircuit 5, a logic control module 3, a driving subcircuit 6 and a voltage regulation subcircuit 7; wherein the first sampling circuit 1 is configured to sample the output voltage Vout to generate a first feedback voltage Vfb_vout, and output the first feedback voltage Vfb_vout to the first operation subcircuit 2; the first operation subcircuit 2 is configured to compare the first feedback voltage Vfb_vout with the reference voltage Vref, obtain a first comparison result through comparison, generate a first control signal K1 according to the first comparison result and a preset algorithm, and output the first control signal K1 to the logic control module 3; the second sampling circuit 4 is configured to sample the input voltage Vin to generate a second feedback voltage Vfb_vin, and output the second feedback voltage Vfb_vin to the second operation subcircuit 5; the second operation subcircuit 5 is configured to compare the second feedback voltage Vfb_vin with the reference voltage Vref, and obtain a first comparison result through comparison, generate a first control signal K1 according to the first comparison result and a preset algorithm, and output the first control signal K1 to the logic control module 3; The logic control module 3 is configured to determine whether the working mode of the voltage adjustment subcircuit is the first working mode or the second working mode according to the second control signal K2 input by the second operation subcircuit 5. The logic control module 3 is configured to output a third control signal generated by logic operation according to the first control signal K1 and the clock signal CLK in the first working mode, and output the third control signal to the driving subcircuit 6. In the second working mode, the logic control module 3 is configured to output a fourth control signal generated by logic operation according to the second control signal K2, and output the fourth control signal to the driving subcircuit 6; the driving subcircuit 6 is configured to generate a first driving signal according to the third control signal, or to generate a second driving signal according to the fourth control signal, so as to drive the voltage regulation subcircuit 7; the voltage regulation subcircuit 7 is configured to adjust the input voltage Vin according to the first driving signal or the second driving signal to generate the output voltage Vout.

[0048] Specifically, Figure 3 As shown, the voltage adjustment circuit provided by the embodiment of the present disclosure is structurally different from the above-mentioned Figure 1 and Figure 2 The voltage regulation circuit shown mainly adds a second sampling circuit 4 and a second operator circuit 5, and the logic control module 3 adds a working mode recognition function. The first working mode is actually a boost mode when the BOOST circuit works normally. The second working mode can also be called a bypass mode. In the bypass mode, the output voltage Vout changes with the input voltage Vin, so that the normal operation of the circuit can be achieved when the input voltage Vin is greater than the preset output voltage value Vs.

[0049] Specifically, in the embodiment of the present disclosure, the first sampling circuit 1 samples the output voltage Vout, and the second sampling circuit 4 samples the input voltage Vin; the first sampling circuit 1 includes a first voltage-dividing resistor RFB1 and a second voltage-dividing resistor RFB2; the first end of the first voltage-dividing resistor RFB1 is electrically connected to the output voltage Vout end, the second end of the first voltage-dividing resistor RFB1 and the first end of the second voltage-dividing resistor RFB2 and the second end of the first operation sub-circuit 2 are all electrically connected, and the second end of the second voltage-dividing resistor RFB2 is electrically connected to the first reference voltage end; and / or, the second sampling circuit 4 includes a third voltage-dividing resistor RFB3 and a fourth voltage-dividing resistor RFB4; the first end of the third voltage-dividing resistor RFB3 is electrically connected to the input voltage Vin end, the second end of the third voltage-dividing resistor RFB3 and the first end of the fourth voltage-dividing resistor RFB4 and the second end of the second operation sub-circuit 5 are all electrically connected, and the second end of the fourth voltage-dividing resistor RFB4 is electrically connected to the first reference voltage end.

[0050] Among them, after the circuit loop is established and works normally, the output voltage setting value Vs satisfies the following formula:

[0051]

[0052] Therefore, after the output voltage setting value Vs is fixed, if the first feedback voltage Vfb_vout is equal to the reference voltage Vref, it means that the output voltage Vout reaches the setting value. It can be seen that the relationship between the circuit output voltage Vout and the output voltage setting value Vs can be confirmed by comparing the first feedback voltage Vfb_vout with the reference voltage Vref.

[0053] Similarly, the second sampling circuit 4 in the embodiment of the present disclosure samples the input voltage Vin, and the second feedback voltage Vfb_vin can reflect the magnitude of the input voltage Vin, and when the input voltage Vin is equal to the output voltage setting value Vs, the second feedback voltage Vfb_vin is equal to the reference voltage Vref. It can be seen that the second sampling circuit 4 can sample the input voltage Vin to determine the magnitude of the input voltage Vin and the output voltage preset value Vs, and then determine the working mode of the voltage adjustment circuit.

[0054] For example, in the embodiment of the present disclosure, the resistance values ​​of the first sampling resistor and the second sampling resistor are the same, then

[0055] Vs=2Vref

[0056] Assuming that the output voltage setting value Vs is 3.6v, then the reference voltage Vref is 1.8v. Therefore, it is not difficult to judge that when the second feedback voltage Vfb_vin collected by the second sampling circuit 4 is greater than 1.8v, the input voltage Vin is greater than the output voltage setting value Vs, and the circuit cannot work normally at this time. The logic control module 3 will judge that the circuit enters the second working mode, and the input voltage Vin will change with the output voltage Vout, thereby ensuring the normal operation of the circuit.

[0057] In the embodiment of the present disclosure, when the second feedback voltage Vfb_vin collected by the second sampling circuit 4 is less than the reference voltage Vref, the logic control module 3 can determine that the input voltage Vin of the circuit is less than the preset output voltage value Vs, and the system is in the first working mode, that is, the BOOST boost mode; when the second feedback voltage Vfb_vin collected by the second sampling circuit 4 is equal to the reference voltage Vref, the logic control module 3 can determine that the input voltage Vin of the circuit is equal to the preset output voltage value Vs, and the system is in a critical state; when the second feedback voltage Vfb_vin collected by the second sampling circuit 4 is greater than the reference voltage Vref, the logic control module 3 can determine that the input voltage Vin of the circuit is greater than the preset output voltage value Vs, and the system is in the second working mode, that is, the bypass mode, and the output voltage Vout changes with the input voltage Vin, and the system can still work normally.

[0058] Preferably, in some embodiments, when the first sampling circuit 1 includes a first voltage-dividing resistor RFB1 and a second voltage-dividing resistor RFB2, and the second sampling circuit 4 includes a third voltage-dividing resistor RFB3 and a fourth voltage-dividing resistor RFB4, the ratio of the first voltage-dividing resistor RFB1 to the second voltage-dividing resistor RFB2 is M1, and the ratio of the third voltage-dividing resistor RFB3 to the fourth voltage-dividing resistor RFB4 is M2, and M1=M2. At this time, the input voltage Vin is sampled with resistors of the same proportion, and its sampled feedback voltage, the second feedback voltage Vfb_vin, can reflect the magnitude of the input voltage Vin, and when the input voltage Vin is equal to the output voltage setting value Vs, the second feedback voltage Vfb_vin is equal to the reference voltage Vref. In other words, the input voltage Vin and the output voltage Vout can be sampled respectively by using resistors of the same resistance ratio, so as to determine the magnitude of the input voltage Vin and the output voltage preset value Vs, and then determine which working mode the voltage adjustment circuit is in. In this embodiment, since the input voltage Vin and the output voltage Vout adopt exactly the same resistance sampling method, the design difficulty of the layout can be reduced, and it is easier to match the layout, which can have a higher suppression ability for process deviation and improve sampling reliability.

[0059] In some embodiments, the ratio M1 of the first voltage-dividing resistor RFB1 and the second voltage-dividing resistor RFB2 and the ratio M2 of the third voltage-dividing resistor RFB3 and the fourth voltage-dividing resistor RFB4 both match the code value. Specifically, when the ratio M1 of the first voltage-dividing resistor RFB1 and the second voltage-dividing resistor RFB2 and the ratio M2 of the third voltage-dividing resistor RFB3 and the fourth voltage-dividing resistor RFB4 are equal, that is, when M1=M2, the values ​​of M1 and M2 can change and can match the code value. For example, when M1=M2=1, the output voltage preset value Vs is twice the reference voltage Vref, and when M1=M2=2, the output voltage preset value Vs is three times the reference voltage Vref, thereby changing the output voltage preset value Vs, thereby changing the range of the output voltage Vout, and then realizing the voltage regulation function of the output voltage Vout. For example, the range of the output voltage Vout can be 3.6~5v, and the voltage can be adjusted in steps of 100mv. At this time, the voltage-dividing resistors of the first sampling circuit 1 and the second sampling circuit 4 can be matched with the voltage adjustment, and the voltage adjustment function of the output voltage Vout can be realized by changing the values ​​of M1 and M2. For example, when the code value output is 00, M1=M2=1, and when the code value output is 01, M1=M2=2. In this way, the preset value of the output voltage Vout can be changed, so that the circuit can adapt to a changing output range. Further, the change in the ratio of the voltage-dividing resistor can be controlled by the control signal of the output voltage Vout. For example, the output voltage Vout defaults to 3.6v. When the output voltage Vout needs to be adjusted to 3.7v, the code value can be changed from the original 00 to 01, and the resistance ratio of the corresponding voltage-dividing resistor is matched to realize the synchronous change process.

[0060] Furthermore, in the embodiment of the present disclosure, the logic control module 3 includes a pattern recognition sub-circuit and a logic control sub-circuit; the pattern recognition sub-circuit is configured to determine whether the operating mode of the voltage adjustment circuit is the first operating mode or the second operating mode according to the second control signal K2; the logic control sub-circuit is configured to output the third control signal or the fourth control signal to the driving sub-circuit 6 according to the recognition result of the pattern recognition sub-circuit.

[0061] Specifically, the logic control module 3 in the disclosed embodiment includes a mode recognition subcircuit and a logic control subcircuit; wherein, the mode recognition subcircuit can determine the working mode of the circuit according to the second control signal K2 generated by the second comparison result after the second operation subcircuit 5 compares the second feedback voltage Vfb_vin with the reference voltage Vref. The logic control subcircuit can output the third control signal or the fourth control signal after the logic operation to the driving subcircuit 6 according to the recognition result of the mode recognition subcircuit, the third control signal is a signal when the control circuit works in the BOOST normal boost mode, and the fourth control signal is a signal when the control circuit works in the bypass mode, that is, the output voltage Vout follows the input voltage Vin.

[0062] It should be noted that the voltage adjustment circuit provided by the present disclosure can be applied to a variety of control methods, such as several basic types such as pulse width modulation (PWM) and pulse frequency modulation (PFM) commonly used in switching power supplies. The main modulation method of pulse width modulation is: keep the switching frequency unchanged, change the duty cycle by adjusting the width of the pulse signal, thereby adjusting the on-time of the MOS tube and adjusting the output voltage Vout. PWM modulation mainly keeps the frequency unchanged and adjusts the pulse width. On the contrary, PFM modulation mainly keeps the pulse width unchanged, that is, fixes the time when the MOS tube is turned on or off, and changes the duty cycle by adjusting the frequency of the control signal. It is a variable frequency control method. Below, the present disclosure specifically describes the voltage adjustment circuit under PWM modulation and the voltage adjustment circuit under PFM modulation.

[0063] like Figure 3 As shown, the embodiment of the present disclosure is a voltage adjustment circuit under PWM modulation, which includes: a first sampling circuit 1, a first operation sub-circuit 2, a second sampling circuit 4, a second operation sub-circuit 5, a logic control module 3, a driving sub-circuit 6 and a voltage adjustment sub-circuit; wherein, the first sampling circuit 1 includes a first voltage-dividing resistor RFB1 and a second voltage-dividing resistor RFB2, the second sampling circuit 4 includes a third voltage-dividing resistor RFB3 and a fourth voltage-dividing resistor RFB4, the first operation sub-circuit 2 includes an error amplifier EA and a first comparator CMP1, the second operation sub-circuit 5 includes a bypass comparator CMP3, and the voltage adjustment sub-circuit 7 includes an inductor L, a first transistor LS, a second transistor HS1 and a load capacitor Cout.

[0064] Specifically, the first end of the first voltage-dividing resistor RFB1 is electrically connected to the output voltage Vout end, the second end of the first voltage-dividing resistor RFB1, the first end of the second voltage-dividing resistor RFB2, and the in-phase input end of the error amplifier EA are all electrically connected, the second end of the second voltage-dividing resistor RFB2 is electrically connected to the first reference voltage end, the first end of the third voltage-dividing resistor RFB3 is electrically connected to the input voltage Vin end, the second end of the third voltage-dividing resistor RFB3, the first end of the fourth voltage-dividing resistor RFB4, and the inverting input end of the bypass comparator CMP3 are all electrically connected, and the second end of the fourth voltage-dividing resistor RFB4 is electrically connected to the first reference voltage end; the inverting input end of the error amplifier EA is electrically connected to the reference voltage Vref end, and the output end of the error amplifier EA is electrically connected to the inverting input end of the first comparator CMP1 The inverting input terminal and the non-inverting input terminal of the first comparator CMP1 are configured to receive the sawtooth wave signal STW, and the output terminal of the first comparator CMP1 is electrically connected to the logic control module 3; the non-inverting input terminal of the bypass comparator CMP3 is electrically connected to the reference voltage Vref terminal, and the output terminal of the bypass comparator CMP3 is electrically connected to the logic control module 3; the first end of the inductor L is electrically connected to the input voltage Vin terminal, the second end of the inductor L is electrically connected to the first end of the first transistor LS and the first end of the second transistor HS1, the second end of the first transistor LS is electrically connected to the second reference voltage terminal, the control end of the first transistor LS is electrically connected to the driving sub-circuit 6, the second end of the second transistor HS1 is electrically connected to the first end of the load capacitor Cout, and the control end of the second transistor HS1 is electrically connected to the driving sub-circuit 6.

[0065] It should be noted that the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and drain. In order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. According to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the first electrode is the source of the P-type transistor, the second electrode is the drain of the P-type transistor, and the source and drain are turned on when a low-level signal is input to the gate; when an N-type transistor is used, the first electrode is the drain of the N-type transistor, the second electrode is the source of the N-type transistor, and the source and drain are turned on when a high-level signal is input to the gate. In the embodiment of the present disclosure, the first transistor LS is an N-type transistor, and the second transistor HS1 is a P-type transistor as an example for specific description.

[0066] Specifically, the error amplifier EA compares the first feedback voltage Vfb_vout with the reference voltage Vref, and outputs an error amplified voltage. The error amplified voltage is used as a modulation signal of the first comparator CMP1 (PWM comparator) and is input to the inverting input terminal of the first comparator CMP1. At this time, the sawtooth wave signal STW is input to the non-inverting input terminal of the first comparator CMP1, where the sawtooth wave signal STW can be generated by an oscillator; the output terminal of the first comparator CMP1 outputs the first control signal K1, where the first control signal K1 is actually a pulse wave signal with a certain duty cycle to control the switching power supply circuit to operate in a desired state. The bypass comparator CMP3 compares the reference voltage Vref and the second feedback voltage Vfb_vin, and outputs a second control signal K2. When the second feedback voltage Vfb_vin is less than the reference voltage Vref, the bypass comparator CMP3 outputs a high level, and the voltage adjustment circuit works in the normal BOOST mode. When the second feedback voltage Vfb_vin is greater than the reference voltage Vref, the bypass comparator CMP3 outputs a low level, and the voltage adjustment circuit works in the bypass mode, and the output voltage Vout changes with the input voltage Vin.

[0067] Specifically, when the logic control module 3 recognizes the high-level signal output by the bypass comparator CMP3, it outputs the third control signal generated by the logic operation according to the first control signal K1 and the clock signal CLK to drive the driving sub-circuit 6, and the driving sub-circuit 6 outputs the first driving signal capable of driving the first transistor LS and the second transistor HS1; when the logic control module 3 recognizes the low-level signal output by the bypass comparator CMP3, it shields the first control signal K1 and the clock signal CLK, and outputs the fourth control signal generated by the logic operation according to the second control signal K2 to drive the driving sub-circuit 6, and the driving sub-circuit 6 outputs the second driving signal to keep the first transistor LS in the off state and the second transistor HS1 in the fully on state. In this working mode, there is no switching cycle, and the output voltage Vout changes with the input voltage Vin.

[0068] Figure 4 for Figure 3 The waveform diagram of the mode switching of the medium voltage regulation circuit is as follows: Figure 4 As shown, the three time periods t0~t1, t1~t2, and t2~t3 are used for explanation:

[0069] Time period t0~t1: the input voltage Vin is less than the preset output voltage Vs, and the second control signal K2 output by the bypass comparator CMP3 is at a high level. At this time, the system is in the BOOST working mode, and part of the input energy is stored in the inductor L. Then, the energy is transmitted to the output end through the conduction and shutdown of the first transistor LS, thereby realizing voltage conversion.

[0070] In some embodiments, the third control signal includes a first control sub-signal K31 and a second control sub-signal K32, and the driving sub-circuit 6 includes a first driving sub-circuit 61 and a second driving sub-circuit 62, that is, the logic control module 3 outputs two control signals, the first control sub-signal K31 is input to the first driving sub-circuit 61, so that the first driving sub-circuit 61 generates a first driving sub-signal, and the first driving sub-signal drives the first transistor LS; the second control sub-signal K32 is input to the second driving sub-circuit 62, so that the second driving sub-circuit 62 generates a second driving sub-signal, and the second driving sub-signal drives the second transistor HS1. In this way, the first transistor LS and the second transistor HS1 can be driven separately without affecting each other.

[0071] In some embodiments, the first control sub-signal K31 and the second control sub-signal K32 are dead zone complementary signals. Figure 4 As shown, since the first transistor LS is a P-type transistor and the second transistor HS1 is an N-type transistor, the two are reversely controlled. When the first control sub-signal K31 is in the process of falling and the second control sub-signal K32 is in the process of rising, an overlap is generated, and a direct path is generated from the output voltage Vout to the ground. Therefore, a dead time period needs to be added to avoid the first transistor LS and the second transistor HS1 being turned on at the same time. For example, when the first transistor LS is completely turned off, the second transistor HS1 is turned on, thereby ensuring that the first transistor LS and the second transistor HS1 have a staggered control, and avoiding that the output voltage Vout has a direct path to the ground.

[0072] In some embodiments, since the rising edge of the first control sub-signal K31 for controlling the conduction of the first transistor LS is actually determined by the clock signal CLK, that is, the clock signal CLK determines the generation time of a high level of the first transistor LS, the duty cycle of the conduction of the first transistor LS can be adjusted according to the loop working condition, thereby achieving the adjustment of the output voltage Vout.

[0073] Time t1: At this time, the input voltage Vin is equal to the output voltage Vout, and the logic control module 3 recognizes that the second control signal K2 is flipped to a low level. At this time, the clock signal CLK and the first control signal K1 are shielded, the second control signal K2 is received, and the fourth control signal after the logic operation is output. At this time, the first transistor LS remains in the off state, the second transistor HS1 remains in the on state, and the system enters the bypass working mode.

[0074] Time period t1-t2: At this time, the system is in bypass working mode, and the output voltage Vout changes with the input voltage Vin. It can be seen that if the input voltage Vin continues to rise, the output voltage Vout follows and keeps rising, if the input voltage Vin continues to drop, the output voltage Vout follows and keeps falling, and if the input voltage Vin remains unchanged, the output voltage Vout follows and keeps unchanged. At this time, the first transistor LS remains in a fixed off state, and the second transistor HS1 remains in a fixed on state.

[0075] At time t2: At this time, the input voltage Vin is less than the preset output voltage value Vs, and the logic control module 3 recognizes that the second control signal K2 is flipped to a high level. At this time, the bypass working mode is exited and returned to the BOOST boost mode. At this moment, the second transistor HS1 is immediately turned off, and the first transistor LS remains turned off, canceling the shielding of the clock signal CLK and the first control signal K1.

[0076] In some embodiments, when switching from BOOST mode to bypass mode, the preset values ​​of input voltage Vin and output voltage Vout are equal or the input voltage Vin is less than the difference between the preset value of output voltage Vout and the first hysteresis voltage; when switching from bypass mode to BOOST mode, the preset values ​​of input voltage Vin and output voltage Vout are equal or the input voltage Vin is less than the difference between the preset value of output voltage Vout and the second hysteresis voltage; wherein the value of the first hysteresis voltage is less than the value of the second hysteresis voltage. This setting can prevent the system from frequent jittering when switching between BOOST mode and bypass mode. Figure 4 As shown, when the system switches from bypass mode to BOOST mode (i.e., time t2), the input voltage Vin drops to a lower value than when the system switches from BOOST mode to bypass mode (i.e., time t1), and the system operating mode is reversed at this time. For example, when the output voltage preset value Vs is 3.6v, the default input voltage Vin reaches 3.55v to switch from BOOST mode to bypass mode, that is, the first hysteresis voltage is 50mv, but when exiting the bypass mode, in order to prevent frequent jitter of the system under critical state, the input voltage Vin needs to be reduced to a lower level, for example, when it drops to 3v, the system can switch from bypass mode to BOOST mode, that is, the second hysteresis voltage is 600mv. It can be seen that when the system enters the bypass mode and exits the bypass mode, the input voltage Vin differs by 550mv, that is, the final hysteresis voltage Voffset is 550mv.

[0077] It should be noted that, since the first hysteresis voltage is relatively small when the system switches from the BOOST mode to the bypass mode, it can be considered that when the input voltage Vin increases to the output voltage preset value Vs, the system can switch from the BOOST mode to the bypass mode. Figure 5 for Figure 3 Schematic diagram of hysteresis output in bypass mode of medium voltage regulation circuit, as shown in Figure 5 As shown, the horizontal axis indicates that the input voltage Vin gradually increases from 0. When the input voltage Vin increases to the preset output voltage value Vs, the logic control module 3 determines that the system enters the bypass working mode (i.e., the arrow is downward, and the second control signal K2 is at the falling edge). At this time, the output voltage Vout changes with the input voltage Vin; however, when the input voltage Vin gradually decreases and wants to exit the bypass mode and switch to the BOOST boost mode (i.e., the arrow is upward, and the second control signal K2 is at the rising edge), the input voltage Vin needs to drop to a lower level, that is, to have a difference in the final hysteresis voltage Voffset. This setting can avoid jitter when the system switches between the BOOST boost mode and the bypass mode, and maintain the stability of the system operation.

[0078] Time period t2-t3: At this time, the system is in BOOST mode. The state maintained at t2 triggers the first transistor LS to turn on at the first rising edge after the clock signal CLK is unshielded. Since the output voltage Vout is less than the preset value at this time, the system is in a dynamic response state, and the duty cycle of the first transistor LS increases; the output voltage Vout after adjustment may be greater than the preset value Vs of the output voltage. At this time, the duty cycle of the first transistor LS begins to decrease, and this adjustment state may last for several clock cycles. Finally, after the adjustment is completed, the output voltage Vout remains at the preset value, the input voltage Vin is less than the preset value at this time, and the first transistor LS and the second transistor HS1 are in a switching state.

[0079] In the voltage regulation circuit of the embodiment of the present disclosure, assuming that the resistance of the second transistor HS1 in the fully turned-on state is Ron1, in the bypass mode, the voltage difference between the input voltage Vin and the output voltage Vout is

[0080] Vout=Vin-(Iload×Ron1)

[0081] And as Figure 2 In the voltage regulation circuit shown in FIG. 1 using the superimposed second transistor HS1, the voltage difference between the input voltage Vin and the output voltage Vout is

[0082] Vout=Vin-(Iload×Req)-(Iload×Ron1)

[0083] Wherein, Req is the equivalent impedance of the superimposed transistor HS2, and Iload is the load current (ie, the output current).

[0084] Therefore, the voltage adjustment circuit of the embodiment of the present disclosure is better than the Figure 2 The step-down method shown in the figure reduces the voltage drop and loss caused by the fixed impedance. The voltage difference between the input voltage Vin and the output voltage Vout of the voltage adjustment circuit in the embodiment of the present disclosure is lower, which can achieve more efficient energy conversion. In addition, the bypass comparator CMP3 is introduced in the embodiment of the present disclosure, and the working mode can be switched according to the second control signal K2 output by the bypass comparator CMP3. When the output of the second comparator CMP2 is a low level, the system enters the bypass state, shields the clock signal CLK, and the first transistor LS remains in the off state. The second transistor HS1 remains in the fully on state, which is equivalent to the second transistor HS1 becoming a wire with a very small on-resistance. Then the output voltage Vout will change with the input voltage Vin. The advantage of this is that when the input voltage Vin is greater than the preset output voltage value Vs, the output range can still be changed. For example, in the application scenario, the output voltage Vout needs to be between 3.6 and 5v, the preset output voltage value Vs is 3.6v, and the input range of the input voltage Vin is a range of 2.9 to 5v. At this time, if the following is adopted Figure 1 The voltage adjustment circuit shown in the figure cannot output the output voltage Vout normally when the output voltage Vout is 4V, and the system is in a chaotic state. However, after adopting the voltage adjustment circuit of the embodiment of the present disclosure, the normal output of the system can be achieved, which is equivalent to widening the range of the input voltage Vin. In the embodiment of the present disclosure, the voltage adjustment circuit does not have a switching cycle in the bypass mode, and the input voltage Vin directly supplies power to the output voltage Vout, thereby expanding the range of the input voltage Vin and increasing the application scenarios of the system.

[0085] The above is the specific working process of the voltage regulating circuit under PWM modulation in the embodiment of the present disclosure. However, the control method of the voltage regulating circuit of the present disclosure is not limited to this, and it can also operate normally under PFM modulation. Figure 6 Another schematic diagram of a voltage adjustment circuit structure provided by an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the voltage regulation circuit is similar to Figure 3 The voltage adjustment circuit shown has no difference when operating in the bypass mode, but has a difference in the BOOS boost mode in that the first operation subcircuit 2 includes a second comparator CMP2, a non-inverting input terminal of the second comparator CMP2 is electrically connected to the first sampling circuit 1, an inverting input terminal of the second comparator CMP2 is electrically connected to the reference voltage Vref terminal, and an output terminal of the second comparator CMP2 is electrically connected to the logic control module 3.

[0086] Specifically, Figure 6 As shown, the in-phase input terminal of the second comparator CMP2 is electrically connected to the first end of the second voltage-dividing resistor RFB2, the inverting input terminal of the second comparator CMP2 is electrically connected to the reference voltage Vref terminal, and the output terminal of the second comparator CMP2 is electrically connected to the logic control module 3. The logic control module 3 outputs a third control signal for driving the driving sub-circuit 6 according to the comparison result between the clock signal CLK and the output of the second comparator CMP2. When the first feedback voltage Vfb_vout and the reference voltage Vref are compared by the second comparator CMP2, when the first feedback voltage Vfb_vout is less than the reference voltage Vref, it means that the output voltage Vout is less than the preset value, and the second comparator CMP2 outputs a high level. At this time, the conduction and shutoff of the first transistor LS completely depend on the fixed clock signal CLK. For example, the clock signal CLK can be a fixed clock signal CLK with a duty cycle of 50%. As the output voltage Vout gradually increases, when the first feedback voltage Vfb_vout touches the reference voltage Vref, the output of the second comparator CMP2 is low level, and the output after the logic operation in the logic control module 3 together with the fixed clock signal CLK is always low level. In this stage, the first transistor LS remains off, and the circuit charges the load capacitor Cout, so that the output voltage Vout decreases. This is repeated to achieve the effect of making the output voltage Vout constant.

[0087] It should be noted that the voltage adjustment circuit under the above PFM modulation is only a simple modulation method, and the present disclosure does not impose any limitation on this, as long as the normal BOOST voltage increase of the system can be achieved.

[0088] In the second aspect, the embodiments of the present disclosure further provide an electronic device, which includes the voltage regulating circuit of any one of the above embodiments. The electronic device provided by the embodiments of the present disclosure may be a wearable device, such as a watch. Of course, it can also be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a car display, etc. Among them, the electronic device mainly includes a battery, a load and the voltage regulating circuit provided by any of the above embodiments, and the voltage regulating circuit is connected to the battery and the load respectively. The voltage regulating circuit can receive the battery voltage provided by the battery, convert the battery voltage into the working voltage of the load, and then output it to the load.

[0089] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A voltage regulating circuit, characterized in that: include: A first sampling circuit is configured to sample the output voltage to generate a first feedback voltage, and output the first feedback voltage to a first operation sub-circuit; a first operation subcircuit, configured to compare the first feedback voltage with a reference voltage, obtain a first comparison result through comparison, generate a first control signal according to the first comparison result and a preset algorithm, and output the first control signal to a logic control module; A second sampling circuit is configured to sample the input voltage to generate a second feedback voltage, and output the second feedback voltage to a second operation sub-circuit; a second operation subcircuit, configured to compare the second feedback voltage with a reference voltage, obtain a second comparison result through comparison, generate a second control signal according to the second comparison result, and output the second control signal to a logic control module; a logic control module, configured to determine a first working mode or a second working mode according to the second control signal, configured to output a third control signal generated by a logic operation according to the first control signal and a clock signal in the first working mode, and output the third control signal to the driving sub-circuit, and configured to output a fourth control signal generated by a logic operation according to the second control signal in the second working mode, and output the fourth control signal to the driving sub-circuit; a driving subcircuit, configured to generate a first driving signal according to the third control signal, or to generate a second driving signal according to the fourth control signal, so as to drive the voltage regulating subcircuit; The voltage regulating subcircuit is configured to regulate the input voltage according to the first driving signal or the second driving signal to generate the output voltage.

2. The voltage regulating circuit according to claim 1, characterized in that: The logic control module includes a pattern recognition subcircuit and a logic control subcircuit; the pattern recognition subcircuit is configured to determine whether the operating mode of the voltage adjustment circuit is the first operating mode or the second operating mode according to the second control signal; the logic control subcircuit is configured to output the third control signal or the fourth control signal to the driving subcircuit according to the recognition result of the pattern recognition subcircuit.

3. The voltage regulating circuit according to claim 1, characterized in that: The third control signal includes a first control sub-signal and a second control sub-signal, the driving sub-circuit includes a first driving sub-circuit and a second driving sub-circuit, and the first driving signal includes a first driving sub-signal and a second driving sub-signal; the first driving sub-circuit is configured to generate a first driving sub-signal according to the first control sub-signal, and the second driving sub-circuit is configured to generate a second driving sub-signal according to the second control sub-signal.

4. The voltage regulating circuit according to claim 3, characterized in that: The first control sub-signal and the second control sub-signal are dead zone complementary signals.

5. The voltage regulating circuit according to claim 1, characterized in that: The first sampling circuit includes a first voltage-dividing resistor and a second voltage-dividing resistor; the first end of the first voltage-dividing resistor is electrically connected to the output voltage end, the second end of the first voltage-dividing resistor is electrically connected to the first end of the second voltage-dividing resistor and the second end of the first operation subcircuit, and the second end of the second voltage-dividing resistor is electrically connected to the first reference voltage end; and / or, The second sampling circuit includes a third voltage-dividing resistor and a fourth voltage-dividing resistor; the first end of the third voltage-dividing resistor is electrically connected to the input voltage end, the second end of the third voltage-dividing resistor is electrically connected to the first end of the fourth voltage-dividing resistor and the second end of the second operation subcircuit, and the second end of the fourth voltage-dividing resistor is electrically connected to the first reference voltage end.

6. The voltage regulating circuit according to claim 5, characterized in that: When the first sampling circuit includes the first voltage-dividing resistor and the second voltage-dividing resistor, and the second sampling circuit includes the third voltage-dividing resistor and the fourth voltage-dividing resistor, the ratio of the first voltage-dividing resistor to the second voltage-dividing resistor is M1, the ratio of the third voltage-dividing resistor to the fourth voltage-dividing resistor is M2, and M1=M2.

7. The voltage regulating circuit according to claim 6, characterized in that: A ratio M1 of the first voltage-dividing resistor to the second voltage-dividing resistor and a ratio M2 of the third voltage-dividing resistor to the fourth voltage-dividing resistor both match the code value.

8. The voltage regulating circuit according to claim 1, characterized in that: The first operation subcircuit includes an error amplifier and a first comparator; the non-inverting input terminal of the error amplifier is electrically connected to the first sampling circuit, the inverting input terminal of the error amplifier is electrically connected to the reference voltage terminal, the output terminal of the error amplifier is electrically connected to the inverting input terminal of the first comparator, the non-inverting input terminal of the first comparator is configured to receive a sawtooth wave signal, and the output terminal of the first comparator is electrically connected to the logic control module.

9. The voltage regulating circuit according to claim 1, characterized in that: The first operation subcircuit includes a second comparator; the non-inverting input terminal of the second comparator is electrically connected to the first sampling circuit, the inverting input terminal of the second comparator is electrically connected to the reference voltage terminal, and the output terminal of the second comparator is electrically connected to the logic control module.

10. The voltage regulating circuit according to claim 1, characterized in that: The second operation subcircuit includes a bypass comparator; the non-inverting input terminal of the bypass comparator is electrically connected to the reference voltage terminal, the inverting input terminal of the bypass comparator is electrically connected to the second sampling circuit, and the output terminal of the bypass comparator is electrically connected to the logic control module.

11. The voltage regulating circuit according to claim 1, characterized in that: The voltage regulation subcircuit includes an inductor, a first transistor, a second transistor and a load capacitor; the first end of the inductor is electrically connected to the input voltage end, the second end of the inductor is electrically connected to the first end of the first transistor and the first end of the second transistor, the second end of the first transistor is electrically connected to the second reference voltage end, the control end of the first transistor is electrically connected to the drive subcircuit, the second end of the second transistor is electrically connected to the first end of the load capacitor, and the control end of the second transistor is electrically connected to the drive subcircuit.

12. An electronic device comprising the voltage regulating circuit according to any one of claims 1 to 11.

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