Low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation in all CMOS

Abstract

This disclosure provides a low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation in all-CMOS, which can be applied in the field of analog circuit technology. The voltage reference circuit includes: a startup circuit for starting the voltage reference circuit; a first input terminal of a current source circuit connected to the output terminal of the startup circuit, and a second input terminal of the current source circuit connected to the power supply voltage; the output terminal of the current source circuit connected to the input terminals of an active load circuit and a third-order temperature coefficient current generation circuit; wherein, the first expression of the output voltage V0 of the current source circuit is obtained based on the positive temperature coefficient current, where the current in the active load circuit represents the difference between the positive temperature coefficient current and the third-order temperature coefficient current; the second expression of the output voltage V0 of the current source circuit contains temperature-dependent polynomial coefficients, and the sum of the polynomial coefficients is 0, so as to obtain a temperature-independent output voltage V0 of the current source circuit.

Description

Technical Field

[0001] This disclosure relates to the field of analog circuits, and more particularly to a low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation in full CMOS. Background Technology

[0002] In analog circuits, voltage reference circuits are crucial devices that provide a reference voltage that remains constant regardless of temperature, power supply voltage, or manufacturing process. Their accuracy directly impacts the performance of the analog system.

[0003] In voltage reference circuits, the temperature coefficient is a crucial parameter. It measures the change in output reference voltage caused by variations in ambient temperature. Currently, voltage reference circuits typically employ first-order temperature compensation, achieving a temperature coefficient of only around 30 ppm / ℃. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation in full CMOS.

[0005] According to the first aspect of this disclosure, a low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation in full CMOS is provided, comprising: a startup circuit, a current source circuit, an active load circuit, and a third-order temperature coefficient current generation circuit.

[0006] The aforementioned startup circuit is used to start the aforementioned voltage reference circuit;

[0007] The first input terminal of the current source circuit is connected to the output terminal of the startup circuit, and the second input terminal of the current source circuit is connected to the power supply voltage. The current source circuit is used to generate a positive temperature coefficient current, and the power supply voltage is used to provide voltage to the current source circuit.

[0008] The output terminal of the aforementioned current source circuit is connected to the input terminal of the aforementioned active load circuit and the aforementioned third-order temperature coefficient current generating circuit. The aforementioned current source circuit and the aforementioned third-order temperature coefficient current generating circuit jointly provide the current in the aforementioned active load circuit, and the aforementioned third-order temperature coefficient current generating circuit is used to generate a third-order temperature coefficient current.

[0009] The first expression for the output voltage V0 of the current source circuit is obtained based on the positive temperature coefficient current. The current in the active load circuit represents the difference between the positive temperature coefficient current and the third-order temperature coefficient current.

[0010] The second expression for the output voltage V0 of the aforementioned current source circuit contains temperature-dependent polynomial coefficients, and the sum of these polynomial coefficients is 0, so as to obtain the temperature-independent output voltage V0 of the aforementioned current source circuit; wherein, the second expression for the output voltage V0 is obtained by substituting the expression for the positive temperature coefficient current and the expression for the third-order temperature coefficient current into the first expression for the output voltage V0 and performing a Taylor expansion.

[0011] According to embodiments of this disclosure, the startup circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first PMOS transistor;

[0012] The source of the first NMOS transistor is connected to the source of the second NMOS transistor and grounded, and the drain of the first NMOS transistor is connected to the gate of the third NMOS transistor and the source and drain of the fourth NMOS transistor.

[0013] The gate and drain of the second NMOS transistor are connected together and connected to the source of the third NMOS transistor.

[0014] The drain of the third NMOS transistor is connected to the drain of the first PMOS transistor.

[0015] The drain and source of the fourth NMOS transistor are connected, and the gate of the fourth NMOS transistor is connected to the gate and source of the first PMOS transistor.

[0016] The source and gate of the first PMOS transistor are connected.

[0017] According to embodiments of this disclosure, the current source circuit includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor;

[0018] The source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor. The drain of the eighth NMOS transistor is connected to the drain and gate of the eighth PMOS transistor and the drain of the third NMOS transistor. The gate of the eighth NMOS transistor is connected to the gate of the first NMOS transistor and the drain of the thirteenth PMOS transistor.

[0019] The gate and drain of the eighth PMOS transistor are connected, and the drain of the third NMOS transistor is also connected.

[0020] The source of the second PMOS transistor is connected to the source of the first PMOS transistor.

[0021] The source of the ninth NMOS transistor is connected to the drain of the fifth NMOS transistor and the source of the seventh NMOS transistor, and the gate of the ninth NMOS transistor is connected to the drain of the sixth NMOS transistor and the drain of the ninth PMOS transistor.

[0022] The source of the sixth NMOS transistor is grounded, the drain of the sixth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the gate of the sixth NMOS transistor is connected to the gate and drain of the seventh NMOS transistor.

[0023] The gate of the seventh NMOS transistor is connected to the drain and is connected to the drain of the tenth PMOS transistor. The source of the seventh NMOS transistor is connected to the drain of the fifth NMOS transistor.

[0024] The source of the fifth NMOS transistor is grounded, and the gate of the fifth NMOS transistor is connected to the gate and drain of the twelfth NMOS transistor. The fifth NMOS transistor is used to form an equivalent resistance.

[0025] The gate of the tenth NMOS transistor is connected to the drain and is connected to the drain of the twelfth PMOS transistor. The source of the tenth NMOS transistor is connected to the source of the twelfth NMOS transistor and the drain of the eleventh NMOS transistor.

[0026] The source of the eleventh NMOS transistor is grounded, and the gate of the eleventh NMOS transistor is connected to the gate of the tenth NMOS transistor.

[0027] The drain of the twelfth NMOS transistor is connected to its gate and is also connected to the drain of the eleventh PMOS transistor.

[0028] According to an embodiment of this disclosure, the common-source cascode current mirror includes the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, and the thirteenth PMOS transistor in the current source circuit, wherein the input terminal of the common-source cascode current mirror is connected to the power supply voltage;

[0029] The current source includes the third PMOS transistor, the fourth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor, wherein the current source is used to generate current I0;

[0030] The seventh and thirteenth PMOS transistors in the aforementioned common-source cascode current mirror amplify the current I0 by a factor of N to generate the positive temperature coefficient current. The second, third, fourth, fifth, sixth, eighth, ninth, tenth, eleventh, and twelfth PMOS transistors in the aforementioned common-source cascode current mirror have the same width-to-length ratio. The width-to-length ratio of the seventh and thirteenth PMOS transistors is N times the aforementioned parameter, where N is a natural number greater than 1.

[0031] The bias voltage generation circuit includes the aforementioned tenth NMOS transistor, the aforementioned eleventh NMOS transistor, and the aforementioned twelfth NMOS transistor.

[0032] According to embodiments of this disclosure, the above-mentioned active load circuit includes a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, and a sixteenth NMOS transistor;

[0033] The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, the source of the fourteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the source of the fifteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor, and the source of the sixteenth NMOS transistor is grounded.

[0034] The gates of the aforementioned thirteenth NMOS transistor, the aforementioned fourteenth NMOS transistor, the aforementioned fifteenth NMOS transistor, and the aforementioned sixteenth NMOS transistor are connected, and are also connected to the drain of the aforementioned thirteenth NMOS transistor.

[0035] The drain of the thirteenth NMOS transistor is connected to the drain of the thirteenth PMOS transistor and the gate of the eighth NMOS transistor.

[0036] According to an embodiment of this disclosure, the above-described third-order temperature coefficient current generating circuit includes a fourteenth PMOS transistor;

[0037] The source and gate of the fourteenth PMOS transistor are connected, and the gate of the thirteenth NMOS transistor is connected. The drain of the fourteenth PMOS transistor is grounded.

[0038] According to embodiments of this disclosure, the voltage reference circuit further includes a low-pass filter circuit;

[0039] The input terminal of the aforementioned low-pass filter circuit is connected to the output terminal of the aforementioned current source circuit. The aforementioned low-pass filter circuit is used to achieve a high power supply rejection ratio at high frequencies.

[0040] The aforementioned low-pass filter circuit includes a fifteenth PMOS transistor and a seventeenth NMOS transistor;

[0041] The source of the fifteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, and the gate of the fifteenth PMOS transistor is connected to the drain and to the gate of the seventeenth NMOS transistor. The fifteenth PMOS transistor is used to form a resistor.

[0042] The drain and source of the aforementioned seventeenth NMOS transistor are connected and grounded, and the aforementioned seventeenth NMOS transistor is used to form a capacitor.

[0043] According to an embodiment of this disclosure, the eighth NMOS transistor is used to form the first feedback branch;

[0044] The aforementioned second PMOS transistor, eighth PMOS transistor, and ninth NMOS transistor are used to form a second feedback branch, wherein the aforementioned first feedback branch, second feedback branch, and common-source cascode current mirror are used to achieve a high power supply rejection ratio at low frequencies.

[0045] According to embodiments of this disclosure, the transistors in the above-described active load circuit operate in the saturation region;

[0046] The fifth NMOS transistor in the aforementioned current source circuit operates in the deep linear region;

[0047] The other transistors in the aforementioned current source circuit operate in the subthreshold region;

[0048] The transistors in the aforementioned third-order temperature coefficient current generating circuit and the aforementioned low-pass filter circuit operate in the cutoff region.

[0049] According to an embodiment of this disclosure, the above-described startup circuit, used to start the above-described voltage reference circuit, includes:

[0050] When the first NMOS transistor is turned off, the voltage division of the first NMOS transistor is high, the gate of the third NMOS transistor is high, and the third NMOS transistor is turned on.

[0051] When the third NMOS transistor is turned on, a leakage current will be generated at the drain of the third NMOS transistor.

[0052] Based on the aforementioned leakage current, the gate voltage of the eighth PMOS transistor decreases, and the aforementioned voltage reference circuit is activated.

[0053] During the startup process of the voltage reference circuit, the first PMOS transistor is used to counteract the effect of the leakage current in the third NMOS transistor on the temperature coefficient of the voltage reference; the second NMOS transistor reduces the static current of the startup circuit by raising the source voltage of the third NMOS transistor, thereby reducing the effect of the static current on the temperature coefficient of the voltage reference.

[0054] According to the low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation provided in this disclosure, the first input terminal of the current source circuit is connected to the output terminal of the startup circuit, which can start the voltage reference circuit through the startup circuit. The second input terminal of the current source circuit is connected to the power supply voltage, which can provide voltage to the current source circuit. The output terminal of the current source circuit is connected to the input terminals of the active load circuit and the third-order temperature coefficient current generation circuit, so that the third-order temperature coefficient current generated by the third-order temperature coefficient current generation circuit and the positive temperature coefficient current generated by the current source circuit can compensate for the negative temperature characteristics of the threshold voltage in the active load circuit, thereby obtaining the temperature-independent output voltage V0 of the current source circuit, reducing the temperature coefficient, and realizing high-order temperature compensation. Attached Figure Description

[0055] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0056] Figure 1 A schematic diagram of a low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation according to an embodiment of the present disclosure is shown.

[0057] Figure 2 A schematic diagram of the structure of a startup circuit according to an embodiment of the present disclosure is shown.

[0058] Figure 3 A schematic diagram of the structure of a current source circuit according to an embodiment of the present disclosure is shown.

[0059] Figure 4 A schematic diagram of the structure of an active load circuit according to an embodiment of the present disclosure is shown.

[0060] Figure 5 A schematic diagram of a third-order temperature coefficient current generating circuit according to an embodiment of the present disclosure is shown.

[0061] Figure 6 A schematic cross-sectional view of a reverse diode composed of a PMOS transistor according to an embodiment of the present disclosure is shown.

[0062] Figure 7 A schematic diagram of a low-pass filter circuit according to an embodiment of the present disclosure is shown.

[0063] Figure 8 A schematic diagram illustrating the power supply rejection ratio as a function of frequency according to an embodiment of the present disclosure is shown.

[0064] Figure 9 The diagram illustrates the process of establishing a voltage reference with a low-pass filter after the improvement (circuit a) and the process of establishing a voltage reference with a low-pass filter before the improvement (circuit b) according to an embodiment of the present disclosure.

[0065] Figure 10 A circuit diagram of a low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation according to an embodiment of the present disclosure is shown schematically.

[0066] Figure 11 A schematic diagram illustrating the voltage variation with temperature generated by a voltage reference circuit according to an embodiment of the present disclosure is shown.

[0067] Figure 12 A small-signal model based on a cascode current mirror circuit according to an embodiment of the present disclosure is illustrated schematically.

[0068] Figure 13 A small-signal model of a conventional current mirror according to an embodiment of the present disclosure is illustrated schematically;

[0069] Figure 14 A small-signal model of a current source circuit according to an embodiment of the present disclosure is illustrated schematically;

[0070] Figure 15 The diagram schematically illustrates the voltage variation curves of a voltage reference under different power supply voltages according to embodiments of the present disclosure; and

[0071] Figure 16 The diagram illustrates the variation curve of the output reference voltage with the power supply voltage according to an embodiment of the present disclosure. Detailed Implementation

[0072] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0074] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0075] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0076] In implementing this disclosure, it was discovered that the accuracy of the voltage reference directly affects the performance of the analog system. The temperature coefficient is a crucial parameter of the voltage reference, measuring the magnitude of the change in the output reference voltage when the external temperature changes. Therefore, the smaller the temperature coefficient, the smaller the change in the output reference voltage when the external temperature changes. However, related technologies typically employ first-order temperature compensation methods, achieving a temperature coefficient as low as approximately 30 ppm / ℃, which is still relatively high. Consequently, the output reference voltage changes significantly when the external temperature changes.

[0077] Therefore, embodiments of this disclosure provide a low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation in full CMOS.

[0078] Figure 1 The schematic diagram illustrates a low-power voltage reference circuit structure with high power supply rejection ratio and high-order temperature compensation according to an embodiment of the present disclosure.

[0079] like Figure 1 As shown, the all-CMOS (Complementary Metal Oxide Semiconductor) high power supply rejection ratio high-order temperature compensation low-power voltage reference circuit 100 may include a startup circuit 110, a current source circuit 120, an active load circuit 130, and a third-order temperature coefficient current generation circuit 140.

[0080] Start-up circuit 110 is used to start the voltage reference circuit.

[0081] The first input terminal of the current source circuit 120 is connected to the output terminal of the startup circuit 110, and the second input terminal of the current source circuit 120 is connected to the power supply voltage VDD. The current source circuit 120 is used to generate a positive temperature coefficient current, and the power supply voltage VDD is used to provide voltage for the current source circuit 120.

[0082] The output terminal of the current source circuit 120 is connected to the input terminal of the active load circuit 130 and the third-order temperature coefficient current generating circuit 140. The current source circuit 120 and the third-order temperature coefficient current generating circuit 140 jointly provide the current in the active load circuit 130, and the third-order temperature coefficient current generating circuit 140 is used to generate the third-order temperature coefficient current.

[0083] The first expression for the output voltage V0 of the current source circuit 120 is obtained from the positive temperature coefficient current, where the current in the active load circuit can characterize the difference between the positive temperature coefficient current and the third-order temperature coefficient current.

[0084] The second expression for the output voltage V0 of the current source circuit 120 contains temperature-dependent polynomial coefficients, and the sum of the polynomial coefficients is 0, so as to obtain the output voltage V0 of the current source circuit that is independent of temperature; wherein, the second expression for the output voltage V0 is obtained by substituting the expression for the positive temperature coefficient current and the expression for the third-order temperature coefficient current into the first expression for the output voltage V0 and performing a Taylor expansion.

[0085] According to embodiments of this disclosure, the positive temperature coefficient current generated by the current source circuit 120 can be characterized by I1. The third-order temperature coefficient current generated by the third-order temperature coefficient current generating circuit 140 can be characterized by I2. The current in the active load circuit 130 can be characterized by I... ref .

[0086] According to embodiments of this disclosure, the current I in the active load circuit 130 ref It can be expressed as the following formula (1).

[0087]

[0088] Where C can represent the carrier mobility. ox This can represent the gate oxide capacitance per unit area. V can represent the width-to-length ratio of the NMOS transistor in the active load circuit 130. GS,130 This can represent the gate-source voltage (V) of the NMOS transistor in the active load circuit 130. TH,130 It can represent the threshold voltage of the NMOS transistor in the active load circuit 130.

[0089] According to embodiments of this disclosure, the current I in the active load circuit 130 refThis can characterize the difference between the positive temperature coefficient current I1 and the third-order temperature coefficient current I2. The current I in the active load circuit 130... ref It can be expressed as the following formula (2).

[0090] I ref =I1-I2 (2)

[0091] According to formulas (1) and (2), the first expression of the output voltage V0 of the current source circuit 120 can be expressed as formula (3) below.

[0092]

[0093] According to embodiments of this disclosure, the current source circuit 120 and the third-order temperature coefficient current generating circuit 140 jointly provide current in the active load circuit 130. The active load circuit 130 can determine the gate-source voltage V of the circuit based on the ambient temperature, the magnitude of the current in the circuit, and the circuit parameters. GS That is, the output voltage V0 of the current source circuit 120, wherein the circuit parameters may include carrier mobility, unit gate oxide capacitance and the width-to-length ratio of the NMOS transistor in the circuit.

[0094] According to an embodiment of this disclosure, the second expression for the output voltage V0 of the current source circuit 120 is obtained by substituting the expressions for the positive temperature coefficient current I1 and the third-order temperature coefficient current I2 into the first expression for the output voltage V0 and performing a Taylor expansion.

[0095] According to an embodiment of this disclosure, V0 is Taylor expanded at T0, considering only the first-order and second-order terms. The second expression for the output voltage V0 of the current source circuit 120 can be expressed as the following formula (4).

[0096]

[0097] Where A, B, α, and β can represent constants independent of temperature, V TH0,130 This can represent the initial threshold voltage of the NMOS transistor in the active load circuit 130.

[0098]

[0099]

[0100] According to embodiments of this disclosure, by setting C1+α=0 and C2+β=0, an output voltage V0 independent of temperature can be obtained.

[0101] According to an embodiment of this disclosure, the first input terminal of the current source circuit 120 is connected to the output terminal of the startup circuit 110, enabling the startup circuit 110 to start the voltage reference circuit. The second input terminal of the current source circuit 120 is connected to the power supply voltage, providing voltage to the current source circuit 120. The output terminal of the current source circuit 120 is connected to the input terminals of the active load circuit 130 and the third-order temperature coefficient current generation circuit 140, so that the third-order temperature coefficient current generated by the third-order temperature coefficient current generation circuit 140 and the positive temperature coefficient current generated by the current source circuit 120 can compensate for the negative temperature characteristics of the threshold voltage in the active load circuit 130, thereby obtaining a temperature-independent output voltage V0 of the current source circuit 120, reducing the temperature coefficient, and achieving high-order temperature compensation.

[0102] Figure 2 A schematic diagram of the structure of a startup circuit according to an embodiment of the present disclosure is shown.

[0103] like Figure 2 As shown, the startup circuit 110 may include a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first PMOS transistor.

[0104] According to embodiments of this disclosure, the first NMOS transistor can represent MS1, the second NMOS transistor can represent MS2, the third NMOS transistor can represent MS3, the fourth NMOS transistor can represent MC1, and the first PMOS transistor can represent MD2.

[0105] According to embodiments of this disclosure, the source of the first NMOS transistor is connected to the source of the second NMOS transistor and grounded; the drain of the first NMOS transistor is connected to the gate of the third NMOS transistor and the source and drain of the fourth NMOS transistor; the gate and drain of the second NMOS transistor are connected and connected to the source of the third NMOS transistor; the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor; the drain and source of the fourth NMOS transistor are connected, and the gate of the fourth NMOS transistor is connected to the gate and source of the first PMOS transistor; the source and gate of the first PMOS transistor are connected.

[0106] According to embodiments of this disclosure, the startup circuit can be used to start the voltage reference circuit, enabling the voltage reference circuit to operate normally.

[0107] According to embodiments of this disclosure, the startup circuit 110, used to start a voltage reference circuit, may include: when the first NMOS transistor is off, the voltage divider of the first NMOS transistor is high, the gate of the third NMOS transistor is high, and the third NMOS transistor is turned on; when the third NMOS transistor is on, a current is generated at the drain of the third NMOS transistor; based on the current generated at the drain of the third NMOS transistor, the gate voltage of the eighth PMOS transistor decreases, and the voltage reference circuit is started; during the startup process of the voltage reference circuit, the first PMOS transistor is used to counteract the influence of the leakage current in the third NMOS transistor on the temperature coefficient of the voltage reference; the second NMOS transistor reduces the quiescent current of the startup circuit by raising the source voltage of the third NMOS transistor, thereby reducing the influence of the quiescent current on the temperature coefficient of the voltage reference.

[0108] According to embodiments of this disclosure, the first PMOS transistor can represent a reverse diode composed of PMOS transistors. The fourth NMOS transistor can represent a capacitor composed of NMOS transistors.

[0109] According to embodiments of this disclosure, when the voltage reference circuit is not operating, the output voltage V0 of the current source circuit 120 is 0, and the fourth NMOS transistor forms a large capacitor. At the connection point between the drain of the first NMOS transistor and the gate of the third NMOS transistor, there is a parasitic capacitance effect, and the first NMOS transistor forms a small capacitor.

[0110] According to embodiments of this disclosure, when the circuit starts up, the fourth NMOS transistor and the first NMOS transistor perform a capacitive voltage divider. Since the first NMOS transistor forms a small capacitor, its voltage division is large, and current will not leak out when the first NMOS transistor is turned off. Due to the large voltage division of the first NMOS transistor, the gate of the third NMOS transistor is at a high voltage, causing the third NMOS transistor to conduct. Current flows through the drain of the third NMOS transistor, causing the voltage of the eighth NMOS transistor to decrease. Since the eighth NMOS transistor is at a high voltage when not in operation, its voltage decreases, causing it to conduct and allowing current to flow. Because current flows through the drain of the third NMOS transistor, the gate voltage of the eighth PMOS transistor decreases, causing the eighth PMOS transistor to conduct and allowing current to flow through it. This current then flows through all the transistors in the voltage reference circuit, and the voltage reference circuit successfully starts up.

[0111] According to embodiments of this disclosure, during the startup process of the voltage reference circuit, the output voltage V0 of the current source circuit 120 will have a certain value. When the first NMOS transistor is turned on, current is discharged through the first NMOS transistor, allowing all the current in the first NMOS transistor to leak out, thus reducing the voltage of the first NMOS transistor to 0. The third NMOS transistor then turns off, and the startup circuit stops working. When the voltage reference circuit is operating normally, the startup circuit stops working.

[0112] According to embodiments of this disclosure, when the voltage reference circuit is started, the third NMOS transistor has a leakage current, and this leakage current increases with increasing temperature. When the quiescent current of the current source circuit is sufficiently low, the leakage current of the third NMOS transistor affects the temperature coefficient of the voltage reference. To suppress the effect of the leakage current of the third NMOS transistor, a first PMOS transistor is connected to the drain terminal of the third NMOS transistor. Since the reverse-biased diode can generate a PTAT (Proportional to absolute temperature) current, it can offset the effect of the leakage current of the third NMOS transistor on the current source circuit 120.

[0113] According to embodiments of this disclosure, the quiescent current of the startup circuit 110 should be zero when the voltage reference circuit is operating normally. However, as the temperature increases, the quiescent current of the startup circuit increases. In a voltage reference with a very small bias current, the quiescent current of the startup circuit 110 can affect the temperature coefficient of the voltage reference. The second NMOS transistor can reduce the quiescent current of the startup circuit by raising the source voltage of the third NMOS transistor, thereby reducing the impact of the quiescent current on the temperature coefficient of the voltage reference.

[0114] According to embodiments of this disclosure, the first PMOS transistor in the startup circuit 110 can be configured as a reverse-biased diode to counteract the effect of leakage current on the temperature coefficient of the voltage reference. The second NMOS transistor reduces the quiescent current of the startup circuit by raising the source voltage of the third NMOS transistor, thereby reducing the effect of quiescent current on the temperature coefficient of the voltage reference. The first PMOS transistor and the second NMOS transistor in the startup circuit 110 can reduce the impact of the startup circuit 110 on the temperature coefficient of the voltage reference.

[0115] Figure 3 A schematic diagram of the structure of a current source circuit according to an embodiment of the present disclosure is shown.

[0116] like Figure 3As shown, the current source circuit 120 may include a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor.

[0117] According to embodiments of this disclosure, the second PMOS transistor can represent MP1, the third PMOS transistor can represent MP2, the fourth PMOS transistor can represent MP3, the fifth PMOS transistor can represent MP4, the sixth PMOS transistor can represent MP5, the seventh PMOS transistor can represent MP6, the eighth PMOS transistor can represent MP7, the ninth PMOS transistor can represent MP8, the tenth PMOS transistor can represent MP9, the eleventh PMOS transistor can represent MP10, the twelfth PMOS transistor can represent MP11, the thirteenth PMOS transistor can represent MP12, the fifth NMOS transistor can represent MR1, the sixth NMOS transistor can represent MN1, the seventh NMOS transistor can represent MN2, the eighth NMOS transistor can represent MN3, the ninth NMOS transistor can represent MN4, the tenth NMOS transistor can represent MN5, the eleventh NMOS transistor can represent MN6, and the twelfth NMOS transistor can represent MN7.

[0118] According to an embodiment of this disclosure, the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor, the drain of the eighth NMOS transistor is connected to the drain and gate of the eighth PMOS transistor and the drain of the third NMOS transistor, and the gate of the eighth NMOS transistor is connected to the gate of the first NMOS transistor and the drain of the thirteenth PMOS transistor.

[0119] According to embodiments of this disclosure, the gate and drain of the eighth PMOS transistor are connected, and the drain of the third NMOS transistor is also connected; the source of the second PMOS transistor is connected to the source of the first PMOS transistor; the source of the ninth NMOS transistor is connected to the drain of the fifth NMOS transistor and the source of the seventh NMOS transistor, and the gate of the ninth NMOS transistor is connected to the drain of the sixth NMOS transistor and the drain of the ninth PMOS transistor; the source of the sixth NMOS transistor is grounded, the drain of the sixth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the gate of the sixth NMOS transistor is connected to the gate and drain of the seventh NMOS transistor.

[0120] According to embodiments of this disclosure, the gate and drain of the seventh NMOS transistor are connected, and the drain of the tenth PMOS transistor is also connected; the source of the seventh NMOS transistor is connected, and the drain of the fifth NMOS transistor is also connected. The source of the fifth NMOS transistor is grounded, and its gate is connected, along with the gate and drain of the twelfth NMOS transistor, wherein the fifth NMOS transistor is used to form an equivalent resistance. The gate and drain of the tenth NMOS transistor are connected, and the drain of the twelfth PMOS transistor is also connected; the source of the tenth NMOS transistor is connected, along with the source of the twelfth NMOS transistor and the drain of the eleventh NMOS transistor. The source of the eleventh NMOS transistor is grounded, and its gate is connected, along with the gate of the tenth NMOS transistor. The drain of the twelfth NMOS transistor is connected, and the drain of the eleventh PMOS transistor is also connected.

[0121] According to embodiments of this disclosure, the iV characteristic of a MOS transistor located in the subthreshold region can be expressed as the following formula (5).

[0122]

[0123] in, It can represent the aspect ratio of a transistor, C ox V can represent the gate oxide capacitance per unit area, μ can represent the carrier mobility, and V T V can represent thermal voltage, η can represent the subthreshold slope factor, and V GS It can represent the gate-source voltage, V TH It can represent the threshold voltage, V DS It can represent the drain-source voltage.

[0124] If V DS >100mV, the simplified formula (5) can be expressed as the following formula (6).

[0125]

[0126] The current I in the branch containing the fifth NMOS transistor D It can be expressed as the following formula (7).

[0127]

[0128] Among them, V DS,MR1 R can represent the drain-source voltage of the fifth NMOS transistor. MR1 This can represent the resistance of the fifth NMOS transistor.

[0129] The fifth NMOS transistor is located in the deep linear region, and the resistor R operates in the linear region. MR1 It can be expressed as the following formula (8).

[0130]

[0131] Among them, V GS,MR1 This can represent the gate-source voltage of the fifth NMOS transistor, V. TH,MR1 This can represent the threshold voltage of the fifth NMOS transistor. It can represent the width-to-length ratio of the fifth NMOS transistor.

[0132] The sixth and seventh NMOS transistors are both located in the subthreshold region, and the drain-source voltage V of the fifth NMOS transistor is... DS,MR1 It can be expressed as the following formula (9).

[0133]

[0134] Among them, K MN1 K can represent the width-to-length ratio of the sixth NMOS transistor. MN2 It can represent the width-to-length ratio of the seventh NMOS transistor.

[0135] Substituting equations (8) and (9) into equation (7), the current I in the branch containing the fifth NMOS transistor MR1 is... D It can be expressed as the following formula (10).

[0136]

[0137] V GS,MR1 It is derived from the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor, and can be expressed as the following formula (11).

[0138]

[0139] Among them, V GS,MN6 This can represent the gate-source voltage of the eleventh NMOS transistor, V. GS,MN5 This can represent the gate-source voltage of the tenth NMOS transistor, V. GS,MN7 K can represent the gate-source voltage of the twelfth NMOS transistor. M5 K can represent the width-to-length ratio of the tenth NMOS transistor. M7 This can represent the width-to-length ratio of the twelfth NMOS transistor.

[0140] Substituting formula (11) into formula (10), the current I in the branch where the fifth NMOS transistor is located... D It can be expressed as the following formula (12).

[0141]

[0142] μ is the carrier mobility, and its temperature coefficient can be expressed as the following formula (13).

[0143]

[0144] Where μ0 represents carrier mobility, T represents temperature, and m represents the effective mass of carriers.

[0145] Both sides simultaneously on I D The derivative can be expressed as the following formula (14).

[0146]

[0147] Here, C can represent a constant that is independent of temperature.

[0148] Solving the differential equation using formula (14) yields the following formula (15).

[0149] I D =I D0 T C(2-m) (15)

[0150] Among them, I D0 It can represent a coefficient that is independent of temperature, and m can represent a natural number greater than 0 and less than 2.

[0151] According to embodiments of this disclosure, I D It can represent positive temperature coefficient current.

[0152] According to embodiments of this disclosure, I D It can characterize the sum of the currents passing through the second PMOS transistor, the eighth PMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor, and the currents passing through the fourth PMOS transistor, the tenth PMOS transistor, and the seventh NMOS transistor.

[0153] According to the embodiments of this disclosure, since the second and eighth PMOS transistors, the third and ninth PMOS transistors, the fourth and tenth PMOS transistors, the fifth and eleventh PMOS transistors and the sixth and twelfth PMOS transistors in the common-source cascode current mirror have the same structure, the current flowing through each branch is the same, which is I0.

[0154] According to an embodiment of this disclosure, I0 can be expressed as the following formula (16).

[0155]

[0156] Among them, due to I D It is twice the value of I0, and I0 can represent the positive temperature coefficient current.

[0157] According to embodiments of this disclosure, the seventh and thirteenth PMOS transistors in the common-source cascode current mirror can amplify the current I0 by a factor of N. I1 can represent I0 by a factor of N, where N can represent a natural number greater than 1. I1 can be expressed as follows (17).

[0158]

[0159] Since I1 and I0 are N times each other, I1 can represent the positive temperature coefficient current.

[0160] According to embodiments of this disclosure, the current source circuit 120 can be used to generate a positive temperature coefficient current I1.

[0161] According to embodiments of this disclosure, the common-source cascode current mirror may include a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor in the current source circuit 120, wherein the input terminal of the common-source cascode current mirror is connected to the power supply voltage VDD.

[0162] According to embodiments of this disclosure, the current source may include a third PMOS transistor, a fourth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, wherein the current source is used to generate a current I0.

[0163] According to embodiments of this disclosure, the seventh and thirteenth PMOS transistors in the common-source cascode current mirror amplify the current I0 by a factor of N to generate a positive temperature coefficient current. The second, third, fourth, fifth, sixth, eighth, ninth, tenth, eleventh, and twelfth PMOS transistors in the common-source cascode current mirror have the same width-to-length ratio, and the width-to-length ratio of the seventh and thirteenth PMOS transistors is N times the parameter, where N is a natural number greater than 1.

[0164] According to embodiments of this disclosure, the bias voltage generation circuit may include a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor.

[0165] According to embodiments of this disclosure, the bias voltage generation circuit can be used to determine the gate-source voltage of the fifth NMOS transistor.

[0166] According to an embodiment of this disclosure, the bias voltage generation circuit in the current source circuit 120 can be used to determine the gate-source voltage of the fifth NMOS transistor. The current source can be used to generate current I0. The seventh PMOS transistor and the thirteenth PMOS transistor in the common-source common-gate current mirror can amplify current I0 by N times to obtain the positive temperature coefficient current I1 generated by the current source circuit 120.

[0167] Figure 4A schematic diagram of the structure of an active load circuit according to an embodiment of the present disclosure is shown.

[0168] like Figure 4 As shown, the active load circuit 130 may include a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, and a sixteenth NMOS transistor.

[0169] According to embodiments of this disclosure, the thirteenth NMOS transistor can represent MN8, the fourteenth NMOS transistor can represent MN9, the fifteenth NMOS transistor can represent MN10, and the sixteenth NMOS transistor can represent MN11.

[0170] According to embodiments of this disclosure, the source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, the source of the fourteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the source of the fifteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor, and the source of the sixteenth NMOS transistor is grounded; the gates of the thirteenth, fourteenth, fifteenth, and sixteenth NMOS transistors are connected together and connected to the drain of the thirteenth NMOS transistor; the drain of the thirteenth NMOS transistor is connected to the drain of the thirteenth PMOS transistor and the gate of the eighth NMOS transistor.

[0171] According to embodiments of this disclosure, the current source circuit 120 and the third-order temperature coefficient current generating circuit 140 jointly provide current in the active load circuit 130.

[0172] Figure 5 A schematic diagram of a third-order temperature coefficient current generating circuit according to an embodiment of the present disclosure is shown.

[0173] like Figure 5 As shown, the third-order temperature coefficient current generation circuit 140 may include a fourteenth PMOS transistor.

[0174] According to embodiments of this disclosure, the fourteenth PMOS transistor can characterize MD1.

[0175] According to an embodiment of this disclosure, the source of the fourteenth PMOS transistor is connected to its gate and is connected to the gate of the thirteenth NMOS transistor, while the drain of the fourteenth PMOS transistor is grounded.

[0176] According to embodiments of this disclosure, the fourteenth PMOS transistor can characterize a reverse-biased diode composed of PMOS transistors. The reverse-biased diode can generate PTAT current.

[0177] According to embodiments of this disclosure, the third-order temperature coefficient current generating circuit 140 can be used to generate a third-order temperature coefficient current.

[0178] Figure 6A schematic cross-sectional view of a reverse diode composed of a PMOS transistor according to an embodiment of the present disclosure is shown.

[0179] like Figure 6 As shown, the transistor is operating in the cutoff region.

[0180] The reverse saturation current of a diode can be expressed as the following formula (18).

[0181]

[0182] Where q can represent the electron charge, and D p D can represent the diffusion coefficient of holes. n L can represent the electron diffusion coefficient. p L can represent the diffusion length of a hole. n P can represent the diffusion length of electrons. no It can represent the hole equilibrium concentration, n po It can represent the electron equilibrium concentration.

[0183] The intrinsic carrier concentration can be expressed as the following formula (19).

[0184]

[0185] Among them, V G0 It can represent the bandgap voltage, which is approximately 1.205V, and D can represent a coefficient that is independent of temperature.

[0186] n po ,P no The relationship with intrinsic carrier concentration can be expressed as formulas (20) and (21) below.

[0187]

[0188]

[0189] Where, N D It can represent the donor impurity concentration, N A It can represent the concentration of acceptor impurities.

[0190] The reverse saturation current of the fourteenth PMOS transistor in the third-order temperature coefficient current generation circuit, i.e. the third-order temperature coefficient current I2, can be expressed as the following formula (22).

[0191]

[0192] Where A can represent a constant independent of temperature, I S It can represent PTAT current.

[0193] Differentiating both sides of equation (22) with respect to T, we can express it as equation (23) below.

[0194]

[0195] Here, K can represent the Bolmantz constant.

[0196] The threshold voltage V of the NMOS transistor in the active load circuit TH,130 It can be expressed as the following formula (24).

[0197]

[0198] Where, φ ms This can represent the contact potential difference between the substrate and the gate, φ. F It can represent the Fermi potential, Q ss It can represent surface charge density, C ox It can represent the gate oxide capacitance per unit area.

[0199] φ is affected by temperature ms and φ F V TH,130 A Taylor expansion is performed at T0. To simplify the analysis, only the first and second terms are taken, which can be expressed as the following formula (25).

[0200]

[0201] in, α and β can represent constants independent of temperature, V TH0,130 It can represent the initial threshold voltage of the NMOS transistor in an active load circuit.

[0202] Figure 7 A schematic diagram of a low-pass filter circuit according to an embodiment of the present disclosure is shown.

[0203] like Figure 7 As shown, the voltage reference circuit also includes a low-pass filter circuit; the low-pass filter circuit may include a fifteenth PMOS transistor and a seventeenth NMOS transistor.

[0204] According to embodiments of this disclosure, the fifteenth PMOS transistor can characterize MR2 and the seventeenth NMOS transistor can characterize MC2.

[0205] According to an embodiment of this disclosure, the input terminal of the low-pass filter circuit is connected to the output terminal of the current source circuit 120, and the low-pass filter circuit is used to achieve a high power supply rejection ratio at high frequencies.

[0206] According to an embodiment of this disclosure, the source of the fifteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, the gate of the fifteenth PMOS transistor is connected to the drain and is connected to the gate of the seventeenth NMOS transistor, wherein the fifteenth PMOS transistor is used to form a resistor; the drain and source of the seventeenth NMOS transistor are connected to ground, wherein the seventeenth NMOS transistor is used to form a capacitor.

[0207] According to embodiments of this disclosure, the gate and drain of the fifteenth PMOS transistor are connected, which can accelerate the establishment of the reference voltage.

[0208] Since the iV characteristic of a MOS transistor located in the subthreshold region can be expressed as the following formula (5).

[0209]

[0210] The equivalent resistance of the fifteenth PMOS transistor can be expressed as the following formula (26).

[0211]

[0212] in, This can represent the width-to-length ratio of the fifteenth PMOS transistor, V. GS,MR2 This can represent the gate-source voltage of the fifteenth PMOS transistor, V. TH,MR2 This can represent the threshold voltage of the fifteenth PMOS transistor, V. DS,MR2 It can represent the drain-source voltage of the fifteenth PMOS transistor.

[0213] In steady state, V DS,MR2 =V GS,MR2 =0, the equivalent resistance of the fifteenth PMOS transistor can be expressed as the following formula (27).

[0214]

[0215] In steady state, the capacitance of the seventeenth NMOS transistor can be represented by C. MC2 =C ox (W MC2 L MC2 ) MC2 Among them, W MC2 L can represent the width of the seventeenth NMOS transistor. MC2 It can represent the length of the seventeenth NMOS transistor.

[0216] The cutoff frequency of a low-pass filter can be expressed as follows (28).

[0217]

[0218] According to embodiments of this disclosure, the fifteenth PMOS transistor in the low-pass filter circuit is used to form a resistor and the seventeenth NMOS transistor is used to form a capacitor, which can achieve a high power supply rejection ratio at high frequencies. The power supply rejection ratio of the voltage reference at high frequencies can reach -30dB. The gate and drain of the fifteenth PMOS transistor are connected. Compared with the low-pass filter composed of conventional MOS transistors, the establishment of the reference voltage can be accelerated.

[0219] Figure 8 A graph illustrating the power supply rejection ratio as a function of frequency according to an embodiment of the present disclosure is shown schematically.

[0220] like Figure 8 As shown, the power supply rejection ratio (PSRR) decreases with increasing frequency. With other voltage reference properties remaining constant, the PSRR reaches as high as -80 dB.

[0221] Figure 9 The diagram illustrates the process of establishing a voltage reference with a low-pass filter after the improvement (circuit a) and the process of establishing a voltage reference with a low-pass filter before the improvement (circuit b) according to an embodiment of the present disclosure.

[0222] like Figure 9 As shown, when the power supply voltage and output voltage remain stable, the establishment process of circuit a is faster and takes less time than that of circuit b.

[0223] Figure 10 A schematic diagram of a low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation according to an embodiment of the present disclosure is shown.

[0224] like Figure 10 As shown, a full CMOS structure is used, which reduces the layout area.

[0225] According to embodiments of this disclosure, the voltage reference circuit uses the positive temperature coefficient current I1 generated by the current source circuit 120 and the third-order temperature coefficient current I2 generated by the third-order temperature coefficient current generation circuit 140 to jointly bias the active load in the active load circuit 130. I1 and I2 can represent PTAT currents, which can compensate for the negative temperature characteristics of the threshold voltage of the active load and achieve a temperature-independent output voltage V0.

[0226] According to embodiments of this disclosure, the current I in the active load circuit 130 ref It can be expressed as the following formula (1).

[0227]

[0228] Where μ can represent carrier mobility, C ox This can represent the gate oxide capacitance per unit area. V can represent the width-to-length ratio of the NMOS transistor in the active load circuit 130. GS,130 This can represent the gate-source voltage of the active load circuit 130, V. TH,130 It can represent the threshold voltage of the NMOS transistor in the active load circuit 130.

[0229] According to embodiments of this disclosure, the current I in the active load circuit ref This can characterize the difference between the positive temperature coefficient current I1 and the third-order temperature coefficient current I2. The current I in an active load circuit... ref It can be expressed as the following formula (2).

[0230] I ref =I1-I2 (2)

[0231] According to formulas (1) and (2), the first expression of the output voltage V0 of the current source circuit 120 can be expressed as formula (3) below.

[0232]

[0233] According to an embodiment of this disclosure, the second expression for the output voltage V0 of the current source circuit 120 is obtained by substituting the expressions for the positive temperature coefficient current I1 and the third-order temperature coefficient current I2 into the first expression for the output voltage V0 and performing a Taylor expansion.

[0234] According to embodiments of this disclosure, the expression for the positive temperature coefficient current I1 can be derived from formulas (5) to (17). The expression for the third-order temperature coefficient current I2 can be derived from formulas (18) to (22).

[0235] According to an embodiment of this disclosure, in order to simplify the analysis, formula (22) is simplified by letting I2 = A0T 3 , where A0 can represent a constant that is independent of temperature.

[0236] According to embodiments of this disclosure, the threshold voltage V of the NMOS transistor in the active load circuit TH,130 It can be derived from formulas (24) to (25).

[0237] According to an embodiment of this disclosure, V0 is Taylor expanded at T0, considering only the first-order and second-order terms. The second expression for the output voltage V0 of the current source circuit 120 can be expressed as the following formula (4).

[0238]

[0239] Where A, B, α, and β can represent constants independent of temperature, V TH0,130This can represent the initial threshold voltage of the NMOS transistor in the active load circuit 130.

[0240]

[0241]

[0242] According to embodiments of this disclosure, by setting C1+α=0 and C2+β=0, an output voltage V0 independent of temperature can be obtained.

[0243] Figure 11 The diagram illustrates the voltage variation with temperature generated by the voltage reference circuit according to an embodiment of the present disclosure.

[0244] like Figure 11 As shown, the reference voltage changes waveformically with increasing temperature. When the temperature varies between -20℃ and 10℃, the reference voltage decreases with increasing temperature. When the temperature varies between 10℃ and 90℃, the reference voltage increases with increasing temperature. When the temperature varies between 90℃ and 120℃, the reference voltage decreases with increasing temperature. Based on the voltage-temperature curve generated by the voltage reference circuit, the lowest temperature coefficient achieved is 18.4 ppm / ℃.

[0245] According to embodiments of this disclosure, the first feedback branch may include an eighth NMOS transistor; the second feedback branch may include a second PMOS transistor, an eighth PMOS transistor, and a ninth NMOS transistor.

[0246] According to embodiments of this disclosure, the first feedback branch, the second feedback branch, and the cascode current mirror can be used to achieve a high power supply rejection ratio at low frequencies.

[0247] According to embodiments of this disclosure, in the current source circuit, because the additional branches MP1 and MP7 are diode-connected MOSFETs, changes in the power supply voltage will be directly reflected at the drain of MN4. To mitigate the channel length modulation effect of MN4, transistor MN3 is connected to the drain of MN4, and its gate is connected to the output reference voltage V. ref Therefore, the drain voltage of MN4 will not change with the power supply voltage, which improves the power supply rejection ratio of the current source circuit, that is, improves the power supply rejection ratio of the voltage reference.

[0248] According to embodiments of this disclosure, constructing a feedback branch and building a cascode current mirror can be used to achieve a high power supply rejection ratio at low frequencies.

[0249] Figure 12 A small-signal model based on a common-source cascode current mirror circuit according to an embodiment of the present disclosure is illustrated schematically.

[0250] like Figure 12As shown, the current source circuit can be equivalent to a single current source. An active load can be equivalent to a small-signal resistor. The current source circuit provides current to the resistor through a common-source, common-gate current mirror.

[0251] List v x v y v z v out Solving the KCL (Kirchhoff's Current Law) equations together yields v. out The relationship with the power supply voltage and current source can be expressed as the following formula (29).

[0252]

[0253] in,

[0254] Figure 13 A small-signal model of a conventional current mirror according to an embodiment of the present disclosure is illustrated schematically.

[0255] like Figure 13 As shown, v is listed x v out Solving the KCL equations together, we obtain v. out The relationship with the power supply voltage and current source can be expressed as the following formula (30).

[0256]

[0257] According to embodiments of this disclosure, it can be seen from formulas (29) and (30) that after using the common source cascode structure, v out to v in The gain was reduced by g m2 r 02 This increases the power supply rejection ratio of the voltage reference by a factor of 1, which is 10 times higher.

[0258] From formulas (29) and (30), we can see that v out With v in and I ref Both are related. Among them, v in It also affects I ref The size of v. If v can be reduced in To I ref The gain can also further improve the power supply rejection ratio of the voltage reference.

[0259] Figure 14 A small-signal model of a current source circuit according to an embodiment of the present disclosure is illustrated schematically.

[0260] like Figure 14As shown, to improve the PSRR (Power Supply Rejection Ratio) of the voltage reference, an additional branch, MP1, MP7, and MN4, is introduced into the classic current reference source. This branch makes the leakage voltages of MN1 and MN4 nearly identical, improving the PSRR of the current source circuit and thus also improving the PSRR of the voltage reference.

[0261] According to the embodiments of this disclosure, the KCL equations for v1, v2, v3, v4, v5, v6, and v7 are listed and solved together. The relationship between v7 and the power supply voltage can be expressed as the following formula (31).

[0262]

[0263] in,

[0264] From formula (31), we can see that the gain from the power source to the current is: The order of magnitude. Therefore, using this structure improves the power supply rejection ratio of the current source and also enhances the voltage rejection ratio of the voltage reference.

[0265] According to embodiments of this disclosure, the transistors in the active load circuit operate in the saturation region; the fifth NMOS transistor in the current source circuit operates in the deep linear region; the other transistors in the current source circuit operate in the subthreshold region; and the transistors in the third-order temperature coefficient current generation circuit and the low-pass filter circuit operate in the cutoff region.

[0266] According to embodiments of this disclosure, most of the transistors in the voltage reference circuit are located in the subthreshold region, which reduces the static power consumption of the voltage reference, and the total current of the voltage reference circuit is only 45na.

[0267] Figure 15 The diagram illustrates the voltage variation curves of a voltage reference under different power supply voltages according to embodiments of the present disclosure.

[0268] like Figure 15 As shown, the reference voltage changes waveformically with increasing temperature. When the temperature varies between -20℃ and 10℃, the reference voltage decreases with increasing temperature. When the temperature varies between 10℃ and 90℃, the reference voltage increases with increasing temperature. When the temperature varies between 90℃ and 120℃, the reference voltage decreases with increasing temperature. At the same temperature, the higher the power supply voltage, the higher the reference voltage.

[0269] Figure 16 The diagram illustrates the variation curve of the output reference voltage with the power supply voltage according to an embodiment of the present disclosure.

[0270] like Figure 16As shown, when the power supply voltage is between 1.0V and 3.5V, the output reference voltage increases with the increase of the power supply voltage, but the rate of change is slow. When the power supply voltage is between 3.5V and 4.0V, the output reference voltage increases with the increase of the power supply voltage, but the rate of change is fast.

[0271] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0272] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0273] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A low-power voltage reference circuit with high power supply rejection ratio and high-order temperature compensation in full CMOS, the voltage reference circuit comprising: Start-up circuit, current source circuit, active load circuit, and third-order temperature coefficient current generation circuit; The startup circuit is used to start the voltage reference circuit; The first input terminal of the current source circuit is connected to the output terminal of the starting circuit, and the second input terminal of the current source circuit is connected to the power supply voltage. The current source circuit is used to generate a positive temperature coefficient current, and the power supply voltage is used to provide voltage to the current source circuit. The output terminal of the current source circuit is connected to the input terminal of the active load circuit and the third-order temperature coefficient current generating circuit. The current source circuit and the third-order temperature coefficient current generating circuit jointly provide the current in the active load circuit, and the third-order temperature coefficient current generating circuit is used to generate a third-order temperature coefficient current. The first expression for the output voltage V0 of the current source circuit is obtained based on the current in the active load circuit and the threshold voltage of the NMOS transistor in the active load circuit. The current in the active load circuit represents the difference between the positive temperature coefficient current and the third-order temperature coefficient current. The second expression for the output voltage V0 of the current source circuit contains temperature-related polynomial coefficients, and the sum of these polynomial coefficients is 0, so as to obtain an output voltage V0 of the current source circuit that is independent of temperature; wherein, the second expression for the output voltage V0 is obtained by substituting the expression for the positive temperature coefficient current and the expression for the third-order temperature coefficient current into the first expression for the output voltage V0 and performing a Taylor expansion. The current source circuit includes the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor; The source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor. The drain of the eighth NMOS transistor is connected to the drain and gate of the eighth PMOS transistor and the drain of the third NMOS transistor in the startup circuit. The gate of the eighth NMOS transistor is connected to the gate of the first NMOS transistor and the drain of the thirteenth PMOS transistor in the startup circuit. The gate of the eighth PMOS transistor is connected to its drain, and is also connected to the drain of the third NMOS transistor. The source of the second PMOS transistor is connected to the source of the first PMOS transistor in the startup circuit; The source of the ninth NMOS transistor is connected to the drain of the fifth NMOS transistor and the source of the seventh NMOS transistor, and the gate of the ninth NMOS transistor is connected to the drain of the sixth NMOS transistor and the drain of the ninth PMOS transistor. The source of the sixth NMOS transistor is grounded, the drain of the sixth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the gate of the sixth NMOS transistor is connected to the gate and drain of the seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to the drain and is connected to the drain of the tenth PMOS transistor. The source of the seventh NMOS transistor is connected to the drain of the fifth NMOS transistor. The source of the fifth NMOS transistor is grounded, and the gate of the fifth NMOS transistor is connected to the gate and drain of the twelfth NMOS transistor. The fifth NMOS transistor is used to form an equivalent resistance. The gate of the tenth NMOS transistor is connected to the drain and is connected to the drain of the twelfth PMOS transistor. The source of the tenth NMOS transistor is connected to the source of the twelfth NMOS transistor and the drain of the eleventh NMOS transistor. The source of the eleventh NMOS transistor is grounded, and the gate of the eleventh NMOS transistor is connected to the gate of the tenth NMOS transistor. The drain of the twelfth NMOS transistor is connected to the gate and is also connected to the drain of the eleventh PMOS transistor.

2. The circuit according to claim 1, wherein, The startup circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first PMOS transistor; The source of the first NMOS transistor is connected to the source of the second NMOS transistor and grounded, and the drain of the first NMOS transistor is connected to the gate of the third NMOS transistor and the source and drain of the fourth NMOS transistor. The gate and drain of the second NMOS transistor are connected together and connected to the source of the third NMOS transistor; The drain of the third NMOS transistor is connected to the drain of the first PMOS transistor. The drain and source of the fourth NMOS transistor are connected, and the gate of the fourth NMOS transistor is connected to the gate and source of the first PMOS transistor. The source and gate of the first PMOS transistor are connected.

3. The circuit according to claim 1, wherein, The common-source common-gate current mirror includes the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, and the thirteenth PMOS transistor in the current source circuit, wherein the input terminal of the common-source common-gate current mirror is connected to the power supply voltage; The current source includes the third PMOS transistor, the fourth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor, wherein the current source is used to generate current I0; The seventh and thirteenth PMOS transistors in the common-source cascode current mirror amplify the current I0 by a factor of N to generate the positive temperature coefficient current. The second, third, fourth, fifth, sixth, eighth, ninth, tenth, eleventh, and twelfth PMOS transistors in the common-source cascode current mirror have the same width-to-length ratio. The width-to-length ratio of the seventh and thirteenth PMOS transistors is N times the width-to-length ratio of the sixth PMOS transistor, where N is a natural number greater than 1. The bias voltage generation circuit includes the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor.

4. The circuit according to claim 1, wherein, The active load circuit includes a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, and a sixteenth NMOS transistor; The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, the source of the fourteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the source of the fifteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor, and the source of the sixteenth NMOS transistor is grounded. The gates of the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the sixteenth NMOS transistor are connected, and are also connected to the drain of the thirteenth NMOS transistor. The drain of the thirteenth NMOS transistor is connected to the drain of the thirteenth PMOS transistor and the gate of the eighth NMOS transistor.

5. The circuit according to claim 4, wherein, The third-order temperature coefficient current generating circuit includes a fourteenth PMOS transistor; The source and gate of the fourteenth PMOS transistor are connected, and the gate of the thirteenth NMOS transistor is also connected. The drain of the fourteenth PMOS transistor is grounded.

6. The circuit according to claim 5, wherein, The voltage reference circuit also includes a low-pass filter circuit; The input terminal of the low-pass filter circuit is connected to the output terminal of the current source circuit, and the low-pass filter circuit is used to achieve a high power supply rejection ratio at high frequencies. The low-pass filter circuit includes a fifteenth PMOS transistor and a seventeenth NMOS transistor; The source of the fifteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, and the gate of the fifteenth PMOS transistor is connected to the drain and is also connected to the gate of the seventeenth NMOS transistor. The fifteenth PMOS transistor is used to form a resistor. The drain and source of the seventeenth NMOS transistor are connected and grounded, and the seventeenth NMOS transistor is used to form a capacitor.

7. The circuit according to claim 3, wherein, The first feedback branch includes the eighth NMOS transistor; The second feedback branch includes the second PMOS transistor, the eighth PMOS transistor, and the ninth NMOS transistor, wherein the first feedback branch, the second feedback branch, and the common-source cascode current mirror are used to achieve a high power supply rejection ratio at low frequencies.

8. The circuit according to claim 6, wherein, The transistors in the active load circuit operate in the saturation region; The fifth NMOS transistor in the current source circuit operates in the deep linear region; The other transistors in the current source circuit operate in the subthreshold region; The transistors in the third-order temperature coefficient current generating circuit and the low-pass filter circuit operate in the cutoff region.

9. The circuit according to claim 2, wherein, The startup circuit, used to start the voltage reference circuit, includes: When the first NMOS transistor is off, the voltage division of the first NMOS transistor is high, the gate of the third NMOS transistor is high, and the third NMOS transistor is on. When the third NMOS transistor is turned on, a current will be generated at the drain of the third NMOS transistor; Based on the current generated at the drain of the third NMOS transistor, the gate voltage of the eighth PMOS transistor decreases, and the voltage reference circuit is activated. During the startup process of the voltage reference circuit, the first PMOS transistor is used to counteract the effect of the leakage current in the third NMOS transistor on the temperature coefficient of the voltage reference; the second NMOS transistor reduces the quiescent current of the startup circuit by raising the source voltage of the third NMOS transistor, thereby reducing the effect of the quiescent current on the temperature coefficient of the voltage reference.

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