Base Chip, Memory System, and Semiconductor Structure

Abstract

An embodiment of the present application provides a basic chip, a storage system, and a semiconductor structure. The basic chip includes: The basic chip is configured to receive first data and first encoded data during a write phase and perform a first error detection and correction process. The first encoded data is obtained by performing a first error correction code encoding process on the first data. During the write phase, the basic chip transmits second data to a storage chip, and the second data includes the first data after the first error detection and correction process. The basic chip is further configured to receive the second data from the storage chip during a read phase and perform a second error correction code encoding process on the second data to generate second encoded data, and transmit third data during the read phase. The third data includes the second encoded data and the first data after the first error detection and correction process.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and particularly to a basic chip, a storage system, and a semiconductor structure. Background Art

[0002] Semiconductor storage can be divided into non-volatile storage and volatile storage. As volatile storage, Dynamic Random Access Memory (DRAM) has the advantages of high storage density, fast read and write speed, etc., and is widely used in various electronic systems.

[0003] As the manufacturing process of DRAM becomes more and more advanced and the storage density becomes higher and higher, the stored data in DRAM may be incorrect, seriously affecting the performance of DRAM. Therefore, Error Checking and Correction (ECC) technology is usually adopted in DRAM to detect or correct errors in the stored data. Summary of the Invention

[0004] Embodiments of the present application provide a basic chip, a storage system, and a semiconductor structure, which are at least beneficial to solving the problem of tight area of the controller or the storage chip.

[0005] According to some embodiments of the present application, on the one hand, an embodiment of the present application provides a basic chip applied to a storage system, including: the basic chip is configured to receive first data and first encoded data in a write stage and perform first error detection and correction processing, the first encoded data is obtained by performing first error correction code encoding processing on the first data, and transmit second data to a storage chip in the write stage, the second data includes the first data after the first error detection and correction processing; the basic chip is further configured to receive the second data from the storage chip in a read stage and perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the read stage, the third data includes the second encoded data and the first data after the first error detection and correction processing.

[0006] In addition, the basic chip includes: a first error detection and correction module configured to receive the first data and the first encoded data in the write stage and perform the first error detection and correction processing; a second encoding module configured to receive the first data after the first error detection and correction processing in the read stage and perform the second error correction code encoding processing to generate the second encoded data.

[0007] In addition, the base chip is further configured to perform a third error correction code encoding process on the first data after the first error detection and correction process during the writing stage to generate third encoded data, and the second data further includes the third encoded data; during the reading stage, before performing the second error correction code encoding process, it further includes performing a second error detection and correction process on the second data, and the first data after the first error detection and correction process included in the third data is the first data after the second error detection and correction process.

[0008] In addition, the base chip further includes: a third encoding module, which is configured to receive the first data after the first error detection and correction process during the writing stage and perform the third error correction code encoding process to generate the third encoded data; a second error detection and correction module, which is configured to receive the second data during the reading stage and perform the second error detection and correction process.

[0009] In addition, the base chip further includes: a first serial-to-parallel conversion module, which is configured to receive the first data and the first encoded data during the writing stage, perform a first serial-to-parallel conversion process on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion process to the first error detection and correction module; a first parallel-to-serial conversion module, which is configured to receive the third data from the second encoding module during the reading stage, perform a first parallel-to-serial conversion process on the third data, and transmit the third data after the first parallel-to-serial conversion process to the controller.

[0010] In addition, the base chip further includes: a second parallel-to-serial conversion module, which is configured to receive the second data during the writing stage and perform a second parallel-to-serial conversion process, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module, which is configured to receive the second data from the storage chip during the reading stage and perform a second serial-to-parallel conversion process, and transmit the second data after the second serial-to-parallel conversion process to the second encoding module.

[0011] In addition, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data and the first encoded data during the transmission process based on the first error detection flag signal.

[0012] In addition, the base chip further includes: a first storage buffer module configured to store the first data and the error conditions during the transmission of the first encoded data; a first command module that receives a first polling instruction and generates a first command signal and a first clock signal; the first storage buffer module is further configured to output a first characterization signal based on the first command signal and the first clock signal, where the first characterization signal characterizes the error conditions during the transmission of the first data and the first encoded data.

[0013] In addition, the base chip is further configured to generate a second error detection flag signal during the second error detection and correction process, and record the error conditions during the transmission of the third encoded data and the first data after the first error detection and correction process based on the second error detection flag signal.

[0014] In addition, the base chip further includes: a second storage buffer module configured to store the error conditions during the transmission of the third encoded data and the first data after the first error detection and correction process; a second command module that receives a second polling instruction and generates a second command signal and a second clock signal; the second storage buffer module is further configured to output a second characterization signal based on the second command signal and the second clock signal, where the second characterization signal characterizes the error conditions during the transmission of the third encoded data and the first data after the first error detection and correction process.

[0015] According to some embodiments of the present application, on the other hand, an embodiment of the present application provides a storage system, including a controller, a base chip, and a storage chip, further including: The controller is configured to perform a first error correction code encoding process on first data in a write phase to generate first encoded data, and transmit the first data and the first encoded data to the base chip; The base chip is configured to receive the first data and the first encoded data in the write phase and perform a first error detection and correction process, and transmit second data to the storage chip in the write phase, where the second data includes the first data after the first error detection and correction process; The base chip is further configured to receive the second data from the storage chip in a read phase and perform a second error correction code encoding process on the second data to generate second encoded data, and transmit third data to the controller in the read phase, where the third data includes the second encoded data and the first data after the first error detection and correction process; The storage chip is configured to receive the second data from the base chip in the write phase and store the second data, and transmit the second data to the base chip in the read phase; The controller is further configured to receive the third data from the base chip in the read phase, perform a third error detection and correction process on the third data, and obtain the first data after the third error detection and correction process.

[0016] In addition, the controller includes: a first encoding module configured to perform the first error correction code encoding process on the first data in the write phase to generate the first encoded data; a third error detection and correction module configured to receive the third data and perform the third error detection and correction process in the read phase.

[0017] In addition, the base chip includes: a first error detection and correction module configured to receive the first data and the first encoded data and perform the first error detection and correction process in the write phase; a second encoding module configured to receive the first data after the first error detection and correction process and perform the second error correction code encoding process to generate the second encoded data in the read phase.

[0018] In addition, the base chip is further configured to perform a third error correction code encoding process on the first data after the first error detection and correction process during the writing stage to generate third encoded data, and the second data further includes the third encoded data; during the reading stage, before performing the second error correction code encoding process, it further includes performing a second error detection and correction process on the second data, and the first data after the first error detection and correction process included in the third data is the first data after the second error detection and correction process; the storage chip includes: a first storage module configured to store the first data after the first error detection and correction process; a second storage module configured to store the third encoded data.

[0019] In addition, the base chip further includes: a third encoding module configured to receive the first data after the first error detection and correction process during the writing stage and perform the third error correction code encoding process to generate the third encoded data; a second error detection and correction module configured to receive the second data and perform the second error detection and correction process during the reading stage.

[0020] In addition, the first error correction code encoding process, the second error correction code encoding process, the first error detection and correction process, and the third error detection and correction process are performed using a first compilation algorithm, the third error correction code encoding process and the second error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm.

[0021] In addition, the base chip further includes: a first serial-to-parallel conversion module configured to receive the first data and the first encoded data during the writing stage, perform a first serial-to-parallel conversion process on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion process to the first error detection and correction module; a first parallel-to-serial conversion module configured to receive the third data from the second encoding module during the reading stage, perform a first parallel-to-serial conversion process on the third data, and transmit the third data after the first parallel-to-serial conversion process to the controller.

[0022] In addition, the base chip further includes: a second parallel-to-serial conversion module configured to receive the second data and perform a second parallel-to-serial conversion process during the write phase, and transmit the second data after the second parallel-to-serial conversion process to the memory chip; a second serial-to-parallel conversion module configured to receive the second data from the memory chip and perform a second serial-to-parallel conversion process during the read phase, and transmit the second data after the second serial-to-parallel conversion process to the second encoding module.

[0023] In addition, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data and the first encoded data during transmission based on the first error detection flag signal; the storage system further includes: a first register configured to store the error conditions of the first data and the first encoded data during transmission.

[0024] In addition, the base chip is further configured to generate a second error detection flag signal during the second error detection and correction process, and record the error conditions of the first data after the first error detection and correction process during transmission based on the second error detection flag signal; the storage system further includes: a second register configured to store the error conditions of the first data after the first error detection and correction process during transmission.

[0025] In addition, the controller is further configured to generate a third error detection flag signal during the third error detection and correction process, and record the error conditions of the first data after the second error detection and correction process during transmission based on the third error detection flag signal; the storage system further includes: a third register configured to store the error conditions of the first data after the second error detection and correction process during transmission.

[0026] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a semiconductor structure, including: a carrier substrate; the aforementioned storage system, and both the controller and the base chip are located on the surface of the carrier substrate, and the memory chip is located on the surface of the base chip away from the carrier substrate. The technical solutions provided by the embodiments of the present application have the following advantages:

[0027] In the technical solution of the basic chip provided by the embodiment of the present application, the basic chip performs error detection and correction processing on the first data and the first encoded data during the writing stage, and transmits the first data after the error detection and correction processing to the storage chip as the second data; and the basic chip receives the second data from the storage chip during the reading stage and performs error correction code encoding processing to generate the second encoded data, and transmits the third data, where the third data includes the second encoded data and the first data after the error detection and correction processing. Therefore, the basic chip has an encoding processing function and an error detection and correction function, so that the storage chip in the storage system does not need to have an encoding processing function and an error detection and correction function, and the basic chip can share the encoding processing function and the error detection and correction function required by the controller, which is beneficial to improving the performance of the controller and the storage chip, and reasonably utilizing the chip area of the basic chip, and further beneficial to improving the storage performance of the storage system. Description of the Drawings

[0028] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.

[0029] Figure 1 It is a schematic structural diagram of a semiconductor structure;

[0030] Figure 2 is Figure 1 A schematic diagram of data transmission in the provided semiconductor structure;

[0031] Figures 3 to 10 It is a schematic structural diagram of the basic chip provided by the embodiment of the present application;

[0032] Figures 11 to 15 It is a schematic structural diagram of the storage system provided by the embodiment of the present application;

[0033] Figure 16 It is a schematic cross-sectional structural diagram of the semiconductor structure provided by the embodiment of the present application. Detailed Description of the Embodiments

[0034] Figure 1 It is a schematic structural diagram of a semiconductor structure, Figure 2 is Figure 1 A schematic diagram of data transmission in the provided semiconductor structure.

[0035] Refer to Figure 1, a semiconductor structure may include: a substrate 11; a base die 12 and a processor 13 respectively located on the surface of the substrate 11; a plurality of core dies 14 are stacked on the base die 12, and the core die 14 may be a DRAM chip. Refer to Figure 2 , during the data transmission process in the semiconductor structure, it includes: in the writing stage, the controller 13 transmits data to the base die 12, and the base die 12 transmits the data into the core die 14. Before transmitting the data, the controller 13 may first perform error correction code encoding processing on the data; in the reading stage, the core die 14 transmits the data to the base die 12, and then the base die 12 transmits the data to the controller 13. The controller 13 receives the data and performs error correction code decoding processing to detect and correct errors in the data.

[0036] It is not difficult to find that in the above semiconductor structure, the base die 12 does not participate in the error detection and correction processing, that is, there is no error correction code encoding function and corresponding error detection and correction function in the base die 12. The controller 13 or the core die 14 needs to complete the error detection, which makes the chip areas of the controller 13 and the core die 14, where the chip area is already tight, even more tense. Therefore, the performance of the controller 13 and the core die 14 is affected, and further the storage performance of the entire semiconductor structure needs to be improved.

[0037] The present application provides a base die, a storage system, and a semiconductor structure, and the base die has an error detection and correction function. Figure 3 It is the first structural schematic diagram of the base die provided by some embodiments of the present application. Figure 4 It is the second structural schematic diagram of the base die provided by some embodiments of the present application. Figure 5 It is the third structural schematic diagram of the base die provided by the embodiments of the present application. Figure 6 It is the fourth structural schematic diagram of the base die provided by the embodiments of the present application. Figure 7 It is the fifth structural schematic diagram of the base die provided by the embodiments of the present application. Figure 8 It is the sixth structural schematic diagram of the base die provided by the embodiments of the present application. Figure 9 It is the seventh structural schematic diagram of the base die provided by the embodiments of the present application.

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will elaborate on each embodiment of the present application with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0039] Reference Figure 3 The basic chip 100 is applied to a storage system. In the write stage, the basic chip 100 is configured to receive a first data data1 and a first encoded data ecc1 and perform a first error detection and correction process. The first encoded data ecc1 is obtained by encoding the first data data1 with a first error correction code (ECC, Error Correction Code). In the write stage, the basic chip 100 transmits a second data data2 to the storage chip. The second data data2 includes the first data data1 after the first error detection and correction process. The basic chip 100 is further configured to, in the read stage, receive the second data data2 from the storage chip and perform a second error correction code encoding process on the second data data2 to generate a second encoded data ecc2, and transmit a third data data3 in the read stage. The third data data3 includes the second encoded data ecc2 and the first data data1 after the first error detection and correction process.

[0040] In the embodiments of the present application, the basic chip 100 participates in the error correction code encoding process and the error detection and correction process during data transmission.

[0041] In some embodiments, the basic chip 100 may be connected between a first port A and a second port B. The first port A is connected to the data transmission port of the controller of the storage system, and the second port B is connected to the data transmission port of the storage chip of the storage system. It can be understood that the first port A and the second port B are general terms. The first port A includes multiple data transmission ports, and the second port B includes multiple data transmission ports. The number of data transmission ports is related to the number of data to be transmitted by the basic chip 100. For example, the number of data transmission ports may be the same as the number of data to be transmitted by the basic chip 100, and one data can be transmitted through one data transmission port.

[0042] Both the error correction code encoding process and the error detection and correction process are used to implement ECC error detection and correction to detect and locate the errors occurring in the first data transmission process and correct the errors. In some embodiments, the ECC error detection and correction may adopt the error correction mechanism of Reed Solomon code (RS). Correspondingly, the error correction code encoding process may adopt the RS encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process may adopt the RS decoding algorithm. In other embodiments, the ECC error detection and correction may adopt the error correction mechanism of Hamming code. Correspondingly, the error correction code encoding process may adopt the Hamming code encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process may adopt the Hamming code decoding algorithm.

[0043] In some embodiments, the first data data1 may be data of 256 bits, and correspondingly, the first encoded data ecc1 may be data of 16 bits. It can be understood that in other embodiments, due to the difference in the specific algorithm used for error correction code encoding processing, the number of bits of the first encoded data may also be correspondingly different. In addition, the number of bits of the first data data1 may also be other quantities, such as 128, 512, etc.

[0044] In addition, in some embodiments, the basic chip 100 may also be configured to generate a first error detection flag signal during error detection and correction processing, and record the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process based on the first error detection flag signal. Specifically, if an error occurs in the first data data1 or the first encoded data ecc1 during the transmission process, a first error detection flag signal is generated; if no error occurs in the first data data1 and the first encoded data ecc1 during the transmission process, the first error detection flag signal is not generated. In addition, in some embodiments, the first error detection flag signal may be defined as follows: if an error occurs in the first data data1 or the first encoded data ecc1 during the transmission process, the first error detection flag signal is 1; if no error occurs in the first data data1 and the first encoded data ecc1 during the transmission process, the first error detection flag signal is 0. In other embodiments, the first error detection flag signal may also be defined as follows: if an error occurs in the first data data1 or the first encoded data ecc1 during the transmission process, the first error detection flag signal is 0; if no error occurs in the first data data1 and the first encoded data ecc1 during the transmission process, the first error detection flag signal is 1.

[0045] As Figure 4 shown, in some embodiments, the basic chip 100 may further include: a first storage buffer module 101, which is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process; a first command module 102, which receives a first polling instruction PS1 and generates a first command signal CMD1 and a first clock signal CLK1; the first storage buffer module is further configured to output a first characterization signal flag1 based on the first command signal CMD1 and the first clock signal CLK1, and the first characterization signal flag1 characterizes the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process.

[0046] It can be understood that the above-mentioned error conditions of the first data data1 and the first encoded data ecc1 during the transmission process refer to the error conditions during the transmission process from the controller to the basic chip 100 of the first data data1 and the first encoded data ecc1.

[0047] In addition, in the case where the first round of polling instruction PS1 is not received, the first storage buffer module 101 only stores the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process; after the first command module 102 receives the first round of polling instruction PS1, it controls the first storage buffer module 101 to output a first representation signal flag1 indicating the error conditions of the first data data1 or the first encoded data ecc1 during the transmission process. Based on the first representation signal flag1, the error conditions of the first data data1 and the first encoded data ecc1 can be obtained.

[0048] In some embodiments, the first representation signal flag1 can be a binary string. For example, if an error is detected in the transmission of the first data data1 or the first encoded data ecc1, 1 is recorded; if no error is detected in the transmission of the first data data1 and the first encoded data ecc1, 0 is recorded. Thus, after a period of time, the first representation signal flag1 is a binary string composed of 0 and 1. In other embodiments, the first representation signal flag1 can also be a decimal value. For example, the first storage buffer module 101 can be a counter, and if an error is detected in the transmission of the first data data1, it is incremented by 1. Thus, after a period of time, the first representation signal flag1 is a decimal value related to the number of errors.

[0049] In some embodiments, the first storage buffer module 101 can be a first-in, first-out (FIFO, First Input First Output) register. Using a first-in, first-out register as the first storage buffer module 101 can cache continuous data streams to prevent data loss during storage operations; in addition, the error conditions of the first data data1 during the transmission process are centralized for stacking and storage, which can avoid frequent bus operations and is beneficial to improving the data transmission speed.

[0050] In addition, in some embodiments, the first clock signal CLK1 can be independently generated by the first command module 102; in other embodiments, the first clock signal CLK1 can also be externally provided, such as being generated by the controller that generates the first round of polling instruction PS1.

[0051] Figure 5 This is the third structural schematic diagram of the basic chip provided by the embodiments of the present application. Refer to Figure 5, in some embodiments, the base chip 100 may include: a first error detection and correction module 110, configured to receive a first data data1 and a first encoded data ecc1 during the write phase and perform a first error detection and correction process; a second encoding module 120, configured to receive the first data data1 after the first error detection and correction process during the read phase and perform a second error correction code encoding process to generate a second encoded data ecc2.

[0052] Since the first error detection and correction module 110 and the second encoding module 120 are separate modules respectively, it is beneficial to further improve the independence between the encoding operation and the decoding operation, and avoid the problem of data crosstalk. It should be noted that the "first", "second", and "third" in the embodiments of the present application are only for descriptive distinction, and there is no special limitation on the order of appearance of the corresponding features.

[0053] Among them, the first error correction code encoding process may adopt Hamming code encoding operation or RS code encoding operation. Correspondingly, the first error detection and correction module 110 may adopt Hamming code decoding operation or RS code decoding operation. The second encoding module 120 may adopt Hamming code encoding operation or RS code encoding operation. In some embodiments, the first error detection and correction module 110 may receive the first data data1 and the first encoded data ecc1 from the controller, perform a first error detection and correction process on the first data data1, and then transmit a second data data2 to the storage chip. The second data data2 is the first data data1 after the first error detection and correction process; the second encoding module 120 may receive the second data data2 from the storage chip, perform a second error correction code encoding process on the second data data2 to obtain a second encoded data ecc2, and transmit the second encoded data ecc2 and the first data data1 after the first error detection and correction process to the controller, so that the controller can continue to perform error detection and correction on the first data data1 after the first error detection and correction process by using the second encoded data ecc2.

[0054] Figure 6 This is the fourth structural schematic diagram of the base chip provided in the embodiments of the present application. Refer to Figure 6, in some embodiments, in addition to the first error detection and correction module 110 and the second encoding module 120, the base chip 100 may further include: a first serial-to-parallel conversion (DES, DESerializer) module 130, which is configured to receive the first data data1 and the first encoded data ecc1 during the write phase, perform a first serial-to-parallel conversion process on the first data data1 and the first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 after the first serial-to-parallel conversion process to the first error detection and correction module 110; a first parallel-to-serial conversion (SER, SERlializer) module 140, which is configured to receive the third data data3 from the second encoding module 120 during the read phase, perform a first parallel-to-serial conversion process on the third data data3, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller.

[0055] The settings of the first serial-to-parallel conversion module 130 and the first parallel-to-serial conversion module 140 can reduce the number of transmission channels between the base chip 100 and the controller, and increase the number of bits transmitted per transmission channel; in addition, since the number of transmission channels is reduced, the number of data transmission ports required to be set on the base chip 100 and the controller can be saved, thereby saving the chip area of the base chip 100 and the chip area of the controller. The first data data1 is transmitted to the first serial-to-parallel conversion module 130 in a serial manner, and the first serial-to-parallel conversion module 130 can also be referred to as a deserialization device, that is, deserializing the serial first data data1 and the first encoded data ecc1. The first parallel-to-serial conversion module 140 performs serial processing on the third data data3 and transmits the third data data3 after the serial processing. The first parallel-to-serial conversion module 140 can also be referred to as a serializer.

[0056] For example, if the first data data1 is 256 bits, the first data data1 is transmitted to the first serial-to-parallel conversion module 130 through 32 transmission channels. If the first encoded data ecc1 is 16 bits, the first encoded data ecc1 is transmitted to the first serial-to-parallel conversion module 130 through 2 transmission channels. After the first data data1 and the first encoded data ecc1 are deserialized by the first serial-to-parallel conversion module 130, the first data data1 is transmitted to the first error detection and correction module 110 in parallel through 256 transmission channels, and the first encoded data ecc1 is transmitted to the first error detection and correction module 110 through 16 transmission channels. The third data is 256 bits + 16 bits, where 256 bits is the first data after the first error detection and correction process, and 16 bits is the second encoded data ecc2. After the third data datat3 is serially processed by the first parallel-to-serial conversion module 140, it can be changed into 32 + 2 string data, and the 32 + 2 string data can be transmitted through 32 + 2 transmission channels. Among them, 32 string data is the first data data1 after the first error detection and correction process, and 2 string data is the second encoded data ecc2.

[0057] Figure 7 This is the fifth structural schematic diagram of the basic chip provided in the embodiment of the present application. Refer to Figure 7 , in some embodiments, in addition to the first error detection and correction module 110, the second encoding module 120, the first serial-to-parallel conversion module 130, and the first parallel-to-serial conversion module 140, the basic chip 100 may further include: a second parallel-to-serial conversion module 150, which is configured to receive the second data data2 and perform a second parallel-to-serial conversion process during the write phase, and transmit the second data data2 after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module 160, which is configured to receive the second data data2 from the storage chip and perform a second serial-to-parallel conversion process during the read phase, and transmit the second data data2 after the second serial-to-parallel conversion process to the second encoding module 120.

[0058] The second parallel-to-serial conversion module 150 performs serial processing on the second data data2, which is beneficial to reducing the transmission channels between the basic chip 100 and the storage chip, thereby saving the number of data transmission ports required on the basic chip 100 and the storage chip, and further saving the chip area of the basic chip 100 and the chip area of the storage chip. For example, the second data data2 may include the first data data1 of 256 bits after the first error detection and correction process. After the parallel-to-serial conversion process by the second parallel-to-serial conversion module 150, the second data data2 can be transmitted to the storage chip through 128 transmission channels.

[0059] The second serial-to-parallel conversion module 160 performs parallel processing on the second data data2 transmitted from the storage chip, that is, performs serial-to-parallel processing on the second data data2, and the second data data2 after the serial-to-parallel processing is transmitted to the second encoding module 120. For example, the second serial-to-parallel conversion module 160 can convert the second data data2 of 128 strings into parallel data of 256 bits.

[0060] Figure 8 This is the sixth structural schematic diagram of the basic chip provided by the embodiment of the present application. In some other embodiments, referring to Figure 8 , the basic chip 100 can also be configured to perform third error correction code encoding processing on the first data data1 after the first error detection and correction processing during the writing stage to generate third encoded data ecc3, and the second data data2 also includes the third encoded data ecc3; during the reading stage, before performing the second error correction code encoding processing, it further includes performing second error detection and correction processing on the second data data2. The first data data1 included in the third data data3 after the first error detection and correction processing is the first data data1 after the second error detection and correction processing.

[0061] In this way, the second data data2 includes both the first data data1 after the first error detection and correction processing and the third encoded data ecc3. Through the first error detection and correction processing, the transmission process of the first data data1 and the first encoded data ecc1 from the controller to the basic chip 100 can be error-detected, and if a data error occurs, the error can be corrected; and through the second error detection and correction processing, the transmission process of the second data data2 between the basic chip 100 and the storage chip can be error-detected, and if a data error occurs, the error can also be corrected. It can be understood that the transmission process of the second data data2 between the basic chip 100 and the storage chip includes the writing stage when the second data data2 is transmitted from the basic chip 100 to the storage chip, and the reading stage when the second data data2 is transmitted from the storage chip to the basic chip 100. In this way, the data transmission of at least 2 transmission paths can be error-detected and corrected, which is beneficial to locating the specific path where the data transmission goes wrong, and at least two error detection and correction processes are beneficial to improving the correct rate of data error correction.

[0062] In addition, it can be understood that the first error correction code encoding process and the third error correction code encoding process can adopt different encoding algorithms. For example, the first encoded data ecc1 can be 16-bit data, and the third encoded data ecc3 can be 32-bit data. Correspondingly, the first error detection and correction process and the second error detection and correction process can adopt different decoding algorithms, that is, the first error correction code encoding process and the first error detection and correction process adopt the first compilation algorithm, and the third error correction code encoding process and the second error detection and correction process adopt the second compilation algorithm. The first compilation algorithm and the second compilation algorithm can be different. Using different compilation algorithms for ECC error detection is beneficial to further improve the correct rate of data error correction and reduce the difficulty for the basic chip 100 to identify different encoded data. In some other embodiments, the first compilation algorithm and the second compilation algorithm can also be the same.

[0063] Reference Figure 8 , in addition to the first error detection and correction module 110 and the second encoding module 120, the basic chip 100 may further include: a third encoding module 111, which is configured to receive the first data data1 after the first error detection and correction process during the writing stage and perform a third error correction code encoding process to generate the third encoded data ecc3. Correspondingly, the second data data2 includes the first data data1 after the first error detection and correction process and the third encoded data ecc3; a second error detection and correction module 121, which is configured to receive the second data data2 and perform a second error detection and correction process during the reading stage.

[0064] The third encoding module 111 is connected between the first error detection and correction module 110 and the storage chip, and the second error detection and correction module 121 is connected between the storage chip and the second encoding module 120. The second error detection and correction module 121 receives the third encoded data ecc3 and the first data data1 after the first error detection and correction process, and performs a second error detection and correction process on the third encoded data ecc3 and the first data data1 after the first error detection and correction process.

[0065] The setting of the second error detection and correction module 121 is beneficial to detecting whether the data is in error during the process of being transmitted from the storage chip to the basic chip 100 during the reading stage and correcting the erroneous data, which is beneficial to further improving the data error detection and correction ability.

[0066] Figure 9 This is the seventh structural schematic diagram of the basic chip provided by the embodiment of the present application. Reference Figure 9 , in some embodiments, the first error detection and correction module 110 may further generate a first error detection flag signal during the first error detection and correction process. Continue to refer to Figures 4 to 7 And Figure 9, in some embodiments, the base chip 100 may further include: a first storage buffer module 101 configured to store the error condition of the first data data1 during transmission; a first command module 102 that receives a first polling instruction PS1 and generates a first command signal CMD1 and a clock signal CLK1; the first storage buffer module 101 is further configured to output a first characterization signal flag1 based on the first command signal CMD1 and the first clock signal CLK1, and the first characterization signal flag1 characterizes the error condition of the first data data1 or the first encoded data ecc1 during transmission.

[0067] For a detailed description of the first storage buffer module 101 and the first command module 102, reference may be made to the corresponding description in the foregoing embodiments, which will not be repeated here. Specifically, the first storage buffer module 101 is connected to the first error detection and correction module 110.

[0068] Figure 10 This is the eighth structural schematic diagram of the base chip provided by the embodiments of the present application. Refer to Figure 10 , in some embodiments, the base chip 100 may further include: a first serial-to-parallel conversion module 130 and a first parallel-to-serial conversion module 140. For a detailed description of the first serial-to-parallel conversion module 130 and the first parallel-to-serial conversion module 140, reference may be made to the foregoing description, which will not be repeated here. In addition, refer to Figure 9 , in some embodiments, the base chip 100 may further include: a second parallel-to-serial conversion module 150 and a second serial-to-parallel conversion module 160; wherein, the second parallel-to-serial conversion module 150 is connected between the third encoding module 111 and the storage chip. In addition to performing parallel-to-serial conversion on the first data data1 after the first error detection basic processing, the second parallel-to-serial conversion module 150 also performs parallel-to-serial conversion on the third encoded data ecc3; the second serial-to-parallel conversion module 160 is connected between the storage chip and the second error detection and correction module 121, and the second serial-to-parallel conversion module 160 performs serial-to-parallel conversion on the third encoded data ecc3 transmitted from the storage chip and the first data data1 after the first error detection and correction processing.

[0069] For the description of the first serial-to-parallel conversion module 130, the first parallel-to-serial conversion module 140, the second serial-to-parallel conversion module 160, and the second parallel-to-serial conversion module 150, reference may be made to the foregoing detailed description, which will not be repeated here. It can be understood that, in some embodiments, the base chip 100 includes the first serial-to-parallel conversion module 130 and the first parallel-to-serial conversion module 140; in other embodiments, the base chip 100 includes the first serial-to-parallel conversion module 130, the first parallel-to-serial conversion module 140, the second parallel-to-serial conversion module 150, and the second serial-to-parallel conversion module 160.

[0070] In some embodiments, the base chip 100 may also be configured to generate a second error detection flag signal during the second error detection and correction process, and based on the second error detection flag signal, record the error situation of the third encoded data ecc1 and the first data data1 after the first error detection and correction process during transmission, that is, record the error situation of the second data data2 during transmission. Specifically, the transmission paths involved in the transmission of the second data data2 during transmission include the transmission from the third encoding module 111 to the storage chip during the writing stage, and the transmission from the storage chip to the second error detection and correction module 121 during the reading stage.

[0071] Based on the second error detection flag signal, it is convenient to view the error situation of the third encoded data ecc1 and the first data data1 after the first error detection and correction process during transmission.

[0072] Reference Figure 9 and Figure 10 In some embodiments, the base chip 100 may further include: a second storage buffer module 131, which is configured to store the error situation of the third encoded data ecc3 and the first data data1 after the first error detection and correction process during transmission; a second command module 132, which receives the second polling instruction PS2 and generates a second command signal CMD2 and a second clock signal CLK2; the second storage buffer module 131 is further configured to output a second characterization signal flag2 based on the second command signal CMD2 and the second clock signal CLK2, and the second characterization signal flag2 characterizes the error situation of the third encoded data ecc3 and the first data data1 after the first error detection and correction process during transmission.

[0073] Specifically, the second storage buffer module 131 is connected to the second error detection and correction module 121.

[0074] For a detailed description of the second storage buffer module, reference may be made to the foregoing description of the first storage buffer module. For a detailed description of the second command module, reference may be made to the foregoing description of the first command module, and details are not described herein again.

[0075] The base chip 100 provided in the above embodiments not only has the function of data transmission, but also has the functions of error correction code encoding processing and error detection and correction processing. In this way, the chip area of the base chip 100 can be effectively utilized, reducing the chip area pressure on the controller and the storage chip, and saving the chip area of the controller and the storage chip.

[0076] In addition, the basic chip 100 may also have the functions of data serial processing and deserialization processing, which is beneficial to reducing the transmission channels between the controller and the basic chip 100 and between the storage chip and the basic chip 100, thereby saving the number of data transmission ports required on the controller, the basic chip 100, and the storage chip, and further saving the chip areas of the controller, the basic chip 100, and the storage chip.

[0077] In addition, both the first error detection and correction module 110 and the second error detection and correction module 121 can perform error detection and correction on data, which is beneficial to improving the data error detection and correction ability and can locate the transmission path where the data goes wrong.

[0078] Another embodiment of the present application further provides a storage system, which includes a controller, a storage chip, and a basic chip as provided in the foregoing embodiment. The storage system provided in another embodiment of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiment, reference may be made to the detailed description of the foregoing embodiment, which will not be repeated below.

[0079] Figure 11 It is a schematic diagram of the first structure of the storage system provided in the embodiment of the present application.

[0080] Reference Figure 11, the storage system includes: a base chip 200, a controller 300, and a storage chip 400; the controller 300 is configured to perform a first error correction code encoding process on the first data data1 during the write phase to generate first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 to the base chip 200; the base chip 200 is configured to receive the first data data1 and the first encoded data ecc1 during the write phase and perform a first error detection and correction process, and transmit second data data2 to the storage chip 400 during the write phase, where the second data data2 includes the first data data1 after the first error detection and correction process; the base chip 200 is further configured to receive the second data data2 from the storage chip 400 during the read phase and perform a second error correction code encoding process to generate second encoded data ecc2, and transmit third data data3 to the controller 300 during the read phase, where the third data data3 includes the second encoded data ecc2 and the first data data1 after the first error detection and correction process; the storage chip 400 is configured to receive the second data data2 from the base chip 200 during the write phase and store the second data data2, and transmit the second data data2 to the base chip 200 during the read phase; the controller 300 is further configured to receive the third data data3 from the storage chip 200 during the read phase, perform a third error detection and correction process on the third data data3, and obtain the first data data1 after the third error detection and correction process.

[0081] In the above storage system, the error correction code encoding process and the error detection and correction process performed on the data are both implemented by the base chip 200. Thus, the storage chip 400 does not need to perform the encoding process and the error detection and correction process, and the base chip 200 can share the encoding process and the error detection and correction process required by the controller 300, so that the functions required by the controller 300 and the storage chip 400 are relatively reduced. Therefore, the pressure on the tight chip area of the controller 300 and the storage chip 400 can be relieved, so as to better improve the performance of the controller 300 and the storage chip 400. For example, the reliability of the storage chip 400 can be improved, thereby enhancing the storage performance of the storage system.

[0082] In some embodiments, the storage system may be a DRAM storage system, such as a DDR (double data rate) 4 DRAM storage system or a DDR5 DRAM storage system. In other embodiments, the storage system may also be an SRAM (Static Random-Access Memory) storage system, a NAND storage system, a NOR storage system, a FeRAM storage system, or a PcRAM storage system.

[0083] The controller 300 may include: a first encoding module 301 configured to perform a first error correction code encoding process on the first data data1 during a write phase to generate first encoded data ecc1; and a third error detection and correction module 302 configured to receive third data data3 and perform a third error detection and correction process during a read phase.

[0084] The base chip 200 can provide a high-speed interface for data transmission in the storage system. In addition, the base chip 200 is also used to manage and control the storage chip 400. In some embodiments, the base chip 200 can be used to monitor and manage the temperature of the storage chip 400, and can also be used to perform a Memory Build-In-Self Test (MBIST) and self-repair on the storage chip 400. In addition, the base chip 200 is also used to perform error detection and correction on the transmitted data.

[0085] Figure 12 This is the second structural schematic diagram of the storage system provided by the embodiments of the present application. Refer to Figure 12 In some embodiments, the base chip 200 may include: a first error detection and correction module 210 configured to receive the first data data1 and the first encoded data ecc1 and perform a first error detection and correction process during a write phase; and a second encoding module 220 configured to receive the first data data1 after the first error detection and correction process and perform a second error correction code encoding process to generate second encoded data ecc2 during a read phase.

[0086] Specifically, the first error detection and correction module 210 is connected between the data transmission port of the controller 300 and the data transmission port of the storage chip 400, and the second encoding module 220 is connected between the data transmission port of the controller 300 and the data transmission port of the storage chip 400. Since the second data data2 does not include encoded data, the storage chip 400 may include a storage module for storing the first data after the first error detection and correction process, and there is no need to design an encoding module for storing the encoded data, which is beneficial to saving the area of the storage chip 400 and reducing the design difficulty of the storage chip 400.

[0087] The following will take the first data data1 as 256 bits and the first encoded data ecc1 as 16 bits as an example to illustrate Figure 12 the working principle of the storage system shown:

[0088] In the writing stage, the controller 300 transmits 256-bit first data data1 and 16-bit first encoded data ecc1 to the first error detection and correction module 210; the first error detection and correction module 210 receives the 256-bit first data data1 and 16-bit first encoded data ecc1 and performs first error detection and correction processing, outputting the 256-bit first data data1 after the first error detection and correction processing, and the 256-bit first data data1 after the first error detection and correction processing constitutes the second data data2. Specifically, if no error occurs in the 256-bit first data data1, the 256-bit first data data1 is transmitted to the storage chip 400; if an error occurs in the 256-bit first data data1, error correction processing is performed on the bit positions where the error occurs, and the 256-bit first data data1 after the error correction processing is transmitted to the storage chip 400.

[0089] In the reading stage, the storage chip 400 transmits the second data data2 to the second encoding module 220, and the second encoding module 220 performs second error correction code encoding processing to generate 16-bit second encoded data ecc2, and transmits the 256-bit first data data1 and 16-bit second encoded data ecc2 to the controller 300.

[0090] In the above solution, there is no need to design a storage module for storing encoded data in the storage chip 400, which is beneficial to saving the chip area of the storage chip 400. In addition, both the basic chip 200 and the controller 300 have error detection and correction processing functions, and the dual error detection and correction processing is beneficial to improving the data error detection and correction ability.

[0091] Figure 13 This is the third structural schematic diagram of the storage system provided by the embodiment of the present application. Refer to Figure 13 , in some embodiments, in addition to including the first error detection and correction module 210 and the second encoding module 220, the basic chip 200 is further configured to perform third error correction code encoding processing on the first data data1 after the first error detection and correction processing in the writing stage to generate third encoded data ecc3, and the second data data2 further includes the third encoded data ecc3; in the reading stage, before performing the second error correction code encoding processing, it further includes performing second error detection and correction processing on the second data data2, and the first data data1 included in the third data data3 after the first error detection and correction processing is the first data data1 after the second error detection and correction processing.

[0092] In this way, the second data data2 includes both the first data after the first error detection and correction processing and the third encoded data ecc3. Correspondingly, refer toFigure 13 The storage chip 400 includes: a first storage module 410 for storing the first data data1 after the first error detection and correction process; and a second storage module 420 for storing the third encoded data ecc3.

[0093] Correspondingly, referring to Figure 13 the base chip 200 may further include: a third encoding module 211 configured to receive the first data data1 after the first error detection and correction process and perform a third error correction code encoding process during the writing stage to generate the third encoded data ecc3; and a second error detection and correction module 221 configured to receive the second data data2 and perform a second error detection and correction process during the reading stage.

[0094] In some embodiments, the first error correction code encoding process, the second error correction code encoding process, the first error detection and correction process, and the third error detection and correction process are performed using a first compilation algorithm, and the third error correction code encoding process and the second error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm. Using different compilation algorithms for error detection and correction of data is beneficial to further improve the accuracy of error detection and correction of data. Specifically, the encoding algorithms used by the third encoding module 211 and the first encoding module 301 may be different, the encoding algorithms used by the third encoding module 211 and the second encoding module 220 may be different, and the decoding algorithms used by the first error detection and correction module 210 and the second error detection and correction module 221 may be different.

[0095] Figure 14 and Figure 15 is the fourth structural schematic diagram of the storage system provided by the embodiments of the present application. Referring to Figure 14 and Figure 15 in some embodiments, the base chip 200 may further include: a first serial-to-parallel conversion module 230 configured to receive the first data data1 and the first encoded data ecc1 and perform a first serial-to-parallel conversion process on the first data data1 and the first encoded data ecc1 during the writing stage, and transmit the first data data1 and the first encoded data ecc1 after the first serial-to-parallel conversion process to the first error detection and correction module 210; and a first parallel-to-serial conversion module 240 configured to receive the third data data3 from the second encoding module 220 and perform a first parallel-to-serial conversion process on the third data data3 during the reading stage, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller 300.

[0096] Specifically, the first serial-parallel conversion module 230 is connected between the data transmission port of the controller 300 and the data transmission port of the first error detection and correction module 210, and the first parallel-serial conversion module 240 is connected between the data transmission port of the controller 300 and the data transmission port of the first error detection and correction module 210. In this way, the number of transmission channels between the controller 300 and the base chip 200 can be less than the number of bits of the first data data1, thereby saving the number of transmission channels between the controller 300 and the base chip 200, and saving the number of data transmission ports that need to be set on the base chip 200 and the controller 300, which is beneficial to reducing the complexity of the electrical connection structure between the controller 300 and the base chip 200 and saving the chip areas of the controller 300 and the base chip 200. The following will take the first data data1 as 256 bits and the first encoded data as 16 bits as an example to Figure 14 illustrate the working principle of the storage system shown. It should be noted that the first error detection and correction module 210 and the second encoding module 220 will not be described in detail below:

[0097] In the writing stage, there can be 32 + 2 transmission channels between the controller 300 and the first error detection and correction module 210. The 256-bit first data data1 is transmitted to the first serial-parallel conversion module 230 through 32 transmission channels for serial-to-parallel processing, and the 16-bit first encoded data ecc1 is transmitted to the first serial-parallel conversion module 230 through 2 transmission channels for serial-to-parallel processing. The first serial-parallel conversion module 230 outputs the 256-bit first data data1 and the 16-bit first encoded data ecc1 for parallel transmission. The first data data1 and the first encoded data ecc1 are transmitted to the first error detection and correction module 210 for the first error detection and correction process and then continue to be transmitted to the storage chip 400. In the reading stage, the 256-bit first data and the 16-bit second encoded data ecc2 output by the second encoding module 220 are transmitted to the first parallel-serial conversion module 240 for parallel-to-serial processing. The 256-bit first data data1 after parallel-to-serial processing can be transmitted to the controller 300 through 32 transmission channels, and the 16-bit second encoded data ecc2 after parallel-to-serial processing can be transmitted to the controller 300 through 2 transmission channels.

[0098] It can be understood that in other embodiments, the number of transmission channels between the controller 300 and the first error detection and correction module 210 can also be other appropriate numbers, such as 128, 64, or 16, etc.

[0099] Refer to Figure 14 and Figure 15, the base chip 200 may further include: a second parallel-to-serial conversion module 250, configured to receive the second data data2 during the writing phase and perform a second parallel-to-serial conversion process, and transmit the second data data2 after the second parallel-to-serial conversion process to the storage chip 400; a second serial-to-parallel conversion module 260, configured to receive the second data data2 from the storage chip 400 during the reading phase and perform a second serial-to-parallel conversion process, and transmit the second data after the second serial-to-parallel conversion process to the second encoding module 220.

[0100] Reference Figure 14 , in some examples, the second parallel-to-serial conversion module 250 is connected between the data transmission port of the first error detection and correction module 210 and the data transmission port of the storage chip 400, and the second serial-to-parallel conversion module 260 is connected between the data transmission port of the storage chip 400 and the data transmission port of the second encoding module 220. Reference Figure 15 , in other examples, the second parallel-to-serial conversion module 250 is connected between the data transmission port of the storage chip 400 and the data transmission port of the third encoding module 211, and the second serial-to-parallel conversion module 260 is connected between the data transmission port of the storage chip 400 and the data transmission port of the second error detection and correction module 221.

[0101] In this way, the number of transmission channels between the storage chip 400 and the base chip 200 can be less than the number of bits of the first data data1, thereby saving the number of transmission channels between the storage chip 400 and the base chip 200, which is beneficial to reducing the number of data transmission ports required to be set on the base chip 200 and the storage chip 400, beneficial to reducing the complexity of the electrical connection structure between the storage chip 400 and the base chip 200, and saving the chip areas of the storage chip 400 and the base chip 200.

[0102] It can be understood that the number of data transmission channels between the controller 300 and the base chip 200 is M, and the number of data transmission channels between the base chip 200 and the storage chip 400 is N; where both M and N are positive integers greater than 1. In some embodiments, the second data includes the first data after the first error detection and correction process. Taking the first data as 256 bits and the first encoded data as 16 bits as an example, M can be 32 + 2, where 32 data transmission channels are used to transmit the first data, and 2 data transmission channels are used to transmit the first encoded data; the first data after the first error detection and correction process is 256 bits, and N can be 32, 64, or 128, and N data transmission channels are used to transmit the first data after the first error detection and correction process.

[0103] In some other embodiments, the second data includes, in addition to the first data after the first error detection and correction processing, third encoded data. Taking the first data as 256 bits, the first encoded data as 16 bits, and the third encoded data as 32 bits as an example, M can be 32 + 2, N can be 128 + 16. 32 data transmission channels in M are used to transmit the first data, 2 data transmission channels in M are used to transmit the first encoded data, 128 data transmission channels in N are used to transmit the first data after the first error detection and correction, and 6 data transmission channels in N are used to transmit the third data.

[0104] Reference Figures 12 to 15 , in some embodiments, the base chip 200 can also be configured to generate a first error detection flag signal during the first error detection and correction processing, and record the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process based on the first error detection flag signal; the storage system can also include: a first register 501, and the first register 501 is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process.

[0105] Specifically, with reference to Figures 12 to 15 , the base chip 200 can include: a first storage buffer module 201, and the first storage buffer module 201 is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process; a first command module 202, and the first command module 202 receives the first polling instruction PS1 and generates a first command signal CMD1 and a first clock signal CLK1; the first storage buffer module 201 is further configured to output a first characterization signal flag1 to the first register 500 based on the first command signal CMD1 and the first clock signal CLK1, and the first characterization signal flag1 characterizes the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process.

[0106] In some embodiments, the controller 300 can also be configured to issue the first polling instruction PS1 to the first command module 202, that is, the controller 300 periodically issues an inquiry to control the first storage buffer module 201 to output the first characterization signal flag1 to the first register 501. It can be understood that in other embodiments, the first polling instruction can also be provided by an external circuit.

[0107] Reference Figure 13 and Figure 15, in some embodiments, the base chip 200 may further be configured to generate a second error detection flag signal during the second error detection and correction process, and record the error situation of the first data data1 after the first error detection and correction process during transmission based on the second error detection flag signal flag2; the storage system may further include: a second register 502, which is configured to store the error situation of the first data data1 after the first error detection and correction process during transmission.

[0108] Reference Figure 13 and Figure 15 , in some embodiments, the base chip 200 may further include: a second storage cache module 251, which is configured to store the error situation of the first data data1 after the first error detection and correction process during transmission; a second command module 261, which receives a second polling instruction PS2 and generates a second command signal CMD2 and a second clock signal CLK2; the second storage cache module 251 is further configured to output a second characterization signal flag2 to the second register 502 based on the second command signal CMD2 and the second clock signal CLK2, and the second characterization signal flag2 characterizes the error situation of the first data data1 after the first error detection and correction process during transmission.

[0109] Reference Figure 13 and Figure 15 , in some embodiments, the controller 300 may further be configured to generate a third error detection flag signal during the third error detection and correction process, and record the error situation of the first data data1 after the second error detection and correction process during transmission based on the third error detection flag signal; the storage system may further include: a third register 503, which is configured to store the error situation of the first data data1 after the second error detection and correction process during transmission.

[0110] Reference Figure 13 and Figure 15 , in some embodiments, the controller 300 may further include: a third storage cache module 271, which is configured to store the error situation of the first data after the second error detection and correction process during transmission; a third command module 281, which receives a third polling instruction PS3 and generates a third command signal CMD3 and a third clock signal CLK3; the third storage cache module 271 is further configured to output a third characterization signal flag3 to the third register 503 based on the third command signal CMD3 and the third clock signal CLK3, and the third characterization signal flag3 characterizes the error situation of the first data data1 after the second error detection and correction process during transmission.

[0111] It can be understood that the first register 501, the second register 502, and the third register 503 can be the same register.

[0112] In the storage system provided by the above embodiment, the base chip 200 can implement error detection and correction functions. Correspondingly, the storage chip 400 does not need to have error detection and correction functions, and the base chip 200 can share the error detection and correction functions originally borne by the controller 300. Therefore, it is beneficial to save the space area of the controller 300 and the storage chip 400, improve the storage performance of the storage chip 400, and thus improve the storage performance of the storage system.

[0113] In addition, the settings of the first error detection and correction module 210, the second error detection and correction module 221, and the third error detection and correction module 302 enable error detection and correction to be performed on different data transmission paths, improve the error detection and correction ability of the storage system, and are beneficial to locating the specific data transmission path where the error occurs.

[0114] Correspondingly, the embodiment of the present application also provides a semiconductor structure, which may include the storage system provided by the above embodiment. The semiconductor structure provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, which will not be repeated below.

[0115] Figure 16 It is a schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiment of the present application.

[0116] Referring to Figure 16 , the semiconductor structure includes: a carrier substrate 600; the storage system provided by the foregoing embodiment, and both the controller 300 and the base chip 200 are located on the surface of the carrier substrate 600, and the storage chip 400 is located on the surface of the base chip 200 away from the carrier substrate 600.

[0117] Among them, the semiconductor structure may include a plurality of storage chips 400 stacked in sequence. The semiconductor structure may be a memory such as a DRAM device or an SRAM device.

[0118] In some embodiments, the carrier substrate 600 may be a PCB (Printed Circuit Board) circuit board. For a detailed description of the storage system, reference may be made to the foregoing embodiments, which will not be repeated here.

[0119] The semiconductor structure may be a 2.5D (dimensions) device, that is, the semiconductor structure is a stacked structure, which is beneficial to saving the size in the horizontal direction, and using the base chip 200 in the semiconductor structure to implement the ECC error detection and correction function is beneficial to improving the performance of the semiconductor structure.

[0120] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present application. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A basic chip is applied to a storage system. It is characterized in that it includes: The basic chip is configured to receive first data and first encoded data in a write phase and perform first error detection and correction processing. The first encoded data is obtained by performing first error correction code encoding processing on the first data. In the write phase, the basic chip transmits second data to a storage chip. The second data includes the first data after the first error detection and correction processing. The basic chip is further configured to receive the second data from the storage chip in a read phase and perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the read phase. The third data includes the second encoded data and the first data after the first error detection and correction processing. The basic chip includes: A first error detection and correction module, which is configured to receive the first data and the first encoded data in the write phase and perform the first error detection and correction processing. A second encoding module, which is configured to receive the first data after the first error detection and correction processing in the read phase and perform the second error correction code encoding processing to generate the second encoded data. The basic chip is further configured to perform third error correction code encoding processing on the first data after the first error detection and correction processing in the write phase to generate third encoded data, and the second data further includes the third encoded data. In the read phase, before performing the second error correction code encoding processing, the basic chip further includes performing second error detection and correction processing on the second data. The first data after the first error detection and correction processing included in the third data is the first data after the second error detection and correction processing. The basic chip further includes: A third encoding module, which is configured to receive the first data after the first error detection and correction processing in the write phase and perform the third error correction code encoding processing to generate the third encoded data. A second error detection and correction module, which is configured to receive the second data in the read phase and perform the second error detection and correction processing.

2. The basic chip according to claim 1, It is characterized in that the basic chip further includes: A first serial-to-parallel conversion module, which is configured to receive the first data and the first encoded data in a write phase, perform first serial-to-parallel conversion processing on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion processing to the first error detection and correction module. A first parallel-to-serial conversion module, which is configured to receive the third data from the second encoding module in a read phase, perform first parallel-to-serial conversion processing on the third data, and transmit the third data after the first parallel-to-serial conversion processing to a controller.

3. The basic chip according to claim 2, It is characterized in that the base chip further includes: a second parallel-to-serial conversion module, which is configured to receive the second data during the writing phase, perform a second parallel-to-serial conversion process on the second data, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module, which is configured to receive the second data from the storage chip during the reading phase, perform a second serial-to-parallel conversion process on the second data, and transmit the second data after the second serial-to-parallel conversion process to the second encoding module.

4. The base chip according to claim 1, It is characterized in that the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data and the first encoded data during the transmission process based on the first error detection flag signal.

5. The base chip according to claim 4, It is characterized in that the base chip further includes: a first storage buffer module, which is configured to store the error conditions of the first data and the first encoded data during the transmission process; a first command module, which receives a first polling instruction and generates a first command signal and a first clock signal; the first storage buffer module is further configured to output a first characterization signal based on the first command signal and the first clock signal, and the first characterization signal characterizes the error conditions of the first data and the first encoded data during the transmission process.

6. The base chip according to claim 1, It is characterized in that the base chip is further configured to generate a second error detection flag signal during the second error detection and correction process, and record the error conditions of the third encoded data and the first data after the first error detection and correction process during the transmission process based on the second error detection flag signal.

7. The base chip according to claim 6, It is characterized in that the base chip further includes: a second storage buffer module, which is configured to store the error conditions of the third encoded data and the first data after the first error detection and correction process during the transmission process; a second command module, which receives a second polling instruction and generates a second command signal and a second clock signal; the second storage buffer module is further configured to output a second characterization signal based on the second command signal and the second clock signal, and the second characterization signal characterizes the error conditions of the third encoded data and the first data after the first error detection and correction process during the transmission process.

8. A storage system, It is characterized in that it includes a controller, a base chip, and a storage chip, and further includes: the controller is configured to perform a first error correction code encoding process on the first data during the writing phase to generate first encoded data, and transmit the first data and the first encoded data to the base chip; The base chip is configured to receive the first data and the first encoded data during the write phase and perform a first error detection and correction process, and transmit second data to the storage chip during the write phase, where the second data includes the first data after the first error detection and correction process; The base chip is further configured to receive the second data from the storage chip during the read phase and perform a second error correction code encoding process on the second data to generate second encoded data, and transmit third data to the controller during the read phase, where the third data includes the second encoded data and the first data after the first error detection and correction process; The storage chip is configured to receive the second data from the base chip during the write phase and store the second data, and transmit the second data to the base chip during the read phase; The controller is further configured to receive the third data from the base chip during the read phase, perform a third error detection and correction process on the third data, and obtain the first data after the third error detection and correction process; The controller includes: A first encoding module configured to perform the first error correction code encoding process on the first data during the write phase to generate the first encoded data; A third error detection and correction module configured to receive the third data and perform the third error detection and correction process during the read phase; The base chip includes: A first error detection and correction module configured to receive the first data and the first encoded data and perform the first error detection and correction process during the write phase; A second encoding module configured to receive the first data after the first error detection and correction process and perform the second error correction code encoding process to generate the second encoded data during the read phase; The base chip is further configured to perform a third error correction code encoding process on the first data after the first error detection and correction process during the write phase to generate third encoded data, and the second data further includes the third encoded data; during the read phase, before performing the second error correction code encoding process, it further includes performing a second error detection and correction process on the second data, and the first data after the first error detection and correction process included in the third data is the first data after the second error detection and correction process; The storage chip includes: A first storage module for storing the first data after the first error detection and correction process; A second storage module for storing the third encoded data; The base chip further includes: A third encoding module configured to receive the first data after the first error detection and correction process and perform the third error correction code encoding process to generate the third encoded data during the write phase; A second error detection and correction module, which is configured to receive the second data and perform the second error detection and correction process during the reading stage.

9. The storage system according to claim 8, wherein, the first error correction code encoding process, the second error correction code encoding process, the first error detection and correction process, and the third error detection and correction process are performed using a first compilation algorithm, the third error correction code encoding process and the second error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm.

10. The storage system according to claim 8, wherein, the basic chip further includes: a first serial-to-parallel conversion module, which is configured to receive the first data and the first encoded data during the writing stage, perform a first serial-to-parallel conversion process on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion process to the first error detection and correction module; a first parallel-to-serial conversion module, which is configured to receive the third data from the second encoding module during the reading stage, perform a first parallel-to-serial conversion process on the third data, and transmit the third data after the first parallel-to-serial conversion process to the controller.

11. The storage system according to claim 10, wherein, the basic chip further includes: a second parallel-to-serial conversion module, which is configured to receive the second data during the writing stage and perform a second parallel-to-serial conversion process, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module, which is configured to receive the second data from the storage chip during the reading stage and perform a second serial-to-parallel conversion process, and transmit the second data after the second serial-to-parallel conversion process to the second encoding module.

12. The storage system according to claim 8, wherein, the basic chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data and the first encoded data during the transmission process based on the first error detection flag signal; the storage system further includes: a first register, which is configured to store the error conditions of the first data and the first encoded data during the transmission process.

13. The storage system according to claim 8, wherein, the basic chip is further configured to generate a second error detection flag signal during the second error detection and correction process, and record the error conditions of the first data after the first error detection and correction process during the transmission process based on the second error detection flag signal; the storage system further includes: a second register, which is configured to store the error conditions of the first data after the first error detection and correction process during the transmission process.

14. The storage system according to claim 8, wherein, The controller is further configured to generate a third error detection flag signal during the third error detection and correction process, and record the error condition of the first data after the second error detection and correction process during transmission based on the third error detection flag signal; The storage system further includes: A third register, which is configured to store the error condition of the first data after the second error detection and correction process during transmission.

15. A semiconductor structure, characterized in that, it includes: A carrier substrate; The storage system according to any one of claims 8-14, wherein the controller and the base chip are both located on the surface of the carrier substrate, and the storage chip is located on the surface of the base chip away from the carrier substrate.

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