Silicon wafers and epitaxial silicon wafers

Abstract

A silicon wafer is provided, wherein the dopant is phosphorus, the resistivity is 0.5 mΩ·cm to 1.2 mΩ·cm, and the carbon concentration is 3.0 × 10⁻⁶. 16 atoms / cm 3 Or even higher. The carbon concentration near the surface of a silicon wafer is reduced by 10% or more compared to the depth at the center of the wafer.

Description

Technical Field

[0001] This invention relates to silicon wafers and epitaxial silicon wafers. Background Technology

[0002] For example, before forming the silicon epitaxial layer, the epitaxial silicon wafer used for power MOS transistors is required to have extremely low silicon wafer resistivity. Therefore, in order to achieve a resistivity of 1.2 mΩ·cm or less, an epitaxial silicon wafer is provided on the surface of a phosphorus-doped silicon wafer on which the silicon epitaxial layer is formed.

[0003] In recent years, there has been a demand for n-type silicon wafers with extremely low resistivity of 0.9 mΩ·cm or less. However, when the resistivity of the silicon wafer is extremely low, stacking faults (SF) may be generated on the silicon epitaxial layer during the epitaxial growth process, and therefore, it is necessary to reduce the SF density in the silicon epitaxial layer.

[0004] As described in WO 2014 / 175120, the applicant of this application has discovered a technique to suppress the formation of SF in silicon epitaxial layers by adjusting the dwell time (thermal history) of the single crystal ingot at 570°C ± 70°C during single crystal growth (reducing the amount of dwell time in the temperature region where SF nuclei are formed). Furthermore, as described in Japanese Patent Publication No. 2014-011293, it has been found that the formation of SF in silicon epitaxial layers can be suppressed by performing high-temperature heat treatment (argon annealing) before silicon epitaxial layer growth.

[0005] As described in WO 2014 / 175120, when a silicon wafer (a silicon wafer with a small number of SF cores) is cut from a crystal region having a shortened residence time in the temperature region where SF cores are formed, the SF density in the epitaxial layer after the growth of the silicon epitaxial layer can be reduced. However, even for silicon wafers with a shortened residence time in the temperature region where SF cores are formed, the SF density appearing in the silicon epitaxial layer after the growth of the silicon epitaxial layer may increase when the resistivity of the silicon wafer is below 0.7 mΩ·cm.

[0006] Furthermore, as described in Japanese Patent Publication No. 2014-011293, argon annealing of a silicon wafer (a silicon wafer with many SF cores) cut from a crystal region having a long residence time in the temperature region where SF cores are formed can reduce the SF density in the epitaxial layer after the growth of the silicon epitaxial layer. However, the SF density cannot be reduced to 100 defects / wafer or less. Although the prior art described in WO 2014 / 175120 and Japanese Patent Publication No. 2014-011293 effectively suppresses the generation of SF in the silicon epitaxial layer, users require further reduction in SF density. Summary of the Invention

[0007] The present invention provides a silicon wafer with low density of dislocation loop defects that may cause SF, and an epitaxial silicon wafer with low SF generated in a silicon epitaxial layer.

[0008] After conducting an in-depth study of the causes of SF generation in silicon epitaxial layers, the inventors of this invention discovered that, based on the thermal history experienced by the crystal during the growth process of a single crystal ingot, phosphorus-dopant silicon wafers have two main types of dislocation ring defects (where the disturbed portions of the lattice are connected in rings).

[0009] The following describes the details leading to the discovery of dislocation ring defects. First, a silicon single crystal ingot with a diameter of 200 mm is grown, in which phosphorus is densely added as a dopant, and silicon wafers are produced from crystal regions with long residence times in the temperature region where SF nucleation occurs (hereinafter referred to as residence time in the SF nucleation temperature region) and from crystal regions with short residence times in the SF nucleation temperature region.

[0010] Specifically, silicon wafers with a resistivity of 0.75 mΩ·cm, cut from the top side of a straight single-crystal ingot held at 570℃±70℃ for 350 minutes or more, were produced as silicon wafers with a long residence time in the SF nucleation temperature region. Silicon wafers with a resistivity of 0.7 mΩ·cm, cut from the bottom side of a straight single-crystal ingot held at 570℃±70℃ for 50 minutes or less, were produced as silicon wafers with a short residence time in the SF nucleation temperature region. Each silicon wafer was cleaved in the thickness direction, and the cleaved cross-sections were observed using transmission electron microscopy (TEM). The results are shown in... Figure 1A and 1B middle.

[0011] The result is that, in silicon wafers cut from crystal regions (top-side crystal regions) that have a long residence time in the SF nucleation temperature region, it is observed that... Figure 1A The large composite dislocation loop defect 2 shown is an example of overlapping dislocation loops, and many large defects with a density exceeding 60 nm were found. Figure 1B It was taken from different angles. Figure 1A The photograph of the composite dislocation loop 2 shown indicates that the composite dislocation loop 2 has a planar shape. On the other hand, in a silicon wafer cut from a crystal region (the crystal region on the bottom side) having a short residence time in the SF nucleation temperature region, it was observed that... Figure 2 The small dislocation loop defect 4 is shown in the figure, and the density of large composite dislocation loop defects with a size greater than 60 nm is found to be low.

[0012] Furthermore, SF (dislocation loop) formation was observed in silicon epitaxial layers originating from large compound dislocation loop defects. This is believed to indicate that the conditions for SF formation in silicon epitaxial layers differ depending on the presence or absence of compound dislocation loop defects. Therefore, the inventors of this invention considered the mechanism of dislocation loop formation and reached the following conclusions.

[0013] The inventors of this invention made the following assumptions regarding the generation of dislocation loop defects. First, during the cooling of the silicon single crystal ingot, interstitial phosphorus present between the crystal lattice points pushes out lattice silicon present at the lattice positions (ejecting lattice silicon), thereby generating interstitial silicon. The excess interstitial silicon generated agglomerates to form dislocation loops, and separates the interstitial phosphorus at the dislocation loops, resulting in dislocation loop defects.

[0014] Furthermore, suppressing interstitial silicon agglomeration is effective in suppressing the formation of dislocation loop defects, and the inventors believe that the agglomeration of interstitial silicon can be suppressed by intentionally adding impurity elements that can pair with interstitial silicon, and conceived the idea of ​​doping carbon into the crystal during the single crystal growth stage. By doping (adding) carbon into the silicon melt to grow silicon single crystal ingots, and when evaluating the defects formed in the carbon-doped silicon wafer, the inventors found that the defect density of large dislocation loops formed in the silicon wafer can be reduced, thus improving the present invention.

[0015] On the other hand, Japanese Unexamined Patent Publication No. 2003-505324 describes a method that increases the density of oxygen precipitates (bulk microdefects (BMD)) formed within a silicon wafer by adding carbon to the wafer, thereby improving the getter performance of the epitaxial silicon wafer. Specifically, the invention described in Japanese Unexamined Patent Publication No. 2003-505324 attempts to address the reduction in getter performance caused by the decrease in oxygen concentration during the latter half of single-crystal ingot growth by adding carbon. Besides Japanese Unexamined Patent Publication No. 2003-505324, increasing the BMD density by adding carbon to silicon crystals to provide epitaxial wafers with excellent getter performance is well known.

[0016] Typically, regions with high phosphorus concentrations in silicon wafers are used as getter layers (also known as phosphorus gettering methods) through phosphorus thermal diffusion treatment, phosphorus ion implantation treatment, and the formation of phosphorus-containing epitaxial layers. In other words, the silicon wafer of the present invention, densely doped with phosphorus to maintain a resistivity of 1.2 mΩ·cm or less, possesses sufficient gettering properties due to the presence of high phosphorus concentration. Therefore, the epitaxial wafer of the present invention does not require increased BMD density. Therefore, there is no incentive to add carbon to the phosphorus-densely doped silicon wafer of the present invention to increase BMD density and improve gettering performance. Furthermore, the specific problem of frequent SF generation in phosphorus-densely doped silicon wafers to maintain a substrate resistivity of 1.2 mΩ·cm or less is not discussed in Japanese Unexamined Patent Publication No. 2003-505324.

[0017] The silicon wafer according to the invention has a diameter of 200 mm, wherein the dopant is phosphorus, the resistivity is from 0.5 mΩ·cm to 1.2 mΩ·cm, and the carbon concentration is 3.0 × 10⁻⁶. 16 atoms / cm 3 Or larger.

[0018] The resistivity of the silicon wafer as defined in this invention is a value obtained by measuring the surface of the silicon wafer using a four-point probe method. The carbon concentration of the silicon wafer as defined in this invention is a value obtained by polishing and thinning the silicon wafer and measuring the carbon concentration approximately at the center of the silicon wafer in the depth direction (center depth position) using secondary ion mass spectrometry (SIMS). Due to a large amount of noise components, it is difficult to accurately measure the carbon concentration at the outermost surface of the silicon wafer; therefore, it is possible to accurately measure the carbon concentration when measured at a depth of 1 μm or greater from the wafer surface (excluding the outermost surface). In this invention, to obtain a more accurate value, the concentration is defined by the concentration approximately at the center of the silicon wafer in the depth direction.

[0019] For the aforementioned silicon wafer, the oxygen concentration of the silicon wafer can be 4.0 × 10⁻⁶. 17 atoms / cm 3 Or even larger than 10×10 17 atoms / cm 3 Or even less. The oxygen concentration of the silicon wafer defined in this invention is obtained by polishing and thinning the silicon wafer, and then measuring the oxygen concentration approximately at the center of the silicon wafer in the depth direction using SIMS. Due to a large amount of noise components, it is difficult to accurately measure the oxygen concentration at the outermost surface of the silicon wafer, and therefore, it is possible to accurately measure the oxygen concentration when measured at a depth of 1 μm or more from the wafer surface (excluding the outermost surface). In this invention, to obtain a more accurate value, the concentration is defined by the concentration approximately at the center of the silicon wafer in the depth direction.

[0020] Preferably, the silicon wafers described above are substantially free of COP. In this invention, "substantially free of COP" means that silicon wafers in which COP is not detected by the following observation evaluation. Specifically, firstly, silicon wafers cut and processed from single-crystal silicon ingots grown using the CZ method are cleaned with SC-1 (using a liquid mixture of ammonia, hydrogen peroxide solution, and ultrapure water in a 1:1:15 ratio). The surface of the cleaned silicon wafer is then observed and evaluated using a SURFSCAN SP-1 manufactured by KLA-Tencor Corporation as a surface defect inspection device, and a light spot defect (LPD) is designated as an estimate of surface pits. At this time, the observation mode is set to tilt mode (oblique incidence mode), and the surface pits are estimated based on the detected wide / narrow channel size ratio. The presence of COP in the LPD designated in this manner is evaluated using atomic force microscopy (AFM). In this observation evaluation, silicon wafers in which no COP is observed are referred to as "COP-free silicon wafers".

[0021] The epitaxial silicon wafer according to the present invention comprises a silicon wafer with a diameter of 200 mm, wherein the dopant is phosphorus, the resistivity is from 0.5 mΩ·cm to 1.2 mΩ·cm, and the carbon concentration is 3.0 × 10⁻⁶. 16 atoms / cm 3 ; and the silicon epitaxial layer on the surface of the silicon wafer.

[0022] The resistivity of the epitaxial silicon wafer defined in this invention is a value obtained by measuring the back side of the silicon wafer using a four-point probe method. Furthermore, when an oxide film is provided on the back side of the epitaxial silicon wafer, this value is obtained by measuring the back side of the silicon wafer from which the back oxide film has been removed using the four-point probe method. The carbon concentration of the epitaxial silicon wafer defined in this invention is a value obtained by polishing and thinning the silicon wafer and measuring the carbon concentration approximately at the center of the silicon wafer in the depth direction using SIMS.

[0023] During the production of epitaxial silicon wafers, carbon diffuses outwards and reduces the carbon concentration in the surface layer of the silicon wafer due to high-temperature heat treatments performed during and before epitaxial growth. Therefore, it is necessary to measure the carbon concentration of the epitaxial silicon wafer at depths where carbon diffusion is not present. Accurate measurement of the carbon concentration is possible when measured at depths approximately 40 μm or greater from the wafer surface in the depth direction of the wafer thickness. In this invention, to obtain more accurate values, the concentration is defined by the concentration approximately at the center of the silicon wafer in the depth direction.

[0024] The epitaxial silicon wafer according to the present invention comprises a silicon wafer with a diameter of 200 mm, wherein the dopant is phosphorus, the resistivity is from 0.5 mΩ·cm to 1.2 mΩ·cm, and the carbon concentration is 3.0 × 10⁻⁶. 16atoms / cm 3 The silicon wafer has a silicon epitaxial layer on its surface, wherein the silicon wafer has a low-carbon concentration layer on the surface side in contact with the silicon epitaxial layer, the carbon concentration of the low-carbon concentration layer being at most 0.9 times the carbon concentration at approximately the center of the silicon wafer in the depth direction, and the depth of the low-carbon concentration layer being 5 μm or more and 15 μm or less from the silicon wafer surface. That is, compared to the carbon concentration at approximately the center of the silicon wafer in the depth direction, the carbon concentration is reduced by 10% or more starting from a depth of approximately 5 μm from the boundary of the silicon substrate. In another embodiment, compared to the carbon concentration at approximately the center of the silicon wafer in the depth direction, the carbon concentration is reduced by 10% or more starting from any location at a depth of 5 μm to 15 μm from the boundary of the silicon substrate.

[0025] The depth of the low-carbon concentration layer is based on the carbon concentration profile in the depth direction obtained by SIMS measurement, and represents the depth position (width) of the interface between the epitaxial layer and the silicon wafer in the depth direction of the silicon wafer.

[0026] In epitaxial silicon wafers, the resistivity of the silicon wafer is preferably 0.9 mΩ·cm or less.

[0027] In an epitaxial silicon wafer, the carbon concentration on the silicon wafer surface in contact with the epitaxial layer is preferably 1.0 × 10⁻⁶. 16 atoms / cm 3 Or smaller.

[0028] In epitaxial silicon wafers, the oxygen concentration is preferably 4.0 × 10⁻⁶. 17 atoms / cm 3 Or larger and 10×10 17 atoms / cm 3 Or smaller.

[0029] The oxygen concentration of the epitaxial silicon wafer defined in this invention is obtained by polishing and thinning the silicon wafer, and then measuring the oxygen concentration approximately at the center of the silicon wafer in the depth direction using SIMS. The oxygen concentration of the epitaxial silicon wafer needs to be measured at a depth where no oxygen diffuses outward, and accurate measurement of the oxygen concentration is possible when measured at a depth of approximately 150 μm or more in the depth direction of the wafer thickness, almost from the wafer surface. In this invention, to obtain a more accurate value, the concentration is defined by the concentration approximately at the center of the silicon wafer in the depth direction.

[0030] In epitaxial silicon wafers, it is preferable that there is no COP in the silicon wafer.

[0031] In epitaxial silicon wafers, it is preferable to provide an oxide film on the back side of the silicon wafer.

[0032] In epitaxial silicon wafers, it is preferable that there is no oxide film on the outer periphery of the back side and at the ends of the silicon wafer.

[0033] In an epitaxial silicon wafer, the LPD density with a size of 0.09 μm or larger observed on the surface of the epitaxial layer is preferably 100 defects / wafer or less.

[0034] In an epitaxial silicon wafer, the LPD density with a size of 0.09 μm or larger observed on the surface of the epitaxial layer is preferably 60 defects / wafer or less.

[0035] In an epitaxial silicon wafer, the LPD density with a size of 0.09 μm or larger observed on the surface of the epitaxial layer is preferably 10 defects / wafer or less. Attached Figure Description

[0036] The invention is further described in the following detailed description with reference to the various accompanying drawings, through non-limiting examples of exemplary embodiments thereof, wherein the same reference numerals denote similar parts in several views throughout the drawings, and wherein:

[0037] Figure 1A and 1B This is a photograph of a complex dislocation loop observed in a silicon wafer cut from a crystal region that has a long residence time in the SF nucleation temperature region;

[0038] Figure 2 This is a photograph of a dislocation loop observed in a silicon wafer cut from a crystal region with a short dwell time in the SF nucleation temperature region;

[0039] Figure 3 This is a flowchart illustrating an embodiment of a method for manufacturing an epitaxial silicon wafer according to the present invention;

[0040] Figure 4A and 4B This is a cross-sectional view of an embodiment of an epitaxial silicon wafer according to the present invention;

[0041] Figure 5A and 5B This is a diagram illustrating the evaluation results of dislocation loops in the epitaxial silicon wafer of Example 1 and Comparative Example 1;

[0042] Figure 6 This is a graph illustrating the results of the study on the carbon concentration profile of the epitaxial silicon wafers in Examples 4 and 5;

[0043] Figures 7A-7D X-ray morphology images of the silicon wafer surfaces of Examples 6 and 7, and comparative Examples 4 and 5; and

[0044] Figure 8This is a graph illustrating the relationship between LPD density and resistivity when an epitaxial layer is formed on the surface of a silicon wafer in Examples 8 and 9 and Comparative Examples 6 and 7. Detailed Implementation

[0045] The details shown herein are by way of example and are merely for the purpose of illustrative discussion of embodiments of the invention, and are given to provide a description of the principles and concepts of the invention that are considered most useful and readily understood. In this respect, no attempt is made to show the structural details of the invention in greater detail, except for those necessary for a basic understanding of the invention; the description, taken in conjunction with the accompanying drawings, enables those skilled in the art to understand how to implement the forms of the invention in practice.

[0046] Embodiments of the present invention are described below with reference to the accompanying drawings. The silicon wafer according to the present invention has a diameter of 200 mm, is doped with phosphorus, phosphorus being a dopant used for resistivity adjustment, having a resistivity of 0.5 mΩ·cm or greater and 1.2 mΩ·cm or less, and a carbon concentration of 3.0 × 10⁻⁶. 16 atoms / cm 3 Or larger. A silicon wafer with a diameter of 200 mm as defined by this invention refers to a silicon wafer with a diameter of 200 ± 0.5 mm due to processing errors, etc. Furthermore, the epitaxial silicon wafer according to this invention includes a silicon epitaxial layer on the silicon wafer.

[0047] exist Figure 3 The diagram shows an advantageous manufacturing process for obtaining an epitaxial silicon wafer according to the invention. The manufacturing process preferably includes the steps of manufacturing a single crystal ingot (S1), forming an oxide film on the back side (S2), removing the oxide film on the outer periphery (S3), argon annealing (S4), pre-baking (S5), and forming an epitaxial layer (S6).

[0048] In the single crystal ingot manufacturing step S1, according to the Czochralski (CZ) method, a 200 mm diameter single crystal silicon ingot with phosphorus doping as an n-type dopant is manufactured using a single crystal ingot pulling instrument (not shown) that meets the following conditions.

[0049] Phosphorus concentration

[0050] By doping with red phosphorus, the phosphorus concentration in the single crystal ingot was increased to 6.0 × 10⁻⁶. 19 atoms / cm 3 Or larger and 1.64 × 10 20 atoms / cm 3 Or even smaller, single-crystal ingots with resistivity of 0.5 mΩ·cm or greater and 1.2 mΩ·cm or less can be obtained. Furthermore, by configuring a phosphorus concentration of 8.3 × 10⁻⁶... 19 atoms / cm3 Or even higher, single-crystal ingots with resistivity of 0.9 mΩ·cm or less can be obtained. The phosphorus concentration of the silicon wafer is a value obtained by measuring the phosphorus concentration approximately at the center of the silicon wafer in the depth direction using SIMS. The phosphorus concentration can be found from the resistivity measured using the formula or graph specified in SEMI MF723-0307 via a four-point probe method. When phosphorus is doped before the silicon raw material is melted, the phosphorus may evaporate during the melting of the silicon raw material, and the desired resistivity cannot be obtained. Therefore, it is preferable to dope red phosphorus into the silicon melt after the silicon raw material has melted.

[0051] carbon concentration

[0052] By adding carbon powder together with silicon raw material into a crucible and melting the material, the carbon concentration in the single crystal ingot is made to be 3.0 × 10⁻⁶. 16 atoms / cm 3 Or larger and 5.0×10 17 atoms / cm 3 Or even smaller, single-crystal ingots with a predetermined carbon concentration can be grown. This is achieved by setting the carbon concentration to 3.0 × 10⁻⁶. 16 atoms / cm 3 This can reduce the size and density of dislocation loop defects formed within the silicon wafer, and can significantly reduce the SF density generated in the epitaxial layer after the epitaxial growth process. Specifically, even silicon wafers cut from the top side of a crystal with a long residence time in the SF nucleation temperature region, used as silicon wafers, can reliably achieve an LPD density of 100 defects / wafer or less on the surface of the silicon epitaxial layer after the epitaxial growth process.

[0053] Although the effect of reducing the LPD density (SF density) generated in the epitaxial layer is enhanced with increasing carbon concentration, when the carbon concentration exceeds 5.0 × 10⁻⁶, the reduction is more pronounced. 17 atoms / cm 3 During the growth of a single crystal ingot, dislocations are more likely to occur within the single crystal, making it difficult to grow a dislocation-free single crystal ingot. From the viewpoint of stable single crystal ingot manufacturing, a carbon concentration of 3.0 × 10⁻⁶ is more preferable. 17 atoms / cm 3 Or smaller.

[0054] Oxygen concentration

[0055] When the oxygen concentration in a silicon wafer is high, as described below, the device's breakdown voltage characteristics tend to deteriorate. Therefore, it is preferable to maintain a low oxygen concentration in the single crystal ingot, and the oxygen concentration is preferably 4.0 × 10⁻⁶. 17 atoms / cm 3 Or even larger than 10×10 17 atoms / cm 3 Or within a smaller range.

[0056] To grow single-crystal ingots with low oxygen concentration, it is preferable to apply a magnetic field to the silicon melt, and well-known horizontal or shear magnetic fields can be applied. The oxygen concentration introduced into the single crystal can be reduced to the desired concentration by slowing down the rotation of the crucible storing the silicon melt and by reducing the furnace pressure of the pulling apparatus. When the oxygen concentration is less than 4.0 × 10⁻⁶... 17 atoms / cm 3 At this stage, silicon wafers have low strength, and slip dislocations may occur when silicon wafers undergo high-temperature heat treatment. Therefore, the oxygen concentration is preferably 4.0 × 10⁻⁶. 17 atoms / cm 3 Or larger.

[0057] Subsequently, silicon wafers are cut from the single crystal ingot manufactured using the single crystal ingot manufacturing step S1, and predetermined processes (such as grinding, etching, and polishing processes) are performed to produce mirror-finish silicon wafers with excellent surface roughness and flatness.

[0058] In the back oxide film formation step S2, it is preferable to use a CVD device to form an oxide film (hereinafter referred to as back oxide film) on the back side of the silicon wafer under the following conditions.

[0059] Raw material gas: a mixture of silane (SiH4) and oxygen (O2)

[0060] Thickness of the back oxide film: 100 nm to 1500 nm

[0061] Film formation temperature: 400℃ to 450℃.

[0062] Providing this type of back oxide film can suppress self-doping and can suppress resistance fluctuations in the epitaxial layer.

[0063] In the back oxide film formation step S2, it is difficult to form an oxide film only on the back side of the silicon wafer, and after the back oxide film formation step S2, an oxide film may inevitably form at the ends (beveled portions) of the silicon wafer. When an epitaxial layer is formed on the surface of the oxide film, grains (granular silicon) may appear in this area, so it is preferable to remove the oxide film formed at the periphery and ends of the back side of the silicon wafer.

[0064] Therefore, in the peripheral oxide film removal step S3, various methods (e.g., polishing and etching) can be used to remove the oxide film present on the edges (beveled portions) and the outer periphery of the back side of the silicon wafer. Preferably, the oxide film present on the periphery of the back side of the wafer is removed in an area less than 5 mm from the outer edge of the silicon wafer. By removing the periphery of the back oxide film and the edges of the silicon wafer in this manner, grain formation during the growth of the silicon epitaxial layer can be prevented, and grain formation from the wafer edge can be prevented.

[0065] In the argon annealing step S4, the heat treatment is preferably carried out under the following conditions.

[0066] Gas atmosphere: Argon gas

[0067] Heat treatment temperature: 1150℃ to 1250℃

[0068] Heat treatment time: 30-120 minutes.

[0069] It is preferable to use a batch furnace (vertical heat treatment device) capable of heat-treating multiple silicon wafers at once as the heat treatment device for heat treatment.

[0070] High concentrations of carbon doping suppress the formation of large dislocation loop defects in silicon wafers, and argon annealing of silicon wafers can eliminate small dislocation loop defects present on silicon wafers, and minimize the formation of SF in epitaxial layers.

[0071] Furthermore, by annealing the silicon wafer with argon gas prior to the epitaxial growth process, carbon diffusion from the silicon wafer to the silicon epitaxial layer during epitaxial layer formation step S6 can be reduced. This is described below. Figure 4A This is a schematic diagram illustrating the formation of a low-carbon concentration layer on the surface of a silicon wafer through argon annealing. (Example) Figure 4A As shown, by subjecting the silicon wafer 11 to high-temperature argon annealing, carbon in the surface layer of the silicon wafer 11 diffuses outward, and the carbon concentration in the surface layer decreases. Consequently, a low-carbon concentration layer 12 is formed on the front and back sides of the silicon wafer 11, and the carbon concentration of this low-carbon concentration layer 12 is lower than the carbon concentration at approximately the center C of the silicon wafer 11, where no outward carbon diffusion occurs.

[0072] Figure 4B This is a schematic diagram illustrating the carbon concentration during an epitaxial growth process on a silicon wafer that has undergone argon annealing.

[0073] like Figure 4BAs shown, the carbon concentration profile after epitaxial layer formation step S6 illustrates the reduction in carbon concentration in the surface layer of the silicon wafer. Here, when the region is defined as low-carbon concentration layer 12, the carbon concentration in this region is 0.9 times or less than the carbon concentration at the center C of the silicon wafer 11 where no outward carbon diffusion occurs. After the epitaxial growth process, the depth D of the low-carbon concentration layer 12 formed on the surface 11a side of the silicon wafer 11 in contact with the silicon epitaxial layer 13 can be 5 μm or more and 15 μm or less. That is, compared to the carbon concentration approximately at the center of the silicon wafer in the depth direction, the carbon concentration is reduced by 10% or more starting from a depth of approximately 5 μm from the boundary of the silicon substrate. In another embodiment, compared to the carbon concentration approximately at the center of the silicon wafer in the depth direction, the carbon concentration is reduced by 10% or more starting from any location at a depth of 5 μm to 15 μm from the boundary of the silicon substrate. By forming the low-carbon concentration layer 12, carbon diffusion from the silicon wafer 11 to the silicon epitaxial layer 13 generated during epitaxial layer formation step S6 can be further reduced. The thickness of the low-carbon concentration layer 12 can be adjusted as needed by regulating the argon annealing time and heat treatment temperature.

[0074] In the pre-calcination step S5 under a gaseous atmosphere including hydrogen and hydrogen chloride, the silicon wafer is preferably heat-treated in an internal epitaxial device (CENTURA®, manufactured by Applied Materials, Inc.) under the following conditions.

[0075] Atmosphere: Hydrogen, hydrogen chloride gas

[0076] Hydrogen flow rate: 40 L / min

[0077] Hydrogen chloride gas flow rate: 1 L / min

[0078] Heat treatment temperature: 1150℃ to 1250℃

[0079] Heat treatment time: 30-300 seconds.

[0080] The edge of the surface layer of the silicon wafer produced by the pre-baking step S5 is preferably 100 nm to 300 nm, and more preferably 150 nm ± 10 nm.

[0081] In the epitaxial layer formation step S6, the epitaxial layer is preferably grown on the silicon wafer that has undergone the pre-baking step S5 under the following conditions.

[0082] Dopant gas: Phosphine (PH3) gas

[0083] Source gas for materials: Trichlorosilane (SiHCl3) gas

[0084] Carrier gas: hydrogen

[0085] Growth temperature: 1050℃ to 1150℃

[0086] Epitaxial layer thickness: 1 μm to 10 μm

[0087] Epitaxial layer resistivity: 0.01 mΩ·cm to 10 mΩ·cm

[0088] Phosphorus concentration: 4.44 × 10 14 atoms / cm 3 Up to 4.53×10 18 atoms / cm 3 .

[0089] By performing the epitaxial layer formation step S6, an epitaxial silicon wafer with a silicon epitaxial layer formed on the surface of a silicon wafer is manufactured.

[0090] By performing the above process, a silicon wafer can be provided that reduces the generation of phosphorus (SF) in the epitaxial layer, and provides an epitaxial silicon wafer in which the SF density in the epitaxial layer is reduced. Specifically, a new silicon wafer not previously available is provided, wherein the silicon wafer has a diameter of 200 mm, phosphorus is added to achieve a resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm, and the silicon wafer is densely doped with carbon to achieve a carbon concentration of 3.0 × 10⁻⁶. 16 atoms / cm 3 Or larger.

[0091] High concentrations of carbon doping reduce the density of large dislocation loop defects in silicon wafers. Silicon wafers can be effectively used as bulk wafers for epitaxial growth, which can reduce the generation of epitaxial defects (LPDs or SFs observed on the surface of the epitaxial layer).

[0092] Furthermore, by configuring the oxygen concentration of the silicon wafer at 4.0 × 10⁻⁶... 17 atoms / cm 3 Up to 10×10 17 atoms / cm 3 Within a certain range, when carbon is doped, poor device breakdown voltage can be prevented.

[0093] Furthermore, by annealing the silicon wafer with argon gas before forming the silicon epitaxial layer, the carbon concentration in the surface layer of the silicon wafer is reduced, and the amount of carbon generated during the formation of the silicon epitaxial layer diffuses into the silicon epitaxial layer. By reducing the amount of carbon diffusion into the silicon epitaxial layer, the degradation of electrical properties caused by defects due to carbon doping in the silicon epitaxial layer can be suppressed during heat treatment in the device fabrication process on the epitaxial silicon wafer.

[0094] In the above embodiments, the resistivity of the silicon wafer is from 0.5 mΩ·cm to 1.2 mΩ·cm. However, as a silicon wafer with better resistivity, a resistivity of 0.5 mΩ·cm to 0.9 mΩ·cm is preferred. The lower the resistivity, the more pronounced the generation of SF in the epitaxial layer becomes, and therefore the more pronounced the effect of carbon doping according to the invention.

[0095] Furthermore, the silicon wafer according to this embodiment is manufactured from a single crystal ingot grown from a phosphorus-doped silicon melt, resulting in a resistivity of 1.2 mΩ·cm or less. Due to the dense addition of phosphorus, the OSF ring regions that eliminate oxidation-induced stacking faults (OSF) generated during the manufacturing process of the single crystal ingot are concentrated around the ingot and become COP-free crystal regions. In other words, by densely adding phosphorus, the silicon wafer according to this embodiment can be configured as a COP-free silicon wafer, and defects caused by COP can be prevented in the epitaxial layer. Example

[0096] The following describes the experimental conditions and evaluation results of embodiments of the present invention and comparative embodiments.

[0097] <Evaluation of Dislocation Loops>

[0098] The dislocation loops of Example 1 and Comparative Example 1 are evaluated below.

[0099] <Example 1>

[0100] In Example 1, in reference Figure 3 The epitaxial silicon wafer manufacturing process described herein is used to manufacture epitaxial silicon wafers under specific conditions. The single-crystal ingot growth conditions involve adding carbon powder before melting the silicon feedstock and adding phosphorus to the silicon melt after melting the feedstock, resulting in a resistivity of 0.9 mΩ·cm at the top of the straight body of the single-crystal ingot. Sample wafers are cut from the top of the carbon-added single-crystal ingot and manufactured as mirror-finished silicon wafers through predetermined processing. The resistivity of the silicon wafer is 0.75 mΩ·cm when measured using a four-point probe method, and the carbon concentration of the silicon wafer is 5.0 × 10⁻⁶. 16 atoms / cm 3 .

[0101] <Comparative Example 1>

[0102] Compared to Example 1 above, except that carbon doping is not performed during the single crystal ingot growth stage, silicon wafers are manufactured under the same manufacturing conditions as in Example 1. Similar to Example 1, sample wafers with a resistivity of 0.75 mΩ·cm are cut, and mirror silicon wafers are produced by performing predetermined processing.

[0103] The silicon wafers of Example 1 and Comparative Example 1 were cleaved in the depth direction, and the cleaved cross sections were observed by transmission electron microscopy (TEM). Figure 5A and 5B This is a graph illustrating the evaluation results of dislocation loops in the epitaxial silicon wafer of Example 1 and Comparative Example 1. Figure 5A and 5B In the diagram, the horizontal axis represents the size of the dislocation loops, and the vertical axis represents the density of the dislocation loops. Figure 5A The results show the undoped silicon wafer of Comparative Example 1, and due to the use of a sample wafer cut from the top side of a crystal with a long residence time in the SF nucleation temperature region, a large number of dislocation loops with a size exceeding 60 nm were observed. On the other hand, Figure 5B The results of Example 1, showing a densely carbon-doped silicon wafer, demonstrate that, due to the use of a sample wafer cut from the top side of a crystal with a long residence time in the SF nucleation temperature region, a significant reduction in the density of large dislocation loops exceeding 60 nm was observed, despite the presence of numerous small dislocation loops. In other words, carbon doping was found to reduce the density of large dislocation loops formed in the silicon wafer.

[0104] [LPD Density Evaluation]

[0105] When a silicon epitaxial layer is formed using a sample silicon wafer cut from the top side of a straight body of an ingot that has a long residence time in the temperature region where the SF core is formed, SF is frequently generated in the epitaxial layer, and the LPD density increases. Therefore, in this embodiment, sample silicon wafers cut from the top side of the straight body for use in Examples 2 and 3 below and Comparative Examples 2 and 3 are produced, and the LPD density observed on the surface of the epitaxial layer after its formation is measured.

[0106] The specific conditions for the back oxide film formation step and the epitaxial layer formation step, which are performed as a common process in the embodiments and comparative embodiments, are as follows.

[0107] [Conditions for the formation of the oxide film on the back side]

[0108] Under the following conditions, a back oxide film is formed on the back side of each silicon wafer (the surface opposite to the surface where the epitaxial layer is formed).

[0109] Raw material gas: a mixture of silane (SiH4) and oxygen (O2)

[0110] Film formation method: CVD method

[0111] Film formation temperature: 400℃

[0112] Thickness of the oxide film on the back side: 550 nm.

[0113] The oxide film present on the beveled portion and the outer periphery of the back side of each silicon wafer is removed by an etching process.

[0114] [Hydrogen roasting treatment conditions]

[0115] Atmosphere: Hydrogen

[0116] Heat treatment temperature: 1200℃

[0117] Heat treatment time: 30 seconds

[0118] [Epitaxial film growth conditions]

[0119] Dopant gas: Phosphine (PH3) gas

[0120] Source gas for materials: Trichlorosilane (SiHCl3) gas

[0121] Carrier gas: hydrogen

[0122] Growth temperature: 1080℃

[0123] Epitaxial layer thickness: 4 μm

[0124] Resistivity (epitaxy film resistivity): 0.3 Ω·cm.

[0125] <Comparative Example 2>

[0126] An epitaxial silicon wafer was manufactured by forming a silicon epitaxial layer with a thickness of 4 μm on the surface of the silicon wafer of Comparative Example 1, in which a large number of dislocation loops were observed, without carbon doping.

[0127] <Comparative Example 3>

[0128] After argon annealing (heat treatment at 1200°C for 30 minutes in an argon atmosphere) on the silicon wafer of Comparative Example 1, an epitaxial silicon wafer was manufactured by forming a silicon epitaxial layer with a thickness of 4 μm on the surface of the silicon wafer.

[0129] <Example 2>

[0130] In Example 1, the silicon wafer with carbon doping was not subjected to argon annealing. Instead, an epitaxial silicon wafer was manufactured by forming a silicon epitaxial layer with a thickness of 4 μm on the surface of the silicon wafer.

[0131] <Example 3>

[0132] After argon annealing (heat treatment at 1200°C for 30 minutes in an argon atmosphere) of the carbon-doped silicon wafer of Example 1, an epitaxial silicon wafer was manufactured by forming a silicon epitaxial layer with a thickness of 4 μm on the surface of the silicon wafer. The conditions of the epitaxial growth process were the same as those of Examples 2 and 3, as well as Comparative Examples 2 and 3.

[0133] The LPD density on the surface of the silicon epitaxial layer of the epitaxial silicon wafer in Comparative Example 2 was measured using a surface defect inspection device (SURFSCAN SP-1, manufactured by KLA-Tencor Corporation). Specifically, measurements were performed in normal mode (DCN mode), and the density of LPDs with a size of 90 nm or larger observed on the surface of the epitaxial layer was measured. The measurement area was the surface of the epitaxial layer excluding a ring-shaped region radially from the circumferential edge of the epitaxial silicon wafer to a distance of 3 mm from the circumferential edge. The number of LPDs counted can be considered as the number of SFs. As a result, the LPDs themselves could not be measured due to overflow caused by the large number of defects detected (100,000 defects / wafer or more). In Comparative Example 3, where the silicon wafer was annealed with argon, although the LPD density was reduced compared to Comparative Example 2, 235 LPDs / wafer were still observed. The following LPD density measurements for each example and each comparative example were performed under the same conditions as in Comparative Example 2.

[0134] When the LPD density on the surface of the silicon epitaxial layer of the epitaxial silicon wafer in Example 2 was measured, 90,000 LPDs / wafer or more were observed. This is assumed to be due to the presence of a large number of small dislocation loops with a size less than 60 nm, although the density of large composite dislocation loops in the silicon wafer is reduced by carbon doping.

[0135] In Example 3, where the silicon wafer was annealed with argon gas prior to the epitaxial growth process, the LPD density on the surface of the epitaxial layer was significantly reduced, and an LPD density of 56 defects per wafer was observed. This is attributed to the removal of small dislocation loops smaller than 60 nm present in the surface layer of the silicon wafer by argon annealing.

[0136] Considering the above, when silicon wafers are carbon-doped and argon-annealed, the effect of reducing SF generation in the silicon epitaxial layer is enhanced, and it is clear that the LPD density after the formation of the epitaxial layer can be reduced to about one-quarter compared to Comparative Example 3.

[0137] [Carbon Concentration Overview Assessment]

[0138] When densely doped with carbon, carbon may diffuse into the silicon epitaxial layer due to the heat treatment during the formation of the silicon epitaxial layer, and therefore, the behavior of carbon diffusion into the silicon epitaxial wafer is evaluated.

[0139] <Example 4>

[0140] Fabrication with high carbon concentration (carbon concentration approximately at the center of the wafer in the depth direction: 6.5 × 10⁻⁶) 16 atoms / cm 3The silicon wafer is formed, and an epitaxial silicon wafer is manufactured, wherein a silicon epitaxial layer similar to that in Example 2 is formed without argon annealing.

[0141] <Example 5>

[0142] After performing the same argon annealing on a silicon wafer similar to that in Example 4 as in Example 3, an epitaxial silicon wafer in which a silicon epitaxial layer is formed is manufactured.

[0143] Figure 6 This is a graph illustrating the findings of a study on the carbon concentration profile of the epitaxial silicon wafers in Examples 4 and 5, measured by secondary ion mass spectrometry. Figure 6 The horizontal axis represents the depth from the surface of the epitaxial silicon wafer, and the vertical axis represents the carbon concentration. An interface exists between the silicon epitaxial layer and the silicon wafer at a depth of 4 μm from the surface of the epitaxial silicon wafer.

[0144] In Example 4, where the silicon wafer was not argon-annealed, the width of the low-carbon concentration layer was less than 1 μm. That is, compared to the carbon concentration near the center depth of the silicon wafer, the carbon concentration decreased at a depth of 1 μm from the silicon wafer surface. On the other hand, in Example 5, where argon annealing was performed before forming the silicon epitaxial layer, a low-carbon concentration layer with a thickness of 8.2 μm was formed in the depth direction of the wafer at the interface between the silicon epitaxial layer and the silicon wafer. It was found that the carbon concentration of the silicon epitaxial layer almost covered the entire epitaxial layer except for the area near the silicon wafer interface, and the carbon concentration was at or below the detection limit (2.0 × 10⁻⁶). 15 atoms / cm 3 (or even less). That is, compared to the carbon concentration near the center depth of the silicon wafer, the carbon concentration decreases at a depth within 8.2 μm of the silicon wafer surface. The thickness of the low-carbon-concentration layer depends on the argon annealing conditions. For example, all other conditions are set similarly to those in Example 5, and the thickness is 5.6 μm when the heat treatment conditions are changed to 1150°C for 10 minutes, 7.3 μm when the heat treatment conditions are changed to 1200°C for 10 minutes, 7.3 μm when the heat treatment conditions are changed to 1150°C for 60 minutes, and 9.4 μm when the heat treatment conditions are changed to 1200°C for 60 minutes. In other words, the thickness of the low-carbon-concentration layer can be adjusted as desired by adjusting the heat treatment temperature and time of argon annealing. By forming a low-carbon-concentration layer of predetermined thickness on the surface layer of the silicon wafer, the amount of carbon diffusion from the silicon wafer to the epitaxial layer can be reduced.

[0145] [Evaluation of Slip Dislocation]

[0146] For the following comparative examples 4 and 5, and examples 6 and 7, the occurrence of slip dislocations (defects along the silicon crystal surface) was investigated based on whether carbon doping or argon annealing was performed. The descriptions and conditions shared by comparative examples 4 and 5, and examples 6 and 7 are listed below.

[0147] Resistivity: 0.82 mΩ·cm

[0148] Carbon concentration: 4.0 × 10 16 atoms / cm 3

[0149] Furthermore, in Comparative Examples 5 and 7, where argon annealing was performed, the argon annealing was carried out at 1200°C for 30 minutes in an argon atmosphere. Additionally, in the following description, "heat treatment corresponding to the epitaxial layer growth conditions" refers to heat treatment performed without introducing a material source gas into the epitaxial device (CENTURA®, manufactured by Applied Materials, Inc.), and specifically refers to heat treatment at 1150°C for 10 minutes in a hydrogen atmosphere.

[0150] <Comparative Example 4>

[0151] For undoped silicon wafers, argon annealing is not performed; instead, heat treatment corresponding to the epitaxial layer growth conditions is applied (the heat treatment alone does not induce silicon epitaxial layer growth).

[0152] <Comparative Example 5>

[0153] The undoped silicon wafers were annealed with argon and subjected to heat treatment corresponding to the epitaxial layer growth conditions.

[0154] <Example 6>

[0155] The carbon-doped silicon wafers are not annealed with argon gas, but are subjected to heat treatment corresponding to the epitaxial layer growth conditions.

[0156] <Example 7>

[0157] The carbon-doped silicon wafer was annealed with argon and subjected to heat treatment corresponding to the epitaxial layer growth conditions.

[0158] For each silicon wafer, the presence of slip dislocations observed on the wafer surface was examined by X-ray morphology. The results, as shown in Figure 7, indicate that no slip dislocations were found in any silicon wafer, and it was also found that no slip dislocations occurred even when the silicon wafer was densely doped with carbon.

[0159] [Verification of resistivity, carbon concentration, and LPD density]

[0160] For Comparative Examples 6 and 7, and Examples 8 and 9 below, to verify the correlation between resistivity, carbon concentration, and LPD density, silicon wafers were fabricated under various conditions, an epitaxial layer was formed on the surface of each silicon wafer, and the LPD density observed on the surface of the epitaxial layer was measured. Furthermore, the argon annealing in Comparative Examples 7 and 9 below was performed by heat treatment at 1200°C for 30 minutes in an argon atmosphere.

[0161] <Comparative Example 6>

[0162] Instead of carbon doping, phosphorus doping is used to achieve a resistivity of 1.2 mΩ·cm at the top of the straight body of the single crystal ingot. The single crystal ingot is grown with a resistivity ranging from 0.5 mΩ·cm to 1.2 mΩ·cm, and multiple silicon wafers with different resistivities are fabricated from the single crystal ingot. No argon annealing is performed on any of the silicon wafers, resulting in a silicon epitaxial layer with a thickness of 4 μm.

[0163] <Comparative Example 7>

[0164] Similar to Comparative Example 6, no carbon doping was performed, and the single crystal ingot was grown with a resistivity ranging from 0.5 mΩ·cm to 1.2 mΩ·cm. Multiple silicon wafers with different resistivities were fabricated from the single crystal ingot. Without carbon doping, an epitaxial layer with a thickness of 4 μm was formed after argon annealing of each silicon wafer.

[0165] <Example 8>

[0166] Similar to Comparative Example 6, a single crystal ingot with a resistivity ranging from 0.5 mΩ·cm to 1.2 mΩ·cm was grown, and multiple silicon wafers with different resistivities were fabricated from the single crystal ingot. Carbon doping was performed so that the carbon concentration at the top of the straight body of the single crystal ingot was 3.0 × 10⁻⁶. 16 atoms / cm 3 However, no argon annealing is performed on any silicon wafer to form an epitaxial layer with a thickness of 4 μm.

[0167] <Example 9>

[0168] Similar to Comparative Example 6, a single crystal ingot with a resistivity ranging from 0.5 mΩ·cm to 1.2 mΩ·cm was grown, and multiple silicon wafers with different resistivities were fabricated from the single crystal ingot. Carbon doping was performed so that the carbon concentration at the top of the straight body of the single crystal ingot was 3.0 × 10⁻⁶. 16 atoms / cm 3 Furthermore, after argon annealing of each silicon wafer, an epitaxial layer with a thickness of 4 μm is formed.

[0169] Figure 8These are diagrams of the epitaxial layers in Examples 8 and 9 and Comparative Examples 6 and 7, illustrating the relationship between the resistivity and LPD density of the silicon wafer observed on the surface of the epitaxial layer. Figure 8 The horizontal axis in the figure shows the position where the silicon wafer is cut using the solidification rate of the ingot's straight body when the solidification amount of the entire length of the grown ingot is set to 1.

[0170] like Figure 8 As shown, in Example 8, where carbon doping is performed before the epitaxial growth process without argon annealing, an LPD density of approximately 5,000 defects / wafer was observed in silicon wafers cut from a position on the straight body of the ingot (which is the crystal region on the top side) near a solidification rate of 0.1, confirming the effect of reducing LPD density. However, in silicon wafers cut from a position on the straight body of the ingot near a solidification rate of 0.3, the LPD density overflowed. Furthermore, when using silicon wafers cut from the crystal region on the bottom side, even for silicon wafers with a limiting resistivity of 0.5 mΩ·cm, the LPD density can be reduced to 150 defects / wafer or less.

[0171] In Example 9, where carbon doping and argon annealing are performed prior to the epitaxial growth process, the LPD density can be reduced to 60 defects / wafer or less even when using silicon wafers cut from the crystal region on the top side. This is due to the refinement of dislocation loop defects achieved by high-concentration carbon doping, and the elimination of refined dislocation loop defects by argon annealing of the silicon wafer. The synergistic effect of high-concentration carbon doping and argon annealing in reducing SF is found to be extremely significant. On the other hand, when using silicon wafers cut from the crystal region on the bottom side (where the solidification rate is 0.6 or greater), which have a short residence time in the SF nucleation temperature region, the LPD density can be reduced to a total of 10 defects / wafer or less.

[0172] On the other hand, in Comparative Example 6, where no carbon doping and no argon annealing of the silicon wafer are performed, the LPD density overflows when a silicon wafer cut from the crystal region on the top side is used. Although the LPD density decreases significantly when a silicon wafer cut from the crystal region on the bottom side is used, the LPD density is still 100 defects / wafer or greater for a silicon wafer with a resistivity of 0.5 mΩ·cm. Furthermore, in Comparative Example 7, where the silicon wafer is argon annealed without carbon doping prior to the epitaxial growth process, the LPD density can be reduced compared to Comparative Example 6. However, when a silicon wafer cut from the crystal region on the top side is used, the LPD density is between 100 and 300 defects / wafer.

[0173] Based on the above results, by performing 3.0 × 10⁻⁶ ppm of the epitaxial growth process before the epitaxial growth process... 16 atoms / cm3 With further carbon doping and argon annealing of the silicon wafer, the LPD density observed on the surface of the epitaxial layer in all crystalline regions of a single crystal ingot can be reduced to at least 100 defects / wafer. Furthermore, even without argon annealing of the silicon wafer, by performing carbon doping, the LPD density in the crystalline regions on the bottom side can be reduced to 100 defects / wafer or less. Although not all experimental embodiments have been disclosed in this embodiment, the inventors of the present invention have found that when at least 3.0 × 10⁻⁶ carbon is added... 16 atoms / cm 3 When carbon concentrations are high or even higher, the LPD density of silicon wafers with resistivity of 0.5 mΩ·cm to 1.2 mΩ·cm can be reduced after the epitaxial growth process compared to the case without carbon addition.

[0174] [Evaluation of Device Withstand Voltage Characteristics]

[0175] Evaluate the device's breakdown voltage characteristics. In this embodiment, the device breakdown voltage is one of the quality characteristics of a semiconductor device, and refers to the voltage at which breakdown occurs when the path between the gate and source of the semiconductor device is short-circuited, by gradually increasing the voltage between the drain and source.

[0176] There are concerns that the breakdown voltage characteristics of semiconductor devices may be affected when oxygen diffuses from a silicon wafer into the epitaxial layer. Therefore, the inventors of this invention fabricated silicon wafers with six different oxygen concentrations, formed silicon epitaxial layers on each wafer, and investigated whether there were differences in device breakdown voltage characteristics based on differences in oxygen concentration. Furthermore, they investigated whether there were differences in device breakdown voltage characteristics based on whether the silicon wafer was doped with carbon.

[0177] Specifically, semiconductor devices are fabricated on each of the epitaxial silicon wafers in samples 1-12 of Table 1. With the path between the gate and source of the semiconductor device being short-circuited, a predetermined voltage is applied between the drain and source. The breakdown voltage characteristic is determined to be "poor" when breakdown occurs and "good" when no breakdown occurs.

[0178] Samples 1-6 have epitaxial silicon wafers with a diameter of 200 mm, phosphorus is added, and a 4 μm thick silicon epitaxial layer is formed on a silicon wafer with a resistivity of 0.75 mΩ·cm. These are sample wafers in which epitaxial layers are formed on each silicon wafer with six different oxygen concentrations and no carbon is added. Similar to samples 1-6, samples 7-12 have epitaxial silicon wafers with a diameter of 200 mm, phosphorus is added, and a 4 μm thick silicon epitaxial layer is formed on a silicon wafer with a resistivity of 0.75 mΩ·cm. These samples have a carbon concentration of 6.0 × 10⁻⁶. 16 atoms / cm 3Sample wafers were formed with epitaxial layers on each silicon wafer having six different oxygen concentration levels. The carbon and oxygen concentrations were each obtained by polishing and thinning the silicon wafers, and then measuring the concentration approximately at the center of the silicon wafer in the depth direction using SIMS.

[0179] Table 1

[0180] Epitaxial silicon wafers <![CDATA[Carbon concentration (atoms / cm 3 )]]> <![CDATA[Oxygen concentration (atoms / cm 3 )]]> Pressure resistance characteristics Sample 1 Detection limits or less <![CDATA[18×10 17 ]]> Difference Sample 2 Detection limits or less <![CDATA[15×10 17 ]]> good Sample 3 Detection limits or less <![CDATA[13×10 17 ]]> good Sample 4 Detection limits or less <![CDATA[10×10 17 ]]> good Sample 5 Detection limits or less <![CDATA[8.0×10 17 ]]> good Sample 6 Detection limits or less <![CDATA[4×10 17 ]]> good Sample 7 <![CDATA[6.0×10 16 ]]> <![CDATA[18×10 17 ]]> Difference Sample 8 <![CDATA[6.0×10 16 ]]> <![CDATA[15×10 17 ]]> Difference Sample 9 <![CDATA[6.0×10 16 ]]> <![CDATA[13×10 17 ]]> Difference Sample 10 <![CDATA[6.0×10 16 ]]> <![CDATA[10×10 17 ]]> good Sample 11 <![CDATA[6.0×10 16 ]]> <![CDATA[8.0×10 17 ]]> good Sample 12 <![CDATA[6.0×10 16 ]]> <![CDATA[4.0×10 17 ]]> good

[0181] As shown in Table 1, it is confirmed that the breakdown voltage of devices in samples 7-9 may be poor when carbon doping is performed. However, even when carbon doping is performed, it is confirmed that by configuring the oxygen concentration to 10 × 10⁻⁶, the breakdown voltage can be improved. 17 atoms / cm 3 Or even smaller, to prevent poor device withstand voltage.

[0182] Note that the foregoing embodiments are provided for illustrative purposes only and are not intended to limit the invention in any way. Although the invention has been described with reference to exemplary embodiments, it should be understood that the terms used herein are descriptive and illustrative, not restrictive. Changes may be made within the scope of the appended claims, as described and modified herein, without departing from the scope and spirit of various aspects of the invention. Although the invention has been described herein with reference to specific structures, materials, and embodiments, the invention is not intended to be limited to the details disclosed herein; rather, the invention extends to all functionally equivalent structures, methods, and uses, for example, within the scope of the appended claims.

[0183] The present invention is not limited to the above embodiments, and various changes and modifications are possible without departing from the scope of the present invention.

Claims

1. An epitaxial wafer with a diameter of 200 mm, comprising: A phosphorus-doped silicon substrate with a resistivity of 0.9 mΩ·cm or less; Epitaxial layer on the silicon substrate; and The boundary between the epitaxial layer and the silicon substrate; The carbon concentration of the silicon substrate at its center in the depth direction is 3.0 × 10⁻⁶. 16 atoms / cm 3 Or larger.

2. The epitaxial wafer of claim 1, wherein the carbon concentration at the center of the silicon substrate in the depth direction is 3.0 × 10⁻⁶. 16 atoms / cm 3 Up to 5.0×10 17 atoms / cm 3 Within the range.

3. The epitaxial wafer of claim 1, wherein the top surface of the epitaxial layer contains 100 or fewer optical spot defects (LPDs) with a size of 0.09 μm or larger.

4. The epitaxial wafer of claim 1, wherein the top surface of the epitaxial layer contains 60 or fewer LPDs with a size of 0.09 μm or larger.

5. The epitaxial wafer of claim 1, further comprising a 4.0 × 10⁻⁶ mm² core. 17 atoms / cm 3 Up to 10×10 17 atoms / cm 3 The oxygen concentration of the silicon substrate within the range specified.

6. The epitaxial wafer of claim 1, wherein the resistivity of the silicon substrate is in the range of 0.5 mΩ·cm to 0.9 mΩ·cm.

7. The epitaxial wafer of claim 1, wherein the silicon substrate is free of crystal-originating particles.

8. An epitaxial wafer with a diameter of 200 mm, comprising: A phosphorus-doped silicon substrate with a resistivity of 1.2 mΩ·cm or less, and a carbon concentration of 3.0 × 10⁻⁶ at the center of the silicon substrate in the depth direction. 16 atoms / cm 3 Or larger; Epitaxial layer on the silicon substrate; and The boundary between the epitaxial layer and the silicon substrate; The silicon substrate further has a low-carbon concentration layer on the surface side in contact with the epitaxial layer.

9. The epitaxial wafer of claim 8, wherein the carbon concentration is 3.0 × 10⁻⁶. 16 atoms / cm 3 Up to 5.0×10 17 atoms / cm 3 Within the range.

10. The epitaxial wafer of claim 8, wherein the low-carbon concentration layer in the silicon substrate is within 5 µm of the boundary, and the carbon concentration in the low-carbon concentration layer is reduced by 10% or more.

11. The epitaxial wafer of claim 8, wherein the low-carbon concentration layer in the silicon substrate is within 8 µm of the boundary, and the carbon concentration in the low-carbon concentration layer is reduced by 10% or more.

12. The epitaxial wafer of claim 8, wherein the low-carbon concentration layer in the silicon substrate is within 15 µm of the boundary, and the carbon concentration in the low-carbon concentration layer is reduced by 10% or more.

13. The epitaxial wafer of claim 8, wherein the top surface of the epitaxial layer contains 100 or fewer optical spot defects (LPDs) with a size of 0.09 μm or larger.

14. The epitaxial wafer of claim 8, wherein the top surface of the epitaxial layer contains 60 or fewer LPDs with a size of 0.09 μm or larger.

15. The epitaxial wafer of claim 8, further comprising a 4.0 × 10⁻⁶ mm² core. 17 atoms / cm 3 Up to 10×10 17 atoms / cm 3 The oxygen concentration of the silicon substrate within the range specified.

16. The epitaxial wafer of claim 8, wherein the resistivity of the silicon substrate is in the range of 0.5 mΩ·cm to 1.2 mΩ·cm.

17. The epitaxial wafer of claim 8, wherein the resistivity of the silicon substrate is below 0.9 mΩ·cm.

18. The epitaxial wafer of claim 8, wherein the silicon substrate is free of crystal-originating particles.

19. A silicon wafer with a diameter of 200 mm, phosphorus-doped and with a resistivity of 0.9 mΩ·cm or less, and a carbon concentration of 3.0 × 10⁻⁶ at the center of the silicon wafer in the depth direction. 16 atoms / cm 3 Or larger.

20. The silicon wafer of claim 19, wherein the carbon concentration at the center of the silicon wafer in the depth direction is 3.0 × 10⁻⁶. 16 atoms / cm 3 Up to 5.0×10 17 atoms / cm 3 Within the range.

21. The silicon wafer of claim 19, further comprising a 4.0 × 10⁻⁶ mm² diameter. 17 atoms / cm 3 Up to 10×10 17 atoms / cm 3 The oxygen concentration within the range.

22. The silicon wafer of claim 19, wherein the resistivity of the silicon wafer is in the range of 0.5 mΩ·cm to 0.9 mΩ·cm.

23. The silicon wafer of claim 19, wherein the silicon wafer is free of crystal-originating particles.

24. An epitaxial wafer with a diameter of 200 mm, comprising: A phosphorus-doped silicon substrate with a resistivity of 1.2 mΩ·cm or less; An epitaxial layer on top of the silicon substrate; and The boundary between the epitaxial layer and the silicon substrate; in The carbon concentration in the silicon substrate at the center in the depth direction is 3.0 × 10⁻⁶. 16 atoms / cm 3 Or larger, The carbon concentration in the region of the silicon substrate between the boundary and a position 5 µm to 15 µm from the boundary is 10% or more lower than the carbon concentration at the center of the silicon substrate in the depth direction.

25. The epitaxial wafer of claim 24, wherein the resistivity of the silicon substrate is in the range of 0.5 mΩ·cm to 0.9 mΩ·cm.

26. The epitaxial wafer of claim 24, wherein the carbon concentration at the center of the silicon substrate in the depth direction is 3.0 × 10⁻⁶. 16 atoms / cm 3 Up to 5.0×10 17 atoms / cm 3 Within the range.

27. The epitaxial wafer of claim 24, wherein the top surface of the epitaxial layer has 100 or fewer LPDs with a size of 0.09 μm or larger.

28. The epitaxial wafer of claim 24, further comprising a 4.0 × 10⁻⁶ mm² core. 17 atoms / cm 3 Up to 10×10 17 atoms / cm 3 The oxygen concentration of the silicon substrate within the range specified.

29. The epitaxial wafer of claim 24, wherein the silicon substrate has a top surface and a bottom surface, and the resistivity measured from the top surface or the bottom surface is 1.2 mΩ·cm or less.

30. A silicon wafer with a diameter of 200 mm, doped with phosphorus and with a resistivity of 1.2 mΩ·cm or less. The silicon wafer includes a top surface and a bottom surface; The carbon concentration in the silicon wafer at its center along the depth direction is 3.0 × 10⁻⁶. 16 atoms / cm 3 Or larger, The carbon concentration in the region of the silicon wafer between the top surface and a position 5 µm to 15 µm from the top surface is 10% or more lower than the carbon concentration at the center of the silicon wafer in the depth direction.

31. The silicon wafer of claim 30, wherein the resistivity of the silicon wafer is in the range of 0.5 mΩ·cm to 0.9 mΩ·cm.

32. The silicon wafer of claim 30, wherein the carbon concentration at the center of the silicon wafer in the depth direction is 3.0 × 10⁻⁶. 16 atoms / cm 3 Up to 5.0×10 17 atoms / cm 3 Within the range.

33. The silicon wafer of claim 30, further comprising a 4.0 × 10⁻⁶ mm² diameter. 17 atoms / cm 3 Up to 10×10 17 atoms / cm 3 The oxygen concentration within the range.

34. The silicon wafer of claim 30, wherein the resistivity measured from the top surface or the bottom surface is 1.2 mΩ·cm or less.

35. A method for manufacturing an epitaxial wafer with a diameter of 200 mm, comprising: Place the crucible in the furnace; Phosphorus and carbon are added to the silicon melt in the crucible; Single crystals are pulled from the silicon melt by rotation using a puller; The single crystal is cut into at least one silicon wafer with a resistivity of 0.9 mΩ·cm or less; and An epitaxial layer is formed on the surface of the silicon wafer, wherein the carbon concentration of the silicon wafer at the center in the depth direction is 3.0 × 10⁻⁶. 16 atoms / cm 3 Or larger.

36. The method of claim 35, further comprising heating the silicon wafer in an argon-filled atmosphere at a temperature between 1150°C and 1250°C.

37. The method of claim 36, wherein the silicon wafer is heated for a duration between 30 and 120 minutes.

38. The method of claim 35, further comprising applying a magnetic field to the silicon melt and controlling the pressure in the furnace such that the oxygen concentration of the silicon wafer is 4.0 × 10⁻⁶. 17 atoms / cm 3 Up to 10×10 17 atoms / cm 3 between.

39. The method of claim 38, wherein the oxygen concentration is measured from halfway down the depth direction of the silicon wafer.

Images