LDMOS-based electrostatic protection semiconductor device

Abstract

The present invention provides an electrostatic protection semiconductor device based on LDMOS, comprising: a substrate, a drift region, a drain doping region, a first trench isolation structure, a second trench isolation structure, an annular well region, a first annular isolation structure, an annular source doping region, an annular body end doping region, and an annular gate. The present application designs the left side of the device as a first LDMOS and the right side as a second LDMOS, so that the device has two electrostatic current discharge paths from the anode to the cathode, and makes the depth of the first trench isolation structure smaller than that of the second trench isolation structure. The current clamping after the breakdown of the first LDMOS with a low breakdown voltage controls the gate voltage of the second LDMOS with a high breakdown voltage, turns on the second LDMOS, and quickly discharges the ESD current through the channel, thereby improving the overall ESD protection capability of the device, avoiding failure caused by the Kirk effect inside the device under ultrafast electrostatic pulses, and enhancing the stability of the device performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an electrostatic protection semiconductor device based on LDMOS. Background Art

[0002] ESD (electrostatic discharge) failure is one of the most common reliability issues facing the electronics industry. Statistics show that up to 35% of integrated circuit failures are caused by ESD, costing the electronics industry billions of dollars annually. Currently, a common approach is to integrate carefully designed protection structures into electronic circuits through process technology to protect integrated circuits from electrostatic shock.

[0003] Over the past few decades, people have worked tirelessly to develop a variety of ESD protection structures, such as diodes, gate-grounded MOS transistors, silicon controlled rectifiers (SCRs), and lateral double-diffused MOS devices (LDMOS). Among them, LDMOS devices are widely used for ESD protection of high-voltage channels because they can withstand higher breakdown voltages.

[0004] In traditional ESD LDMOS devices, the existing method for improving their ESD resistance is to increase the channel length. As the channel length increases, the channel resistance increases, and thus the voltage it can withstand increases. However, increasing the channel length increases the size of the ESD LDMOS device, thereby increasing the cost of the integrated circuit. Therefore, how to achieve a device with a small device area and strong ESD resistance is an urgent semiconductor technology problem that needs to be solved. Summary of the Invention

[0005] The present application provides an LDMOS-based electrostatic protection semiconductor device, which can solve at least one of the problems of traditional ESD LDMOS devices, such as large chip area occupation and insufficient voltage resistance.

[0006] On the one hand, an embodiment of the present application provides an electrostatic protection semiconductor device based on LDMOS, comprising:

[0007] substrate;

[0008] a drift region located in the substrate and close to a surface of the substrate;

[0009] a drain doping region, wherein the drain doping region is located in the drift region;

[0010] a first trench isolation structure, wherein the first trench isolation structure is located in the drift region and on one side of the drain doping region;

[0011] a second trench isolation structure, the second trench isolation structure being located in the drift region and on the other side of the drain doping region;

[0012] an annular well region, the annular well region being located in the substrate and surrounding the drift region;

[0013] a first annular isolation structure, wherein the first annular isolation structure is located in the annular well region;

[0014] an annular source doping region, the annular source doping region being located in the annular well region and inside the first annular isolation structure;

[0015] an annular body end doped region, the annular body end doped region being located in the annular well region and outside the first annular isolation structure; and

[0016] an annular gate, the annular gate being located on the substrate between the drift region and the annular well region;

[0017] in,

[0018] The depth of the first trench isolation structure is less than the depth of the second trench isolation structure;

[0019] With the drain doping region as the center, the semiconductor structure from the center of the drain doping region to the left constitutes a first LDMOS, and the semiconductor structure from the center of the drain doping region to the right constitutes a second LDMOS;

[0020] The drain doped region is connected to the anode of an external power supply, the annular source doped region, the annular body end doped region and the annular gate in the first LDMOS are all connected to the cathode of the external power supply, and the annular source doped region, the annular body end doped region and the annular gate in the second LDMOS are all connected to the cathode of the external power supply.

[0021] Optionally, in the LDMOS-based electrostatic protection semiconductor device, the depth of the first trench isolation structure is at least less than the depth of the second trench isolation structure.

[0022] Optionally, in the LDMOS-based electrostatic protection semiconductor device, the LDMOS-based electrostatic protection semiconductor device further includes: a second annular isolation structure, wherein the second annular isolation structure is located in the substrate and is arranged around the annular well region.

[0023] Optionally, in the LDMOS-based electrostatic protection semiconductor device, the LDMOS-based electrostatic protection semiconductor device further includes: an annular deep trench isolation structure, wherein the annular deep trench isolation structure is located in the substrate and passes through the second annular isolation structure.

[0024] Optionally, in the LDMOS-based electrostatic protection semiconductor device, the LDMOS-based electrostatic protection semiconductor device further includes: a resistor, which is connected in series between the cathode of the external power supply and the annular source doping region in the first LDMOS.

[0025] Optionally, in the LDMOS-based electrostatic protection semiconductor device, the depth of the first trench isolation structure is

[0026] Optionally, in the LDMOS-based electrostatic protection semiconductor device, the depth of the second trench isolation structure is

[0027] Optionally, in the LDMOS-based electrostatic protection semiconductor device, the drift region, the drain doping region, the first trench isolation structure and the second trench isolation structure are all in a strip shape.

[0028] Optionally, in the LDMOS-based electrostatic protection semiconductor device, the conductivity type of the doped ions in the substrate, the annular well region, and the annular body end doping region is the same.

[0029] Optionally, in the LDMOS-based electrostatic protection semiconductor device, the conductivity type of the doped ions in the drift region, the annular source doped region, and the drain doped region is the same.

[0030] The technical solution of this application has at least the following advantages:

[0031] The present application forms a first LDMOS in the left area of the drain doping region and a second LDMOS in the right area, and designs the depth of the first trench isolation structure to be significantly smaller than the depth of the second trench isolation structure. Two LDMOSs with a common drain doping region are used, and the difference in the depth of the trench isolation structure (STI) is used to form two LDMOSs with different breakdown voltages (a first LDMOS with a lower breakdown voltage and a second LDMOS with a higher breakdown voltage). This allows the electrostatic protection semiconductor device to have two electrostatic current discharge paths from the anode to the cathode. The current clamping after the breakdown of the first LDMOS with a lower breakdown voltage is used to control the gate voltage of the second LDMOS with a higher breakdown voltage, thereby turning on the second LDMOS to quickly discharge the ESD current through the channel. This can effectively improve the overall ESD protection capability of the semiconductor device, avoid failure caused by the Kirk effect inside the semiconductor device under ultrafast electrostatic pulses, and enhance the stability of the device performance. In addition, the present application does not require an increase in channel length like traditional ESD devices. The electrostatic protection semiconductor device proposed in the present application achieves a larger ESD current capability with a smaller chip area.

[0032] Furthermore, the electrostatic protection semiconductor device provided by the present application is compatible with the existing BCD process platform and does not require an additional mask, thereby indirectly improving production efficiency and saving manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 is a cross-sectional view of an LDMOS-based electrostatic protection semiconductor device according to an embodiment of the present invention;

[0035] The description of the accompanying drawings is as follows:

[0036] 10-substrate, 11-drift region, 12-first trench isolation structure, 13-second trench isolation structure, 14-drain doping region, 15-annular well region, 16-annular source doping region, 17-annular body end doping region, 18-first annular isolation structure, 19-annular deep trench isolation structure, 20-second annular isolation structure, 21-annular gate dielectric layer, 22-annular gate. DETAILED DESCRIPTION

[0037] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0038] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0040] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0041] The present application embodiment provides an electrostatic protection semiconductor device based on LDMOS, referring to Figure 1 , Figure 1 1 is a cross-sectional view of an electrostatic protection semiconductor device based on LDMOS according to an embodiment of the present invention, wherein the electrostatic protection semiconductor device based on LDMOS includes: a substrate 10, a drift region 11, a drain doping region 14, a first trench isolation structure 12, a second trench isolation structure 12, an annular well region 15, a first annular isolation structure 18, an annular source doping region 16, an annular body end doping region 17 and an annular gate 22; wherein,

[0042] The substrate 10 may be a substrate having an epitaxial layer;

[0043] The drift region 11 is located in the substrate 10 and close to the surface of the substrate 10;

[0044] The drain doping region 14 is located in the drift region 11;

[0045] The first trench isolation structure 12 is located in the drift region 11 and close to the surface of the drift region 11 , and the first trench isolation structure 12 is located on one side of the drain doping region 14 ;

[0046] a second trench isolation structure 12 , the second trench isolation structure 12 being located in the drift region 11 and on the other side of the drain doping region 14 ;

[0047] The annular well region 15 is located in the substrate 10 and close to the surface of the substrate 10 , and the annular well region 15 is arranged around the drift region 11 , with a certain distance between the annular well region 15 and the drift region 11 ;

[0048] The first annular isolation structure 18 is located in the annular well region 15 and close to the surface of the annular well region 15;

[0049] The annular source doping region 16 is located in the annular well region 15 and close to the surface of the annular well region 15 , and the annular source doping region 16 is located inside the first annular isolation structure 18 (close to the second trench isolation structure 12 );

[0050] The annular body end doping region 17 is located in the annular well region 15 and close to the surface of the annular well region 15 , and the annular body end doping region 17 is located outside the first annular isolation structure (close to the second trench isolation structure 12 );

[0051] The annular gate 22 is located on the substrate 10 between the drift region 11 and the annular well region 15. The annular gate 22 overlaps with the drift region 11 and the annular well region 15 on the projection surface of the substrate. That is, the annular gate 22 covers part of the annular well region 15 and covers part of the first trench isolation structure 12 in the drift region 11. The length of the overlapping area between the annular gate 22 and the first trench isolation structure 12 is one of the key parameters for measuring the electrical performance of the device. The area (overlapping area) where the annular gate 22 covers the first trench isolation structure 12 can be called a field plate. The width of the field plate directly affects the electric field distribution and determines the voltage resistance level of the device.

[0052] The semiconductor structure from the center of the drain doping region 14 to the left constitutes a first LDMOS, and the semiconductor structure from the center of the drain doping region 14 to the right constitutes a second LDMOS.

[0053] In this embodiment, the drain doping region 14 is connected to the anode of the external power supply, the annular source doping region 16, the annular body end doping region 17 and the annular gate 22 in the first LDMOS are all connected to the cathode of the external power supply, and the annular source doping region 16, the annular body end doping region 17 and the annular gate 22 in the second LDMOS are all connected to the cathode of the external power supply.

[0054] Furthermore, the depth of the first trench isolation structure 12 is less than the depth of the second trench isolation structure 13. Preferably, the depth of the first trench isolation structure 12 is at least less than the depth of the second trench isolation structure 13.

[0055] Preferably, the depth of the first trench isolation structure 12 is The depth of the second trench isolation structure 13 is

[0056] In this embodiment, the depth of the first trench isolation structure 12 can be The depth of the second trench isolation structure 13 can be

[0057] In the present application, the left side area of the drain doping region 14 is formed into a first LDMOS, and the right side area is formed into a second LDMOS, and the depth of the first trench isolation structure 12 is designed to be significantly smaller than the depth of the second trench isolation structure 13. Two LDMOSs with a common drain doping region 14 are used, and the difference in depth between the first trench isolation structure 12 and the second trench isolation structure 13 is utilized to form two LDMOSs with different breakdown voltages (a first LDMOS with a lower breakdown voltage and a second LDMOS with a higher breakdown voltage). This enables the electrostatic protection semiconductor device to have two electrostatic current discharge paths from the anode to the cathode. The current clamping after the breakdown of the first LDMOS with a lower breakdown voltage is utilized to control the gate voltage of the second LDMOS with a higher breakdown voltage, thereby turning on the second LDMOS to quickly discharge the ESD current through the channel. This can effectively improve the overall ESD protection capability of the semiconductor device, achieve a larger ESD current capability with a smaller chip area, avoid failure caused by the Kirk effect inside the semiconductor device under ultrafast electrostatic pulses, and enhance the stability of the device performance. Furthermore, the electrostatic protection semiconductor device provided by the present application is compatible with the existing BCD process platform and does not require an additional mask, thereby indirectly improving production efficiency and saving manufacturing costs.

[0058] Further, such as Figure 1As shown, the LDMOS-based electrostatic protection semiconductor device further includes a second annular isolation structure 20 , which is located in the substrate and surrounds the annular well region 15 .

[0059] Preferably, Figure 1 As shown, the LDMOS-based electrostatic protection semiconductor device further includes: an annular deep trench isolation structure 19 , which is located in the substrate 10 and passes through the second annular isolation structure 20 .

[0060] Further, such as Figure 1 As shown, the LDMOS-based electrostatic protection semiconductor device further includes: a resistor R, which is connected in series between the cathode of the external power supply and the annular source doping region 16 in the first LDMOS. The resistance value of the resistor R can be set higher according to actual needs, for example, 2KΩ. The function of the resistor R is to increase the voltage of the cathode. When the ESD current impacts the anode, the first LDMOS with a lower breakdown voltage is broken down to form a current path. The current passes through the high resistance to form a clamping voltage applied to the gate of the second LDMOS with a higher breakdown voltage, thereby turning on the second LDMOS and quickly discharging the ESD current through the channel, thereby effectively improving the ESD protection capability of the entire device. The device can achieve a larger ESD current capability with a smaller chip area.

[0061] In this embodiment, the drift region 11 , the drain doping region 14 , the first trench isolation structure 12 , and the second trench isolation structure 13 are all in a strip shape.

[0062] Furthermore, the dopant ions in the substrate 10, the annular well region 15, and the annular body-end doping region 17 have the same conductivity type, which can be P-type or N-type; the dopant ions in the drift region 11, the annular source doping region 16, and the drain doping region 14 have the same conductivity type, which can be N-type or P-type. It is worth noting that the present application requires that the conductivity type of the dopant ions in the substrate 10 be opposite to the conductivity type of the dopant ions in the drift region.

[0063] In this embodiment, the conductivity type of the doped ions in the substrate 10, the annular well region 15, and the annular body end doping region 17 may be P-type, and the conductivity type of the doped ions in the drift region 11, the annular source doping region 16, and the drain doping region 14 may be N-type. Furthermore, the annular body end doping region 17, the annular source doping region 16, and the drain doping region 14 are all heavily doped (N+).

[0064] Further, such as Figure 1As shown, the LDMOS-based electrostatic protection semiconductor device may further include: an annular gate dielectric layer 21 , wherein the annular gate dielectric layer 21 is located between the substrate 10 and the annular gate 22 .

[0065] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. An electrostatic protection semiconductor device based on LDMOS, characterized in that: include: substrate; a drift region located in the substrate and close to a surface of the substrate; a drain doping region, wherein the drain doping region is located in the drift region; a first trench isolation structure, wherein the first trench isolation structure is located in the drift region and on one side of the drain doping region; a second trench isolation structure, the second trench isolation structure being located in the drift region and on the other side of the drain doping region; an annular well region, the annular well region being located in the substrate and surrounding the drift region; a first annular isolation structure, wherein the first annular isolation structure is located in the annular well region; an annular source doping region, the annular source doping region being located in the annular well region and inside the first annular isolation structure; an annular body end doped region, the annular body end doped region being located in the annular well region and outside the first annular isolation structure; as well as, an annular gate, the annular gate being located on the substrate between the drift region and the annular well region; in, The depth of the first trench isolation structure is less than the depth of the second trench isolation structure; With the drain doping region as the center, the semiconductor structure from the center of the drain doping region to the left constitutes a first LDMOS, and the semiconductor structure from the center of the drain doping region to the right constitutes a second LDMOS; The drain doped region is connected to the anode of an external power supply, the annular source doped region, the annular body end doped region and the annular gate in the first LDMOS are all connected to the cathode of the external power supply, and the annular source doped region, the annular body end doped region and the annular gate in the second LDMOS are all connected to the cathode of the external power supply.

2. The electrostatic protection semiconductor device based on LDMOS according to claim 1, characterized in that: The depth of the first trench isolation structure is at least less than the depth of the second trench isolation structure.

3. The electrostatic protection semiconductor device based on LDMOS according to claim 1, characterized in that: The LDMOS-based electrostatic protection semiconductor device further includes a second annular isolation structure, which is located in the substrate and surrounds the annular well region.

4. The electrostatic protection semiconductor device based on LDMOS according to claim 3, characterized in that: The LDMOS-based electrostatic protection semiconductor device further includes: an annular deep trench isolation structure, wherein the annular deep trench isolation structure is located in the substrate and penetrates the second annular isolation structure.

5. The electrostatic protection semiconductor device based on LDMOS according to claim 1, characterized in that: The LDMOS-based electrostatic protection semiconductor device further includes: a resistor connected in series between a cathode of an external power source and the annular source doping region in the first LDMOS.

6. The electrostatic protection semiconductor device based on LDMOS according to claim 1, characterized in that: The depth of the first trench isolation structure is 7. The electrostatic protection semiconductor device based on LDMOS according to claim 1, characterized in that: The depth of the second trench isolation structure is 8. The electrostatic protection semiconductor device based on LDMOS according to claim 1, characterized in that: The drift region, the drain doping region, the first trench isolation structure and the second trench isolation structure are all in a strip shape.

9. The electrostatic protection semiconductor device based on LDMOS according to claim 1, characterized in that: The conductive types of the doped ions in the substrate, the annular well region and the annular body end doped region are the same.

10. The electrostatic protection semiconductor device based on LDMOS according to claim 1, characterized in that: The conductivity type of the doped ions in the drift region, the annular source doped region and the drain doped region is the same.

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